Semiconductor device

Abstract

This semiconductor device is provided with: a semiconductor substrate having an element region in which a transistor is formed; an interlayer insulating film provided on the semiconductor substrate; and a semiconductor layer provided on the interlayer insulating film. The semiconductor layer includes: a first semiconductor layer of a first conductivity type connected to a gate of the transistor; a second semiconductor layer of a second conductivity type connected to the first semiconductor layer; and a third semiconductor layer of the first conductivity type connected to the second semiconductor layer and connected to the low potential terminal of the transistor.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses a semiconductor device including a main transistor and a protection transistor. The protection transistor is connected between the gate and source of the main transistor, and the gate of the protection transistor is connected to the gate of the main transistor.

[0003] In this semiconductor device, the threshold voltage of the protection transistor is higher than the threshold voltage of the main transistor. Therefore, during normal operation, the protection transistor is not turned on, and the operation of the main transistor is not hindered. On the other hand, if an overcurrent flows in the main transistor and the temperature of the main transistor rises, the temperature of the protection transistor also rises, and the threshold voltage of the protection transistor decreases. As a result, the protection transistor is turned on, the gate source of the main transistor is short-circuited, and the main transistor is forcibly turned off. As a result, the main transistor can be protected from thermal breakdown.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-212738 Summary of the invention

[0007] In the semiconductor device of Patent Document 1, the main transistor and the protection transistor are formed adjacent to each other inside the same semiconductor substrate. Therefore, when the main transistor is operating, the protection transistor may operate parasitically and hinder the operation of the main transistor. In this specification, a technology capable of protecting a transistor from thermal breakdown when an overcurrent flows in the transistor is provided through a structure different from that of Patent Document 1.

[0008] The semiconductor device disclosed in this specification comprises: a semiconductor substrate having a device region in which a transistor is formed; an interlayer insulating film provided on the semiconductor substrate; and a semiconductor layer provided on the interlayer insulating film. The semiconductor layer comprises: a first semiconductor layer of the first conductivity type connected to the gate of the transistor; a second semiconductor layer of the second conductivity type connected to the first semiconductor layer; and a third semiconductor layer of the first conductivity type connected to the second semiconductor layer and to the low potential terminal of the transistor.

[0009] In the above-mentioned semiconductor device, between the gate and the low potential terminal, the semiconductor layer is connected in the order of the first semiconductor layer of the first conductivity type, the second semiconductor layer of the second conductivity type, and the third semiconductor layer of the first conductivity type, so that when the semiconductor device is normally operated, no current flows in the semiconductor layer, and the operation of the transistor is not hindered. On the other hand, if an overcurrent flows in the transistor and the temperature of the semiconductor substrate rises, the heat is transmitted to the semiconductor layer via the interlayer insulating film, so that the temperature of the semiconductor layer also rises. As a result, electron-hole pairs are generated inside the second semiconductor layer, and the resistance of the second semiconductor layer becomes lower. As a result, current flows from the gate of the transistor to the low potential terminal of the transistor via the semiconductor layer, and the gate of the transistor and the low potential terminal are short-circuited. As a result, the transistor is forcibly turned off. In the semiconductor device, the transistor and the semiconductor layer are physically separated by the interlayer insulating film. Therefore, when the transistor is normally operated, it is possible to suppress the situation where the semiconductor layer is parasitically turned on. Therefore, according to the semiconductor device, it is possible to suppress the obstruction of the operation of the transistor and appropriately protect the transistor from thermal breakdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a top view of the semiconductor device according to the first embodiment.

[0011] Figure 2 yes Figure 1 Cross-sectional view of the main parts along line II-II.

[0012] Figure 3 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0013] Figure 4 The semiconductor device of the second embodiment Figure 2 Corresponding cross-sectional view of the main parts.

[0014] Figure 5 This is an equivalent circuit diagram of the semiconductor device according to the second embodiment.

[0015] Figure 6 The semiconductor device of the third embodiment Figure 2 Corresponding cross-sectional view of the main parts.

[0016] Figure 7 A semiconductor device according to a fourth embodiment of the present invention Figure 2 Corresponding cross-sectional view of the main parts.

[0017] Figure 8 This is a diagram of a semiconductor layer of a semiconductor device according to a modified example as viewed from above.

[0018] Fig. 9 This is a diagram of a semiconductor layer of a semiconductor device according to another modification example as viewed from above. DETAILED DESCRIPTION

[0019] In the semiconductor device of one example disclosed in the present specification, when the semiconductor substrate is viewed from above, the semiconductor substrate may further include a peripheral region arranged around the element region, and the semiconductor layer may be arranged in the peripheral region.

[0020] According to such a structure, since the semiconductor layer is arranged in the peripheral region where the main current does not flow, a large area of ​​the element region can be ensured.

[0021] In the semiconductor device of one example disclosed in the present specification, when the semiconductor substrate is viewed from above, the semiconductor layer may be arranged in a range sandwiched between the two element regions.

[0022] When an overcurrent flows through the transistor, the device region generates heat. According to such a structure, since the semiconductor layer is arranged in the range sandwiched by the heated device region, the temperature of the semiconductor layer easily rises, and the gate and the low potential terminal of the transistor can be short-circuited quickly.

[0023] In the semiconductor device of one example disclosed in the present specification, the material constituting the semiconductor layer may have a smaller band gap than the material constituting the semiconductor substrate.

[0024] According to such a structure, the semiconductor layer is turned on before the high potential terminal and the low potential terminal of the transistor are short-circuited, so that the gate and the low potential terminal of the transistor can be short-circuited.

[0025] In the semiconductor device of one example disclosed in this specification, the peak concentration of the first conductivity type impurity in the first semiconductor layer and the third semiconductor layer may be 1×10 18 cm －3 As mentioned above, the peak concentration of the second conductivity type impurity in the second semiconductor layer is 5×10 17 cm －3 the following.

[0026] According to such a structure, the contact resistance between the first semiconductor layer and the third semiconductor layer and each terminal can be reduced. In addition, the resistance of the second semiconductor layer can be rapidly reduced when the temperature thereof rises.

[0027] In one example of a semiconductor device disclosed in this specification, the first conductivity type may be n-type, the second conductivity type may be p-type, and the n-type impurity concentration in the range of the first semiconductor layer in contact with the second semiconductor layer may be lower than the n-type impurity concentration in the range in contact with the gate.

[0028] According to such a structure, since a region with a relatively low n-type impurity concentration exists in the n-type first semiconductor layer located on the gate side, when a positive voltage is applied to the gate, a higher voltage can be maintained between the gate and the low potential terminal.

[0029] In one example of a semiconductor device disclosed in this specification, the first conductivity type may be p-type, the second conductivity type may be n-type, and the p-type impurity concentration in the range of the third semiconductor layer in contact with the second semiconductor layer may be lower than the p-type impurity concentration in the range in contact with the low potential terminal.

[0030] According to such a structure, since a region with a relatively low p-type impurity concentration exists in the p-type third semiconductor layer located on the low potential terminal side, a higher voltage can be maintained between the gate and the low potential terminal when a positive voltage is applied to the gate.

[0031] In the semiconductor device of one example disclosed in the present specification, the semiconductor substrate may be formed of a wide-gap semiconductor, and the semiconductor layer may be formed of polycrystalline silicon.

[0032] (First embodiment)

[0033] Hereinafter, a semiconductor device 10 according to a first embodiment will be described with reference to the drawings. Figure 1 The semiconductor device 10 shown in the figure includes a semiconductor substrate 12, an electrode, an insulating layer, etc. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and orthogonal to the x-direction is referred to as the y-direction, and a thickness direction of the semiconductor substrate 12 is referred to as the z-direction. Figure 1 As shown, the semiconductor substrate 12 includes two element regions 60 and a peripheral region 62. A transistor 20 (see FIG. 2 ) is formed in each element region 60. Figure 3 ), the two element regions 60 are spaced apart in the x direction. The transistor 20 of this embodiment is an n-type MOSFET (Metal-Oxide-Semiconductor Field-effect Transistor). The peripheral region 62 is arranged around each element region 60. The peripheral region 62 is the region between the element region 60 and the outer peripheral end of the semiconductor substrate 12 and the region between the two element regions 60. In addition, Figure 1In order to facilitate viewing of the drawings, the electrodes, insulating layers, etc. on the upper surface 12a of the semiconductor substrate 12 are partially omitted. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 is not limited to SiC, and may be made of other wide-bandgap semiconductors such as GaN, Ga2O3, diamond, or a semiconductor such as Si. In the peripheral region 62, a gate pad 50 is arranged on the upper surface 12a of the semiconductor substrate 12.

[0034] Figure 2 yes Figure 1 A cross-sectional view of the main parts along the II-II line. In detail, Figure 2 FIG. 2 shows a cross section of the upper surface 12a side of the semiconductor substrate 12. Figure 2 As shown, an interlayer insulating film 16 is provided on the upper surface 12a of the semiconductor substrate 12. In addition, although not shown, in the element region 60, an n-type MOSFET structure is formed inside the semiconductor substrate 12. The n-type MOSFET can be a trench type or a planar type. The interlayer insulating film 16 covers most of the upper surface 12a of the semiconductor substrate 12 across the element region 60 and the peripheral region 62.

[0035] The semiconductor layer 14 is provided on the interlayer insulating film 16. The semiconductor layer 14 is physically separated from the semiconductor substrate 12 by the interlayer insulating film 16. The interlayer insulating film 16 is also in contact with the side surface and the upper surface of the semiconductor layer 14. That is, the semiconductor layer 14 is covered by the interlayer insulating film 16. Figure 1 As shown, when the semiconductor substrate 12 is viewed from above, the semiconductor layer 14 is arranged in a range sandwiched between the two element regions 60 in the peripheral region 62 .

[0036] The band gap of the material constituting the semiconductor layer 14 is smaller than the band gap of the material constituting the semiconductor substrate 12. Specifically, the semiconductor layer 14 is composed of polycrystalline silicon. Figure 2 As shown, the semiconductor layer 14 includes a first semiconductor layer 22 , a second semiconductor layer 24 , and a third semiconductor layer 26 .

[0037] The first semiconductor layer 22 is of n-type. The first semiconductor layer 22 is connected to the gate electrode 30 via a contact hole 16a provided in the interlayer insulating film 16. The gate electrode 30 functions as a gate electrode of a transistor (i.e., an n-type MOSFET) provided in the element region 60. The gate electrode 30 is opposed to a body region (specifically, a body region between a source region and a drain region) provided inside the semiconductor substrate 12 via a gate insulating film at a position not shown in the figure. The peak concentration of n-type impurities in the first semiconductor layer 22 is 1×10 18 cm －3 above.

[0038] The second semiconductor layer 24 is of p-type. The second semiconductor layer 24 is connected to the first semiconductor layer 22. The peak concentration of the p-type impurity in the second semiconductor layer 24 is 5×10 17 cm －3 the following.

[0039] The third semiconductor layer 26 is of n-type. The third semiconductor layer 26 is connected to the second semiconductor layer 24. The second semiconductor layer 24 is provided between the third semiconductor layer 26 and the first semiconductor layer 22, and the third semiconductor layer 26 is separated from the first semiconductor layer 22 by the second semiconductor layer 24. In addition, the third semiconductor layer 26 is connected to the source electrode 32 via the contact hole 16b provided in the interlayer insulating film 16. The source electrode 32 functions as a source electrode of a transistor (i.e., an n-type MOSFET) provided in the element region 60. The source electrode 32 is in ohmic contact with a source region provided inside the semiconductor substrate 12 at a position not shown in the figure. The peak concentration of n-type impurities in the third semiconductor layer 26 is 1×10 18 cm －3 above.

[0040] like Figure 1 and Figure 2 As shown, the first semiconductor layer 22 , the second semiconductor layer 24 , and the third semiconductor layer 26 extend along the y direction, respectively.

[0041] Figure 3 1 shows an equivalent circuit diagram of the semiconductor device 10. As described above, the semiconductor device 10 of the first embodiment includes a semiconductor layer 14 in which the first semiconductor layer 22, the second semiconductor layer 24, and the third semiconductor layer 26 are connected in sequence between the gate electrode 30 and the source electrode 32. Figure 3 As shown, in the semiconductor device 10, it can be considered that a diode 42 in the reverse direction and a diode 44 in the forward direction are connected in series between the gate G and the source S of the transistor 20 from the gate G toward the source S. That is, in other words, the semiconductor layer 14 can be said to have a cathode of the diode 42 connected to the gate G of the transistor 20, an anode of the diode 42 connected to the anode of the diode 44, and a cathode of the diode 44 connected to the source S of the transistor 20.

[0042] Next, the operation of the semiconductor device 10 will be described. During normal operation of the semiconductor device 10, Figure 3A positive voltage is applied to the drain D, and the source S is grounded. Furthermore, if a voltage higher than the threshold is applied to the gate G, the transistor 20 is turned on. Since the semiconductor layer 14 is connected in the order of the n-type first semiconductor layer 22, the p-type second semiconductor layer 24, and the n-type third semiconductor layer 26 between the gate G and the source S, no current flows in the semiconductor layer 14 at the normal operating temperature of the semiconductor device 10. Therefore, no short circuit occurs between the gate G and the source S of the transistor 20, and the transistor 20 can perform normal operation.

[0043] On the other hand, when the semiconductor device 10 operates abnormally, for example, if a fault such as a short circuit of a load connected to the semiconductor device 10 occurs, an overcurrent flows through the transistor 20. If an overcurrent flows through the transistor 20, the temperature of the semiconductor substrate 12 rises. Therefore, heat is transmitted to the semiconductor layer 14 via the interlayer insulating film 16, and the temperature of the semiconductor layer 14 also rises. Then, electron-hole pairs are generated in the second semiconductor layer 24, and the resistance of the second semiconductor layer 24 becomes lower. As a result, a current flows from the gate G of the transistor 20 to the source S via the semiconductor layer 14, and the gate G and the source S are short-circuited, and the transistor 20 is forcibly turned off. As a result, the temperature rise of the semiconductor substrate 12 stops, and the transistor 20 is protected from thermal breakdown.

[0044] In the semiconductor device 10 of the present embodiment, the transistor 20 and the semiconductor layer 14 are physically separated by the interlayer insulating film 16. Therefore, it is possible to suppress the semiconductor layer 14 from being parasitically turned on during normal operation of the transistor 20. Therefore, according to the semiconductor device 10 of the present embodiment, it is possible to suppress interference with the operation of the transistor 20 and appropriately protect the transistor 20 from thermal breakdown.

[0045] In addition, in the present embodiment, the semiconductor layer 14 is arranged in the peripheral region 62. Since the semiconductor layer 14 is arranged in the region where the main current does not flow (i.e., outside the element region 60), the area of ​​the element region 60 can be relatively large. Furthermore, the semiconductor layer 14 is arranged in the range sandwiched by the element region 60. Since the semiconductor layer 14 is arranged in the range sandwiched by the element region 60 that generates heat when an overcurrent flows through the transistor 20, the temperature of the semiconductor layer 14 is easily increased, and the gate G and the source S of the transistor 20 can be short-circuited quickly.

[0046] In this embodiment, the band gap of the material (polysilicon) constituting the semiconductor layer 14 may be smaller than that of the material (SiC) constituting the semiconductor substrate 12. Therefore, before the drain D and source S of the transistor 20 are short-circuited, the gate G and source S can be short-circuited.

[0047] In this embodiment, the peak concentration of the n-type impurity in the first semiconductor layer 22 and the third semiconductor layer 26 is 1×10 18 cm －3 As mentioned above, the peak concentration of the p-type impurity in the second semiconductor layer 24 is 5×10 17 cm －3 Therefore, it is possible to reduce the contact resistance between the first semiconductor layer 22 and the gate G and between the third semiconductor layer 26 and the source S. In addition, when the temperature of the second semiconductor layer 24 rises, the resistance is rapidly reduced.

[0048] (Second embodiment)

[0049] In the second embodiment, if Figure 4 As shown in FIG. 1 , the structure of the semiconductor layer 114 is different from that of the semiconductor layer 14 of the first embodiment. The semiconductor layer 114 of the second embodiment includes a first semiconductor layer 122 , a second semiconductor layer 124 , and a third semiconductor layer 126 .

[0050] The first semiconductor layer 122 is p-type. The first semiconductor layer 122 is connected to the gate electrode 30 via a contact hole 16a provided in the interlayer insulating film 16. The gate electrode 30 is opposed to a body region (specifically, a body region between a source region and a drain region) provided inside the semiconductor substrate 12 via a gate insulating film at a position not shown. The peak concentration of p-type impurities in the first semiconductor layer 122 is 1×10 18 cm －3 above.

[0051] The second semiconductor layer 124 is of n-type. The second semiconductor layer 124 is connected to the first semiconductor layer 122. The peak concentration of n-type impurities in the second semiconductor layer 124 is 5×10 17 cm －3 the following.

[0052] The third semiconductor layer 126 is of p-type. The third semiconductor layer 126 is connected to the second semiconductor layer 124. In addition, the third semiconductor layer 126 is connected to the source electrode 32 via the contact hole 16b provided in the interlayer insulating film 16. The source electrode 32 is in ohmic contact with the source region provided inside the semiconductor substrate 12 at a position not shown. The peak concentration of the p-type impurity in the third semiconductor layer 126 is 1×10 18 cm －3 above.

[0053] Figure 5 FIG. 2 is an equivalent circuit diagram of a semiconductor device 100 according to the second embodiment. Figure 5As shown, it can be considered that a diode 142 in the forward direction and a diode 144 in the reverse direction are connected in series from the gate G toward the source S between the gate G and the source S of the transistor 20. That is, in other words, the semiconductor layer 114 can be said to have an anode of the diode 142 connected to the gate G of the transistor 20, a cathode of the diode 142 connected to the cathode of the diode 144, and an anode of the diode 144 connected to the source S of the transistor 20.

[0054] In the second embodiment, similarly to the first embodiment, when the semiconductor device 100 operates abnormally, the resistance of the second semiconductor layer 124 decreases. As a result, the gate G and the source S are short-circuited, and the transistor 20 can be forcibly turned off. In addition, in the second embodiment, the semiconductor layer 114 is also physically separated from the semiconductor substrate 12 by the interlayer insulating film 16, so when the transistor 20 operates normally, it is possible to suppress the semiconductor layer 114 from being parasitically turned on.

[0055] (Third embodiment)

[0056] In the third embodiment, if Figure 6 As shown in FIG. 1 , the first semiconductor layer 22 has a high concentration region 22a and a low concentration region 22b, which is different from the first embodiment. The other structures of the third embodiment are the same as those of the first embodiment.

[0057] The n-type impurity concentration of the low concentration region 22b is lower than the n-type impurity concentration of the high concentration region 22a. The high concentration region 22a is arranged in a range in contact with the gate electrode 30. The low concentration region 22b is arranged in a range in contact with the second semiconductor layer 24. That is, in the third embodiment, the high concentration region 22a, the low concentration region 22b, the second semiconductor layer 24, and the third semiconductor layer 26 are connected in sequence between the gate electrode 30 and the source electrode 32.

[0058] In the semiconductor device of the third embodiment, a low concentration region 22 b having a relatively low n-type impurity concentration exists in the n-type first semiconductor layer 22 located on the gate electrode 30 side, so when a positive voltage is applied to the gate electrode 30 , a higher voltage can be maintained between the gate electrode 30 and the source electrode 32 .

[0059] (Fourth embodiment)

[0060] In the fourth embodiment, if Figure 7 As shown in FIG. 1 , the third semiconductor layer 126 has a high concentration region 126a and a low concentration region 126b, which is different from the second embodiment. The other structures of the fourth embodiment are the same as those of the second embodiment.

[0061] The p-type impurity concentration of the low concentration region 126b is lower than the p-type impurity concentration of the high concentration region 126a. The high concentration region 126a is arranged in a range in contact with the source electrode 32. The low concentration region 126b is arranged in a range in contact with the second semiconductor layer 124. That is, in the fourth embodiment, the first semiconductor layer 122, the second semiconductor layer 124, the low concentration region 126b, and the high concentration region 126a are sequentially connected between the gate electrode 30 and the source electrode 32.

[0062] In the semiconductor device of the fourth embodiment, a low concentration region 126 b having a relatively low p-type impurity concentration exists in the p-type third semiconductor layer 126 located on the source electrode 32 side, so that when a positive voltage is applied to the gate electrode 30 , a higher voltage can be maintained between the gate electrode 30 and the source electrode 32 .

[0063] In the first embodiment described above, the first semiconductor layer 22, the second semiconductor layer 24, and the third semiconductor layer 26 extend linearly in the y direction. Figure 8 As shown in FIG. 1 , when the semiconductor layer 14 is viewed from above, the second semiconductor layer 24 has a meandering shape, and the first semiconductor layer 22 and the third semiconductor layer 26 are disposed on both sides of the second semiconductor layer 24. Fig. 9 As shown, when the semiconductor layer 14 is viewed from above, a plurality of second semiconductor layers 24 are arranged in a hollow rectangular shape, the first semiconductor layer 22 is arranged on the outer peripheral side of the second semiconductor layer 24, and the third semiconductor layer 26 is arranged on the inner peripheral side of the second semiconductor layer 24. According to these structures, the contact area between the first semiconductor layer 22 and the second semiconductor layer 24 and the contact area between the second semiconductor layer 24 and the third semiconductor layer 26 are increased, the resistance of the semiconductor layer 14 can be reduced, and the semiconductor layer 14 can be miniaturized. The same structure can also be applied to the second to fourth embodiments.

[0064] Furthermore, in each of the above-described embodiments, when the semiconductor substrate 12 is viewed from above, the semiconductor layers 14 and 114 are arranged in the peripheral region 62 sandwiched by the two element regions 60. However, the semiconductor layers 14 and 114 may be arranged in the peripheral region 62 between the element region 60 and the outer peripheral end of the semiconductor substrate 12, or may be arranged in the element region 60, for example.

[0065] In the above-mentioned embodiments, the impurity concentration of each semiconductor layer such as the first semiconductor layer 22 and 122 is not particularly limited. The impurity concentration can be appropriately selected according to the rated voltage of the transistor 20 and the like.

[0066] In the above-described embodiments, the band gap of the material constituting the semiconductor layers 14 and 114 is smaller than the band gap of the material constituting the semiconductor substrate 12 . However, for example, the semiconductor layers 14 and 114 may be made of the same material as the semiconductor substrate 12 .

[0067] In the above-mentioned embodiments, MOSFET is described as an example of the transistor 20. However, the transistor 20 may be, for example, an IGBT. In this modification, the low potential terminal and the high potential terminal are the emitter and the collector, respectively.

[0068] The above detailed description of the implementation methods is provided, but these are merely examples and do not limit the scope of the claims. The technology described in the scope of the claims includes various forms of deformation and modification of the specific examples illustrated above. The technical elements described in this specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having a device region where a transistor is formed; an interlayer insulating film provided on the semiconductor substrate; and A semiconductor layer is provided on the interlayer insulating film. The semiconductor layer has: A first semiconductor layer of a first conductivity type connected to the gate of the transistor; a second semiconductor layer of a second conductivity type connected to the first semiconductor layer; as well as The third semiconductor layer of the first conductivity type is connected to the second semiconductor layer and to the low potential terminal of the transistor.

2. The semiconductor device according to claim 1, wherein When the semiconductor substrate is viewed from above, the semiconductor substrate further includes a peripheral region arranged around the element region. The semiconductor layer is disposed in the peripheral region.

3. The semiconductor device according to claim 2, wherein: When the semiconductor substrate is viewed from above, the semiconductor layer is arranged in a range sandwiched between the two element regions.

4. The semiconductor device according to claim 1, wherein: The material constituting the semiconductor layer has a smaller band gap than the material constituting the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein The peak concentration of the first conductivity type impurity in the first semiconductor layer and the third semiconductor layer is 1×10 18 cm －3 above, The peak concentration of the second conductivity type impurity in the second semiconductor layer is 5×10 17 cm －3 the following.

6. The semiconductor device according to claim 1, wherein: The first conductivity type is n-type, and the second conductivity type is p-type. In the first semiconductor layer, a region in contact with the second semiconductor layer has an n-type impurity concentration lower than a region in contact with the gate electrode.

7. The semiconductor device according to claim 1, wherein The first conductivity type is p-type, and the second conductivity type is n-type. In the third semiconductor layer, a p-type impurity concentration in a region in contact with the second semiconductor layer is lower than a p-type impurity concentration in a region in contact with the low potential terminal.

8. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor substrate is composed of a wide bandgap semiconductor. The semiconductor layer is made of polycrystalline silicon.

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