Solar cell and preparation method and application thereof

Abstract

The invention discloses a solar cell and a preparation method and application thereof, and relates to the technical field of solar cells. P-type doped regions and N-type doped regions are alternately arranged on the back surface of the crystalline silicon substrate, a boron diffusion doped layer, a first passivation layer and a first antireflection layer are sequentially arranged in the P-type doped regions, and a phosphorus-doped silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, a second passivation layer and a second antireflection layer are sequentially arranged in the N-type doped regions from the surface of the crystalline silicon substrate. A traditional TBC battery P region mostly adopts a two-step process of intrinsic amorphous silicon deposition and boron diffusion to form a polycrystalline silicon layer, but the P region does not contain the polycrystalline silicon layer and can be prepared through a one-step boron diffusion process, so that the process steps can be reduced, and the process time can be shortened; and the action of laser and P-region polycrystalline silicon is avoided, the patterning difficulty of the battery is reduced, and the production yield of the battery can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell and a preparation method and application thereof. Background Art

[0002] TBC cells are a fusion of TOPCon and BC technologies. There is no metal electrode shading on the front, and the PN area on the back is passivated using a tunneling layer + poly layer structure. Compared with conventional PERC cells and TOPCon cells, TBC cells are more efficient, have a beautiful front, and are more suitable for distributed photovoltaic scenarios.

[0003] At present, the existing commercial TBC battery PN area adopts tunneling oxidation passivation contact technology, that is, the PN area is deposited with doped polysilicon thin film, which can greatly reduce the metal recombination of the battery and improve the open circuit voltage (Voc) and photoelectric conversion efficiency of the battery. However, the preparation process of TBC battery is relatively complicated, and the doping concentration and crystallization rate of doped polysilicon will change after being exposed to high-energy-density laser, which increases the difficulty of wet alkaline etching and patterning. Pattern defects are prone to occur during the preparation process, affecting the preparation yield of TBC battery.

[0004] Therefore, there is an urgent need to improve the structure and preparation process of TBC batteries to reduce the difficulty of graphics of TBC batteries and improve the production yield of TBC batteries.

[0005] In view of this, the present invention is proposed. Summary of the invention

[0006] The purpose of the present invention is to provide a solar cell and a preparation method and application thereof, aiming to reduce the difficulty of battery patterning and improve the production yield of the battery.

[0007] The present invention is achieved in that:

[0008] In a first aspect, the present invention provides a solar cell, comprising: a crystalline silicon substrate having a front side and a back side opposite to the front side;

[0009] P-type doped regions and N-type doped regions are alternately arranged on the back side of the crystalline silicon substrate;

[0010] In the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged on the surface of the self-crystalline silicon substrate;

[0011] The P-type doped region uses a boron diffusion doped layer as a PN junction, with a sheet resistance of 200Ω / sq-1000Ω / sq and a doping concentration of 7E17cm -3 -7E18cm -3 , junction depth is 0.3μm-1.0μm;

[0012] In the N-type doped region, an N-type doped layer, a second passivation layer and a second anti-reflection layer are sequentially arranged on the surface of the self-crystalline silicon substrate; the N-type doped layer in the N-type doped region includes a phosphorus-doped silicon oxide layer and a phosphorus-doped polysilicon layer which are sequentially arranged, and the phosphorus-doped polysilicon layer is located between the phosphorus-doped silicon oxide layer and the second passivation layer.

[0013] In an optional embodiment, the PN junction square resistance of the P-type doped region is 300Ω / sq-800Ω / sq, and the doping concentration is 1E18cm -3 -5E18cm -3 , the junction depth is 0.5μm-0.8μm;

[0014] Preferably, the P-type doped region is further provided with a first metal electrode, and the N-type doped region is further provided with a second metal electrode, the first metal electrode is in contact with the boron diffusion doped layer, and a hole and a conductive structure are provided on the contact surface between the first metal electrode and the boron diffusion doped layer, the conductive structure comprises a silver-silicon eutectic layer close to the boron diffusion doped layer and a conductive crystal extending from the silver-silicon eutectic layer toward the hole, the silver-silicon eutectic layer comprises a eutectic formed by silver element and silicon element, and the conductive crystal comprises a crystal formed by crystallization of the silver element;

[0015] More preferably, the conductive crystal includes a crystalline main chain and crystalline side chains extending from the crystalline main chain in a growth direction different from that of the crystalline main chain.

[0016] In an optional embodiment, an isolation trench is provided between adjacent P-type doping regions and N-type doping regions;

[0017] In the area where the isolation trench is located, a third passivation layer and a third anti-reflection layer are sequentially arranged on the surface of the self-crystalline silicon substrate;

[0018] Preferably, the distance between the phosphorus-doped silicon oxide layer and the front surface of the crystalline silicon substrate is smaller than the distance between the boron diffusion doping layer and the front surface of the crystalline silicon substrate, and the distance between the second anti-reflection layer and the front surface of the crystalline silicon substrate is smaller than the distance between the first anti-reflection layer and the front surface of the crystalline silicon substrate, so that there is a height difference between the P-type doped region and the N-type doped region at the end away from the front surface of the crystalline silicon substrate; more preferably, the height difference is 0.5 μm-5.0 μm;

[0019] Preferably, the boron diffusion doping junction depth of the P-type doping region is 0.3 μm-1.0 μm, the thickness of the phosphorus-doped silicon oxide layer is 0.5 nm-3.0 nm, and the thickness of the phosphorus-doped polysilicon layer is 50 nm-300 nm.

[0020] In an optional embodiment, the crystalline silicon substrate is N-type single crystal silicon, the N-type doped region and the crystalline silicon substrate form a high-low junction, the square resistance of the high-low junction is 10Ω / sq-100Ω / sq, and the doping concentration is 1E20cm-3 -9E20cm -3 , the junction depth is 0.07μm-0.5μm, and the inner expansion depth under the silicon substrate is 0.02μm-0.1μm;

[0021] Preferably, the high and low junction square resistance of the N-type doped region is 10Ω / sq-50Ω / sq, and the doping concentration is 2-6E20cm -3 The junction depth is 0.1μm-0.4μm, and the inner expansion depth under the silicon substrate is 0.03μm-0.08μm.

[0022] In an optional embodiment, the width of the P-type doping region is 200 μm-1000 μm, and the width of the N-type doping region is 200 μm-1000 μm;

[0023] Preferably, the area ratio of the P-type doping region to the N-type doping region is (0.5-2.0):1, preferably (0.8-1.2):1;

[0024] Preferably, the width of the isolation trench is 50 μm-200 μm, and the depth of the isolation trench is 0.5 μm-5.0 μm;

[0025] Preferably, the distance between two adjacent N-type doped regions is 0.5 mm to 2.0 mm;

[0026] Preferably, the silicon substrate corresponding to the P-type doped region, the N-type doped region and the isolation trench are all planar structures or velvet structures, and the pyramid base size of the velvet structure is 1 μm-5 μm, and the pyramid height is 0.5 μm-2.0 μm.

[0027] In an optional embodiment, the first metal electrode of the P-type doped region includes a plurality of first sub-gate electrodes and a first main gate electrode for connecting the plurality of first sub-gate electrodes, and the second metal electrode on the N-type doped region includes a plurality of second sub-gate electrodes and a second main gate electrode for connecting the plurality of second sub-gate electrodes;

[0028] Preferably, each first sub-gate electrode intersects the first main gate electrode perpendicularly and is connected through the first main gate electrode; each second sub-gate electrode intersects the second main gate electrode perpendicularly and is connected through the second main gate electrode.

[0029] In an optional embodiment, on the front side of the crystalline silicon substrate, a front side passivation layer and a front side anti-reflection layer are sequentially provided on the surface of the crystalline silicon substrate;

[0030] Preferably, the materials of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently selected from at least one of Al2O3 and SiO2;

[0031] Preferably, the materials of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are independently selected from SiNx and SiO x N y At least one of;

[0032] Preferably, the thickness of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently 2nm-5nm;

[0033] Preferably, the thickness of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are independently 70nm-100nm;

[0034] Preferably, the thickness of the crystalline silicon substrate is 100 μm-150 nm.

[0035] In a second aspect, the present invention provides a method for preparing a solar cell according to any one of the aforementioned embodiments, comprising:

[0036] Providing a crystalline silicon substrate, wherein the crystalline silicon substrate has a front side and a back side opposite to the front side;

[0037] A P-type doped region and an N-type doped region are formed alternately on the back of the crystalline silicon substrate; and in the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate, and the P-type doped region uses the boron diffusion doped layer as a PN junction, with a sheet resistance of 200Ω / sq-1000Ω / sq and a doping concentration of 7E17cm -3 -7E18cm -3 , junction depth is 0.3μm-1.0μm;

[0038] In the N-type doped region, a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer, a second passivation layer and a second anti-reflection layer are sequentially arranged on the surface of the self-crystalline silicon substrate.

[0039] In an optional embodiment, the method includes: forming an isolation trench on the back side of the crystalline silicon substrate, using the isolation trench to separate the back side of the crystalline silicon substrate into P-type doped regions and N-type doped regions that are alternately arranged, and forming a functional layer on each region on the back side of the crystalline silicon substrate and on the front side of the crystalline silicon substrate, thereby obtaining an intermediate film layer having a functional layer;

[0040] A plurality of first auxiliary gate electrodes and at least one first main gate electrode are prepared in the P-type doping region of the intermediate film layer, and a plurality of second auxiliary gate electrodes and at least one second main gate electrode are prepared in the N-type doping region, and laser induced sintering is performed after a complete cell structure is formed;

[0041] Preferably, the laser induced sintering process includes: applying a reverse bias voltage to the main grid of the battery cell to form a loop, and then performing laser scanning on at least the P-type doped area; controlling the reverse bias voltage to 10V-50V, the applied laser power to 20W-120W, and the laser scanning rate to 50mm / s-500mm / s.

[0042] In an optional embodiment, a first probe row is used to press each first main gate electrode on the P-type doped region, a second probe row is used to press each second main gate electrode on the N-type doped region, and the first probe row and the second probe row are used to apply a reverse bias to each main gate to form a loop, and laser induced sintering is performed on at least the P-type doped region.

[0043] In an optional embodiment, in the region where the isolation trench is located, a third passivation layer and a third anti-reflection layer are sequentially disposed on the surface of the self-crystalline silicon substrate;

[0044] The preparation process of the intermediate film layer includes:

[0045] A boron diffusion doping layer, a phosphorus doped silicon oxide layer and a phosphorus doped polysilicon layer are formed on the back side of the crystalline silicon substrate, and at the same time, by forming an intermediate protective layer and partially opening and removing the film, only the boron diffusion doping layer is retained in the P-type doping area, and only the phosphorus doped silicon oxide layer and the phosphorus doped polysilicon layer are retained in the N-type doping area, and a hollow groove area is formed between the P-type doping area and the N-type doping area;

[0046] A passivation layer and an anti-reflection layer corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region on the back of the crystalline silicon substrate; a front passivation layer and a front anti-reflection layer are formed on the front of the crystalline silicon substrate.

[0047] In an optional embodiment, the process of forming the hollow groove region includes: pre-processing the back side of the crystalline silicon substrate, sequentially forming a boron diffusion doping layer and a borosilicate glass layer on the back side of the crystalline silicon substrate, locally opening the film using a laser, removing the local borosilicate glass layer using a laser, and removing the boron diffusion doping layer in the laser region using an alkali etching method, wherein the width of the film opening is equal to the sum of an N-type doping region and two isolation trench regions, and the etching depth is deep into the crystalline silicon substrate;

[0048] forming a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer and a phosphorus-silicate glass layer in sequence on the entire back side of the crystalline silicon substrate;

[0049] The laser is used to perform local film opening to remove the phosphorus silicon glass layer on the P-type doped area, and the width of the film opening is greater than the width of the P-type doped area, and the difference between the width of the film opening and the width of the P-type doped area is 50μm-200μm;

[0050] The front side of the crystalline silicon substrate is subjected to acid etching and groove texturing treatment, so that the area protected by the borosilicate glass layer and the phosphosilicate glass layer is not etched, and then all the borosilicate glass layers and the phosphosilicate glass layers on the back side are removed by etching, so that only the boron diffusion doping layer is retained in the P-type doping area, and only the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer are retained in the N-type doping area, and a hollow groove area is formed between the P-type doping area and the N-type doping area, and the width of the hollow groove area is 50μm-200μm;

[0051] Preferably, the pre-treatment is to prepare a polished surface or a velvet surface;

[0052] Preferably, the crystalline silicon substrate is single-sidedly doped with boron by high-temperature boron diffusion, and the diffusion temperature is controlled to be 980° C.-1050° C. to form a boron diffusion doping layer;

[0053] Preferably, the thickness of the formed borosilicate glass layer is 20nm-100nm, and the thickness of the formed phosphosilicate glass layer is 20nm-80nm;

[0054] Preferably, the process of forming the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer comprises: forming a tunneling silicon oxide layer with a thickness of 1nm-3nm and an intrinsic amorphous silicon film with a thickness of 50nm-300nm by chemical vapor deposition, and then performing high-temperature phosphorus diffusion, controlling the diffusion temperature to be 800°C-900°C;

[0055] Preferably, the phosphorus-doped polysilicon layer is formed by plasma enhanced chemical vapor deposition and annealing.

[0056] In an optional embodiment, the first sub-gate electrode, the second sub-gate electrode, the first main gate electrode and the second main gate electrode are prepared by screen printing;

[0057] Preferably, the process of preparing the secondary gate electrode and the main gate electrode comprises:

[0058] Prepare a first auxiliary grid slurry, a second auxiliary grid slurry, a first main grid slurry and a second main grid slurry;

[0059] Printing a first auxiliary grid paste, a second auxiliary grid paste, a first main grid paste and a second main grid paste on the intermediate film layer respectively;

[0060] The cell after printing the slurry is sintered and light injected, and the sintering temperature is controlled at 700℃-800℃.

[0061] In a third aspect, the present invention provides a photovoltaic module, comprising the solar cell according to any one of the aforementioned embodiments or a solar cell prepared by any one of the preparation methods according to the aforementioned embodiments.

[0062] The present invention has the following beneficial effects: a P-type doped region and an N-type doped region are alternately arranged on the back of a crystalline silicon substrate, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged in the P-type doped region, and a phosphorus doped silicon oxide layer, a phosphorus doped polysilicon layer, a second passivation layer and a second anti-reflection layer are sequentially arranged on the surface of the N-type doped region from the crystalline silicon substrate. The traditional TBC cell P region mostly adopts a two-step process of depositing intrinsic amorphous silicon + boron diffusion to form a polysilicon layer, while the P region of the present invention does not contain a polysilicon layer and can be prepared by a one-step boron diffusion process, which can reduce the process steps and process time; it also avoids the effect of laser and polysilicon in the P region, reduces the difficulty of battery patterning, and can greatly improve the production yield of the battery.

[0063] It should be added that the sheet resistance of the boron diffusion doping layer of the traditional BC battery is relatively small, and the boron diffusion doping layer of the P-type doping area in the present invention is significantly different from the boron diffusion doping layer of the traditional BC battery in terms of sheet resistance. Generally speaking, the traditional BC battery directly performs boron diffusion on the silicon substrate, which often has a high doping concentration and a deep diffusion junction depth, which will change the arrangement of crystalline silicon, cause lattice distortion defects, and a large recombination of carriers, thereby affecting the performance of the battery. The present invention optimizes the preparation process of the P region of the TBC battery, directly performs boron diffusion on the crystalline silicon substrate to form a PN junction and cooperates with the laser induced sintering process (LIF), without the need for high doping concentration and deep diffusion junction depth, thereby avoiding the problem of silicon lattice distortion and disordered arrangement caused by excessive doping concentration in the non-metallic region of the P region, while ensuring the metal contact performance of the P region, effectively reducing the carrier recombination in the non-metallic region of the P region, which is beneficial to improving the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A schematic diagram of the structure of a solar cell provided by an embodiment of the present invention;

[0066] Figure 2 for Figure 1 A schematic diagram of a conductive structure generated at the contact between the first metal electrode and the boron diffusion doped layer;

[0067] Figure 3 for Figure 2 A magnified view of the conductive structure;

[0068] Figure 4A schematic diagram of a crystalline silicon substrate provided in an embodiment of the present invention;

[0069] Figure 5 It is a schematic diagram after forming a boron diffusion doping layer and a borosilicate glass layer on a crystalline silicon substrate;

[0070] Figure 6 For Figure 5 Schematic diagram of laser film opening to remove local boron diffusion doping layer and borosilicate glass layer;

[0071] Figure 7 For Figure 6 Schematic diagram after a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer and a phosphorus-silicate glass layer are formed on the base;

[0072] Figure 8 For Figure 7 Schematic diagram of using laser to perform local film opening to remove the phosphorus silicon glass layer on the P-type doped area;

[0073] Fig. 9 For Figure 8 Schematic diagram of the base after acid etching and slot texturing;

[0074] Fig.10 For Fig. 9 Schematic diagram after forming a passivation layer and an anti-reflection layer on the base;

[0075] Fig.11 For Fig.10 Schematic diagram after preparing the main gate electrode and the auxiliary gate electrode on the basis;

[0076] Fig.12 For Fig.11 Schematic diagram of laser-induced sintering on the basis of.

[0077] Explanation of the main component symbols: 1-crystalline silicon substrate; 2-boron diffusion doped layer; 3-borosilicate glass layer; 4-phosphorus doped silicon oxide layer; 5-phosphorus doped polysilicon layer; 6-phosphorus silicon glass layer; 7-passivation layer; 8-anti-reflection layer; 9-first sub-gate electrode; 10-second sub-gate electrode; 11-first main gate electrode; 12-second main gate electrode; 13-first probe row; 14-second probe row; 15-hole; 16-conductive structure; 161-silver silicon eutectic layer; 162-conductive crystal; 1621-crystalline main chain; 1622-crystalline side chain. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be described clearly and completely below. If the specific conditions are not specified in the embodiments, they are carried out according to conventional conditions or conditions recommended by the manufacturer. If the manufacturer of the reagents or instruments used is not specified, they are all conventional products that can be purchased commercially.

[0079] The P region of existing TBC cells mostly adopts a two-step process of depositing intrinsic amorphous silicon + boron diffusion to form a polysilicon layer, and the preparation process is complicated. After the doped polysilicon is exposed to high-energy-density lasers, the doping concentration and crystallization rate will change, increasing the difficulty of wet alkaline etching and patterning. Pattern defects are prone to occur during the preparation process, affecting the preparation yield of TBC cells.

[0080] In order to solve the above technical problems, the inventors optimized the structure and preparation process of the P region of the TBC battery, and directly prepared a boron diffusion doping layer on the crystalline silicon substrate to form a PN junction, avoiding the interaction between the laser and the P region polysilicon, reducing the difficulty of battery graphics, and greatly improving the production yield of the battery.

[0081] like Figure 1 As shown, the present invention provides a solar cell, comprising: a crystalline silicon substrate 1, the crystalline silicon substrate 1 having a front side and a back side opposite to the front side; P-type doped regions (P regions) and N-type doped regions (N regions) are alternately arranged on the back side of the crystalline silicon substrate 1, and isolation trenches are arranged between adjacent P-type doped regions and N-type doped regions.

[0082] In the P-type doped region, a boron diffusion doped layer 2, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged on the surface of the crystalline silicon substrate 1. Compared with the traditional P region, it does not contain a polysilicon layer, which not only reduces the process steps, but also avoids the effect of laser and polysilicon in the P region, reduces the difficulty of battery patterning, and can greatly improve the production yield of the battery. Specifically, the passivation layer 7 in the P-type doped region is also called the first passivation layer, and the anti-reflection layer 8 is also called the first anti-reflection layer.

[0083] In some embodiments, in the N-type doped region, an N-type doped layer, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged on the surface of the self-crystalline silicon substrate 1. Specifically, the N-type doped layer is doped with phosphorus, and the specific structure can refer to the existing N-region structure. The passivation layer 7 of the N-type doped region is also called the second passivation layer, and the anti-reflection layer 8 is also called the second anti-reflection layer. In some embodiments, the N-type doped layer of the N-type doped region includes a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5 that are sequentially arranged, and the phosphorus-doped polysilicon layer 5 is located between the phosphorus-doped silicon oxide layer 4 and the second passivation layer 7.

[0084] In some embodiments, in the area where the isolation trench is located, the surface of the self-crystalline silicon substrate 1 is sequentially provided with a passivation layer 7 and an anti-reflection layer 8. The passivation layer 7 at the isolation trench is also called a third passivation layer, and the anti-reflection layer 8 at the isolation trench is also called a third anti-reflection layer.

[0085] In some embodiments, on the front side of the crystalline silicon substrate 1, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged on the surface of the crystalline silicon substrate 1. The front passivation layer 7 is also called a front passivation layer, and the front anti-reflection layer 8 is also called a front anti-reflection layer.

[0086] In some embodiments, the width of the P-type doped region is 200 μm-1000 μm, such as 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc. The width of the N-type doped region is 200 μm-1000 μm, such as 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc. Specifically, the width direction and length direction of the P-type doped region can refer to the width and length directions of the crystalline silicon substrate 1, such as Figure 1 What is shown may be the width direction and the thickness direction, but the length direction is not shown.

[0087] Further, the area ratio of the P-type doping region and the N-type doping region is (0.5-2.0):1, such as 0.5:1, 0.8:1, 1.0:1, 1.2:1, 1.5:1, 1.8:1, 2.0:1, etc., preferably (0.8-1.2):1, the area ratio of the P-type doping region and the N-type doping region can be controlled within the above range, and the area ratio of the two can be controlled according to the process requirements, and a high-efficiency solar cell can be prepared. Specifically, the area of ​​the P-type doping region and the N-type doping region is calculated by the product of the length and the width.

[0088] Furthermore, the width of the isolation trench is 50 μm-200 μm, such as 50 μm, 100 μm, 150 μm, 200 μm, etc.; the depth of the isolation trench is 0.5 μm-5.0 μm, such as 0.5 μm, 1.0 μm, 2.0 μm, 3.0 μm, 4.0 μm, 5.0 μm, etc. Figure 1The horizontal direction may be the width direction, which is consistent with the width direction of the P-type doping region and the N-type doping region; the depth of the isolation trench refers to the height difference between the isolation trench and the N-type doping region at the end away from the front surface of the crystalline silicon substrate 1. The spacing between two adjacent N-type doping regions is 0.5mm-2.0mm, such as 0.5μm, 1.0μm, 1.5μm, 2.0μm, etc. The P-type doping region and the N-type doping region are equally spaced on the battery, and the spacing may be 0.5mm-2.0mm.

[0089] In some embodiments, the P-type doped region uses the boron diffusion doped layer 2 as a PN junction, the square resistance is 200Ω / sq-1000Ω / sq, and the doping concentration is 7E17cm -3 -7E18cm -3 , the junction depth is 0.3μm-1.0μm; preferably, the PN junction square resistance of the P-type doped region is 300Ω / sq-800Ω / sq, and the doping concentration is 1E18cm -3 -5E18cm -3 The junction depth is 0.5μm-0.8μm. By optimizing the block resistance, doping concentration and junction depth, it is beneficial to further reduce the surface recombination of the non-metallic area of ​​the P area and improve the efficiency of the battery.

[0090] Specifically, the square resistance of the PN junction in the P-type doped region can be 200Ω / sq, 300Ω / sq, 400Ω / sq, 600Ω / sq, 800Ω / sq, 1000Ω / sq, etc.; the junction depth can be 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, etc.

[0091] In some embodiments, the crystalline silicon substrate 1 is N-type single crystal silicon, and the N-type doped region and the crystalline silicon substrate 1 are doped with phosphorus of different concentrations to form a high-low junction, the square resistance of the high-low junction is 10Ω / sq-100Ω / sq, and the doping concentration is 1E20cm -3 -9E20cm -3 , the junction depth is 0.07μm-0.5μm, and the inner expansion depth under the silicon substrate is 0.02μm-0.1μm; preferably, the high and low junction square resistance of the N-type doped region is 10Ω / sq-50Ω / sq, and the doping concentration is 2E20cm -3 -6E20cm -3 , the junction depth is 0.1μm-0.4μm, and the inner expansion depth under the silicon substrate is 0.03μm-0.08μm. By optimizing the square resistance, doping concentration, junction depth, inner expansion depth and other parameters of the high and low junctions in the N-type doped area, it is beneficial to further improve the field passivation of the non-metallic area of ​​the N region, reduce the metal recombination of the metal area of ​​the N region, and improve the efficiency of the battery.

[0092] Specifically, the high and low junction square resistance of the N-type doped region can be 10Ω / sq, 30Ω / sq, 50Ω / sq, 80Ω / sq, 100Ω / sq, etc.; the doping concentration can be 1E20cm -3 、2E20cm -3 、5E20cm -3 、6E20cm -3 、9E20cm -3 etc.; the junction depth can be 0.07μm, 0.10μm, 0.20μm, 0.30μm, 0.40μm, 0.50μm, etc.; the inner expansion depth under the silicon substrate can be 0.02μm, 0.03μm, 0.05μm, 0.08μm, 0.10μm, etc.

[0093] like Figure 1 As shown, in some embodiments, the distance between the phosphorus-doped silicon oxide layer 4 and the front surface of the crystalline silicon substrate 1 is smaller than the distance between the boron diffusion doping layer 2 and the front surface of the crystalline silicon substrate 1, and the distance between the second anti-reflection layer and the front surface of the crystalline silicon substrate 1 is smaller than the distance between the first anti-reflection layer and the front surface of the crystalline silicon substrate 1, so that there is a height difference between the P-type doped region and the N-type doped region at the end away from the front surface of the crystalline silicon substrate 1, and this height difference is formed by the complete removal of the boron doped layer by wet etching after laser patterning and the laser damage process. In a preferred embodiment, the height difference is 0.5μm-5.0μm, such as 0.5μm, 1.0μm, 2.0μm, 3.0μm, 4.0μm, 5.0μm, etc.

[0094] Furthermore, the thickness of the crystalline silicon substrate 1 is 100μm-150μm (such as 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, etc.), the junction depth of the boron diffusion doped layer 2 is 0.3μm-1μm (such as 0.3μm, 0.5μm, 0.8μm, 1.0μm, etc.), the thickness of the phosphorus-doped silicon oxide layer 4 is 0.5nm-3.0nm (such as 0.5nm, 1.0nm, 2.0nm, 3.0nm, etc.), and the thickness of the phosphorus-doped polysilicon layer 5 is 50nm-300nm (such as 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.).

[0095] Further, the thickness of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently 2nm-5nm (such as 2nm, 3nm, 4nm, 5nm, etc.), and the thickness of the passivation layer in each region may be the same or different. Similarly, the thickness of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are independently 70nm-100nm (such as 70nm, 80nm, 90nm, 100nm, etc.), and the thickness of the anti-reflection layer in each region may be the same or different.

[0096] Furthermore, the material of the passivation layer 7 of each region is independently selected from at least one of Al2O3 and SiO2, and the material of the passivation layer 7 of each region may be the same or different, preferably the same material, prepared by the same process.

[0097] Furthermore, the material of the anti-reflection layer 8 in each region is independently selected from SiN x and SiO x N y At least one of the anti-reflection layers 8 in each region may be made of the same material or different materials, preferably the same material and prepared by the same process.

[0098] It should be noted that the P-type doped region can be a planar structure or a velvet structure, wherein the pyramid base size of the velvet structure is 1-5μm, and the tower height is 0.5-2μm; the N-type doped region is a planar or velvet structure, wherein the pyramid base size of the velvet structure is 1-5μm, and the tower height is 0.5-2μm, and the isolation groove region is a planar or velvet structure, wherein the pyramid base size of the velvet structure is 1-5μm, and the tower height is 0.5-2μm.

[0099] In some embodiments, the solar cell further includes a first metal electrode and a second metal electrode, the first metal electrode is disposed in the first type doping region, and the second metal electrode is disposed in the N-type doping region. The first metal electrode and the second metal electrode can be silver electrodes, and their introduction can refer to the description of the preparation method section.

[0100] In some embodiments, the first metal electrode and the second metal electrode each include a main gate electrode and a sub-gate electrode. Figure 1 Only the first sub-gate electrode 9 and the second sub-gate electrode 10 are shown.

[0101] like Figure 2 As shown, the first metal electrode is in contact with the boron diffusion doped layer 2, and there are holes 15 and a conductive structure 16 on the contact surface between the first metal electrode and the boron diffusion doped layer 2. The conductive structure 16 includes a silver-silicon eutectic layer 161 close to the boron diffusion doped layer and a conductive crystal 162 extending from the silver-silicon eutectic layer 161 toward the hole 15.

[0102] Specifically, since the silver-silicon eutectic layer 161 includes a eutectic formed by a metal element (such as silver) in a metal electrode and a semiconductor element (Si), it is not only beneficial for carriers to be transported from the substrate of the solar cell to the boron diffusion doping layer 2, but also has a lower contact resistance than the non-eutectic contact between metal particles and semiconductor materials. Since the silver-silicon eutectic layer is a eutectic formed by silver and silicon elements, it has a lower resistivity and better conductivity than the direct contact between nano silver powder and the silicon layer, that is, the non-eutectic contact. The contact resistivity of the silver-silicon eutectic layer 161 is 0.1-2mΩ.cm 2 (For example, it can be 0.1Ω.cm 2 、0.5Ω.cm 2 、1.0Ω.cm 2 、1.5Ω.cm 2 , 2.0Ω.cm 2 The present invention forms a silver-silicon alloy layer with low contact resistivity between the doping layer and the metal electrode by laser-induced sintering and loading a reverse bias voltage.

[0103] It should be noted that the principle of forming the silver-silicon eutectic layer 161 during the laser induced sintering process is as follows: laser irradiation generates photogenerated carriers, which gather at the position of the fine grid under the action of reverse bias, and the carriers are transmitted along the path with the highest conductivity. A point with a diameter of about 300nm-500nm appears on the fine grid. The instantaneous temperature can reach above 1000°C (exceeding the melting point of silicon material), melting the silver atoms in the slurry at high temperature, and then diffuse into the crystalline silicon material to form a silver-silicon alloy. The formed silver-silicon alloy has very high conductivity.

[0104] At the same time, the conductive crystals 162 growing from the silver-silicon eutectic layer 161 toward the hole 15 include crystals formed by crystallization of metal elements (such as silver). Compared with the structure in which metal particles are in contact with semiconductor materials, the conductive crystals 162 formed by the crystallization of such metal elements have higher purity, lower resistivity, and better carrier transmission capability. The presence of such high-purity conductive crystals 162 in the hole 15 can further reduce the loss of carriers transported from the silver-silicon eutectic layer 161 to the first metal electrode on the basis of reducing the contact resistance between the first metal electrode and the boron diffusion doping layer 2 by the silver-silicon eutectic layer 161, thereby optimizing the contact performance between the first metal electrode and the boron diffusion doping layer 2 through the cooperation of the silver-silicon eutectic layer 161 and the conductive crystals 162 located in the hole 15, thereby improving the performance indicators of the solar cell such as the series resistance, short-circuit current, and photoelectric conversion efficiency.

[0105] Furthermore, if Figure 2 and Figure 3As shown, the conductive crystal 162 includes a crystalline main chain 1621 and a crystalline side chain 1622 extending from the crystalline main chain 1621 in a growth direction different from the crystalline main chain 1621. In the embodiment of the present invention, the crystalline main chain 1621 and the crystalline side chain 1622 growing laterally from the crystalline main chain 1621 make the conductive crystal 162 present a tree-like structure as a whole. Compared with the conductive crystal 162 that only grows and crystallizes in a single direction (for example, a rod-shaped conductive crystal 162), the tree-like conductive crystal 162 can provide more transport channels for carriers from the boron diffusion doping layer 2, and because the conductive crystal 162 is usually composed of silver particle crystals with higher purity, it has a higher conductivity and is more conducive to reducing the transport loss of carriers.

[0106] An embodiment of the present invention provides a method for preparing a solar cell, comprising the following steps:

[0107] S1. Provide a crystalline silicon substrate 1

[0108] like Figure 4 As shown, a crystalline silicon substrate 1 is provided, the crystalline silicon substrate 1 has a front side and a back side opposite to the front side, and the back side is used to prepare a PN region. The crystalline silicon substrate 1 can be N-type single crystal silicon, and the resistivity of the silicon wafer is greater than 2Ω.cm.

[0109] In some embodiments, the pre-treatment of the crystalline silicon substrate 1 may be to prepare a polished surface. Specifically, an alkaline solution may be used to perform polishing loss treatment on the silicon wafer.

[0110] In another embodiment, the crystalline silicon substrate 1 is pre-treated to prepare a velvet surface. Specifically, the silicon wafer may be velvet treated with additives to make the P-type doped area velvet. The pyramid base size of the velvet structure is 1 μm-5 μm (such as 1 μm, 2 μm, 3 μm, 4 μm, 5 μm), and the tower height is 0.5 μm-2.0 μm (such as 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, etc.).

[0111] It should be noted that in addition to the polished morphology, the high square resistance area of ​​the P zone can also adopt a velvet structure to improve the bifaciality of the battery.

[0112] S2. Preparation of an intermediate film layer with a functional layer

[0113] Alternating P-type doped regions and N-type doped regions are formed on the back side of the crystalline silicon substrate 1, isolation trenches are formed between adjacent P-type doped regions and N-type doped regions, and functional layers are formed in various regions on the back side of the crystalline silicon substrate 1 and on the front side of the crystalline silicon substrate 1 to obtain an intermediate film layer with a functional layer.

[0114] like Figure 1As shown, in the P-type doping region, a boron diffusion doping layer 2, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the self-crystalline silicon substrate 1; in the N-type doping region, an N-type doping layer, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the self-crystalline silicon substrate 1; in the region where the isolation trench is located, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the self-crystalline silicon substrate 1. The N-type doping layer in the N-type doping region includes a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5 arranged in sequence, and the phosphorus-doped polysilicon layer 5 is located between the silicon oxide layer and the second passivation layer 7. The thickness and parameters of each functional layer can refer to the description of the solar cell in the specification, and will not be repeated here.

[0115] The preparation process of the intermediate film layer includes: Figure 4-Figure 10 A boron diffusion doping layer 2, a phosphorus doped silicon oxide layer 4 and a phosphorus doped polysilicon layer 5 are formed on the back of the crystalline silicon substrate 1. At the same time, by forming an intermediate protective layer and partially opening and removing the film, only the boron diffusion doping layer 2 is retained in the P-type doping area, and only the phosphorus doped silicon oxide layer 4 and the phosphorus doped polysilicon layer 5 are retained in the N-type doping area. A hollow groove area is formed between the P-type doping area and the N-type doping area (structure as shown in FIG. Fig. 9 As shown in Fig.10 As shown, a passivation layer 7 and an anti-reflection layer 8 corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region on the back side of the crystalline silicon substrate 1; and a passivation layer 7 and an anti-reflection layer 8 are formed on the front side of the crystalline silicon substrate 1.

[0116] Figure 4-Figure 10 The process of preparing the intermediate film layer is shown, which includes the following steps:

[0117] (1) Figure 5 As shown, a boron diffusion doping layer 2 and a borosilicate glass layer 3 (BSG) are sequentially formed on the back of the crystalline silicon substrate 1, and the borosilicate glass layer 3 is used as a protective layer later. The boron diffusion doping layer 2 can be prepared by single-sided boron doping of the crystalline silicon substrate 1 by high-temperature boron diffusion, and the diffusion temperature is controlled to be 980°C-1050°C, such as 980°C, 1000°C, 1020°C, 1050°C, etc. The borosilicate glass layer 3 can be prepared by diffusion, and the thickness of the borosilicate glass layer 3 is controlled to be 20nm-100nm, such as 20nm, 50nm, 80nm, 100nm, etc.

[0118] It should be noted that the P region of the battery adopts high-square-resistance low-composite boron diffusion instead of LPCVD+boron doping, which reduces the process steps and time, thereby reducing costs; the P region adopts high-square-resistance boron diffusion, which is better matched with laser and wet methods than boron doping, and avoids the problem that the polysilicon in the P region is difficult to remove by alkaline etching due to the effect of laser, and the difficulty of patterning is greatly reduced.

[0119] (2) Figure 6 As shown, laser is used for local film opening, and the film opening width is 200μm-1000μm, and the width of the film opening is equal to the sum of an N-type doped region and two isolation groove regions, and the etching depth is made to penetrate into the crystalline silicon substrate 1, and the film opening width is specifically obtained according to the width of the P region and the N region. The laser can be a picosecond (ps) or nanosecond (ns) pulse laser, and the purpose is to remove the local BSG; then the boron diffusion doping layer 2 in the laser region is removed by groove wet alkali etching, and the silicon wafer is cleaned.

[0120] (3) Figure 7 As shown, a phosphorus-doped silicon oxide layer 4, a phosphorus-doped polysilicon layer 5 and a phosphorus-silicate glass layer 6 are sequentially formed on the entire back side of the crystalline silicon substrate 1. In actual operation, a 1nm-3nm tunneling silicon oxide (SiO2) and a 50nm-300nm intrinsic amorphous silicon film can be sequentially generated on the boron-doped plane by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), and then the silicon wafer is phosphorus-doped by high-temperature phosphorus diffusion, and the diffusion temperature is 800℃-900℃. Afterwards, a phosphorus-silicate glass layer 6 (PSG) is formed on the surface, and the PSG thickness is 20-80nm.

[0121] Specifically, the thickness of the tunneling silicon oxide (SiO2) can be 1 nm, 2 nm, 3 nm, etc., the thickness of the intrinsic amorphous silicon film can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc., and the phosphorus diffusion temperature can be 800° C., 850° C., 900° C., etc. The preparation method of the phosphosilicate glass layer 6 (PSG) is not limited, and can be an existing preparation method, such as generating PSG by diffusion, and the thickness of the PSG can be controlled to be 20 nm, 40 nm, 60 nm, 80 nm, etc.

[0122] In a preferred embodiment, the phosphorus-doped polysilicon layer 5 may be formed by plasma enhanced chemical vapor deposition and annealing, which is simpler to operate than low pressure chemical vapor deposition.

[0123] (4) Figure 8 As shown, laser is used to perform local film opening to remove the phosphosilicate glass layer 6 on the P-type doped area, and the film opening width is greater than the width of the P-type doped area. The difference between the film opening width and the width of the P-type doped area is 50μm-200μm, such as 50μm, 100μm, 150μm, 200μm, etc.

[0124] That is to say, the film opening width is 50μm-200μm wider than the P region, and the width of the isolation grooves on both sides needs to be reserved during the film opening process. The film opening size is determined according to the preset widths of the two doping regions, so that the area ratio of the first type doping region to the N-type doping region is in the range of 0.5-2, preferably 0.8-1.2.

[0125] Specifically, the laser may be a picosecond (ps) or nanosecond (ns) pulse laser, the purpose of which is to remove excess PSG film above the P region.

[0126] (5) Fig. 9 As shown, the front side of the crystalline silicon substrate 1 is subjected to chain acid etching and groove texturing, while the P-type doped area and the N-type doped area on the back side are protected by BSG and PSG respectively and will not be etched, while the n-poly layer in the area between the P and N junctions without PSG protection is etched to form a section containing only the silicon substrate, the width of which is 50μm-200μm; then, a groove HF solution is used to remove all BSG and PSG on the back side, and the silicon wafer is cleaned. Only the boron diffusion doped layer 2 is retained in the P-type doped area, and only the phosphorus doped silicon oxide layer 4 and the phosphorus doped polysilicon layer 5 are retained in the N-type doped area, and a hollow groove area is formed between the P-type doped area and the N-type doped area, the width of which is 50μm-200μm.

[0127] (6) Fig.10 As shown, a passivation layer 7 (including a first passivation layer, a second passivation layer and a third passivation layer) and an anti-reflection layer 8 (including a first anti-reflection layer, a second anti-reflection layer and a third anti-reflection layer) corresponding to each region are formed in the P-type doped region, the N-type doped region and the hollow groove region on the back side of the crystalline silicon substrate 1; a passivation layer 7 (front passivation layer) and an anti-reflection layer 8 (front anti-reflection layer) are also formed on the front side of the crystalline silicon substrate 1.

[0128] Specifically, the passivation layer 7 may be an aluminum oxide (AlOx) thin film, and the anti-reflection layer 8 may be a silicon nitride (SiNx) thin film, but is not limited thereto.

[0129] S3. Preparation of main gate electrode and auxiliary gate electrode

[0130] like Fig.11 and Fig.12 As shown, a main gate electrode and a secondary gate electrode are prepared on the intermediate film layer to form a complete battery structure.

[0131] In some embodiments, a plurality of first sub-gate electrodes 9 and at least one first main gate electrode 11 are prepared on the P-type doped region of the intermediate film layer, a first sub-gate electrode 9 is correspondingly arranged on each P-type doped region, and the number of first main gate electrodes 11 is not limited. A plurality of second sub-gate electrodes 10 and at least one second main gate electrode 12 are prepared on the N-type doped region, a second sub-gate electrode 10 is correspondingly arranged on each N-type doped region, and the number of second main gate electrodes 12 is not limited.

[0132] Specifically, the first main gate electrode 11 is used to connect a plurality of first sub-gate electrodes 9, each of which intersects the first main gate electrode 11 perpendicularly and is connected through the first main gate electrode 11. The second main gate electrode 12 is used to connect a plurality of second sub-gate electrodes 10, each of which intersects the second main gate electrode 12 perpendicularly and is connected through the second main gate electrode 12.

[0133] Furthermore, the first sub-grid electrode 9, the second sub-grid electrode 10, the first main grid electrode 11 and the second main grid electrode 12 can be prepared by screen printing, but it is not limited thereto. When the preparation is performed by screen printing, the following steps are included: preparing the first sub-grid slurry, the second sub-grid slurry, the first main grid slurry and the second main grid slurry; printing the first sub-grid slurry, the second sub-grid slurry, the first main grid slurry and the second main grid slurry on the intermediate film layer respectively; sintering and light injection of the cell after the slurry is printed, and the first sub-grid slurry, the second sub-grid slurry, the first main grid slurry and the second main grid slurry are sintered simultaneously, and the sintering temperature is controlled to be 700°C-800°C. Specifically, the sintering process is carried out in a sintering furnace, and the sintering temperature can be 700°C, 730°C, 750°C, 780°C, 800°C, etc.

[0134] It should be noted that the printing method of the auxiliary gate paste is step-by-step printing, and the order is first printing the first auxiliary gate electrode 9 and then printing the second auxiliary gate electrode 10, or first printing the second auxiliary gate electrode 10 and then printing the first auxiliary gate electrode 9; the first main gate paste and the second main gate paste are prepared simultaneously through a single printing method.

[0135] S4, Laser Induced Sintering

[0136] After forming the complete cell structure in step S3, laser induced sintering is performed. The P-zone metal area adopts laser induced sintering (LIF), which can greatly reduce metal recombination, increase the open circuit voltage of the battery, and then improve the photoelectric conversion efficiency. Specifically, by using laser to form a microstructure on the surface of the battery, an ohmic contact between the metal and the semiconductor is formed, thereby optimizing the contact structure of the battery, reducing the recombination loss of electron-hole pairs in the metal area, and improving the efficiency of the battery.

[0137] In some embodiments, Fig.12As shown, the process of laser induced sintering includes: applying a reverse bias voltage to the main grid of the cell to form a loop, and then performing laser scanning on at least the P-type doped area. The laser can scan the back of each cell or only scan the P-type doped area by controlling the laser precision. The reverse bias voltage is controlled to be 10V-50V, the applied laser power is 20W-120W, and the laser scanning rate is 50mm / s-500mm / s. By further controlling the operating parameters of the laser, the contact performance of the P-type doped area can be further improved and the metal composite can be reduced.

[0138] Specifically, the reverse bias voltage applied to the main grid of the battery cell can be 10V, 20V, 30V, 40V, 50V, etc., the applied laser power can be 20W, 50W, 80W, 100W, 120W, etc., and the laser scanning rate can be 50mm / s, 100mm / s, 150mm / s, 200mm / s, 300mm / s, 400mm / s, 500mm / s, etc.

[0139] Furthermore, the specific operations are as follows: the second probe row 14 is used to press each first main gate electrode 11 on the P-type doped area, the second probe row 14 is used to press each second main gate electrode 12 on the N-type doped area, and the first probe row 13 and the second probe row 14 are used to apply a certain constant reverse bias voltage to each main gate to form a loop, and laser scanning processing is performed at the same time.

[0140] It should be noted that the embodiment of the present invention adopts only a one-step boron diffusion method in the P region to replace the conventional LPCVD deposition of intrinsic amorphous silicon + boron doping method, and forms a high-resistance and low-composite diffusion layer in the non-metallic area of ​​the P region. At the same time, laser-assisted sintering technology is used to reduce the metal composite of the metal region of the P region and improve the contact performance of the metal region of the P region. It can not only reduce the process steps and process time, but also avoid the interaction between the laser and the polysilicon in the P region, reduce the difficulty of battery graphics, and greatly improve the production yield of the battery.

[0141] An embodiment of the present invention also provides a photovoltaic module, including the above-mentioned solar cell, which can be prepared using a traditional back-contact cell module interconnection method. Due to the improvement of the solar cell structure and process, it is beneficial to improve the production yield and photoelectric conversion performance of the photovoltaic module.

[0142] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0143] Example 1

[0144] The present invention provides a method for preparing a solar cell. Figure 4-Figure 12 As shown, the following steps are included:

[0145] (1) Figure 4 As shown, an N-type single crystal silicon wafer with a thickness of 145 μm (length and width are 210 μm and 182 μm, respectively) is provided, and a sodium hydroxide aqueous solution with a concentration (mass fraction, the same below) of 5% is used to polish and remove damage and clean the silicon wafer.

[0146] (2) Figure 5 As shown, a single-sided boron doping of a silicon wafer is performed by high-temperature boron diffusion, the diffusion temperature is 1000°C, the boron raw material is BCl3, and a boron diffusion doping layer 2 with a junction depth of 0.5 μm is formed. A borosilicate glass layer 3 (BSG) is formed on the surface of the boron diffusion doping layer 2 by diffusion, and the BSG thickness is 45 nm. The prepared P-type doped region uses the boron diffusion doping layer 2 as a PN junction, with a square resistance of 300Ω / sq and a doping concentration of 3E18cm -3 , the junction depth is 0.5μm.

[0147] (3) Figure 6 As shown, a picosecond (ps) laser is used to perform local film opening on the boron-doped surface with an opening width of 500 μm to remove local BSG; then a groove-type wet alkaline etching (the alkaline solution is a 5% KOH aqueous solution) is used to remove the boron diffusion doping layer 2 in the laser area, and the silicon wafer is cleaned.

[0148] (4) Figure 7 As shown, low pressure chemical vapor deposition (LPCVD) is used to sequentially generate 1.5nm tunneling silicon oxide (SiO2) and 200nm intrinsic amorphous silicon film; then the silicon wafer is phosphorus doped by high temperature phosphorus diffusion, the diffusion temperature is 850°C, and a phosphorus doped silicon oxide layer 4 and a phosphorus doped polysilicon layer 5 are formed. A phosphorus silicon glass layer 6 (PSG) is formed on the surface by diffusion, and the PSG thickness is 50nm. The prepared N-type doped region and the crystalline silicon substrate 1 are doped with different concentrations of phosphorus to form a high-low junction, the square resistance of the high-low junction is 20Ω / sq, and the doping concentration is 3E20cm -3 , the junction depth is 0.27μm.

[0149] (5) Figure 8 As shown, a picosecond (ps) laser is used to perform local film opening on the boron doped plane to remove the excess PSG film above the P region, and the film opening width is slightly larger than that of the P region, and the film opening width is 100μm more than that of the P region. The width of the formed P-type doped region is 500μm, the width of the N-type doped region is 400μm, the width of the isolation trench is 100μm, the spacing between two adjacent N-type doped regions is 1mm, and the area ratio of the first type doped region to the N-type doped region is 1.25:1.

[0150] (6) Fig. 9As shown, the front side of the silicon wafer is subjected to chain acid etching (using a mixed solution of HF, HNO3 and H2SO4, the total mass fraction of acid in the mixed solution is 10%, and the volume ratio of HF:HNO3:H2SO4 is 1:3:1) and a slot texturing process, while the P-type doped area and the N-type doped area on the back side are protected by BSG and PSG respectively and will not be etched, while the n-poly layer in the area without PSG protection in the middle of the P and N junction area is etched to form a region containing only the silicon substrate, which is 50μm wide; then a slot HF solution is used to remove all BSG and PSG on the back side, and the silicon wafer is cleaned.

[0151] (7) Fig.10 As shown, a 4nm thick aluminum oxide (AlOx) film and a 75nm thick silicon nitride (SiNx) anti-reflection film are deposited on the front and back of the silicon wafer respectively. The aluminum oxide (AlOx) film deposition process is as follows: TMA (trimethylaluminum) and H2O are used as deposition materials, and the film is deposited at 250°C by ALD. The silicon nitride (SiNx) anti-reflection film deposition process is as follows: NH3 and SiH4 are used as deposition materials, and the film is deposited at 500°C by PECVD.

[0152] (8) Fig.11 As shown, the first auxiliary gate electrode 9, the second auxiliary gate electrode 10, the first main gate electrode 11 and the second main gate electrode 12 are prepared, and the electrodes are silver paste. The specific steps are as follows:

[0153] The first auxiliary grid paste, the second auxiliary grid paste, the first main grid paste and the second main grid paste are respectively printed by screen printing, and all the first auxiliary grid electrodes 9 are perpendicularly intersected with the first main grid electrode 11 and connected through the first main grid electrode 11, and all the second auxiliary grid electrodes 10 are perpendicularly intersected with the second main grid electrode 12 and connected through the second main grid electrode 12. The cell after the paste is printed is sintered and light injected, and the paste is sintered simultaneously, and the sintering temperature is controlled to be 750°C and the sintering time is 100s.

[0154] (9) Fig.12 As shown, the first probe row 13 is used to press each first main grid electrode 11 on the P-type doped region, and the second probe row 14 is used to press each second main grid electrode 12 on the N-type doped region, and the first probe row 13 and the second probe row 14 are used to apply a certain constant reverse bias voltage to each main grid to form a loop, and laser scanning is performed at the same time. The reverse bias voltage applied to the main grid of the battery cell is 30V, the laser power is 100W, and the laser scanning speed is 100mm / s.

[0155] Example 2

[0156] The only difference from Example 1 is that in step (9), the reverse bias voltage applied to the main grid of the battery cell is 35V, the laser power is 80W, and the laser scanning speed is 80mm / s.

[0157] Example 3

[0158] The only difference from Example 1 is that in step (9), the reverse bias voltage applied to the main grid of the battery cell is 20V, the laser power is 150W, and the laser scanning speed is 120mm / s.

[0159] Example 4

[0160] The only difference from Example 1 is that the boron diffusion resistance in step (2) is 500Ω / sq and the doping concentration is 1E18cm -3 , the junction depth is 0.4μm; in step (9), the reverse bias voltage applied to the main grid of the battery cell is 33V, the laser power is 120W, and the laser scanning speed is 100mm / s.

[0161] Comparative Example 1

[0162] The difference from Example 1 is that no boron diffusion doping layer 2 is provided in the P-type doping region, and the conventional LPCVD deposition of intrinsic amorphous silicon + boron diffusion is used for preparation, specifically as follows: Step (2) firstly uses LPCVD to deposit a 1.8 nm tunneling silicon oxide layer and a 300 nm intrinsic amorphous silicon layer, and then performs boron diffusion at a temperature of 950° C. to form boron-doped polysilicon with a square resistance of 120 Ω / sq and a doping concentration of 5E18 cm -3 The junction depth is 0.4μm, that is, the P region is composed of tunneling silicon oxide and boron-doped polysilicon.

[0163] Comparative Example 2

[0164] The only difference from Example 1 is that step (9) is not performed.

[0165] Test Example 1

[0166] The photoelectric conversion efficiency Eta, open circuit voltage Voc, short circuit current density Jsc and fill factor FF of the solar cell prepared by the test example and the comparative example are shown in Table 1.

[0167] Table 1 Performance comparison of solar cells prepared in Example and Comparative Example

[0168]

[0169]

[0170] It can be seen from Table 1 that the solar cell prepared in the embodiment of the present invention has a higher photoelectric conversion efficiency.

[0171] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A crystalline silicon substrate having a front surface and a back surface opposite to the front surface; P-type doped regions and N-type doped regions are alternately arranged on the back side of the crystalline silicon substrate; In the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; The P-type doped region uses the boron diffusion doped layer as a PN junction, the square resistance is 200Ω / sq-1000Ω / sq, and the doping concentration is 7E17cm -3 -7E18cm -3 , junction depth is 0.3μm-1.0μm; In the N-type doped region, an N-type doped layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate, and the N-type doped layer in the N-type doped region includes a phosphorus-doped silicon oxide layer and a phosphorus-doped polysilicon layer sequentially arranged, and the phosphorus-doped polysilicon layer is located between the phosphorus-doped silicon oxide layer and the second passivation layer.

2. The solar cell according to claim 1, characterized in that The PN junction square resistance of the P-type doped region is 300Ω / sq-800Ω / sq, and the doping concentration is 1E18cm -3 -5E18cm -3 , the junction depth is 0.5μm-0.8μm; Preferably, the P-type doped region is further provided with a first metal electrode, and the N-type doped region is further provided with a second metal electrode, the first metal electrode is in contact with the boron diffusion doped layer, and a contact surface between the first metal electrode and the boron diffusion doped layer has a hole and a conductive structure, the conductive structure comprises a silver-silicon eutectic layer close to the boron diffusion doped layer and a conductive crystal extending from the silver-silicon eutectic layer toward the hole, the silver-silicon eutectic layer comprises a eutectic formed by silver element and silicon element, and the conductive crystal comprises a crystal formed by crystallization of the silver element; More preferably, the conductive crystal includes a crystalline main chain and crystalline side chains extending from the crystalline main chain in a growth direction different from that of the crystalline main chain.

3. The solar cell according to claim 1, characterized in that An isolation trench is provided between the adjacent P-type doping region and the N-type doping region; In the area where the isolation trench is located, a third passivation layer and a third anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; Preferably, the distance between the phosphorus-doped silicon oxide layer and the front surface of the crystalline silicon substrate is smaller than the distance between the boron diffusion doping layer and the front surface of the crystalline silicon substrate, and the distance between the second anti-reflection layer and the front surface of the crystalline silicon substrate is smaller than the distance between the first anti-reflection layer and the front surface of the crystalline silicon substrate, so that there is a height difference between the P-type doped region and the N-type doped region at the end away from the front surface of the crystalline silicon substrate; more preferably, the height difference is 0.5 μm-5.0 μm; Preferably, the boron diffusion doping layer junction depth of the P-type doping region is 0.3 μm-1.0 μm, the thickness of the phosphorus-doped silicon oxide layer is 0.5 nm-3.0 nm, and the thickness of the phosphorus-doped polysilicon layer is 50 nm-300 nm.

4. The solar cell according to claim 3, characterized in that: The crystalline silicon substrate is N-type single crystal silicon, the N-type doped region and the crystalline silicon substrate form a high-low junction, the square resistance of the high-low junction is 10Ω / sq-100Ω / sq, and the doping concentration is 1E20cm -3 -9E20cm -3 , the junction depth is 0.07μm-0.5μm, and the inner expansion depth under the silicon substrate is 0.02μm-0.1μm; Preferably, the high and low junction square resistance of the N-type doped region is 10Ω / sq-50Ω / sq, and the doping concentration is 2-6E20cm -3 The junction depth is 0.1μm-0.4μm, and the inner expansion depth under the silicon substrate is 0.03μm-0.08μm.

5. The solar cell according to claim 3, characterized in that: The width of the P-type doping region is 200 μm-1000 μm, and the width of the N-type doping region is 200 μm-1000 μm; Preferably, the area ratio of the P-type doping region to the N-type doping region is (0.5-2.0):1, preferably (0.8-1.2):1; Preferably, the width of the isolation trench is 50 μm-200 μm, and the depth of the isolation trench is 0.5 μm-5.0 μm; Preferably, the distance between two adjacent N-type doped regions is 0.5 mm to 2.0 mm; Preferably, the silicon substrate corresponding to the P-type doped region, the N-type doped region and the isolation trench are all planar structures or velvet structures, and the pyramid base size of the velvet structure is 1 μm-5 μm, and the pyramid height is 0.5 μm-2.0 μm.

6. The solar cell according to claim 2, characterized in that: The first metal electrode in the P-type doping region includes a plurality of first sub-gate electrodes and a first main gate electrode for connecting the plurality of the first sub-gate electrodes, and the second metal electrode on the N-type doping region includes a plurality of second sub-gate electrodes and a second main gate electrode for connecting the plurality of the second sub-gate electrodes; Preferably, each of the first sub-gate electrodes intersects the first main gate electrode perpendicularly and is connected through the first main gate electrode; each of the second sub-gate electrodes intersects the second main gate electrode perpendicularly and is connected through the second main gate electrode.

7. The solar cell according to claim 3, characterized in that: On the front side of the crystalline silicon substrate, a front passivation layer and a front anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; Preferably, the materials of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently selected from at least one of Al2O3 and SiO2; Preferably, the materials of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are independently selected from SiN x and SiO x N y At least one of; Preferably, the thickness of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently 2nm-5nm; Preferably, the thickness of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer are independently 70nm-100nm; Preferably, the thickness of the crystalline silicon substrate is 100 μm-150 μm.

8. A method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: include: Providing the crystalline silicon substrate, wherein the crystalline silicon substrate has a front side and a back side opposite to the front side; Forming the P-type doping regions and the N-type doping regions alternately arranged on the back side of the crystalline silicon substrate; In the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate. The P-type doped region uses the boron diffusion doped layer as a PN junction, controls the square resistance to be 200Ω / sq-1000Ω / sq, and the doping concentration is 7E17cm -3 -7E18cm -3 , junction depth is 0.3μm-1.0μm; In the N-type doped region, a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate.

9. The preparation method according to claim 8, characterized in that: include: An isolation trench is formed on the back side of the crystalline silicon substrate, and the back side of the crystalline silicon substrate is separated into the P-type doped regions and the N-type doped regions which are alternately arranged by using the isolation trench, and a functional layer is formed on each region on the back side of the crystalline silicon substrate and the front side of the crystalline silicon substrate, so as to obtain an intermediate film layer having a functional layer; Prepare a plurality of first auxiliary gate electrodes and at least one first main gate electrode on the P-type doping region of the intermediate film layer, prepare a plurality of second auxiliary gate electrodes and at least one second main gate electrode on the N-type doping region, and perform laser induced sintering after forming a complete cell structure; Preferably, the laser induced sintering process includes: applying a reverse bias voltage to the main grid of the battery cell to form a loop, and then laser scanning at least the P-type doped area; controlling the reverse bias voltage to 10V-50V, the applied laser power to 20W-120W, and the laser scanning rate to 50mm / s-500mm / s.

10. The preparation method according to claim 9, characterized in that: A first probe row is used to press each of the first main gate electrodes on the P-type doped region, a second probe row is used to press each of the second main gate electrodes on the N-type doped region, and the first probe row and the second probe row are used to apply a reverse bias voltage to each main gate to form a loop, and laser induced sintering is performed on at least the P-type doped region.

11. The preparation method according to claim 9, characterized in that: In the area where the isolation trench is located, a third passivation layer and a third anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; The preparation process of the intermediate film layer comprises: The boron diffusion doping layer, the phosphorus doped silicon oxide layer and the phosphorus doped polysilicon layer are formed on the back side of the crystalline silicon substrate, and at the same time, by forming an intermediate protective layer and partially opening and removing the film, only the boron diffusion doping layer is retained in the P-type doping area, and only the phosphorus doped silicon oxide layer and the phosphorus doped polysilicon layer are retained in the N-type doping area, and a hollow groove area is formed between the P-type doping area and the N-type doping area; A passivation layer and an anti-reflection layer corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region on the back side of the crystalline silicon substrate; and a front passivation layer and a front anti-reflection layer are formed on the front side of the crystalline silicon substrate.

12. The preparation method according to claim 11, characterized in that: The process of forming the hollow groove area includes: pre-processing the back side of the crystalline silicon substrate, sequentially forming the boron diffusion doping layer and the borosilicate glass layer on the back side of the crystalline silicon substrate, using laser to perform local film opening, removing the local borosilicate glass layer by laser, and removing the boron diffusion doping layer in the laser area by alkali etching, wherein the width of the film opening is equal to the sum of one N-type doping area and two isolation groove areas, and the etching depth is deep into the crystalline silicon substrate; forming the phosphorus-doped silicon oxide layer, the phosphorus-doped polysilicon layer and the phosphorus-silicate glass layer in sequence on the entire back side of the crystalline silicon substrate; Using laser to perform local film opening to remove the phosphosilicate glass layer on the P-type doping area, wherein the width of the film opening is greater than the width of the P-type doping area, and the difference between the width of the film opening and the width of the P-type doping area is 50 μm-200 μm; Acid etching and groove texturing are performed on the front side of the crystalline silicon substrate so that the area protected by the borosilicate glass layer and the phosphosilicate glass layer is not etched, and then all the borosilicate glass layer and the phosphosilicate glass layer on the back side are removed by etching so that only the boron diffusion doping layer is retained in the P-type doped area, and only the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer are retained in the N-type doped area, and a hollow groove area is formed between the P-type doped area and the N-type doped area, and the width of the hollow groove area is 50μm-200μm; Preferably, the pre-treatment is to prepare a polished surface or a velvet surface. Preferably, the crystalline silicon substrate is single-sidedly doped with boron by high-temperature boron diffusion, and the diffusion temperature is controlled to be 980° C.-1050° C. to form the boron diffusion doping layer; Preferably, the thickness of the formed borosilicate glass layer is 20nm-100nm, and the thickness of the formed phosphosilicate glass layer is 20nm-80nm; Preferably, the process of forming the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer comprises: forming a tunneling silicon oxide layer with a thickness of 1nm-3nm and an intrinsic amorphous silicon film with a thickness of 50nm-300nm by chemical vapor deposition, and then performing high-temperature phosphorus diffusion, and controlling the diffusion temperature to be 800°C-900°C; Preferably, the phosphorus-doped polysilicon layer is formed by plasma enhanced chemical vapor deposition and annealing.

13. The preparation method according to any one of claims 9 to 12, characterized in that: The first sub-gate electrode, the second sub-gate electrode, the first main gate electrode and the second main gate electrode are prepared by screen printing; Preferably, the process of preparing the secondary gate electrode and the main gate electrode comprises: Prepare a first auxiliary grid slurry, a second auxiliary grid slurry, a first main grid slurry and a second main grid slurry; Printing the first auxiliary grid paste, the second auxiliary grid paste, the first main grid paste and the second main grid paste on the intermediate film layer respectively; The cell after printing the slurry is sintered and light injected, and the sintering temperature is controlled at 700℃-800℃.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 7 or the solar cell prepared by the preparation method according to any one of claims 8 to 13.

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