Display panel, method for manufacturing display panel, and display device

Abstract

The application provides a display panel, a preparation method of the display panel and a display device. The display panel comprises: a conductive trace arranged on one side of a substrate, the conductive trace being at least partially located in a non-display area; a first planarization layer arranged on a side of the conductive trace away from the substrate, the first planarization layer being located in a second planarization part of the non-display area, and a normal projection of the conductive trace on the substrate being located in a normal projection of the second planarization part on the substrate; and a touch layer arranged on a side of the first pixel definition part away from the substrate; wherein a ratio of a thickness of the second planarization part to a thickness of the first planarization part is greater than or equal to 90% and less than or equal to 100%. The display panel provided by the application retains a second planarization part with sufficient thickness in multiple etching processes, the second planarization part covers the conductive trace in the non-display area, avoids exposure or over-etching damage of the conductive trace in the non-display area, and reduces display abnormal phenomena caused by disconnection of the conductive trace.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] In traditional display panel manufacturing, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision, high development costs, and long development cycles. Fine metal maskless technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance characteristics, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN118678742A, CN118785761A, CN115224220A, CN118678729A, CN118660529A, and CN118660589A describe relevant aspects of fine metal maskless technology and are provided for reference.

[0003] However, current OLED display products are prone to display abnormalities, and the process performance needs to be improved. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a display panel, a method for manufacturing the display panel, and a display device, which improves the product yield of the display panel by reducing over-etching damage.

[0005] To achieve the above objectives, an embodiment of the first aspect of this application provides a display panel, the display panel including a display area and a non-display area at least partially surrounding the display area; the display panel includes:

[0006] substrate;

[0007] A conductive trace is disposed on one side of the substrate, and the conductive trace is at least partially located in the non-display area;

[0008] A first planarization layer is disposed on the side of the conductive trace away from the substrate. The first planarization layer includes a first planarization portion located in the display area and a second planarization portion located in the non-display area. The orthographic projection of the conductive trace on the substrate is located within the orthographic projection of the second planarization portion on the substrate.

[0009] A pixel definition layer is disposed on the side of the first planarization layer away from the substrate. The pixel definition layer includes a first pixel definition portion located in the display area, and the first pixel definition portion includes a plurality of pixel openings.

[0010] A touch layer is located in the display area, and the touch layer is disposed on the side of the first pixel definition portion away from the substrate;

[0011] The ratio of the thickness of the second planarization portion to the thickness of the first planarization portion is greater than or equal to 90% and less than or equal to 100%.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the second planarization portion has the same thickness as the first planarization portion.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes

[0014] The second planarization layer includes a third planarization portion located in the display area and a fourth planarization portion located in the non-display area. The third planarization portion is disposed on the side of the first planarization portion close to the substrate, and the fourth planarization portion is disposed on the side of the conductive trace close to the substrate.

[0015] Preferably, the third planarization portion and the fourth planarization portion have the same thickness. According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes:

[0016] An isolation structure is located in the display area, and the isolation structure is disposed on the side of the first pixel definition portion away from the substrate; the isolation structure encloses and forms a plurality of isolation openings;

[0017] Preferably, the pixel opening corresponds one-to-one with the isolation opening;

[0018] Preferably, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the corresponding isolation opening on the substrate.

[0019] Preferably, the isolation structure includes a support portion and a shielding portion, the shielding portion being located on the side of the support portion away from the substrate, and the orthographic projection of the support portion on the substrate being located within the orthographic projection of the shielding portion on the substrate;

[0020] Preferably, the isolation structure further includes an overlap portion, the overlap portion including a conductive structure;

[0021] Preferably, the overlapping portion is located between the first pixel definition portion and the support portion, and the orthographic projection of the support portion on the substrate is located within the orthographic projection of the overlapping portion on the substrate.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes:

[0023] A light-emitting unit, located in the display area, includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked in a direction away from the substrate;

[0024] Preferably, the orthographic projection of the first pixel definition portion on the substrate and the orthographic projection of the first electrode on the substrate at least partially overlap;

[0025] Preferably, the pixel opening exposes at least a portion of the first electrode;

[0026] Preferably, the light-emitting layer and the second electrode are at least partially located within the isolation opening.

[0027] According to any of the foregoing embodiments of the first aspect of this application, the light-emitting unit includes a first color light-emitting unit, a second color light-emitting unit, and a third color light-emitting unit for emitting light of different colors.

[0028] According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes:

[0029] An encapsulation layer, at least partially located in the display area, and a touch layer disposed on the side of the encapsulation layer away from the substrate;

[0030] Preferably, the encapsulation layer includes a first encapsulation layer, which is disposed within the isolation opening and covers the second electrode;

[0031] Preferably, the encapsulation layer further includes a second encapsulation layer and a third encapsulation layer, wherein the second encapsulation layer covers the first encapsulation layer and the isolation structure, and the third encapsulation layer covers the second encapsulation layer.

[0032] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the touch layer on the substrate and the orthographic projection of the second planarization portion on the substrate do not overlap;

[0033] Preferably, the touch layer includes a first touch metal layer, a touch insulating layer, and a second touch metal layer stacked sequentially, wherein the second touch metal layer is disposed on the side of the first touch metal layer away from the substrate.

[0034] According to any of the foregoing embodiments of the first aspect of this application, the display panel further includes a second metal layer, a third metal layer and a fourth metal layer stacked between the substrate and the pixel definition layer, wherein the fourth metal layer is the metal layer closest to the second electrode, and the conductive trace is disposed in the same layer as the fourth metal layer.

[0035] According to any of the foregoing embodiments of the first aspect of this application, the non-display area includes a bending area, and the conductive trace and the second planarization portion are located in the bending area;

[0036] Preferably, the conductive trace includes a pad.

[0037] A second aspect of this application provides a method for manufacturing a display panel, the display panel including a display area and a non-display area at least partially surrounding the display area; the method includes:

[0038] A conductive trace is formed on one side of the substrate, and the conductive trace is at least partially located in the non-display area;

[0039] A first planarization layer is formed on the side of the conductive trace away from the substrate. The first planarization layer includes a first planarization portion located in the display area and a second planarization portion located in the non-display area. The orthographic projection of the conductive trace on the substrate is located within the orthographic projection of the second planarization portion on the substrate.

[0040] A pixel definition layer is formed on the side of the first planarization layer away from the substrate; wherein, the pixel definition layer includes a first pixel definition portion located in the display area and a second pixel definition portion located in the non-display area, and a plurality of pixel openings are formed in the first pixel definition portion; the orthographic projection of the second planarization portion on the substrate and the orthographic projection of the second pixel definition portion on the substrate at least partially overlap;

[0041] Multiple light-emitting units are formed, and the light-emitting units are at least partially located in the pixel opening;

[0042] A touch layer is formed, and the second pixel definition portion is removed, such that the ratio of the thickness of the second flattened portion to the thickness of the first flattened portion is greater than or equal to 90% and less than or equal to 100%.

[0043] According to any of the foregoing embodiments of the second aspect of this application

[0044] The orthographic projection of the touch layer on the substrate does not overlap with the orthographic projection of the second planarization portion on the substrate;

[0045] Preferably, after the removal of the second pixel definition portion, the surface of the second planarization portion on the side away from the substrate is exposed;

[0046] Preferably, before forming conductive traces on one side of the substrate, the method further includes:

[0047] A second planarization layer is formed on one side of the substrate. The second planarization layer includes a third planarization portion located in the display area and a fourth planarization portion located in the non-display area. The third planarization portion is disposed on the side of the first planarization portion close to the substrate, and the fourth planarization portion is disposed on the side of the conductive trace close to the substrate.

[0048] Preferably, the third planarization portion has the same thickness as the fourth planarization portion.

[0049] According to any of the foregoing embodiments of the second aspect of this application, the formation of a plurality of light-emitting units includes:

[0050] A first electrode layer is disposed on one side of the substrate, and a plurality of first electrodes are formed on the first electrode layer;

[0051] An isolation structure is formed on the side of the first pixel definition portion away from the substrate, such that the isolation structure encloses a plurality of isolation openings, and a plurality of pixel openings are formed in the first pixel definition portion, such that the pixel openings expose at least a portion of the first electrode.

[0052] According to any of the foregoing embodiments of the second aspect of this application, the light-emitting unit includes a first color light-emitting unit, a second color light-emitting unit, and a third color light-emitting unit for emitting light of different colors; the isolation opening includes a first type of isolation opening, a second type of isolation opening, and a third type of isolation opening respectively corresponding to the first color light-emitting unit, the second color light-emitting unit, and the third color light-emitting unit.

[0053] The formation of multiple light-emitting units also includes:

[0054] A first color light-emitting layer, a first color electrode, and a first color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure;

[0055] The first color encapsulation layer, the first color light-emitting layer, and the first color electrode are patterned, and the first color encapsulation layer, the first color electrode, and the first color light-emitting layer are removed from the isolation structure, the second type of isolation opening, and the third type of isolation opening to form the first color light-emitting unit.

[0056] A second color light-emitting layer, a second color electrode, and a second color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure.

[0057] The second color encapsulation layer, the second color light-emitting layer, and the second color electrode are patterned, and the second color encapsulation layer, the second color electrode, and the second color light-emitting layer are removed from the isolation structure and from the first type of isolation opening and the third type of isolation opening to form the second color light-emitting unit.

[0058] A third color light-emitting layer, a third color electrode, and a third color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure.

[0059] The third color encapsulation layer, the third color light-emitting layer, and the third color electrode are patterned, and the third color encapsulation layer, the third color light-emitting layer, and the third color electrode are removed from the isolation structure and from the first type of isolation opening and the second type of isolation opening to form the third color light-emitting unit.

[0060] According to any of the foregoing embodiments of the second aspect of this application, forming the touch layer includes:

[0061] A first touch metal layer, a touch insulating layer, and a second touch metal layer are formed sequentially, with the second touch metal layer disposed on the side of the first touch metal layer away from the substrate;

[0062] Preferably, prior to forming the touch layer, the method further includes:

[0063] A second encapsulation layer and a third encapsulation layer are formed on the side of the first color encapsulation layer, the second color encapsulation layer and the third color encapsulation layer away from the substrate;

[0064] Preferably, the first touch metal layer is located on the side of the third encapsulation layer away from the substrate.

[0065] An embodiment of the third aspect of this application provides a display device, including a display panel prepared by the method for preparing a display panel according to any of the above embodiments.

[0066] Compared with the prior art, the display panel provided in this application retains a second planarization portion of sufficient thickness in multiple etching processes. The second planarization portion covers the conductive traces in the non-display area, avoiding exposure or over-etching damage to the conductive traces in the non-display area, reducing display abnormalities caused by broken conductive traces, and improving the product yield of the display panel. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this application;

[0069] Figure 2 This is a schematic diagram of the hierarchical structure of a display panel provided in an embodiment of this application;

[0070] Figure 3A schematic diagram of the hierarchical structure of a display panel provided in another embodiment of this application;

[0071] Figure 4 This is a schematic diagram of the isolation structure provided in the embodiments of this application;

[0072] Figure 5 This is a schematic diagram of the layered structure of the display panel provided in the embodiments of this application during the manufacturing process;

[0073] Figure 6 This is a schematic diagram of the hierarchical structure of the non-display area of ​​the display panel provided in an embodiment of this application;

[0074] Figure 7 This is a schematic diagram of the display area of ​​the display panel provided in the embodiments of this application;

[0075] Figure 8 This is a schematic flowchart of a method for manufacturing a display panel according to an embodiment of this application.

[0076] Marker explanation:

[0077] 10. Display panel; 101. Display area; 102. Non-display area;

[0078] 1. Substrate; 2. Conductive trace; 20. Fourth metal layer; 31. First planarization layer; 311. First planarization portion; 312. Second planarization portion; 32. Second planarization layer; 321. Third planarization portion; 322. Fourth planarization portion; 4. Pixel definition layer; 41. First pixel definition portion; 410. Pixel opening; 42. Second pixel definition portion; 5. Isolation structure; 50. Isolation opening; 51. Support portion; 52. Shielding portion; 53. Overlapping portion; 6. Light-emitting unit; 601. First color light-emitting unit; 602. Second color light-emitting unit; 603. Third color light-emitting unit; 61. First electrode; 62. Light-emitting layer; 63. Second electrode; 7. Encapsulation layer; 71. First encapsulation layer; 72. Second encapsulation layer; 73. Third encapsulation layer; 8. Touch layer; 81. First touch metal layer; 82. Touch insulating layer; 83. Second touch metal layer. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0080] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0081] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0082] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0083] In related technologies, the isolation structure can separate the functional film layers of adjacent light-emitting units. Thus, in the evaporation process of the functional film layers, it is only necessary to perform evaporation on the entire display panel, without the need to use a metal mask to prepare the functional film layer of each light-emitting unit separately. This technology is a maskless self-alignment pixelation technology, which does not need to consider the alignment accuracy problem during evaporation, thereby allowing the gap between light-emitting units to be designed to be smaller.

[0084] Because display panels undergo multiple pixel etching processes and subsequent touch control etching, the planarization layer above the conductive traces in non-display areas, such as bending areas, suffers significant thickness loss due to continuous etching. This exposes the conductive traces or causes over-etching damage, easily leading to conductive trace breakage during pad bending in the display module, resulting in display failure and other defects. The inventors of this application discovered that the root cause lies in the fact that the pixel definition layer etching steps occur before the touch control process. For example, if the pixel definition layer in the non-display area is etched away during the formation of the light-emitting unit, the conductive traces or planarization layer in the non-display area will lack protection during subsequent etching, exacerbating wear and tear.

[0085] Based on this, this application provides a display panel solution to solve the above problems.

[0086] Firstly, such as Figure 1 , Figure 2 As shown, one embodiment of this application provides a display panel 10, which includes a display area 101 and a non-display area 102 that at least partially surrounds the display area 101. For example, the non-display area 102 may be a border area surrounding the display area 101, or the non-display area 102 may be a bent area located on one side of the display area 101.

[0087] The display panel 10 includes a substrate 1, conductive traces 2, a first planarization layer 31, a pixel definition layer 4, and a touch layer 8. The conductive traces 2 are disposed on one side of the substrate 1, and at least a portion of the conductive traces 2 is located in the non-display area 102. The first planarization layer 31 is disposed on the side of the conductive traces 2 away from the substrate 1. The first planarization layer 31 includes a first planarization portion 311 located in the display area 101 and a second planarization portion 312 located in the non-display area 102. The orthographic projection of the conductive traces 2 on the substrate 1 is located within the orthographic projection of the second planarization portion 312 on the substrate 1.

[0088] A pixel definition layer 4 is disposed on the side of the first planarization layer 31 away from the substrate 1. The pixel definition layer 4 includes a first pixel definition portion 41 located in the display area, and the first pixel definition portion 41 includes a plurality of pixel openings 410. A touch layer 8 is located in the display area 101, and the touch layer 8 is disposed on the side of the first pixel definition portion 41 away from the substrate 1.

[0089] The ratio of the thickness of the second planarization portion 312 to the thickness of the first planarization portion 311 is in the range of 90%-100%. For example, the ratio of the thickness of the second planarization portion 312 to the thickness of the first planarization portion 311 can be 90%, 92%, 95%, 97%, 99%, 100%, etc.

[0090] When the ratio of the thickness of the second planarization portion 312 to the thickness of the first planarization portion 311 is 100%, the thickness of the second planarization portion 312 is the same as the thickness of the first planarization portion 311.

[0091] Specifically, the isolation effect of the pixel definition layer 4 can be used to protect the second planarization section 312 and the conductive traces 2 below it, and finally the portion of the pixel definition layer 4 located in the non-display area 102 can be removed. This can reduce the damage to the second planarization section 312 caused by the pixel etching process and touch control process etching in the display area 101.

[0092] The display panel 10 provided in the embodiments of this application retains a second planarization portion 312 of sufficient thickness in multiple etching processes, making it no less than 90% of the thickness of the first planarization portion 311. The second planarization portion 312 covers the conductive traces 2 in the non-display area 102, avoiding exposure or over-etching damage to the conductive traces 2 in the non-display area 102, reducing display abnormalities caused by broken conductive traces 2, and improving the product yield of the display panel.

[0093] For example, the display panel 10 is a flexible display panel, and the non-display area 102 includes a bending area. Within the bending area, a second planarization portion 312 of sufficient thickness is retained to protect the conductive traces 2, preventing breakage during bending. Depending on the specific circumstances, the conductive traces 2 can be used to transmit signals such as touch signals to meet various needs of the display panel.

[0094] like Figure 3 As shown, in one embodiment, the display panel 10 further includes a second planarization layer 32. The second planarization layer 32 includes a third planarization portion 321 located in the display area 101 and a fourth planarization portion 322 located in the non-display area 102. The third planarization portion 321 is disposed on one side of the first planarization portion 311, and the fourth planarization portion 322 is disposed on the side of the conductive trace 2 near the substrate 1.

[0095] Optionally, the third planarization portion 321 and the fourth planarization portion 322 have the same thickness.

[0096] Specifically, the fourth planarization section 322 is located between the substrate 1 and the conductive trace 2, which can optimize the surface morphology of the substrate, ensure that the conductive trace 2 is evenly distributed, and avoid local over-etching caused by uneven substrate.

[0097] In one embodiment, the display panel 10 further includes an isolation structure 5, which is located in the display area 101 and is disposed on the side of the first pixel definition portion 41 away from the substrate 1; the isolation structure 5 encloses and forms a plurality of isolation openings 50.

[0098] Optionally, the pixel aperture 410 corresponds one-to-one with the isolation aperture 50.

[0099] Optionally, the orthographic projection of the pixel opening 410 on the substrate 1 is located within the orthographic projection of the corresponding isolation opening 50 on the substrate 1.

[0100] The isolation structure 5 allows for independent control of the light-emitting units, preventing optical crosstalk and electrical interference between adjacent pixels. The pixel opening 410 is located within the isolation opening 50, ensuring alignment between the light-emitting units and the isolation structure 5. The pixel opening 410 and the isolation opening 50 precisely define the position of the light-emitting units.

[0101] Furthermore, such as Figure 4 As shown, the isolation structure 5 includes a support portion 51 and a shielding portion 52. The shielding portion 52 is located on the side of the support portion 51 away from the substrate 1, and the orthographic projection of the support portion 51 on the substrate 1 is located within the orthographic projection of the shielding portion 52 on the substrate 1.

[0102] Optionally, the isolation structure 5 also includes an overlap portion 53, which includes a conductive structure.

[0103] Optionally, the overlapping portion 53 is located between the first pixel definition portion 41 and the support portion 51, and the orthographic projection of the support portion 51 on the substrate 1 is located within the orthographic projection of the overlapping portion 53 on the substrate 1.

[0104] Thus, the portion of the isolation structure 5 that is at least away from the substrate 1 is configured to be wider at the top and narrower at the bottom, so that the isolation structure 5 can block the light-emitting layer of the adjacent light-emitting unit, thereby reducing the current crosstalk problem of the adjacent light-emitting unit.

[0105] In one embodiment, the display panel 10 further includes a light-emitting unit 6 located in the display area 101. The light-emitting unit 6 includes a first electrode 61, a light-emitting layer 62, and a second electrode 63 sequentially stacked in a direction away from the substrate 1.

[0106] Optionally, the orthographic projection of the first pixel definition portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the first electrode 61 on the substrate 1.

[0107] Optionally, the pixel opening 410 exposes at least a portion of the first electrode 61.

[0108] Optionally, the light-emitting layer 62 and the second electrode 63 are at least partially located in the isolation opening 50.

[0109] The second electrode 63 is electrically connected to the overlapping part 53.

[0110] like Figure 7 As shown, in one embodiment, the light-emitting unit 6 includes a first color light-emitting unit 601, a second color light-emitting unit 602, and a third color light-emitting unit 603 for emitting light of different colors.

[0111] For example, the first color light-emitting unit 601, the second color light-emitting unit 602, and the third color light-emitting unit 603 are used to emit red light, green light, and blue light, respectively.

[0112] The multi-color light-emitting units achieve independent color control through the physical separation of the isolation structure 5, avoiding color crosstalk and improving the color gamut coverage and color reproduction of the display panel.

[0113] In the process of forming the light-emitting unit 6, firstly, a full-surface vapor deposition is performed to complete the deposition of the first color light-emitting layer and functional layer. Then, a full-surface thin-film encapsulation is performed. Next, through patterning processing, the parts on the substrate that do not need to be retained are selectively removed to form the first color light-emitting unit. Then, the above process is repeated twice more to form the second color light-emitting unit and the third color light-emitting unit, completing the full-color patterning of the three primary colors of red, green and blue (RGB).

[0114] It should be emphasized that in the multiple pixel etching process of forming the light-emitting unit 6, the second pixel definition part 42 located in the non-display area 102 is not etched away, thereby protecting the conductive trace 2 and the first planarization layer 31 in the non-display area 102 and avoiding etching damage.

[0115] In one embodiment, the display panel 10 further includes an encapsulation layer 7, which is at least partially located in the display area 101, and a touch layer 8 is disposed on the side of the encapsulation layer away from the substrate 1.

[0116] Optionally, the encapsulation layer 7 includes a first encapsulation layer 71, which is disposed within the isolation opening 50 and covers the second electrode 63.

[0117] Optionally, the encapsulation layer further includes a second encapsulation layer 72 and a third encapsulation layer 73, wherein the second encapsulation layer 72 covers the first encapsulation layer 71 and the isolation structure 5, and the third encapsulation layer 73 covers the second encapsulation layer 72.

[0118] The second encapsulation layer 72 covers the first encapsulation layer 71 and the isolation structure 5, and the third encapsulation layer 73 covers the second encapsulation layer 72. The first encapsulation layer 71 and the third encapsulation layer 73 are inorganic layers with high density to isolate water and oxygen, while the second encapsulation layer 72 is an organic layer with a large thickness to flatten the surface of the display panel, thus achieving an inorganic-organic-inorganic three-layer encapsulation.

[0119] like Figure 3 As shown, in one embodiment, the orthographic projection of the touch layer 8 on the substrate 1 does not overlap with the orthographic projection of the second planarization portion 312 on the substrate 1.

[0120] The touch layer 8 includes a first touch metal layer 81, a touch insulating layer 82, and a second touch metal layer 83 stacked sequentially, with the second touch metal layer 83 disposed on the side of the first touch metal layer 81 away from the substrate 1.

[0121] Specifically, the first touch metal layer 81 and the second touch metal layer 83 can be used to form touch electrodes and touch traces.

[0122] like Figure 2 , Figure 3As shown, the display panel 10 also includes a second metal layer, a third metal layer, and a fourth metal layer 20 stacked between the substrate 1 and the pixel definition layer 4. The fourth metal layer 20 is the metal layer closest to the second electrode 63. The conductive trace 2 is disposed on the same layer as the fourth metal layer 20, which simplifies the manufacturing process. Specifically, the second electrode 63 is connected to the fourth metal layer 20 via a via.

[0123] For example, the first metal layer, second metal layer, third metal layer, and fourth metal layer 20 are used to fabricate a pixel circuit structure located in the display area 101. For instance, the first metal layer is used to fabricate the gate of the driving transistor in the pixel circuit, the first and second metal layers are used to fabricate the capacitor in the pixel circuit, and the third and fourth metal layers are respectively used to form power signal lines required for transmitting the pixel circuit. An insulating layer is disposed between adjacent metal layers in the first, second, third, and fourth metal layers. For example, the second planarization layer 32 can be used as an insulating layer disposed between the third and fourth metal layers.

[0124] In one embodiment, the non-display area 102 includes a bend area, and the conductive trace 2 and the second planarization portion 312 are located in the bend area.

[0125] Optionally, the conductive trace 2 includes pads.

[0126] like Figures 5 to 6 As shown, after the second touch metal layer 83 is patterned, the second pixel definition portion 42 located in the non-display area 102 of the pixel definition layer 4 is removed, so that the surface of the second planarization portion 312 away from the substrate 1 is exposed outward.

[0127] By covering the conductive traces 2 within the bending area with the pixel definition layer 4, and combining this with the delayed etching method of the second pixel definition section 42, the breakage caused by over-etching damage to the planarization layer when the pad is bent can be avoided.

[0128] Secondly, such as Figure 8 As shown, one embodiment of this application provides a method for manufacturing a display panel. The display panel 10 includes a display area 101 and a non-display area 102 that at least partially surrounds the display area 101. The method for manufacturing the display panel includes the following steps:

[0129] Step S1: A conductive trace 2 is formed on one side of the substrate 1, and the conductive trace 2 is at least partially located in the non-display area 102.

[0130] Step S2: A first planarization layer 31 is formed on the side of the conductive trace 2 away from the substrate 1. The first planarization layer 31 includes a first planarization portion 311 located in the display area 101 and a second planarization portion 312 located in the non-display area 102. The orthographic projection of the conductive trace 2 on the substrate 1 is located within the orthographic projection of the second planarization portion 312 on the substrate 1.

[0131] Step S3: A pixel definition layer 4 is formed on the side of the first planarization layer 31 away from the substrate 1. The pixel definition layer 4 includes a first pixel definition portion 41 located in the display area and a second pixel definition portion 42 located in the non-display area 102. A plurality of pixel openings 410 are formed in the first pixel definition portion 41. The orthographic projection of the second planarization portion 312 onto the substrate 1 at least partially overlaps with the orthographic projection of the second pixel definition portion 42 onto the substrate 1.

[0132] Step S4: Form a plurality of light-emitting units 6, wherein at least part of the light-emitting units 6 are located in the pixel opening 410.

[0133] Step S5: Form the touch layer 8 and remove the second pixel definition portion 42, so that the ratio of the thickness of the second flattening portion 312 to the thickness of the first flattening portion 311 is greater than or equal to 90% and less than or equal to 100%.

[0134] In the above-mentioned method for manufacturing a display panel, by first forming a pixel definition layer 4 and then removing the second pixel definition portion 42, during the process of forming the light-emitting unit and at least part of the process of forming the touch layer 8, the second pixel definition portion 42 located in the non-display area 102 serves as a temporary protective layer. In multiple etching processes, a second planarization portion 312 of sufficient thickness is retained. The second planarization portion 312 covers the conductive traces 2 in the non-display area 102, reducing the damage to the second planarization portion 312 caused by the pixel etching process of the display area 101 and the touch process etching, avoiding the exposure or over-etching damage of the conductive traces 2 in the non-display area 102, reducing display abnormalities caused by the breakage of the conductive traces 2, and improving the product yield of the display panel.

[0135] Furthermore, the orthographic projection of the touch layer 8 on the substrate 1 does not overlap with the orthographic projection of the second planarization portion 312 on the substrate 1.

[0136] Optionally, the orthographic projection of the second planarization portion 312 on the substrate 1 is located within the orthographic projection of the second pixel definition portion 42 on the substrate 1.

[0137] Optionally, after removing the second pixel definition portion 42 in step S5, the surface of the second planarization portion 312 on the side away from the substrate 1 is exposed.

[0138] Specifically, in the non-display area 102, there are ultimately no film layers such as pixel definition layer 4, touch layer 8 or support layer above the second planarization section 312.

[0139] Optionally, conductive traces 2 are formed on one side of the substrate 1. Prior to this, the method for fabricating the display panel further includes the following steps:

[0140] A second planarization layer 32 is formed on one side of the substrate 1. The second planarization layer 32 includes a third planarization portion 321 located in the display area 101 and a fourth planarization portion 322 located in the non-display area 102. The third planarization portion 321 is disposed on one side of the first planarization portion 311, and the fourth planarization portion 322 is disposed on the side of the conductive trace 2 close to the substrate 1.

[0141] Optionally, the third planarization portion 321 and the fourth planarization portion 322 have the same thickness.

[0142] In one embodiment, step S3, forming a plurality of light-emitting units 6, includes:

[0143] Step S31: A first electrode layer is formed on one side of the substrate 1, and a plurality of first electrodes 61 are formed in the first electrode layer.

[0144] An isolation structure 5 is formed on the side of the first pixel definition portion 41 away from the substrate 1, and the isolation structure 5 encloses a plurality of isolation openings 50. A plurality of pixel openings 410 are formed in the first pixel definition portion 41, and the pixel openings 410 expose at least a portion of the first electrode 61.

[0145] The isolation structure 5 provides a physical template for the subsequent partitioning of the light-emitting units, ensuring the precise positioning of the different color light-emitting layers 62. The nested design of the pixel opening 410 and the isolation opening 50 is used to isolate and constrain the light-emitting units 6.

[0146] In one embodiment, the light-emitting unit 6 includes a first-color light-emitting unit 601, a second-color light-emitting unit 602, and a third-color light-emitting unit 603 for emitting light of different colors. The isolation opening 50 includes a first-type isolation opening, a second-type isolation opening, and a third-type isolation opening, respectively corresponding to the first-color light-emitting unit 601, the second-color light-emitting unit 602, and the third-color light-emitting unit 603.

[0147] Step S3, forming multiple light-emitting units 6, also includes:

[0148] Step S32: A first color light-emitting layer, a first color electrode, and a first color encapsulation layer are sequentially formed inside the isolation opening 50 and on the isolation structure 5.

[0149] Step S33: Pattern the first color encapsulation layer, the first color light-emitting layer and the first color electrode, and remove the first color encapsulation layer, the first color electrode and the first color light-emitting layer from the isolation structure 5 and the second type of isolation opening and the third type of isolation opening to form the first color light-emitting unit 601.

[0150] Specifically, the first color encapsulation layer on the isolation structure and inside the second and third type isolation openings can be removed first by etching process, and then the first color electrode and the first color emitting layer on the isolation structure and inside the second and third type isolation openings can be removed by etching process.

[0151] The first electrode 61, the first color light-emitting layer, and the first color electrode together form the first color light-emitting unit 601.

[0152] Step S34: A second color light-emitting layer, a second color electrode, and a second color encapsulation layer are sequentially formed within the isolation opening 50 and on the isolation structure 5.

[0153] Step S35: Pattern the second color encapsulation layer, the second color light-emitting layer, and the second color electrode, and remove the second color encapsulation layer, the second color electrode, and the second color light-emitting layer from the isolation structure 5 and from the first type of isolation opening and the third type of isolation opening to form the second color light-emitting unit 602.

[0154] Specifically, the second color encapsulation layer on the isolation structure and inside the first type of isolation opening and the third type of isolation opening can be removed first by etching process, and then the second color electrode and the second color light-emitting layer on the isolation structure and inside the first type of isolation opening and the third type of isolation opening can be removed by etching process.

[0155] The first electrode 61, the second color light-emitting layer, and the second color electrode together form the second color light-emitting unit 602.

[0156] Step S36: A third color light-emitting layer, a third color electrode, and a third color encapsulation layer are sequentially formed within the isolation opening 50 and on the isolation structure 5.

[0157] Step S37: Pattern the third color encapsulation layer, the third color light-emitting layer, and the third color electrode, and remove the third color encapsulation layer, the third color light-emitting layer, and the third color electrode from the isolation structure 5 and from the first type of isolation opening and the second type of isolation opening to form the third color light-emitting unit 603.

[0158] Specifically, the third color encapsulation layer on the isolation structure and inside the first and second type isolation openings can be removed first by etching, and then the third color electrode and the third color light-emitting layer on the isolation structure and inside the first and second type isolation openings can be removed by etching.

[0159] The first electrode 61, the third color light-emitting layer, and the third color electrode together form the third color light-emitting unit 603.

[0160] In one embodiment, step S4, forming the touch layer 8, includes:

[0161] A first touch metal layer 81, a touch insulating layer 82, and a second touch metal layer 83 are formed sequentially, with the second touch metal layer 83 disposed on the side of the first touch metal layer 81 away from the substrate 1.

[0162] Optionally, before step S4, forming the touch layer 8, the method for manufacturing the display panel further includes the following steps:

[0163] A second encapsulation layer 72 and a third encapsulation layer 73 are formed on the side of the first color encapsulation layer, the second color encapsulation layer and the third color encapsulation layer away from the substrate 1.

[0164] Optionally, the first touch metal layer 81 is located on the side of the third encapsulation layer 73 away from the substrate 1.

[0165] For example, a first touch metal layer 81 is first deposited using physical vapor deposition (PVD). Then, a touch insulating layer 82 is formed on the surface of the first touch metal layer 81. The touch insulating layer 82 is then patterned through a series of processes including exposure, development, and curing. After etching the metal layer, a corresponding bridging structure is formed, and then a second touch metal layer 83 is formed. The second touch metal layer 83 is then patterned and etched to form touch electrodes and / or touch traces. Similarly, during the patterning and etching of the second touch metal layer 83, an insulating layer can also be formed on its surface. This insulating layer is then patterned through a series of processes including exposure, development, and curing before the second touch metal layer 83 is etched.

[0166] It should be noted that after etching the second touch metal layer 83, the second pixel definition part 42 is removed.

[0167] An embodiment of the third aspect of this application also provides a display device, the display device comprising a display panel prepared by the method for preparing the display panel of any of the above embodiments.

[0168] The display device in this application embodiment can be any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator.

[0169] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0170] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0171] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area at least partially surrounding the display area; the display panel includes: substrate; A conductive trace is disposed on one side of the substrate, and the conductive trace is at least partially located in the non-display area; A first planarization layer is disposed on the side of the conductive trace away from the substrate. The first planarization layer includes a first planarization portion located in the display area and a second planarization portion located in the non-display area. The orthographic projection of the conductive trace on the substrate is located within the orthographic projection of the second planarization portion on the substrate. A pixel definition layer is disposed on the side of the first planarization layer away from the substrate. The pixel definition layer includes a first pixel definition portion located in the display area, and the first pixel definition portion includes a plurality of pixel openings. A touch layer is located in the display area, and the touch layer is disposed on the side of the first pixel definition portion away from the substrate; The ratio of the thickness of the second planarization portion to the thickness of the first planarization portion is greater than or equal to 90% and less than or equal to 100%.

2. The display panel as described in claim 1, characterized in that, The second planarization portion has the same thickness as the first planarization portion.

3. The display panel as described in claim 1, characterized in that, The display panel further includes a second planarization layer, which includes a third planarization portion located in the display area and a fourth planarization portion located in the non-display area. The third planarization portion is disposed on the side of the first planarization portion close to the substrate, and the fourth planarization portion is disposed on the side of the conductive trace close to the substrate. Preferably, the third planarization portion has the same thickness as the fourth planarization portion.

4. The display panel as described in claim 1, characterized in that, The display panel also includes: An isolation structure is located in the display area, and the isolation structure is disposed on the side of the first pixel definition portion away from the substrate; the isolation structure encloses and forms a plurality of isolation openings; Preferably, the pixel opening corresponds one-to-one with the isolation opening; Preferably, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the corresponding isolation opening on the substrate; Preferably, the isolation structure includes a support portion and a shielding portion, the shielding portion being located on the side of the support portion away from the substrate, and the orthographic projection of the support portion on the substrate being located within the orthographic projection of the shielding portion on the substrate; Preferably, the isolation structure further includes an overlap portion, the overlap portion including a conductive structure; Preferably, the overlapping portion is located between the first pixel definition portion and the support portion, and the orthographic projection of the support portion on the substrate is located within the orthographic projection of the overlapping portion on the substrate.

5. The display panel as described in claim 4, characterized in that, The display panel also includes: A light-emitting unit, located in the display area, includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked in a direction away from the substrate; Preferably, the orthographic projection of the first pixel definition portion on the substrate and the orthographic projection of the first electrode on the substrate at least partially overlap; Preferably, the pixel opening exposes at least a portion of the first electrode; Preferably, the light-emitting layer and the second electrode are at least partially located within the isolation opening.

6. The display panel as described in claim 5, characterized in that, The light-emitting unit includes a first color light-emitting unit, a second color light-emitting unit, and a third color light-emitting unit for emitting different colors of light.

7. The display panel as described in claim 5, characterized in that, The display panel also includes: An encapsulation layer, at least partially located in the display area, and a touch layer disposed on the side of the encapsulation layer away from the substrate; Preferably, the encapsulation layer includes a first encapsulation layer, which is disposed within the isolation opening and covers the second electrode; Preferably, the encapsulation layer further includes a second encapsulation layer and a third encapsulation layer, wherein the second encapsulation layer covers the first encapsulation layer and the isolation structure, and the third encapsulation layer covers the second encapsulation layer.

8. The display panel as described in claim 1, characterized in that, The orthographic projection of the touch layer on the substrate does not overlap with the orthographic projection of the second planarization portion on the substrate; Preferably, the touch layer includes a first touch metal layer, a touch insulating layer, and a second touch metal layer stacked sequentially, wherein the second touch metal layer is disposed on the side of the first touch metal layer away from the substrate.

9. The display panel as described in claim 5, characterized in that, The display panel further includes a second metal layer, a third metal layer, and a fourth metal layer stacked between the substrate and the pixel definition layer. The fourth metal layer is the metal layer closest to the second electrode, and the conductive trace is disposed on the same layer as the fourth metal layer.

10. The display panel as claimed in claim 1, characterized in that, The non-display area includes a bending area, and the conductive trace and the second planarization portion are located in the bending area; Preferably, the conductive trace includes a pad.

11. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area at least partially surrounding the display area; the method includes: A conductive trace is formed on one side of the substrate, and the conductive trace is at least partially located in the non-display area; A first planarization layer is formed on the side of the conductive trace away from the substrate. The first planarization layer includes a first planarization portion located in the display area and a second planarization portion located in the non-display area. The orthographic projection of the conductive trace on the substrate is located within the orthographic projection of the second planarization portion on the substrate. A pixel definition layer is formed on the side of the first planarization layer away from the substrate; wherein, the pixel definition layer includes a first pixel definition portion located in the display area and a second pixel definition portion located in the non-display area, and a plurality of pixel openings are formed in the first pixel definition portion; the orthographic projection of the second planarization portion on the substrate and the orthographic projection of the second pixel definition portion on the substrate at least partially overlap; Multiple light-emitting units are formed, and the light-emitting units are at least partially located in the pixel opening; A touch layer is formed, and the second pixel definition portion is removed, such that the ratio of the thickness of the second flattened portion to the thickness of the first flattened portion is greater than or equal to 90% and less than or equal to 100%.

12. The method for manufacturing a display panel as described in claim 11, characterized in that, The orthographic projection of the touch layer on the substrate does not overlap with the orthographic projection of the second planarization portion on the substrate; Preferably, after the removal of the second pixel definition portion, the surface of the second planarization portion on the side away from the substrate is exposed; Preferably, before forming conductive traces on one side of the substrate, the method further includes: A second planarization layer is formed on one side of the substrate. The second planarization layer includes a third planarization portion located in the display area and a fourth planarization portion located in the non-display area. The third planarization portion is disposed on the side of the first planarization portion close to the substrate, and the fourth planarization portion is disposed on the side of the conductive trace close to the substrate. Preferably, the third planarization portion has the same thickness as the fourth planarization portion.

13. The method for manufacturing a display panel as described in claim 11, characterized in that, The formation of multiple light-emitting units includes: A first electrode layer is disposed on one side of the substrate, and a plurality of first electrodes are formed on the first electrode layer; An isolation structure is formed on the side of the first pixel definition portion away from the substrate, such that the isolation structure encloses a plurality of isolation openings, and a plurality of pixel openings are formed in the first pixel definition portion, such that the pixel openings expose at least a portion of the first electrode.

14. The method for manufacturing a display panel as described in claim 13, characterized in that, The light-emitting unit includes a first-color light-emitting unit, a second-color light-emitting unit, and a third-color light-emitting unit for emitting light of different colors; the isolation opening includes a first-type isolation opening, a second-type isolation opening, and a third-type isolation opening respectively corresponding to the first-color light-emitting unit, the second-color light-emitting unit, and the third-color light-emitting unit. The formation of multiple light-emitting units also includes: A first color light-emitting layer, a first color electrode, and a first color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure; The first color encapsulation layer, the first color light-emitting layer, and the first color electrode are patterned, and the first color encapsulation layer, the first color electrode, and the first color light-emitting layer are removed from the isolation structure, the second type of isolation opening, and the third type of isolation opening to form the first color light-emitting unit. A second color light-emitting layer, a second color electrode, and a second color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure. The second color encapsulation layer, the second color light-emitting layer, and the second color electrode are patterned, and the second color encapsulation layer, the second color electrode, and the second color light-emitting layer are removed from the isolation structure and from the first type of isolation opening and the third type of isolation opening to form the second color light-emitting unit. A third color light-emitting layer, a third color electrode, and a third color encapsulation layer are sequentially formed inside the isolation opening and on the isolation structure. The third color encapsulation layer, the third color light-emitting layer, and the third color electrode are patterned, and the third color encapsulation layer, the third color light-emitting layer, and the third color electrode are removed from the isolation structure and from the first type of isolation opening and the second type of isolation opening to form the third color light-emitting unit.

15. The method for manufacturing a display panel as described in claim 14, characterized in that, The formation of the touch layer includes: A first touch metal layer, a touch insulating layer, and a second touch metal layer are formed sequentially, with the second touch metal layer disposed on the side of the first touch metal layer away from the substrate; Preferably, prior to forming the touch layer, the method further includes: A second encapsulation layer and a third encapsulation layer are formed on the side of the first color encapsulation layer, the second color encapsulation layer and the third color encapsulation layer away from the substrate; Preferably, the first touch metal layer is located on the side of the third encapsulation layer away from the substrate.

16. A display device, characterized in that, The display panel includes those prepared by the method of any one of claims 10-14.

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