Heterojunction cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a heterojunction cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of solar cells. The heterojunction cell comprises N-type substrate silicon; the first side surface of the N-type substrate silicon comprises a first silicon oxide layer, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, an aluminum oxide layer, a first transparent conductive layer and a first grid line electrode which are stacked in sequence; the second side face of the N-type substrate silicon comprises a second silicon oxide layer, a second intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a third silicon oxide layer, a second transparent conductive layer and a second grid line electrode which are sequentially stacked. The first silicon oxide layer and the second silicon oxide layer are respectively combined with the corresponding intrinsic amorphous silicon to form a composite tunneling structure, so that the bottom layer interface recombination can be effectively reduced, and the open-circuit voltage of the heterojunction cell is improved; the aluminum oxide layer and the third silicon oxide layer are introduced as local passivation layers, so that the surface recombination of the heterojunction cell can be effectively reduced under the condition of thinning the silicon wafer, and the photoelectric conversion rate of the heterojunction cell is greatly improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to heterojunction cells and preparation methods thereof, and photovoltaic modules. Background Art

[0002] Crystalline silicon solar cells are one of the most common and widely used types of solar cells on the market. Crystalline silicon solar cells have attracted attention due to their high energy conversion efficiency, good stability and long service life. Heterojunction cells are a type of high-efficiency crystalline silicon solar cells that form a heterojunction by depositing an amorphous silicon film on a crystalline silicon substrate. This structure can provide excellent surface passivation and reduce the surface recombination of carriers, thereby increasing the open circuit voltage (Voc) and overall efficiency of the cell.

[0003] The existing HJT (heterojunction cell) process mainly uses an intrinsic amorphous silicon layer as an interface defect passivation layer between crystalline silicon and doped amorphous silicon. There are still interface defects such as dangling bonds at the interface between the intrinsic amorphous silicon layer and the crystalline silicon. In addition, the dangling bonds generated by the discontinuous crystal structure at the interface between the doped amorphous silicon surface layer and the transparent conductive oxide (TCO) will lead to carrier recombination, which in turn leads to serious surface recombination of heterojunction cells. In addition, in order to meet market demand, heterojunction cells need to develop towards thinner silicon wafers. As the silicon wafers become thinner, the surface defect density of the silicon wafers will increase, resulting in more serious surface recombination of heterojunction cells, thereby greatly reducing the photoelectric conversion rate of heterojunction cells.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of this application is to provide a heterojunction cell and its preparation method, and a photovoltaic module that can effectively reduce the interface defects and surface defects of the film layer in the heterojunction cell, can adapt to the development of thinning silicon wafers, and can greatly improve the photoelectric conversion rate of the heterojunction cell.

[0006] To achieve the above objectives, this application adopts the following technical solutions: A heterojunction battery, comprising an N-type substrate silicon; The N-type silicon substrate comprises a first side surface and a second side surface arranged opposite to the first side surface; the first side surface of the N-type silicon substrate comprises a first silicon oxide layer, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, an aluminum oxide layer, a first transparent conductive layer, and a first gate line electrode stacked in sequence; The second side surface of the N-type substrate silicon includes a second silicon oxide layer, a second intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a third silicon oxide layer, a second transparent conductive layer, and a second gate line electrode stacked in sequence.

[0007] In some embodiments, a first groove corresponding to the first gate line electrode is provided on the aluminum oxide layer; the projection of the first gate line electrode and the first groove in the thickness direction of the heterojunction battery overlap; And / or, a second groove corresponding to the second gate line electrode is arranged on the third silicon oxide layer; and the projection of the second gate line electrode and the second groove in the thickness direction of the heterojunction battery overlap.

[0008] In some embodiments, the width of the first groove is 20-40 μm; And / or, the width of the second groove is 20-40 μm.

[0009] In some embodiments, the thickness of the aluminum oxide layer is 1 to 5 nm, and the thickness of the third silicon oxide layer is 1 to 5 nm; And / or, the thickness of the first silicon oxide layer is 1-2 nm, and the thickness of the second silicon oxide layer is 1-2 nm.

[0010] In some embodiments, the thickness of the first intrinsic amorphous silicon layer is 5-8 nm, and the thickness of the second intrinsic amorphous silicon layer is 5-8 nm; And / or, the thickness of the P-type amorphous silicon layer is 20-30 nm, and the thickness of the N-type amorphous silicon layer is 20-30 nm; And / or, the thickness of the first transparent conductive layer is 80-120 nm, and the thickness of the second transparent conductive layer is 80-120 nm.

[0011] The present application also provides a method for preparing a heterojunction battery, comprising: Forming a first silicon oxide layer and a second silicon oxide layer respectively on a first side surface and a second side surface which are oppositely arranged on the N-type silicon substrate; forming a first intrinsic amorphous silicon layer on the first silicon oxide layer, and forming a second intrinsic amorphous silicon layer on the second silicon oxide layer; Preparing a P-type amorphous silicon layer on the first intrinsic amorphous silicon layer, and preparing an N-type amorphous silicon layer on the second intrinsic amorphous silicon layer; preparing an aluminum oxide layer on the P-type amorphous silicon layer, and preparing a third silicon oxide layer on the N-type amorphous silicon layer; preparing a first transparent conductive layer on the aluminum oxide layer, and preparing a second transparent conductive layer on the third silicon oxide layer; A first gate line electrode is formed on the first transparent conductive layer, and a second gate line electrode is formed on the second transparent conductive layer.

[0012] In some embodiments, the first silicon oxide layer is prepared by placing an N-type silicon substrate into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400-1600 sccm and oxygen with a flow rate of 400-600 sccm, and generating a first silicon oxide layer with a thickness of 1-2 nm by chemical vapor deposition reaction; And / or, the preparation method of the second silicon oxide layer is: placing an N-type substrate silicon into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400~1600sccm and oxygen with a flow rate of 400~600sccm, and generating a second silicon oxide layer with a thickness of 1~2nm through a chemical vapor deposition reaction.

[0013] In some embodiments, after the aluminum oxide layer is formed on the P-type amorphous silicon layer and before the first transparent conductive layer is formed on the aluminum oxide layer, the method further includes: forming a first groove on the aluminum oxide layer; the first groove coincides with a projection of the first gate electrode in the thickness direction of the heterojunction battery; And / or, after preparing the third silicon oxide layer on the N-type amorphous silicon layer and before preparing the second transparent conductive layer on the third silicon oxide layer, it also includes: opening a second groove on the third silicon oxide layer; the second groove coincides with the projection of the second gate line electrode in the thickness direction of the heterojunction battery.

[0014] In some embodiments, the width of the first groove is 20-40 μm, and the first groove is obtained by picosecond laser scribing with a wavelength of 532 nm; And / or, the width of the second groove is 20-40 μm, and the second groove is obtained by engraving with an ultraviolet nanosecond laser having a wavelength less than 400 nm.

[0015] The present application also provides a photovoltaic module, comprising the above-mentioned heterojunction battery; And / or, a heterojunction battery prepared by the above method.

[0016] In the technical solution of the present application, a first silicon oxide layer is introduced as a passivation contact layer at the interface between the first intrinsic amorphous silicon layer and the N-type substrate silicon, and a second silicon oxide layer is introduced as a passivation contact layer at the interface between the second intrinsic amorphous silicon layer and the N-type substrate silicon. The first silicon oxide layer and the second silicon oxide layer are respectively combined with the corresponding intrinsic amorphous silicon to form a composite tunneling structure, which can effectively reduce the bottom interface recombination and improve the open circuit voltage of the heterojunction battery; then, an aluminum oxide layer is introduced as a local passivation layer at the interface between the P-type amorphous silicon layer and the first transparent conductive layer, and a third silicon oxide layer is introduced as a local passivation layer at the interface between the N-type amorphous silicon layer and the second transparent conductive layer, which can effectively reduce the interface defects and surface defects of the film layer in the heterojunction battery body. In the case of thinning the silicon wafer, the surface recombination of the heterojunction battery can still be effectively reduced, thereby greatly improving the photoelectric conversion rate of the heterojunction battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0018] Figure 1 It is a schematic diagram of the structure of a heterojunction battery according to an embodiment of the present application.

[0019] Numbers in the figure: 1, N-type substrate silicon; 201, first silicon oxide layer; 202, first intrinsic amorphous silicon layer; 301, second silicon oxide layer; 302, second intrinsic amorphous silicon layer; 4, P-type amorphous silicon layer; 5, N-type amorphous silicon layer; 6, aluminum oxide layer; 61, first groove; 7, third silicon oxide layer; 71, second groove; 801, first transparent conductive layer; 802, second transparent conductive layer; 9, first gate line electrode; 10, second gate line electrode. DETAILED DESCRIPTION

[0020] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0021] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0022] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0025] The present application provides a heterojunction battery and a photovoltaic module, wherein a first silicon oxide layer 201 is introduced as a passivation contact layer at the interface between a first intrinsic amorphous silicon layer 202 and an N-type substrate silicon 1, and a second silicon oxide layer 301 is introduced as a passivation contact layer at the interface between a second intrinsic amorphous silicon layer 302 and an N-type substrate silicon 1. The first silicon oxide layer 201 and the second silicon oxide layer 301 are respectively combined with corresponding intrinsic amorphous silicon to form a composite tunneling structure, which can effectively reduce the bottom interface recombination and improve the open circuit voltage of the heterojunction battery; an aluminum oxide layer 6 is introduced as a local passivation layer at the interface between a P-type amorphous silicon layer 4 and a first transparent conductive layer 801, and a third silicon oxide layer 7 is introduced as a local passivation layer at the interface between an N-type amorphous silicon layer 5 and a second transparent conductive layer 802, which can effectively reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and in the case of thinning the silicon wafer, the surface recombination of the heterojunction battery can still be effectively reduced, thereby greatly improving the photoelectric conversion rate of the heterojunction battery.

[0026] A heterojunction battery comprises an N-type substrate silicon 1; The N-type silicon substrate 1 includes a first side surface and a second side surface arranged opposite to the first side surface; the first side surface of the N-type silicon substrate 1 includes a first silicon oxide layer 201, a first intrinsic amorphous silicon layer 202, a P-type amorphous silicon layer 4, an aluminum oxide layer 6, a first transparent conductive layer 801, and a first gate line electrode 9 stacked in sequence; The second side surface of the N-type silicon substrate 1 includes a second silicon oxide layer 301 , a second intrinsic amorphous silicon layer 302 , an N-type amorphous silicon layer 5 , a third silicon oxide layer 7 , a second transparent conductive layer 802 , and a second gate line electrode 10 stacked in sequence.

[0027] In the embodiment of the present application, the preparation methods of the first silicon oxide layer 201, the second silicon oxide layer 301, and the third silicon oxide layer 7 can be selected from one or more of thermal oxidation, plasma enhanced chemical vapor deposition, and electrochemical anodization. The thickness of the first silicon oxide layer 201, the second silicon oxide layer 301, and the third silicon oxide layer 7 can be set according to actual needs.

[0028] In the embodiment of the present application, the preparation methods of the first intrinsic amorphous silicon layer 202, the second intrinsic amorphous silicon layer 302, the P-type amorphous silicon layer 4, and the N-type amorphous silicon layer 5 can be selected from one or more of plasma enhanced chemical vapor deposition, chemical vapor deposition, low pressure chemical vapor deposition, and physical vapor deposition.

[0029] In the embodiment of the present application, the preparation methods of the first transparent conductive layer 801 and the second transparent conductive layer 802 can be selected from one or more of magnetron sputtering, chemical vapor deposition, and atomic layer deposition. The preparation method of the aluminum oxide layer 6 can be selected from one or more of chemical vapor deposition and atomic layer deposition.

[0030] In the embodiment of the present application, a first silicon oxide layer 201 is introduced as a passivation contact layer at the interface between the first intrinsic amorphous silicon layer 202 and the N-type substrate silicon 1, and a second silicon oxide layer 301 is introduced as a passivation contact layer at the interface between the second intrinsic amorphous silicon layer 302 and the N-type substrate silicon 1. The first silicon oxide layer 201 and the second silicon oxide layer 301 are respectively combined with the corresponding intrinsic amorphous silicon to form a composite tunneling structure, which can effectively reduce the bottom interface recombination and improve the open circuit voltage of the heterojunction battery; then, an aluminum oxide layer 6 is introduced as a local passivation layer at the interface between the P-type amorphous silicon layer 4 and the first transparent conductive layer 801, and a third silicon oxide layer 7 is introduced as a local passivation layer at the interface between the N-type amorphous silicon layer 5 and the second transparent conductive layer 802, which can effectively reduce the interface defects and surface defects of the film layer in the heterojunction battery body. In the case of thinning the silicon wafer, the surface recombination of the heterojunction battery can still be effectively reduced, thereby greatly improving the photoelectric conversion rate of the heterojunction battery.

[0031] In some embodiments, the aluminum oxide layer 6 is provided with a first groove 61 corresponding to the first gate electrode 9; the projections of the first gate electrode 9 and the first groove 61 in the thickness direction of the heterojunction battery overlap; And / or, a second groove 71 corresponding to the second gate line electrode 10 is provided on the third silicon oxide layer 7; and the projections of the second gate line electrode 10 and the second groove 71 in the thickness direction of the heterojunction battery overlap.

[0032] In the embodiment of the present application, the aluminum oxide layer 6 can be patterned and grooved by laser ablation to form a selective local passivation contact. The groove pattern is the same as the pattern of the first gate electrode 9, which is convenient for the subsequently deposited first transparent conductive layer 801 to contact with the P-type amorphous silicon layer 4, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery; the third silicon oxide layer 7 is patterned and grooved to form a selective local passivation contact. The groove pattern is the same as the pattern of the second gate electrode 10, which is convenient for the subsequently deposited second transparent conductive layer 802 to contact with the N-type amorphous silicon layer 5, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery.

[0033] In some embodiments, the width of the first groove 61 is 20-40 μm (e.g., 20 μm, 25 μm, 30 μm, 35 μm, 40 μm); And / or, the width of the second groove 71 is 20-40 μm (eg, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm).

[0034] In the embodiment of the present application, the width of the first groove 61 / the second groove 71 is optimized, the contact between the subsequently deposited transparent conductive layer and the amorphous silicon layer is further optimized, the contact resistance is optimized, and the interface defects and surface defects of the film layer in the heterojunction battery body can be further reduced, thereby improving the photoelectric conversion rate of the heterojunction battery. It should be noted that in the embodiment of the present application, the laser ablation method is mainly used for patterned grooving, and the depth of the first groove 61 / the second groove 71 can be adjusted according to the thickness of the aluminum oxide layer 6 / the third silicon oxide layer 7. Ideally, the depth of the first groove 61 / the second groove 71 can be consistent with the thickness of the aluminum oxide layer 6 / the third silicon oxide layer 7; however, due to the operational error of the laser ablation, the depth of the first groove 61 / the second groove 71 may also be different from the thickness of the aluminum oxide layer 6 / the third silicon oxide layer 7.

[0035] In some embodiments, the aluminum oxide layer 6 has a thickness of 1 to 5 nm (e.g., 1 nm, 2 nm, 3 nm, 4 nm, 5 nm), and the third silicon oxide layer 7 has a thickness of 1 to 5 nm (e.g., 1 nm, 2 nm, 3 nm, 4 nm, 5 nm); And / or, the thickness of the first silicon oxide layer 201 is 1~2nm (for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm), and the thickness of the second silicon oxide layer 301 is 1~2nm (for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm).

[0036] In the embodiment of the present application, optimizing the thickness of the first silicon oxide layer 201 and the second silicon oxide layer 301 as the passivation contact layer can further reduce the underlying interface recombination, improve the open circuit voltage of the heterojunction battery, and improve the photoelectric conversion rate of the heterojunction battery; optimizing the thickness of the aluminum oxide layer 6 and the third silicon oxide layer 7 as the local passivation layer can further reduce the interface defects and surface defects of the film layer in the heterojunction battery body, reduce the surface recombination of the heterojunction battery, and thus further improve the photoelectric conversion rate of the heterojunction battery.

[0037] In some embodiments, the thickness of the first intrinsic amorphous silicon layer 202 is 5-8 nm (e.g., 5 nm, 6 nm, 7 nm, 8 nm), and the thickness of the second intrinsic amorphous silicon layer 302 is 5-8 nm (e.g., 5 nm, 6 nm, 7 nm, 8 nm); and / or, the thickness of the P-type amorphous silicon layer 4 is 20-30 nm (for example, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm), and the thickness of the N-type amorphous silicon layer 5 is 20-30 nm (for example, 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm); And / or, the thickness of the first transparent conductive layer 801 is 80~120nm (for example, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm), and the thickness of the second transparent conductive layer 802 is 80~120nm (for example, 80nm, 85nm, 90nm, 95nm, 100nm, 105nm, 110nm, 115nm, 120nm).

[0038] In the embodiment of the present application, optimizing the thickness of each functional layer can further enhance the passivation effect of the heterojunction battery, reduce the interface defects and surface defects of the film layer in the heterojunction battery, reduce the surface recombination of the heterojunction battery, and thus further improve the photoelectric conversion rate of the heterojunction battery.

[0039] The present application also provides a method for preparing a heterojunction battery, comprising: A first silicon oxide layer 201 and a second silicon oxide layer 301 are respectively formed on a first side surface and a second side surface which are oppositely arranged on an N-type silicon substrate 1; Forming a first intrinsic amorphous silicon layer 202 on the first silicon oxide layer 201, and forming a second intrinsic amorphous silicon layer 302 on the second silicon oxide layer 301; A P-type amorphous silicon layer 4 is formed on the first intrinsic amorphous silicon layer 202 , and an N-type amorphous silicon layer 5 is formed on the second intrinsic amorphous silicon layer 302 ; An aluminum oxide layer 6 is formed on the P-type amorphous silicon layer 4, and a third silicon oxide layer 7 is formed on the N-type amorphous silicon layer 5; A first transparent conductive layer 801 is formed on the aluminum oxide layer 6, and a second transparent conductive layer 802 is formed on the third silicon oxide layer 7; A first gate line electrode 9 is formed on the first transparent conductive layer 801 , and a second gate line electrode 10 is formed on the second transparent conductive layer 802 .

[0040] In the embodiment of the present application, a first silicon oxide layer 201 is introduced as a passivation contact layer at the interface between the first intrinsic amorphous silicon layer 202 and the N-type substrate silicon 1, and a second silicon oxide layer 301 is introduced as a passivation contact layer at the interface between the second intrinsic amorphous silicon layer 302 and the N-type substrate silicon 1. The first silicon oxide layer 201 and the second silicon oxide layer 301 are respectively combined with the corresponding intrinsic amorphous silicon to form a composite tunneling structure, which can effectively reduce the bottom interface recombination and improve the open circuit voltage of the heterojunction battery; then an aluminum oxide layer 6 is introduced as a local passivation layer at the interface between the P-type amorphous silicon layer 4 and the first transparent conductive layer 801, and a third silicon oxide layer 7 is introduced as a local passivation layer at the interface between the N-type amorphous silicon layer 5 and the second transparent conductive layer 802, which can effectively reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and in the case of thinning the silicon wafer, the surface recombination of the heterojunction battery can still be effectively reduced, thereby greatly improving the photoelectric conversion rate of the heterojunction battery. The preparation method of the heterojunction battery provided by the present application has the advantages of simple preparation process and easy promotion and application.

[0041] In some embodiments, the preparation method of the first silicon oxide layer 201 is as follows: placing an N-type silicon substrate 1 into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400-1600 sccm (for example, 1400 sccm, 1500 sccm, 1600 sccm) and oxygen with a flow rate of 400-600 sccm (for example, 400 sccm, 500 sccm, 600 sccm), and generating a first silicon oxide layer 201 with a thickness of 1-2 nm (for example, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm) by chemical vapor deposition reaction; And / or, the preparation method of the second silicon oxide layer 301 is: placing an N-type substrate silicon 1 into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400~1600sccm (for example, 1400sccm, 1500sccm, 1600sccm) and oxygen with a flow rate of 400~600sccm (for example, 400sccm, 500sccm, 600sccm), and generating a second silicon oxide layer 301 with a thickness of 1~2nm (for example, 1nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm, 2nm) through a chemical vapor deposition reaction.

[0042] In the embodiment of the present application, the first silicon oxide layer 201 and the first intrinsic amorphous silicon layer 202 are combined into an enhanced passivation layer. The preparation process of the first silicon oxide layer 201 is optimized, and the bonding effect between the first silicon oxide layer 201 and the first intrinsic amorphous silicon layer 202 can be optimized. While optimizing the silicon-based surface passivation, it plays a role in preventing the mutual diffusion of impurity sources, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0043] In the embodiment of the present application, the second silicon oxide layer 301 and the second intrinsic amorphous silicon layer 302 are combined into an enhanced passivation layer, and the preparation process of the second silicon oxide layer 301 is optimized, so that the bonding effect between the second silicon oxide layer 301 and the second intrinsic amorphous silicon layer 302 can be optimized, and while optimizing the silicon-based surface passivation, it plays a role in preventing the mutual diffusion of impurity sources, thereby improving the photoelectric conversion rate of the heterojunction battery. It should be noted that the first silicon oxide layer 201 and the second silicon oxide layer 301 can be prepared at the same time, or the first silicon oxide layer 201 and the second silicon oxide layer 301 can be prepared separately as needed, and the preparation processes of the first silicon oxide layer 201 and the second silicon oxide layer 301 can be the same, or the preparation processes of the first silicon oxide layer 201 and the second silicon oxide layer 301 can be different.

[0044] In some embodiments, after the aluminum oxide layer 6 is formed on the P-type amorphous silicon layer 4 and before the first transparent conductive layer 801 is formed on the aluminum oxide layer 6, a first groove 61 is formed on the aluminum oxide layer 6; the first groove 61 coincides with a projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; And / or, after preparing the third silicon oxide layer 7 on the N-type amorphous silicon layer 5 and before preparing the second transparent conductive layer 802 on the third silicon oxide layer 7, it also includes opening a second groove 71 on the third silicon oxide layer 7; the second groove 71 coincides with the projection of the second gate line electrode 10 in the thickness direction of the heterojunction battery.

[0045] In the embodiment of the present application, the aluminum oxide layer 6 can be patterned and grooved by laser ablation to form a selective local passivation contact. The groove pattern is the same as the pattern of the first gate electrode 9, which is convenient for the subsequently deposited first transparent conductive layer 801 to contact with the P-type amorphous silicon layer 4, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery; the third silicon oxide layer 7 is patterned and grooved to form a selective local passivation contact. The groove pattern is the same as the pattern of the second gate electrode 10, which is convenient for the subsequently deposited second transparent conductive layer 802 to contact with the N-type amorphous silicon layer 5, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery.

[0046] In some embodiments, the width of the first groove 61 is 20-40 μm (e.g., 20 μm, 25 μm, 30 μm, 35 μm, 40 μm), and the first groove 61 is obtained by picosecond laser scribing with a wavelength of 532 nm; And / or, the width of the second groove 71 is 20-40 μm (for example, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm), and the second groove 71 is obtained by scribbling an ultraviolet nanosecond laser with a wavelength less than 400 nm.

[0047] In the embodiment of the present application, the width of the first groove 61 / the second groove 71 is optimized, the contact between the subsequently deposited transparent conductive layer and the amorphous silicon layer is further optimized, the contact resistance is optimized, and the interface defects and surface defects of the film layer in the heterojunction battery body can be further reduced, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0048] In the embodiment of the present application, the method of scratching the first groove 61 / the second groove 71 is optimized, which helps to improve the surface morphology of the first groove 61 / the second groove 71, is beneficial to the deposition effect of the transparent conductive layer, and further optimizes the contact between the subsequently deposited transparent conductive layer and the amorphous silicon layer, optimizes the contact resistance, and can further reduce the interface defects and surface defects of the film layer in the heterojunction battery body, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0049] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application. Specific embodiments Example 1 A heterojunction battery, such as Figure 1 As shown, it includes an N-type silicon substrate 1; The N-type silicon substrate 1 includes a first side surface and a second side surface arranged opposite to the first side surface; the first side surface of the N-type silicon substrate 1 includes a first silicon oxide layer 201, a first intrinsic amorphous silicon layer 202, a P-type amorphous silicon layer 4, an aluminum oxide layer 6, a first transparent conductive layer 801, and a first gate line electrode 9 stacked in sequence; The second side surface of the N-type silicon substrate 1 includes a second silicon oxide layer 301 , a second intrinsic amorphous silicon layer 302 , an N-type amorphous silicon layer 5 , a third silicon oxide layer 7 , a second transparent conductive layer 802 , and a second gate line electrode 10 stacked in sequence.

[0051] The method for preparing the heterojunction battery comprises: (1) Forming a first silicon oxide layer 201 and a second silicon oxide layer 301 on a first side surface and a second side surface disposed opposite to each other on an N-type silicon substrate 1, respectively; The preparation method of the first silicon oxide layer 201 and the second silicon oxide layer 301 is as follows: an N-type silicon substrate 1 is placed in a reaction chamber, tetraethoxysilane with a flow rate of 1400 sccm and oxygen with a flow rate of 400 sccm are introduced, and a first silicon oxide layer 201 with a thickness of 1 nm and a second silicon oxide layer 301 with a thickness of 1 nm are simultaneously generated through a chemical vapor deposition reaction; (2) preparing a first intrinsic amorphous silicon layer 202 with a thickness of 5 nm on the first silicon oxide layer 201 by chemical vapor deposition (CVD); preparing a second intrinsic amorphous silicon layer 302 with a thickness of 5 nm on the second silicon oxide layer 301 by chemical vapor deposition (CVD); (3) preparing a P-type amorphous silicon layer 4 with a thickness of 20 nm on the first intrinsic amorphous silicon layer 202 by chemical vapor deposition (CVD); preparing an N-type amorphous silicon layer 5 with a thickness of 20 nm on the second intrinsic amorphous silicon layer 302 by chemical vapor deposition (CVD); (4) preparing an aluminum oxide layer 6 with a thickness of 1 nm on the P-type amorphous silicon layer 4 by atomic layer deposition (ALD); preparing a third silicon oxide layer 7 with a thickness of 1 nm on the N-type amorphous silicon layer 5 by chemical vapor deposition reaction; (5) A first groove 61 with a width of 20 μm is scratched on the aluminum oxide layer 6 by a picosecond laser with a wavelength of 532 nm, and the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; a second groove 71 with a width of 20 μm is scratched on the third silicon oxide layer 7 by an ultraviolet nanosecond laser with a wavelength of 355 nm, and the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery; (6) preparing a first transparent conductive layer 801 with a thickness of 80 nm on the aluminum oxide layer 6 by physical vapor deposition (PVD); preparing a second transparent conductive layer 802 with a thickness of 80 nm on the third silicon oxide layer 7 by physical vapor deposition (PVD); (7) A metal grid line is prepared on the first transparent conductive layer 801 by screen printing, and a metal grid line is prepared on the second transparent conductive layer 802 by screen printing, and then the metal grid lines are sent to a sintering process to form a first grid line electrode 9 and a second grid line electrode 10.

[0052] Example 2 A heterojunction battery, such as Figure 1 As shown, it includes an N-type silicon substrate 1; The N-type silicon substrate 1 includes a first side surface and a second side surface arranged opposite to the first side surface; the first side surface of the N-type silicon substrate 1 includes a first silicon oxide layer 201, a first intrinsic amorphous silicon layer 202, a P-type amorphous silicon layer 4, an aluminum oxide layer 6, a first transparent conductive layer 801, and a first gate line electrode 9 stacked in sequence; The second side surface of the N-type silicon substrate 1 includes a second silicon oxide layer 301 , a second intrinsic amorphous silicon layer 302 , an N-type amorphous silicon layer 5 , a third silicon oxide layer 7 , a second transparent conductive layer 802 , and a second gate line electrode 10 stacked in sequence.

[0053] The method for preparing the heterojunction battery comprises: (1) Forming a first silicon oxide layer 201 and a second silicon oxide layer 301 on a first side surface and a second side surface disposed opposite to each other on an N-type silicon substrate 1, respectively; The preparation method of the first silicon oxide layer 201 and the second silicon oxide layer 301 is as follows: an N-type silicon substrate 1 is placed in a reaction chamber, tetraethoxysilane with a flow rate of 1600 sccm and oxygen with a flow rate of 600 sccm are introduced, and a first silicon oxide layer 201 with a thickness of 2 nm and a second silicon oxide layer 301 with a thickness of 2 nm are simultaneously generated through a chemical vapor deposition reaction; (2) preparing a first intrinsic amorphous silicon layer 202 with a thickness of 8 nm on the first silicon oxide layer 201 by chemical vapor deposition (CVD); preparing a second intrinsic amorphous silicon layer 302 with a thickness of 8 nm on the second silicon oxide layer 301 by chemical vapor deposition (CVD); (3) preparing a P-type amorphous silicon layer 4 with a thickness of 30 nm on the first intrinsic amorphous silicon layer 202 by chemical vapor deposition (CVD); preparing an N-type amorphous silicon layer 5 with a thickness of 30 nm on the second intrinsic amorphous silicon layer 302 by chemical vapor deposition (CVD); (4) preparing an aluminum oxide layer 6 with a thickness of 5 nm on the P-type amorphous silicon layer 4 by atomic layer deposition (ALD); preparing a third silicon oxide layer 7 with a thickness of 5 nm on the N-type amorphous silicon layer 5 by chemical vapor deposition reaction; (5) A first groove 61 with a width of 40 μm is scratched on the aluminum oxide layer 6 by a picosecond laser with a wavelength of 532 nm, and the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; a second groove 71 with a width of 40 μm is scratched on the third silicon oxide layer 7 by an ultraviolet nanosecond laser with a wavelength of 355 nm, and the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery; (6) preparing a first transparent conductive layer 801 with a thickness of 120 nm on the aluminum oxide layer 6 by physical vapor deposition (PVD); preparing a second transparent conductive layer 802 with a thickness of 120 nm on the third silicon oxide layer 7 by physical vapor deposition (PVD); (7) A metal grid line is prepared on the first transparent conductive layer 801 by screen printing, and a metal grid line is prepared on the second transparent conductive layer 802 by screen printing, and then the metal grid lines are sent to a sintering process to form a first grid line electrode 9 and a second grid line electrode 10.

[0054] Example 3 A heterojunction battery, such as Figure 1 As shown, it includes an N-type silicon substrate 1; The N-type silicon substrate 1 includes a first side surface and a second side surface arranged opposite to the first side surface; the first side surface of the N-type silicon substrate 1 includes a first silicon oxide layer 201, a first intrinsic amorphous silicon layer 202, a P-type amorphous silicon layer 4, an aluminum oxide layer 6, a first transparent conductive layer 801, and a first gate line electrode 9 stacked in sequence; The second side surface of the N-type silicon substrate 1 includes a second silicon oxide layer 301 , a second intrinsic amorphous silicon layer 302 , an N-type amorphous silicon layer 5 , a third silicon oxide layer 7 , a second transparent conductive layer 802 , and a second gate line electrode 10 stacked in sequence.

[0055] The method for preparing the heterojunction battery comprises: (1) Forming a first silicon oxide layer 201 and a second silicon oxide layer 301 on a first side surface and a second side surface disposed opposite to each other on an N-type silicon substrate 1, respectively; The preparation method of the first silicon oxide layer 201 and the second silicon oxide layer 301 is as follows: an N-type silicon substrate 1 is placed in a reaction chamber, tetraethoxysilane with a flow rate of 1500 sccm and oxygen with a flow rate of 500 sccm are introduced, and a first silicon oxide layer 201 with a thickness of 1.2 nm and a second silicon oxide layer 301 with a thickness of 1.2 nm are simultaneously generated through a chemical vapor deposition reaction; (2) preparing a first intrinsic amorphous silicon layer 202 with a thickness of 6 nm on the first silicon oxide layer 201 by chemical vapor deposition (CVD); preparing a second intrinsic amorphous silicon layer 302 with a thickness of 6 nm on the second silicon oxide layer 301 by chemical vapor deposition (CVD); (3) preparing a P-type amorphous silicon layer 4 with a thickness of 25 nm on the first intrinsic amorphous silicon layer 202 by chemical vapor deposition (CVD); preparing an N-type amorphous silicon layer 5 with a thickness of 25 nm on the second intrinsic amorphous silicon layer 302 by chemical vapor deposition (CVD); (4) preparing an aluminum oxide layer 6 with a thickness of 3 nm on the P-type amorphous silicon layer 4 by atomic layer deposition (ALD); preparing a third silicon oxide layer 7 with a thickness of 3 nm on the N-type amorphous silicon layer 5 by chemical vapor deposition reaction; (5) A first groove 61 with a width of 30 μm is scratched on the aluminum oxide layer 6 by a picosecond laser with a wavelength of 532 nm, and the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; a second groove 71 with a width of 30 μm is scratched on the third silicon oxide layer 7 by an ultraviolet nanosecond laser with a wavelength of 355 nm, and the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery; (6) preparing a first transparent conductive layer 801 with a thickness of 100 nm on the aluminum oxide layer 6 by physical vapor deposition (PVD); preparing a second transparent conductive layer 802 with a thickness of 100 nm on the third silicon oxide layer 7 by physical vapor deposition (PVD); (7) A metal grid line is prepared on the first transparent conductive layer 801 by screen printing, and a metal grid line is prepared on the second transparent conductive layer 802 by screen printing, and then the metal grid lines are sent to a sintering process to form a first grid line electrode 9 and a second grid line electrode 10.

[0056] Example 4 The heterojunction battery of Example 4 was prepared by referring to the preparation method of Example 1, except that: Step (1) in Example 4 is: preparing a first silicon oxide layer 201 and a second silicon oxide layer 301 on a first side surface and a second side surface that are oppositely arranged on an N-type silicon substrate 1, respectively; the preparation method of the first silicon oxide layer 201 and the second silicon oxide layer 301 is: placing the N-type silicon substrate 1 in a reaction chamber, introducing tetraethoxysilane with a flow rate of 1300 sccm and oxygen with a flow rate of 300 sccm, and through a chemical vapor deposition reaction, simultaneously generating a first silicon oxide layer 201 with a thickness of 1 nm and a second silicon oxide layer 301 with a thickness of 1 nm.

[0057] Example 5 The heterojunction battery of Example 5 was prepared by referring to the preparation method of Example 1, except that: Step (1) in Example 5 is: preparing a first silicon oxide layer 201 and a second silicon oxide layer 301 on a first side surface and a second side surface that are oppositely arranged on an N-type silicon substrate 1, respectively; the preparation method of the first silicon oxide layer 201 and the second silicon oxide layer 301 is: placing the N-type silicon substrate 1 in a reaction chamber, introducing tetraethoxysilane with a flow rate of 1700sccm and oxygen with a flow rate of 700sccm, and through a chemical vapor deposition reaction, simultaneously generating a first silicon oxide layer 201 with a thickness of 1nm and a second silicon oxide layer 301 with a thickness of 1nm.

[0058] Example 6 The heterojunction battery of Example 6 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 6 is: using a picosecond laser with a wavelength of 532 nm to scribe a first groove 61 with a width of 18 μm on the aluminum oxide layer 6, wherein the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; using an ultraviolet nanosecond laser with a wavelength of 355 nm to scribe a second groove 71 with a width of 18 μm on the third silicon oxide layer 7, wherein the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery.

[0059] Example 7 The heterojunction battery of Example 7 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 7 is: using a picosecond laser with a wavelength of 532 nm to scribe a first groove 61 with a width of 45 μm on the aluminum oxide layer 6, wherein the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; using an ultraviolet nanosecond laser with a wavelength of 355 nm to scribe a second groove 71 with a width of 45 μm on the third silicon oxide layer 7, wherein the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery.

[0060] Example 8 The heterojunction battery of Example 8 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 8 is: using a picosecond laser with a wavelength of 532 nm to carve a first groove 61 with a width of 20 μm on the aluminum oxide layer 6, wherein the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; and the second groove 71 is not carved.

[0061] Example 9 The heterojunction battery of Example 9 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 9 is: using an ultraviolet nanosecond laser with a wavelength of 355 nm to carve a second groove 71 with a width of 20 μm on the third silicon oxide layer 7, wherein the second groove 71 coincides with the projection of the second gate line electrode 10 in the thickness direction of the heterojunction battery; and the first groove 61 is not carved.

[0062] Example 10 The heterojunction battery of Example 10 was prepared by referring to the preparation method of Example 1, except that: in Example 10, neither the first groove 61 nor the second groove 71 was engraved.

[0063] Embodiment 11 The heterojunction battery of Example 11 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 11 is: using an infrared laser with a wavelength of 780 nm to scratch a first groove 61 with a width of 20 μm on the aluminum oxide layer 6, wherein the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; using an infrared laser with a wavelength of 780 nm to scratch a second groove 71 with a width of 20 μm on the third silicon oxide layer 7, wherein the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery.

[0064] Example 12 The heterojunction battery of Example 12 was prepared by referring to the preparation method of Example 1, except that: Step (5) in Example 12 is: using a blue laser with a wavelength of 445 nm to scribe a first groove 61 with a width of 20 μm on the aluminum oxide layer 6, wherein the first groove 61 coincides with the projection of the first gate electrode 9 in the thickness direction of the heterojunction battery; using a blue laser with a wavelength of 445 nm to scribe a second groove 71 with a width of 20 μm on the third silicon oxide layer 7, wherein the second groove 71 coincides with the projection of the second gate electrode 10 in the thickness direction of the heterojunction battery.

[0065] Examples 13-16 The heterojunction batteries of Examples 13-16 were prepared by referring to the preparation method of Example 1, except that the thickness of each layer in Examples 13-16 was different from that in the example, and the thickness data of each layer are shown in Table 1 below.

[0066] The thickness parameters of each layer in the above-mentioned embodiments 13-16 are shown in the following Table 1.

[0067] Table 1

[0068] The device performance data of the above embodiments and comparative examples are shown in Table 2 below.

[0069] Table 2

[0070] It can be seen from the test results in Table 2 above that the first silicon oxide layer 201 is introduced as a passivation contact layer at the interface between the first intrinsic amorphous silicon layer 202 and the N-type substrate silicon 1, and the second silicon oxide layer 301 is introduced as a passivation contact layer at the interface between the second intrinsic amorphous silicon layer 302 and the N-type substrate silicon 1. The first silicon oxide layer 201 and the second silicon oxide layer 301 are respectively combined with the corresponding intrinsic amorphous silicon to form a composite tunneling structure, which can effectively reduce the bottom interface recombination and improve the open circuit voltage of the heterojunction battery; then, the aluminum oxide layer 6 is introduced as a local passivation layer at the interface between the P-type amorphous silicon layer 4 and the first transparent conductive layer 801, and the third silicon oxide layer 7 is introduced as a local passivation layer at the interface between the N-type amorphous silicon layer 5 and the second transparent conductive layer 802, which can effectively reduce the interface defects and surface defects of the film layer in the heterojunction battery body. In the case of thinning the silicon wafer, the surface recombination of the heterojunction battery can still be effectively reduced, thereby greatly improving the photoelectric conversion rate of the heterojunction battery.

[0071] It can be seen from the detection data of the above-mentioned Examples 1 and 8-10 that the aluminum oxide layer 6 is patterned and grooved to form a selective local passivation contact, and the groove pattern is the same as the pattern of the first gate electrode 9, which is convenient for the subsequently deposited first transparent conductive layer 801 to contact with the P-type amorphous silicon layer 4, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery; the third silicon oxide layer 7 is patterned and grooved to form a selective local passivation contact, and the groove pattern is the same as the pattern of the second gate electrode 10, which is convenient for the subsequently deposited second transparent conductive layer 802 to contact with the N-type amorphous silicon layer 5, optimize the contact resistance, reduce the interface defects and surface defects of the film layer in the heterojunction battery body, and improve the photoelectric conversion rate of the heterojunction battery.

[0072] It can be seen from the detection data of the above-mentioned Example 1 and Examples 6-7 that optimizing the width of the first groove 61 / the second groove 71 can further optimize the contact between the subsequently deposited transparent conductive layer and the amorphous silicon layer, optimize the contact resistance, and further reduce the interface defects and surface defects of the film layer in the heterojunction battery body, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0073] It can be seen from the detection data of the above-mentioned Example 1 and Examples 15-16 that optimizing the thickness of the first silicon oxide layer 201 and the second silicon oxide layer 301 as the passivation contact layer can further reduce the underlying interface recombination, increase the open circuit voltage of the heterojunction battery, and improve the photoelectric conversion rate of the heterojunction battery; optimizing the thickness of the aluminum oxide layer 6 and the third silicon oxide layer 7 as the local passivation layer can further reduce the interface defects and surface defects of the film layer in the heterojunction battery body, reduce the surface recombination of the heterojunction battery, and thus further improve the photoelectric conversion rate of the heterojunction battery.

[0074] It can be seen from the detection data of the above-mentioned embodiment 1 and embodiments 4-5 that the first silicon oxide layer 201 and the first intrinsic amorphous silicon layer 202 are combined into an enhanced passivation layer. By optimizing the preparation process of the first silicon oxide layer 201, the bonding effect between the first silicon oxide layer 201 and the first intrinsic amorphous silicon layer 202 can be optimized, and while optimizing the silicon-based surface passivation, it plays a role in preventing the mutual diffusion of impurity sources, thereby improving the photoelectric conversion rate of the heterojunction battery; the second silicon oxide layer 301 and the second intrinsic amorphous silicon layer 302 are combined into an enhanced passivation layer. By optimizing the preparation process of the second silicon oxide layer 301, the bonding effect between the second silicon oxide layer 301 and the second intrinsic amorphous silicon layer 302 can be optimized, and while optimizing the silicon-based surface passivation, it plays a role in preventing the mutual diffusion of impurity sources, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0075] It can be seen from the detection data of the above-mentioned Example 1 and Examples 11-12 that optimizing the scratching method of the first groove 61 / the second groove 71 is helpful to improve the surface morphology of the first groove 61 / the second groove 71, which is beneficial to the deposition effect of the transparent conductive layer, and further optimizes the contact between the subsequently deposited transparent conductive layer and the amorphous silicon layer, optimizes the contact resistance, and can further reduce the interface defects and surface defects of the film layer in the heterojunction battery body, thereby improving the photoelectric conversion rate of the heterojunction battery.

[0076] It can be seen from the test data of the above-mentioned Example 1 and Examples 13-14 that the scheme of the embodiments of the present application can effectively reduce the interface defects and surface defects of the film layer inside the heterojunction battery. Even in the case of thinning the silicon wafer, it can still effectively reduce the surface recombination of the heterojunction battery and greatly improve the photoelectric conversion rate of the heterojunction battery.

[0077] The present application also provides a photovoltaic module, including the above-mentioned heterojunction battery; and / or, including the heterojunction battery prepared by the above-mentioned method.

[0078] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0079] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0080] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0081] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A heterojunction battery, characterized in that: including N-type substrate silicon; The N-type silicon substrate includes a first side surface and a second side surface arranged opposite to the first side surface; The first side surface of the N-type substrate silicon comprises a first silicon oxide layer, a first intrinsic amorphous silicon layer, a P-type amorphous silicon layer, an aluminum oxide layer, a first transparent conductive layer, and a first gate line electrode stacked in sequence; The second side surface of the N-type substrate silicon includes a second silicon oxide layer, a second intrinsic amorphous silicon layer, an N-type amorphous silicon layer, a third silicon oxide layer, a second transparent conductive layer, and a second gate line electrode stacked in sequence.

2. The heterojunction battery according to claim 1, characterized in that: The aluminum oxide layer is provided with a first groove corresponding to the first gate line electrode; the projection of the first gate line electrode and the first groove in the thickness direction of the heterojunction battery overlap; And / or, a second groove corresponding to the second gate line electrode is arranged on the third silicon oxide layer; and the projection of the second gate line electrode and the second groove in the thickness direction of the heterojunction battery overlap.

3. The heterojunction battery according to claim 2, characterized in that: The width of the first groove is 20-40 μm; And / or, the width of the second groove is 20-40 μm.

4. The heterojunction battery according to claim 1, characterized in that: The thickness of the aluminum oxide layer is 1-5 nm, and the thickness of the third silicon oxide layer is 1-5 nm; And / or, the thickness of the first silicon oxide layer is 1-2 nm, and the thickness of the second silicon oxide layer is 1-2 nm.

5. The heterojunction battery according to claim 1, characterized in that: The thickness of the first intrinsic amorphous silicon layer is 5-8 nm, and the thickness of the second intrinsic amorphous silicon layer is 5-8 nm; And / or, the thickness of the P-type amorphous silicon layer is 20-30 nm, and the thickness of the N-type amorphous silicon layer is 20-30 nm; And / or, the thickness of the first transparent conductive layer is 80-120 nm, and the thickness of the second transparent conductive layer is 80-120 nm.

6. A method for preparing a heterojunction battery, characterized in that: include: Forming a first silicon oxide layer and a second silicon oxide layer respectively on a first side surface and a second side surface which are oppositely arranged on the N-type silicon substrate; forming a first intrinsic amorphous silicon layer on the first silicon oxide layer, and forming a second intrinsic amorphous silicon layer on the second silicon oxide layer; Preparing a P-type amorphous silicon layer on the first intrinsic amorphous silicon layer, and preparing an N-type amorphous silicon layer on the second intrinsic amorphous silicon layer; preparing an aluminum oxide layer on the P-type amorphous silicon layer, and preparing a third silicon oxide layer on the N-type amorphous silicon layer; preparing a first transparent conductive layer on the aluminum oxide layer, and preparing a second transparent conductive layer on the third silicon oxide layer; A first gate line electrode is formed on the first transparent conductive layer, and a second gate line electrode is formed on the second transparent conductive layer.

7. The method for preparing a heterojunction battery according to claim 6, characterized in that: The preparation method of the first silicon oxide layer is as follows: placing an N-type silicon substrate into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400-1600 sccm and oxygen with a flow rate of 400-600 sccm, and generating a first silicon oxide layer with a thickness of 1-2 nm through a chemical vapor deposition reaction; And / or, the preparation method of the second silicon oxide layer is: placing an N-type substrate silicon into a reaction chamber, introducing tetraethoxysilane with a flow rate of 1400~1600sccm and oxygen with a flow rate of 400~600sccm, and generating a second silicon oxide layer with a thickness of 1~2nm through a chemical vapor deposition reaction.

8. The method for preparing a heterojunction battery according to claim 6, characterized in that: After the aluminum oxide layer is formed on the P-type amorphous silicon layer and before the first transparent conductive layer is formed on the aluminum oxide layer, the method further includes: forming a first groove on the aluminum oxide layer; the first groove coincides with a projection of the first gate line electrode in the thickness direction of the heterojunction battery; And / or, after preparing the third silicon oxide layer on the N-type amorphous silicon layer and before preparing the second transparent conductive layer on the third silicon oxide layer, it also includes: opening a second groove on the third silicon oxide layer; the second groove coincides with the projection of the second gate line electrode in the thickness direction of the heterojunction battery.

9. The method for preparing a heterojunction battery according to claim 8, characterized in that: The width of the first groove is 20-40 μm, and the first groove is obtained by picosecond laser scribing with a wavelength of 532 nm; And / or, the width of the second groove is 20-40 μm, and the second groove is obtained by engraving with an ultraviolet nanosecond laser having a wavelength less than 400 nm.

10. A photovoltaic module, characterized in that: A heterojunction battery as claimed in any one of claims 1 to 5; And / or, comprising a heterojunction battery prepared by the method according to any one of claims 6-9.

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