Solar cell, photovoltaic module and semiconductor substrate

Abstract

The invention discloses a solar cell, a photovoltaic module and a semiconductor substrate, and relates to the technical field of photovoltaics, so that a passivation layer has a good passivation effect on the semiconductor substrate, and the contact performance of a doped semiconductor layer and an electrode and the shaping of the electrode are improved. The solar cell includes a semiconductor substrate and a passivation layer. At least one of the first surface and the second surface of the semiconductor substrate is a target surface. A part of the surface of one side, departing from the semiconductor substrate, of the passivation layer is provided with a plurality of tower-footing-like texture structures which are recessed towards one side close to the semiconductor substrate. The plurality of tower footing-like texture structures comprise a first tower footing-like texture structure and a second tower footing-like texture structure. All corners in the bottom surface of the first-class tower footing texture structure are round-like corners, part of the corners included in the bottom surface of the second-class tower footing texture structure are round-like corners, and the other corners are sharp-like corners. And in the bottom surface of the same second-class tower footing-shaped texture structure, the number of the similar round corners is greater than or equal to the number of the similar sharp corners.

Description

Technical Field

[0001] The invention relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a semiconductor substrate. Background Art

[0002] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has received more and more attention in recent years. Correspondingly, the application scope of photovoltaic solar cells based on the photoelectric effect is also becoming wider and wider.

[0003] However, it is difficult for existing solar cells to achieve both good passivation effects and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells. Summary of the invention

[0004] The object of the present invention is to provide a solar cell, a photovoltaic module and a semiconductor substrate, which are used to make the passivation layer have a good passivation effect on the semiconductor substrate, while increasing the surface roughness of the passivation layer away from the semiconductor substrate by arranging a second type of tower base-shaped texture structure with a sharp corner on the bottom surface, which is beneficial to increase the specific surface area of ​​the doped semiconductor layer in the passivation layer or formed between the passivation layer and the semiconductor substrate, improve the contact performance between the doped semiconductor layer and the electrode, and the shaping of the electrode, thereby improving the conversion efficiency of the solar cell.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a solar cell, which comprises: a semiconductor substrate and a passivation layer. The semiconductor substrate comprises a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. The passivation layer is arranged on the target surface. Part of the surface of the passivation layer on the side away from the semiconductor substrate has a plurality of tower-like texture structures that are recessed toward the side close to the semiconductor substrate. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than or equal to the number of quasi-sharp corners.

[0006] In the case of adopting the above technical solution, the passivation layer is arranged on the target surface of the semiconductor substrate, and one side of the target surface of the semiconductor substrate can be passivated to reduce the carrier recombination rate. In addition, the side of the passivation layer away from the semiconductor substrate has a plurality of quasi-tower-shaped texture structures. Under the same conditions of other factors, compared with the texture structures with a large degree of undulation such as the pyramid-type velvet structure, the degree of undulation of the quasi-tower-shaped texture structure without a spire is relatively small. In addition, each corner in the bottom surface of the first type of tower-shaped texture structure included in the plurality of quasi-tower-shaped texture structures, and most of the corners in the bottom surface of the second type of tower-shaped texture structure are quasi-rounded corners. Compared with the quasi-pointed corners, the quasi-rounded corner transition of the bottom surface is more rounded and flat, so that the boundary transition of the quasi-tower-shaped texture structure at the quasi-rounded corner is more moderate and blurred, so that the surface of the side of the passivation layer away from the semiconductor substrate is relatively flat from a macroscopic perspective. Moreover, in the actual manufacturing process, the passivation layer is formed on the target surface of the semiconductor substrate through deposition and other processes, and the surface undulation morphology of the passivation layer on the side away from the semiconductor substrate will also be affected by the surface undulation morphology of the target surface, and the corresponding surface undulation morphology of the passivation layer on the side away from the semiconductor substrate can also reflect the surface undulation morphology of the target surface of the semiconductor substrate to a certain extent. Based on this, when the surface of the side of the passivation layer away from the semiconductor substrate is relatively flat macroscopically, the target surface of the semiconductor substrate is also roughly a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer on the target surface, and then it is conducive to improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell.

[0007] In addition, the bottom surface of the second type of tower base-shaped texture structure also includes sharp corners. Compared with rounded corners, the transition of sharp corners is relatively obvious, and its fluctuation is greater, which is conducive to increasing the specific surface area of ​​the passivation layer away from the semiconductor substrate. Moreover, in the bottom surface of the same second type of tower base-shaped texture structure, the number of sharp corners is greater than or equal to the number of rounded corners, ensuring that the passivation layer is macroscopically flat on the side away from the semiconductor substrate, while making the passivation layer away from the semiconductor substrate. The side has a relatively large surface roughness at the microscopic level, so that the doped semiconductor layer included in the passivation layer, or the doped semiconductor layer formed between the passivation layer and the semiconductor substrate has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0008] As a possible implementation scheme, in the same passivation layer on a side facing away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structure is greater than the distribution density of the second type of texture structure.

[0009] When the above technical solution is adopted, all corners in the bottom surface of the first type of tower base-shaped texture structure are quasi-rounded corners, and the proportion of quasi-rounded corners in its bottom surface is relatively large compared to the proportion of quasi-rounded corners in the second type of tower base-shaped texture structure. And, as mentioned above, compared with the quasi-sharp corners, the quasi-rounded corner transition of the bottom surface is smoother and flatter. Therefore, when the distribution density of the first type of tower base-shaped texture structure is greater than the distribution density of the second type of texture structure, it is beneficial to further improve the macroscopic surface flatness of the side surface of the passivation layer away from the semiconductor substrate, and further improve the formation quality and passivation effect of the passivation layer.

[0010] As a possible implementation scheme, in the surface of the area with the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, and within the range of 1cm×1cm, the distribution density of the first type of tower-shaped texture structure is greater than or equal to 80% and less than or equal to 99%. In this case, each corner is a first type of tower-shaped texture structure with a rounded corner having a small degree of undulation, and its distribution density on the side of the passivation layer away from the semiconductor substrate is relatively large, which is conducive to further improving the surface flatness of the side of the passivation layer away from the semiconductor substrate on a macroscopic level, and further improving the formation quality and passivation effect of the passivation layer.

[0011] As a possible implementation scheme, on the side of the passivation layer away from the semiconductor substrate, the number of the remaining first-type tower-shaped texture structures adjacent to the single first-type tower-shaped texture structure is greater than the number of the second-type tower-shaped texture structures. In this case, it is beneficial to increase the distribution density of the first-type tower-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, further improve the macroscopic surface flatness of the side of the passivation layer away from the semiconductor substrate, and further improve the formation quality and passivation effect of the passivation layer.

[0012] As a possible implementation scheme, the surface of the passivation layer facing away from the semiconductor substrate is a quasi-rectangular surface. In the quasi-rectangular surface, the corresponding areas of the four corners are the four corner areas, the corresponding areas of the four contour edges are the peripheral areas, and the area located inside the four corner areas and the peripheral areas is the middle area. Among them, the concave depth of the quasi-tower-like texture structure located in the peripheral area is greater than the concave depth of the quasi-tower-like texture structure located in the middle area; and / or, the concave depth of the quasi-tower-like texture structure located in the four corner areas is less than the concave depth of the quasi-tower-like texture structure located in the middle area.

[0013] When the above technical solution is adopted, in the actual manufacturing process, when the passivation layer is deposited on the semiconductor substrate to form the passivation layer, the growth rate of the passivation layer in the peripheral area of ​​the semiconductor substrate is relatively fast, which easily makes the deposition thickness of the passivation layer in the peripheral area relatively large. In this case, compared with the four corner areas and the middle area of ​​the passivation layer, the concave depth of the tower-like texture structure located in the peripheral area is relatively large, which is conducive to increasing the specific surface area of ​​the passivation layer located in the peripheral area, and the corresponding target surface of the semiconductor substrate corresponding to the above-mentioned peripheral area The partial surface also has a relatively large specific surface area. The deposited film thickness of the passivation layer is inversely proportional to the specific surface area of ​​the target surface. Therefore, increasing the specific surface area of ​​the portion of the target surface corresponding to the above-mentioned peripheral area can prevent the thickness of the passivation layer in the peripheral area from being too large due to the high deposition rate, which is conducive to improving the thickness uniformity of different areas of the passivation layer. In addition, due to the influence of operations such as crystal pulling or cutting, the number of defects in the corresponding four corner areas of the semiconductor substrate is relatively large. Secondly, the recessed depth of the tower-like texture structure located in the four corner areas is small, which is beneficial to reducing the surface roughness of the passivation layer in the four corner areas. The target surface of the corresponding semiconductor substrate corresponding to the above-mentioned four corner areas also has a relatively small surface roughness. There is no need to increase the etching depth of the four corner areas in order to obtain a tower-like texture structure with a larger recessed depth. Correspondingly, the number of defects exposed by etching in the corresponding four corner areas of the semiconductor substrate can be reduced, and it is beneficial to improve the formation quality and film thickness of the passivation layer in the four corner areas, and improve the passivation effect of the passivation layer in the four corner areas. The concave depth of the tower-like texture structure in the middle area of ​​the passivation layer is moderate, which can prevent the passivation effect of the passivation layer in the middle area from being affected by the excessive concave depth of the tower-like texture structure in the middle area, and can also prevent the contact area between the part of the doped semiconductor layer corresponding to the middle area and the electrode from being too small due to the excessive concave depth of the tower-like texture structure in the middle area. This further improves the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, so that the passivation effect and contact performance in the middle area are balanced, which is beneficial to improving the conversion efficiency of solar cells.

[0014] As a possible implementation scheme, along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner regions is less than or equal to 2 cm. In this case, it is possible to prevent the range of the four corner regions from being too large, which may result in too small a contact area between the portion of the doped semiconductor layer near the four corner regions and the electrode, thereby ensuring good contact performance between the doped semiconductor layer and the electrode, and ensuring that the electrode has strong adhesion and good shaping on the portion of the doped semiconductor layer near the four corner regions.

[0015] As a possible implementation scheme, the width of the peripheral area along the direction from the edge of the quasi-rectangular surface to the geometric center is less than or equal to 3 cm. In this case, it can be prevented that the width range of the peripheral area is too large, which causes the deposition thickness of the passivation layer in the middle area with a relatively small corresponding deposition rate to be too small, thereby ensuring that the passivation layer has a higher passivation effect in the middle area.

[0016] As a possible implementation scheme, along a direction parallel to the target surface, the concave depth of one side of at least one of the tower base-like texture structures is smaller than the concave depth of the other side thereof.

[0017] In the case of adopting the above technical solution, in the actual application process, the passivation layer will include a surface passivation layer such as aluminum oxide with a chemical passivation effect, or the above surface passivation layer is arranged between the passivation layer and the semiconductor substrate, so as to passivate the surface defects of the doped semiconductor layer away from the semiconductor substrate by hydrogen injection, thereby improving the conversion efficiency of the solar cell. Secondly, in order to ensure the passivation effect of the surface passivation layer, the hydrogen content therein is relatively high, which easily leads to the hydrogen in the surface passivation layer overflowing during the subsequent high-temperature operation such as sintering of the electrode material, thereby causing the film to burst, and the surface passivation layer at the film burst is difficult to play a passivation role. In this case, when the concave depth of at least one side of the tower-like texture structure is less than the concave depth of the other side of itself, the hydrogen overflowing from the surface passivation layer can escape to other parts through the side with a smaller concave depth of the tower-like texture structure, while reducing the risk of film bursting, the hydrogen escaping to other parts can also passivate the surface of other parts of the doped semiconductor layer, so that the surface passivation layer has a higher passivation effect, further improving the conversion efficiency of the solar cell.

[0018] As a possible implementation scheme, the ratio between the concave depth of one side of at least one quasi-pyramid-shaped texture structure and the concave depth of the other side thereof is greater than or equal to 1.01 and less than 2. In this case, it is possible to prevent the ratio of the concave depth of one side of the quasi-pyramid-shaped texture structure to the concave depth of the other side thereof from being too large, thereby preventing the surface undulation of the passivation layer away from the semiconductor substrate from being too large, thereby ensuring that the side of the passivation layer away from the semiconductor substrate is relatively flat in the macroscopic sense, and correspondingly making the target surface relatively flat, thereby improving the formation quality and film thickness of the passivation layer.

[0019] As a possible implementation scheme, at least one quasi-pointed angle is an angle formed by two intersecting straight line segments. In this case, the transition at the quasi-pointed angle is relatively sharp, which is conducive to increasing the surface undulation at the quasi-pointed angle, further increasing the specific surface area of ​​the side of the passivation layer away from the semiconductor substrate, and then increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0020] As a possible implementation scheme, at least one quasi-sharp corner is an angle with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to half of the fillet radius corresponding to the quasi-fillet corner. In this case, another example is provided for the morphology of the quasi-sharp corner, which improves the applicability of the solar cell provided by the present invention in different application scenarios and helps to reduce the difficulty of the manufacturing process. In addition, when the quasi-sharp corner is an angle with a relatively small fillet radius, the macroscopic flatness of the passivation layer on the side away from the semiconductor substrate can be further increased, thereby improving the formation quality and passivation effect of the passivation layer on the target surface.

[0021] As a possible implementation scheme, one of the first surface and the second surface is the target surface. The passivation layer includes a first doped semiconductor layer and a second doped semiconductor layer that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are alternately distributed. The side surface of the passivation layer corresponding to the first doped semiconductor layer that is away from the semiconductor substrate is the first sub-surface, and the side surface of the passivation layer corresponding to the second doped semiconductor layer that is away from the semiconductor substrate is the second sub-surface. The first type of tower base-like texture structure and the second type of tower base-like texture structure are both distributed on the first sub-surface. The tower base-like texture structure also includes a third type of tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the third type of tower base-like texture structure is a surface with an arc-shaped contour.

[0022] When the above technical solution is adopted, the boundary of the third type of tower base-shaped texture structure with an arc-shaped bottom surface is smoother and more blurred, so that the second sub-surface has a relatively higher flatness than the first sub-surface. According to the difference in surface roughness between the first sub-surface and the second sub-surface, the requirements for different passivation effects of N and P doped semiconductor layers in actual application scenarios, and the requirements for the contact performance between the two and the corresponding electrodes, the conductivity types of the first doped semiconductor layer and the second doped semiconductor layer can be set respectively, so that the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor layer and the second doped semiconductor layer have different surface morphologies, thereby facilitating the reduction of the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively, and facilitating the reduction of the difference in contact performance between the first doped semiconductor layer and the second doped semiconductor layer and the corresponding electrodes respectively.

[0023] As a possible implementation scheme, the tower base-like texture structure also includes a fourth-type tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the fourth-type tower base-like texture structure is a polygonal bottom surface. In this case, the second sub-surface can have not only the third-type tower base-like texture structure, but also the fourth-type tower base-like texture structure, so there is no need to strictly control the etching conditions in order to obtain the second sub-surface having only the third-type tower base-like texture structure, thereby reducing the difficulty of the manufacturing process.

[0024] As a possible implementation scheme, the conductivity type of the first doped semiconductor layer is P type, and the conductivity type of the second doped semiconductor layer is N type.

[0025] In the case of adopting the above technical solution, due to the limitation of doping solid concentration (doping solid concentration refers to the limit doping concentration) and doping difficulty, the doping concentration of the dopant in the N-type doped semiconductor layer is greater than the doping concentration of the dopant in the P-type doped semiconductor layer, and the contact performance between the P-type doped semiconductor layer and the positive electrode is relatively poor. Based on this, when the conductivity type of the first doped semiconductor layer is P-type, and the first sub-surface corresponding to the first doped semiconductor layer on the side of the passivation layer away from the semiconductor substrate is provided with a first type of tower base-shaped texture structure and a second type of tower base-shaped texture structure, the existence of the sharp corners in the bottom surface of the second type of tower base-shaped texture structure is conducive to increasing the specific surface area of ​​the P-type doped semiconductor layer away from the semiconductor substrate, increasing the contact area between the P-type doped semiconductor layer and the positive electrode, improving the contact performance between the P-type doped semiconductor layer and the positive electrode, and the attachment and shaping of the positive electrode on the P-type doped semiconductor layer, which is conducive to improving the conversion efficiency of solar cells.

[0026] As a possible implementation scheme, a one-dimensional size of the bottom surface of the tower-like texture structure located on the first sub-surface is smaller than a one-dimensional size of the bottom surface of the tower-like texture structure located on the second sub-surface.

[0027] In the case of adopting the above technical solution, it can be understood that the larger the one-dimensional size of the bottom surface of the quasi-tower-shaped texture structure, the larger the bottom area of ​​the quasi-tower-shaped texture structure, and within the same area range, the fewer the number of quasi-tower-shaped texture structures that can be set, and the smaller the distribution density. Based on this, when the one-dimensional size of the bottom surface of the quasi-tower-shaped texture structure located on the first sub-surface is small, it is beneficial to increase the surface roughness of the first sub-surface, further increase the contact area between the first doped semiconductor layer and the electrode, improve the contact performance between the first doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the first doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell.

[0028] As a possible implementation scheme, the one-dimensional size of the bottom surface of the tower base-like texture structure located on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm.

[0029] When the above technical solution is adopted, the one-dimensional size of the bottom surface of the quasi-pyramid-shaped texture structure located on the first sub-surface is within the above range, which is conducive to preventing the surface roughness of the passivation layer on the side away from the semiconductor substrate from being too large due to the one-dimensional size being too small, ensuring that the target surface is a macroscopically flat surface, and further improving the formation quality and passivation effect of the passivation layer on the target surface. In addition, it can also prevent the surface roughness of the passivation layer on the side away from the semiconductor substrate from being too small due to the large one-dimensional size, ensuring that the above-mentioned doped semiconductor layer and the electrode have a large contact area, and further improving the contact performance between the doped semiconductor layer and the electrode.

[0030] As a possible implementation scheme, the one-dimensional size of the bottom surface of the quasi-tower-shaped texture structure located on the second sub-surface is greater than or equal to 5μm and less than or equal to 30μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the one-dimensional size of the bottom surface of the quasi-tower-shaped texture structure located on the first sub-surface being greater than or equal to 7μm and less than or equal to 15μm as described above, and will not be repeated here.

[0031] In a second aspect, the present invention provides a photovoltaic module, which includes the solar cell of the first aspect and various implementations thereof.

[0032] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0033] In a third aspect, the present invention provides a semiconductor substrate, which includes a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of tower-like texture structures that are recessed into the semiconductor substrate. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

[0034] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1A schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention;

[0037] Figure 2 A schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention;

[0038] Figure 3 A schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention;

[0039] Figure 4 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 1 ;

[0040] Figure 5 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 2 ;

[0041] Figure 6 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 3 ;

[0042] Figure 7 A schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention;

[0043] Figure 8 A schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided by an embodiment of the present invention;

[0044] Fig. 9 A schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided by an embodiment of the present invention;

[0045] Fig.10 A longitudinal SEM image of a local structure of a solar cell provided by an embodiment of the present invention Figure 1 ;

[0046] Fig.11 A longitudinal SEM image of a local structure of a solar cell provided by an embodiment of the present invention Figure 2 ;

[0047] Fig.12 A longitudinal SEM image of a local structure of a solar cell provided by an embodiment of the present invention Figure 3 ;

[0048] Fig.13 A longitudinal SEM image of a local structure of a solar cell provided by an embodiment of the present invention Figure 4 ;

[0049] Fig.14This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 4 ;

[0050] Fig.15 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 5 .

[0051] Figure numerals: 11 is a semiconductor substrate, 12 is a first surface, 13 is a second surface, 14 is a passivation layer, 15 is a first type of tower-like texture structure, 16 is a second type of tower-like texture structure, 17 is a rounded corner, 18 is a sharp corner, 19 is a first doped semiconductor layer, 20 is a second doped semiconductor layer, 21 is a third type of tower-like texture structure, 22 is a fourth type of tower-like texture structure, 23 is a doped semiconductor layer, 24 is an interface passivation layer, 25 is a surface passivation layer, 26 is an anti-reflection layer, and 27 is a transparent conductive layer. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0053] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0054] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0056] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has received more and more attention in recent years. Correspondingly, the application scope of photovoltaic solar cells based on the photoelectric effect is also becoming wider and wider.

[0058] Specifically, the existing solar cells usually include a semiconductor substrate and a passivation layer formed on the semiconductor substrate. The passivation layer may include a doped semiconductor layer with a field passivation effect, or may include at least one of a surface passivation layer, an anti-reflection layer, and a transparent conductive layer with a chemical passivation effect. Among them, the surface on one side of the semiconductor substrate formed with the passivation layer may be a polished surface, and the bottom surfaces of each texture structure on the polished surface are all bottom surfaces with smooth contours such as elliptical shapes. At this time, the overly flat morphology of the surface is conducive to improving the formation quality of the passivation layer and improving the passivation effect of the passivation layer on the semiconductor substrate. However, the passivation layer formed on the semiconductor substrate with a flat surface also tends to be flat, which makes the electrode material poorly shaped and adhered on the flat surface when an electrode for extracting carriers is formed on the passivation layer, thereby reducing the selection and matching of the electrode material; at the same time, it also causes the contact area between the formed electrode and the doped semiconductor layer formed on the plane surface to become smaller, and the contact loss increases. Although the pyramid-shaped velvet surface with undulating morphology has a large surface roughness, which is conducive to improving the electrical contact performance between the electrode and the doped semiconductor layer, as well as the shaping and adhesion of the electrode, the pyramid-shaped velvet surface has too large surface morphology fluctuations and is too sharp, resulting in poor formation quality of the doped semiconductor layer on the velvet surface, and its passivation effect is deteriorated. It can be seen that it is difficult for existing solar cells to take into account both good passivation effects and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells.

[0059] In order to solve the above technical problems, in a first aspect, an embodiment of the present invention provides a solar cell. Figures 1 to 6 As shown, the solar cell provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a passivation layer 14. The semiconductor substrate 11 includes a first surface 12 and a second surface 13 opposite to each other. At least one of the first surface 12 and the second surface 13 is a target surface. The passivation layer 14 is arranged on the target surface. A portion of the surface of the passivation layer 14 on the side away from the semiconductor substrate 11 has a plurality of tower-like texture structures formed by being recessed toward the side close to the semiconductor substrate 11. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure 15 and a second-type tower-like texture structure 16. Each corner in the bottom surface of the first-type tower-like texture structure 15 is a quasi-rounded corner 17, and the bottom surface of the second-type tower-like texture structure 16 includes a portion of the corners that are quasi-rounded corners 17, and the remaining corners are quasi-sharp corners 18. In the bottom surface of the same second-type tower-like texture structure 16, the number of quasi-rounded corners 17 is greater than or equal to the number of quasi-sharp corners 18.

[0060] When the above technical solution is adopted, Figures 1 to 6As shown, the passivation layer 14 is arranged on the target surface of the semiconductor substrate 11, and can passivate one side of the target surface of the semiconductor substrate 11 to reduce the carrier recombination rate. In addition, the side of the passivation layer 14 away from the semiconductor substrate 11 has a plurality of quasi-tower-shaped texture structures. Under the same conditions of other factors, compared with the texture structure with a large degree of undulation such as the pyramid-shaped velvet structure, the degree of undulation of the quasi-tower-shaped texture structure without a spire is relatively small. In addition, each corner in the bottom surface of the first type of tower-shaped texture structure 15 included in the plurality of quasi-tower-shaped texture structures, and most of the corners in the bottom surface of the second type of tower-shaped texture structure 16 are quasi-rounded corners 17. Compared with the quasi-pointed corners 18, the quasi-rounded corners 17 on the bottom surface have a smoother and flatter transition, so that the boundary transition of the quasi-tower-shaped texture structure at the quasi-rounded corners 17 is more moderate and blurred, so that the surface of the side of the passivation layer 14 away from the semiconductor substrate 11 is relatively flat from a macroscopic perspective. Moreover, in the actual manufacturing process, the passivation layer 14 is formed on the target surface of the semiconductor substrate 11 by deposition and other processes, and the surface undulation morphology of the passivation layer 14 on the side away from the semiconductor substrate 11 will also be affected by the surface undulation morphology of the target surface, and the corresponding surface undulation morphology of the passivation layer 14 on the side away from the semiconductor substrate 11 can also reflect the surface undulation morphology of the target surface of the semiconductor substrate 11 to a certain extent. Based on this, when the surface of the side of the passivation layer 14 away from the semiconductor substrate 11 is relatively flat macroscopically, the target surface of the semiconductor substrate 11 is also roughly a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer 14 on the target surface, and then it is conducive to improving the passivation effect of the passivation layer 14 on the semiconductor substrate 11, and improving the conversion efficiency of the solar cell. In addition, the bottom surface of the second type of tower base texture structure 16 also includes a sharp corner 18. Compared with the rounded corner 17, the sharp corner 18 has a relatively obvious transition and a greater degree of undulation, which is conducive to increasing the specific surface area of ​​the passivation layer 14 on the side away from the semiconductor substrate 11. Moreover, in the bottom surface of the same second-type tower-shaped texture structure 16, the number of the quasi-sharp corners 18 is greater than or equal to the number of the quasi-rounded corners 17, ensuring that the side of the passivation layer 14 facing away from the semiconductor substrate 11 is macroscopically flat, while the side of the passivation layer 14 facing away from the semiconductor substrate 11 has a relatively large surface roughness at the microscopic level, so that the doped semiconductor layer included in the passivation layer 14, or the doped semiconductor layer formed between the passivation layer 14 and the semiconductor substrate 11 has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of the solar cell.

[0061] In actual application, the solar cell provided by the embodiment of the present invention can be a double-sided contact cell, that is, one of the positive electrode and the negative electrode of the solar cell is arranged on the front side of the cell, and the other is arranged on the back side of the cell. Alternatively, the solar cell provided by the embodiment of the present invention can also be a back contact cell, that is, the positive electrode and the negative electrode of the solar cell are both arranged on the back side of the cell.

[0062] Secondly, the solar cell provided in the embodiment of the present invention may be a cell having a tunneling passivation contact structure or a heterogeneous contact structure; or, it may be a conventional solar cell without the interface passivation layer included in the above structure.

[0063] Specifically, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate or a gallium arsenide substrate.

[0064] As for the first surface and the second surface of the semiconductor substrate, the first surface of the semiconductor substrate may correspond to the front surface of the solar cell, and the second surface of the semiconductor substrate may correspond to the back surface of the solar cell; or, the first surface of the semiconductor substrate may correspond to the back surface of the solar cell, and the second surface of the semiconductor substrate may correspond to the front surface of the solar cell. Secondly, whether the first surface and the second surface are target surfaces can be determined according to the type of solar cell and the corresponding relationship between the first surface and the second surface and the front surface and the back surface of the cell, respectively, and no specific limitation is made here.

[0065] For example, in the case where the solar cell is a double-sided contact cell, of the first and second surfaces of the semiconductor substrate, only the first surface may be the target surface, only the second surface may be the target surface, or both the first and second surfaces may be the target surface.

[0066] Exemplarily, in the case where the solar cell is a back-contact cell, one of the first surface and the second surface of the semiconductor substrate corresponding to the back side of the cell is the target surface.

[0067] As for the surface morphology of the target surface of the semiconductor substrate, as mentioned above, the surface undulation morphology of the side of the passivation layer away from the semiconductor substrate can reflect the surface undulation morphology of the target surface of the semiconductor substrate to a certain extent, so the surface morphology of the target surface can refer to the surface morphology of the side of the passivation layer away from the semiconductor substrate. Specifically, because the surface morphology of the side of the passivation layer away from the semiconductor substrate is a macroscopically flat surface with multiple tower-like texture structures, the surface morphology of the target surface is also relatively flat in the macroscopic sense.

[0068] Exemplarily, the target surface may have a plurality of tower-base-like texture structures that are recessed into the semiconductor substrate. The plurality of tower-base-like texture structures include a first-type tower-base-like texture structure and a second-type tower-base-like texture structure. Each corner in the bottom surface of the first-type tower-base-like texture structure is a quasi-rounded corner, and the bottom surface of the second-type tower-base-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-pointed corners. In the bottom surface of the same second-type tower-base-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-pointed corners. In this case, compared with a texture structure with a large degree of undulation, such as a pyramid-type velvet structure, the quasi-tower-like texture structure without a spire has a relatively small degree of undulation. Moreover, each corner in the bottom surface of the first-type tower-base-like texture structure included in the plurality of tower-base-like texture structures, and most of the corners in the bottom surface of the second-type tower-base-like texture structure are quasi-rounded corners. Compared with the quasi-sharp corner, the quasi-rounded corner transition of the bottom surface is smoother and flatter, making the boundary transition of the quasi-tower-shaped texture structure at the quasi-rounded corner more gentle and blurred, so that the target surface of the semiconductor substrate is a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer on the target surface, thereby improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell. In addition, the bottom surface of the second type of tower-shaped texture structure also includes quasi-sharp corners. Compared with the quasi-rounded corner, the transition of the quasi-sharp corner is relatively obvious, and its fluctuation degree is greater, which is conducive to making the doped semiconductor layer formed on the target surface by deposition and other processes also have a relatively large specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell. As for the specific morphology of the tower-like texture structure on the target surface, the distribution density and one-dimensional size of the first type of tower-like texture structure and the second type of tower-like texture structure, etc., you can refer to the specific morphology of the tower-like texture structure on the side of the passivation layer away from the semiconductor substrate, the distribution density and one-dimensional size of the first type of tower-like texture structure and the second type of tower-like texture structure below, which will not be repeated here.

[0069] For the passivation layer, the passivation layer is arranged on the target surface, and the surface of the passivation layer facing away from the semiconductor substrate is the front and / or back of the solar cell. In terms of structure and material, the specific structure of the passivation layer can be determined according to the type of solar cell and the actual application scenario, and is not specifically limited here. Exemplarily, the passivation layer may include at least one of an interface passivation layer, a doped semiconductor layer, a surface passivation layer, an anti-reflection layer, and a transparent conductive layer.

[0070] Among them, Figures 1 to 3As shown, in the case where the passivation layer 14 is only a doped semiconductor layer, a tower-like texture structure is formed on the side of the doped semiconductor layer away from the semiconductor substrate 11. The material of the passivation layer 14 may include any semiconductor material such as silicon, silicon germanium or germanium. The crystal phase of the passivation layer 14 may be single crystal, polycrystalline, microcrystalline, nanocrystalline or amorphous.

[0071] like Figures 4 to 7 As shown, when the passivation layer 14 only includes at least one of the surface passivation layer 25, the anti-reflection layer 26 and the transparent conductive layer, the tower-like texture structure is formed on the outermost one of the film layers included in the passivation layer 14 (i.e., the one with the largest distance from the semiconductor substrate 11 along the thickness direction of the battery), and the surface of one side away from the semiconductor substrate 11. For example: when the passivation layer 14 only includes the surface passivation layer 25 and the anti-reflection layer 26, and the anti-reflection layer 26 is arranged on the side of the surface passivation layer 25 away from the semiconductor substrate 11, the tower-like texture structure is formed on the side of the anti-reflection layer 26 away from the semiconductor substrate 11. In addition, the materials of the surface passivation layer 25, the anti-reflection layer 26 and the transparent conductive layer can be set according to actual needs. Exemplarily, the material of the surface passivation layer 25 can include any material with a passivation effect, such as silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride. The material of the anti-reflection layer 26 can include silicon nitride or silicon oxynitride, etc. The material of the transparent conductive layer may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide. In the above case, the solar cell provided by the embodiment of the present invention further includes a doped semiconductor layer 23 disposed in or on the target surface (when the doped semiconductor layer 23 is disposed on the target surface, the material of the doped semiconductor layer 23 can refer to the above text and will not be repeated here), and the passivation layer 14 is located on the side of the doped semiconductor layer 23 away from the semiconductor substrate 11.

[0072] like Figures 4 to 6 ,as well as Figure 8 As shown, when the passivation layer 14 includes at least one of a surface passivation layer, an anti-reflection layer and a transparent conductive layer 27 in addition to the doped semiconductor layer 23, the tower-like texture structure is formed on the outermost one of the film layers included in the passivation layer 14 (i.e., the one with the largest distance from the semiconductor substrate 11 along the thickness direction of the battery), and its surface on the side away from the semiconductor substrate 11. For example: when the passivation layer 14 only includes the doped semiconductor layer 23 and the transparent conductive layer 27, and the transparent conductive layer 27 is arranged on the side of the doped semiconductor layer 23 away from the semiconductor substrate 11, the tower-like texture structure is formed on the side of the transparent conductive layer 27 away from the semiconductor substrate 11. In addition, the formation position of the doped semiconductor layer 23 in the above-mentioned solar cell, as well as the materials of the surface passivation layer, the anti-reflection layer, the transparent conductive layer 27 and the doped semiconductor layer 23 can be referred to the above text, and will not be repeated here.

[0073] It should be noted that, when the solar cell provided in the embodiment of the present invention is a double-sided contact cell and the passivation layer includes a doped semiconductor layer, the doped semiconductor layer in the same passivation layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. When the solar cell is a back contact cell and the passivation layer includes a doped semiconductor layer, Fig. 9 As shown, along the direction parallel to the target surface, the doped semiconductor layer in the passivation layer 14 includes a first doped semiconductor layer 19 and a second doped semiconductor layer 20 that are alternately distributed, and at least a portion of the first doped semiconductor layer 19 is spaced apart from at least a portion of the second doped semiconductor layer 20. Specifically, at least a portion of the first doped semiconductor layer 19 and at least a portion of the second doped semiconductor layer 20 may be spaced apart along the direction parallel to the target surface, or may be spaced apart along the thickness direction of the semiconductor substrate 11 by a dielectric layer of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0074] In addition, when the doped semiconductor layer is disposed on the target surface, such as Figure 8 As shown, the doped semiconductor layer 23 may be in direct contact with the semiconductor substrate 11; or Fig. 9 As shown, the solar cell may further include an interface passivation layer 24 located between the semiconductor substrate 11 and the doped semiconductor layer. The material and thickness of the interface passivation layer 24 may be determined according to the material of the doped semiconductor layer, and are not specifically limited here. For example, when the doped semiconductor layer includes a doped polysilicon layer, the interface passivation layer is a tunneling oxide layer. For another example, when the doped semiconductor layer includes a doped amorphous silicon layer, the interface passivation layer is an intrinsic amorphous silicon layer.

[0075] In terms of surface morphology, the bottom surfaces of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the passivation layer facing away from the semiconductor substrate can be regular or irregular polygonal bottom surfaces (such as quadrilateral bottom surfaces, pentagonal bottom surfaces, hexagonal bottom surfaces or octagonal bottom surfaces, etc.). The polygons can be regular polygons with the same side lengths or polygons with different side lengths. Figures 4 to 6 As shown, each corner of the bottom surface of the first type of tower base-shaped texture structure 15 is a smooth transition quasi-rounded corner 17. Some corners of the bottom surface of the second type of tower base-shaped texture structure 16 are smooth transition quasi-rounded corners 17, and the remaining corners are quasi-sharp corners 18. Figure 4As shown, at least one quasi-point angle 18 can be the angle formed by two intersecting straight line segments. In this case, the transition at the quasi-point angle 18 is relatively sharp, which is conducive to increasing the surface undulation at the quasi-point angle 18, further increasing the specific surface area of ​​the side of the passivation layer away from the semiconductor substrate, and then increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0076] Or, if Figures 4 to 6 As shown, at least one quasi-point angle 18 may also be an angle with a smooth transition and a smaller fillet radius corresponding to itself. Specifically, the size of the fillet radius corresponding to the quasi-point angle in this case can be determined according to the requirements for the contact performance between the doped semiconductor layer and the electrode, and the attachment and shaping of the electrode on the doped semiconductor layer in practical applications. For example: the fillet radius corresponding to the quasi-point angle 18 may be less than or equal to half of the fillet radius corresponding to the quasi-fillet 17 (such as the ratio between the fillet radius corresponding to the quasi-point angle 18 and the fillet radius corresponding to the above-mentioned quasi-fillet 17 may be half, one-third, one-quarter, one-fifth, one-sixth or one-seventh, etc.). In this case, another example is provided for the morphology of the quasi-point angle 18, which improves the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios, and helps to reduce the difficulty of the manufacturing process. In addition, when the quasi-point angle 18 is an angle with a relatively small fillet radius, the macroscopic flatness of the passivation layer away from the semiconductor substrate can be further increased, and the formation quality and passivation effect of the passivation layer on the target surface can be improved. The sizes of the fillet radii corresponding to the quasi-pointed corners 18 and the quasi-rounded corners 17 can be determined according to the one-dimensional size of the bottom surfaces of the first-type tower base-shaped texture structure 15 and the second-type tower base-shaped texture structure 16 and actual needs, and are not specifically limited here.

[0077] Specifically, the one-dimensional size and recessed depth of the bottom surfaces of the above-mentioned first type of tower-shaped texture structure and the second type of tower-shaped texture structure, as well as the distribution of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, can be determined according to the requirements for the surface roughness of the side of the passivation layer away from the semiconductor substrate in the actual application scenario, as long as it can be applied to the solar cell provided in the embodiment of the present invention. Among them, the one-dimensional size of the bottom surfaces of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure can be the length of the bottom side (the length of the bottom arc segment), the length of the bottom diagonal line, or the length of the fillet radius corresponding to the fillet, etc. Secondly, the recessed depth of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure is the recessed depth relative to the main surface of the side of the passivation layer away from the semiconductor substrate.

[0078] Exemplarily, the one-dimensional size of the bottom surface of the first type of tower base-shaped texture structure and / or the second type of tower base-shaped texture structure can be greater than or equal to 7μm and less than or equal to 15μm. For example, the one-dimensional size of the bottom surface of the tower base-shaped texture structure can be 7μm, 7.5μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm or 15μm, etc. In this case, the one-dimensional size of the bottom surface of the first type of tower base-shaped texture structure and / or the second type of tower base-shaped texture structure is within the above range, which is conducive to preventing the surface roughness of the passivation layer away from the semiconductor substrate from being too large due to the one-dimensional size being too small, ensuring that the target surface is a macroscopically flat surface, and further improving the formation quality and passivation effect of the passivation layer on the target surface. In addition, it can also prevent the surface roughness of the passivation layer away from the semiconductor substrate from being too small due to the large one-dimensional size, ensuring that the above-mentioned doped semiconductor layer and the electrode have a large contact area, and further improving the contact performance between the doped semiconductor layer and the electrode.

[0079] As for the concave depth of the quasi-pyramid-shaped texture structure, the concave depths of different regions of at least one quasi-pyramid-shaped texture structure may be substantially the same along a direction parallel to the target surface. Fig.10 As shown, along the direction parallel to the target surface, the concave depth of at least one side of the tower-like texture structure can be smaller than the concave depth of the other side. In this case, in the actual application process, the passivation layer will include a surface passivation layer such as aluminum oxide with chemical passivation, or the above-mentioned surface passivation layer is arranged between the passivation layer and the semiconductor substrate, so as to passivate the surface defects of the doped semiconductor layer away from the semiconductor substrate by hydrogen injection, thereby improving the conversion efficiency of the solar cell. Secondly, in order to ensure the passivation effect of the surface passivation layer, the hydrogen content therein is relatively high, which easily leads to the overflow of hydrogen in the surface passivation layer during subsequent high-temperature operations such as sintering of electrode materials, thereby causing film explosion, and the surface passivation layer at the film explosion is difficult to play a passivation role. In this case, when the concave depth of at least one side of the tower-like texture structure is smaller than the concave depth of the other side, the hydrogen overflowing from the surface passivation layer can escape to other parts through the side of the tower-like texture structure with a smaller concave depth, thereby reducing the risk of film explosion. At the same time, the hydrogen escaping to other parts can also passivate the surface of other parts of the doped semiconductor layer, so that the surface passivation layer has a higher passivation effect, further improving the conversion efficiency of the solar cell. As for the difference in the concave depth on both sides of the same tower-like texture structure, it can be determined according to actual needs and is not specifically limited here.

[0080] Exemplarily, the ratio of the concave depth on one side of at least one quasi-tower-shaped texture structure to the concave depth on the other side thereof may be greater than or equal to 1.01 and less than 2. For example, the ratio of the concave depth on one side of at least one quasi-tower-shaped texture structure to the concave depth on the other side thereof may be 1.01, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8 or 1.9, etc. In this case, it is possible to prevent the ratio of the concave depth on one side of the quasi-tower-shaped texture structure to the concave depth on the other side thereof from being too large, thereby preventing the surface undulation of the passivation layer away from the semiconductor substrate from being too large, thereby ensuring that the side of the passivation layer away from the semiconductor substrate is relatively flat in the macroscopic sense, and correspondingly making the target surface relatively flat, thereby improving the formation quality and film thickness of the passivation layer.

[0081] In addition, the concave depths at different regions of the surface of the passivation layer on the side away from the semiconductor substrate may be the same or different. When the concave depths at different regions of the surface of the passivation layer on the side away from the semiconductor substrate are different, the magnitude relationship of the concave depths of the tower-like texture structure at different regions may be determined according to the shape of the surface of the passivation layer on the side away from the semiconductor substrate and actual needs.

[0082] For example, when the surface of the passivation layer facing away from the semiconductor substrate is a rectangular surface, the corresponding areas of the four corners in the rectangular surface are defined as the four corner areas, the corresponding areas of the four contour edges are defined as the peripheral areas, and the area located inside the four corner areas and the peripheral areas is defined as the middle area. Fig.11 and Fig.12 As shown, the concave depth of the tower-like base-shaped texture structure located in the peripheral area can be greater than the concave depth of the tower-like base-shaped texture structure located in the middle area; and / or Fig.12 and Fig.13 As shown, the concave depth of the tower-like texture structure located in the four corner areas may be smaller than the concave depth of the tower-like texture structure located in the middle area.

[0083] When the above technical solution is adopted, in the actual manufacturing process, when the passivation layer is deposited on the semiconductor substrate to form the passivation layer, the growth rate of the passivation layer in the peripheral area of ​​the semiconductor substrate is relatively fast, which easily makes the deposition thickness of the passivation layer in the peripheral area relatively large. In this case, compared with the four corner areas and the middle area of ​​the passivation layer, the concave depth of the tower-like texture structure located in the peripheral area is relatively large, which is conducive to increasing the specific surface area of ​​the passivation layer located in the peripheral area, and the corresponding target surface of the semiconductor substrate corresponding to the above-mentioned peripheral area The partial surface also has a relatively large specific surface area. The deposited film thickness of the passivation layer is inversely proportional to the specific surface area of ​​the target surface. Therefore, increasing the specific surface area of ​​the portion of the target surface corresponding to the above-mentioned peripheral area can prevent the thickness of the passivation layer in the peripheral area from being too large due to the high deposition rate, which is conducive to improving the thickness uniformity of different areas of the passivation layer. In addition, due to the influence of operations such as crystal pulling or cutting, the number of defects in the corresponding four corner areas of the semiconductor substrate is relatively large. Secondly, the recessed depth of the tower-like texture structure located in the four corner areas is small, which is beneficial to reducing the surface roughness of the passivation layer in the four corner areas. The target surface of the corresponding semiconductor substrate corresponding to the above-mentioned four corner areas also has a relatively small surface roughness. There is no need to increase the etching depth of the four corner areas in order to obtain a tower-like texture structure with a larger recessed depth. Correspondingly, the number of defects exposed by etching in the corresponding four corner areas of the semiconductor substrate can be reduced, and it is beneficial to improve the formation quality and film thickness of the passivation layer in the four corner areas, and improve the passivation effect of the passivation layer in the four corner areas. The concave depth of the tower-like texture structure in the middle area of ​​the passivation layer is moderate, which can prevent the passivation effect of the passivation layer in the middle area from being affected by the excessive concave depth of the tower-like texture structure in the middle area, and can also prevent the contact area between the part of the doped semiconductor layer corresponding to the middle area and the electrode from being too small due to the excessive concave depth of the tower-like texture structure in the middle area. This further improves the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, so that the passivation effect and contact performance in the middle area are balanced, which is beneficial to improving the conversion efficiency of solar cells.

[0084] Among them, the scope of the four corner areas, peripheral areas and middle areas of the passivation layer facing away from the semiconductor substrate can be determined according to the formation quality of different areas of the semiconductor substrate in the actual application scenario, as well as the passivation effect and specific surface area requirements at different positions of the passivation layer, and no specific limitation is made here.

[0085] Exemplarily, along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner regions may be less than or equal to 2 cm. For example, the width of the four corner regions may be 0.5 cm, 0.8 cm, 1 cm, 1.2 cm, 1.5 cm, 1.8 cm or 2 cm, etc. In this case, it is possible to prevent the four corner regions from being too large, which may result in a too small contact area between the doped semiconductor layer near the four corner regions and the electrode, thereby ensuring good contact performance between the doped semiconductor layer and the electrode, and ensuring that the electrode has strong adhesion and good shaping on the doped semiconductor layer near the four corner regions.

[0086] Exemplarily, along the direction from the edge of the quasi-rectangular surface to the geometric center, the width of the peripheral area may be less than or equal to 3 cm. For example, the width of the peripheral area may be 0.5 cm, 0.8 cm, 1 cm, 1.2 cm, 1.5 cm, 1.8 cm, 2 cm, 2.2 cm, 2.5 cm, 2.8 cm or 3 cm, etc. In this case, it is possible to prevent the width range of the peripheral area from being too large, which may result in the deposition thickness of the passivation layer being too small in the middle area where the deposition rate is relatively small, thereby ensuring that the passivation layer in the middle area has a higher passivation effect.

[0087] As for the distribution density of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the same passivation layer away from the semiconductor substrate, since the corners in the bottom surface of the first type of tower-shaped texture structure are all quasi-rounded corners, the proportion of quasi-rounded corners in its bottom surface is relatively large relative to the proportion of quasi-rounded corners in the second type of tower-shaped texture structure. And, as mentioned above, compared with the quasi-sharp corners, the quasi-rounded corner transition of the bottom surface is smoother and flatter, which is conducive to reducing the specific surface area of ​​the side of the passivation layer away from the semiconductor substrate. However, some of the corners on the bottom surface of the second type of tower-shaped texture structure are quasi-sharp corners, and the transition of the quasi-sharp corners is relatively obvious, and its fluctuation is greater, which is conducive to increasing the specific surface area of ​​the side of the passivation layer away from the semiconductor substrate. In the above case, the distribution density of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure, as well as the distribution number of quasi-rounded corners and quasi-sharp corners in the bottom surface of the second type of tower-shaped texture structure can be determined according to the requirements for the specific surface area of ​​the passivation layer away from the semiconductor substrate in the actual application scenario.

[0088] For example, Figure 4 As shown, on the side of the same passivation layer away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structure 15 can be greater than the distribution density of the second type of texture structure. Such an arrangement is conducive to further improving the macroscopic surface flatness of the side of the passivation layer 14 away from the semiconductor substrate 11, and further improving the formation quality and passivation effect of the passivation layer 14.

[0089] Exemplarily, in the surface of the area with the first type of tower-shaped texture structure and the second type of tower-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, and within the range of 1cm×1cm, the distribution density of the first type of tower-shaped texture structure can be greater than or equal to 80% and less than or equal to 99%. For example, the distribution density of the first type of tower-shaped texture structure can be 80%, 82%, 84%, 86%, 88%, 90%, 92%, 94%, 96%, 98% or 99%. In this case, each corner is a first type of tower-shaped texture structure of the type of fillet 17 with a small degree of undulation, and its distribution density on the side of the passivation layer away from the semiconductor substrate is relatively large, which is conducive to further improving the surface flatness of the side of the passivation layer away from the semiconductor substrate on a macroscopic level, and further improving the formation quality and passivation effect of the passivation layer.

[0090] Exemplarily, in the surface of the area where the passivation layer has a first type of tower-like texture structure and a second type of tower-like texture structure on the side facing away from the semiconductor substrate, and within the range of 1 cm×1 cm, the distribution density of the first type of tower-like texture structure can be less than the distribution density of the second type of tower-like texture structure.

[0091] For example, Figure 4 As shown, on the side of the passivation layer away from the semiconductor substrate, the number of the remaining first-type tower-shaped texture structures 15 adjacent to the single first-type tower-shaped texture structure 15 is greater than the number of the second-type tower-shaped texture structures 16. In this case, it is beneficial to increase the distribution density of the first-type tower-shaped texture structure 15 on the side of the passivation layer away from the semiconductor substrate, further improve the macroscopic surface flatness of the side of the passivation layer away from the semiconductor substrate, and further improve the formation quality and passivation effect of the passivation layer.

[0092] As for the distribution number of quasi-rounded corners and quasi-pointed corners in the bottom surface of the second type of tower base-shaped texture structure, it can be set according to the bottom surface morphology of the second type of tower base-shaped texture structure and actual needs. For example: when the bottom surface morphology of the second type of tower base-shaped texture structure is a regular or irregular quadrilateral, the number of quasi-rounded corners in the bottom surface of the second type of tower base-shaped texture structure can be 2 or 3. For another example: when the bottom surface morphology of the second type of tower base-shaped texture structure is a regular or irregular hexagon, the number of quasi-rounded corners in the bottom surface of the second type of tower base-shaped texture structure can be 3, 4 or 5.

[0093] In addition, in actual application, the distribution density of the first type of tower-shaped texture structure and the second type of tower-shaped texture structure in different regions of the passivation layer away from the semiconductor substrate can be roughly the same or different. Alternatively, in different regions of the passivation layer away from the semiconductor substrate, only some regions have the first type of tower-shaped texture structure and the second type of tower-shaped texture structure, while the remaining regions do not have the first type of tower-shaped texture structure and the second type of tower-shaped texture structure.

[0094] Exemplarily, one of the first surface and the second surface is the target surface. Furthermore, the passivation layer includes a first doped semiconductor layer and a second doped semiconductor layer that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are alternately distributed. Based on this, a side surface of the passivation layer corresponding to a portion of the first doped semiconductor layer that is away from the semiconductor substrate is defined as a first sub-surface, and a side surface of the passivation layer corresponding to a portion of the second doped semiconductor layer that is away from the semiconductor substrate is defined as a second sub-surface. In the above case, the first type of tower-like texture structure and the second type of tower-like texture structure can be both distributed on the first sub-surface. The tower-like texture structure also includes a third type of tower-like texture structure distributed on the second sub-surface. As Fig.14 and Fig.15 As shown, the bottom surface of the third type of tower base-shaped texture structure 21 is a surface with an arc-shaped contour. In this case, the boundary of the third type of tower base-shaped texture structure 21 with an arc-shaped contour at the bottom surface is smoother and more blurred, so that the second sub-surface has a relatively higher flatness than the first sub-surface. The conductivity types of the first doped semiconductor layer and the second doped semiconductor layer can be set respectively according to the difference in surface roughness between the first sub-surface and the second sub-surface, the requirements for different passivation effects of the N and P doped semiconductor layers in actual application scenarios, and the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor layer and the second doped semiconductor layer have different surface morphologies, thereby facilitating the reduction of the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor layer and the second doped semiconductor layer respectively (due to the limitation of the doping solid concentration of the N and P regions, the doping concentration of the P region is low. If the P region is formed on a relatively flat surface, it is conducive to improving the crystal quality and film thickness of the P region, and is conducive to improving the passivation effect of the P region, thereby reducing the passivation difference between the N and P regions.), and is conducive to reducing the difference in contact performance between the first doped semiconductor layer and the second doped semiconductor layer and the corresponding electrodes.

[0095] As for the conductivity type of the first doped semiconductor layer and the second doped semiconductor layer, due to the limitation of doping solid concentration and doping difficulty, the doping concentration of the dopant in the N-type doped semiconductor layer is greater than the doping concentration of the dopant in the P-type doped semiconductor layer, and the contact performance between the P-type doped semiconductor layer and the positive electrode is relatively poor. In addition, as mentioned above, the surface roughness of the first sub-surface provided with the first type of tower base-shaped texture structure is relatively large, while the surface roughness of the second sub-surface provided with the second type of tower base-shaped texture structure is relatively small. Therefore, the conductivity type of the first doped semiconductor layer can be set to P type and the conductivity type of the second doped semiconductor layer can be set to N type. At this time, the presence of the sharp corners in the bottom surface of the second type of tower base-shaped texture structure is conducive to increasing the specific surface area of ​​the P-type doped semiconductor layer away from the semiconductor substrate, increasing the contact area between the P-type doped semiconductor layer and the positive electrode, improving the contact performance between the P-type doped semiconductor layer and the positive electrode, and the attachment and shaping of the positive electrode on the P-type doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0096] Alternatively, the conductivity type of the first doped semiconductor layer can be set to N-type, and the conductivity type of the second doped semiconductor layer can be set to P-type. Based on this, N-type impurities are usually doped by substitutional diffusion, which is difficult to dope; and the doping concentration of the N-type doped semiconductor layer is also relatively high, which easily leads to a large number of defects in the N-type doped semiconductor layer after doping. At this time, the first sub-surface with a larger surface roughness corresponds to the N-type doped semiconductor layer, which is conducive to improving the contact performance between the N-type doped semiconductor layer and the negative electrode, as well as the adhesion and shaping of the negative electrode on the N-type doped semiconductor layer, which is conducive to improving the conversion efficiency of the solar cell.

[0097] In addition, the bottom surface morphology of the third type of tower base-shaped texture structure on the second sub-surface can be a regular surface with an arc-shaped contour (such as an elliptical surface, a circular surface, etc.), or an irregular surface with an arc-shaped contour. Secondly, the second sub-surface can only have the third type of tower base-shaped texture structure. Or, Fig.15 As shown, the tower base-like texture structure can also include a fourth-type tower base-like texture structure 22 distributed on the second sub-surface, and the bottom surface of the fourth-type tower base-like texture structure 22 is a polygonal bottom surface. In this case, the second sub-surface can not only have the third-type tower base-like texture structure 21, but also be provided with the fourth-type tower base-like texture structure 22, so that there is no need to strictly control the etching conditions in order to obtain a second sub-surface having only the third-type tower base-like texture structure 21, thereby reducing the difficulty of the manufacturing process. Among them, the bottom surface of the fourth-type tower base-like texture structure 22 can be a polygonal bottom surface such as a quadrilateral bottom surface, a pentagonal bottom surface, a hexagonal bottom surface or an octagonal bottom surface. The polygon can be a regular polygon with the same side length, or a polygon with different side lengths.

[0098] As for the size of the tower-like texture structure possessed by the first sub-surface and the second sub-surface, the one-dimensional size and / or the recessed depth of the bottom surface of the tower-like texture structure located on the first sub-surface can be the same as the one-dimensional size and / or the recessed depth of the bottom surface of the tower-like texture structure located on the second sub-surface.

[0099] Alternatively, the one-dimensional size of the bottom surface of the tower-like texture structure located on the first sub-surface may be smaller than the one-dimensional size of the bottom surface of the tower-like texture structure located on the second sub-surface, and / or the recessed depth of the tower-like texture structure located on the first sub-surface may be greater than the recessed depth of the tower-like texture structure located on the second sub-surface. In this case, it can be understood that the larger the one-dimensional size of the bottom surface of the tower-like texture structure, the larger the bottom area of ​​the tower-like texture structure, and within the same area range, the fewer the number of tower-like texture structures that can be set, and the smaller the distribution density. Based on this, when the one-dimensional size of the bottom surface of the tower-like texture structure located on the first sub-surface is small, it is beneficial to increase the surface roughness of the first sub-surface, further increase the contact area between the first doped semiconductor layer and the electrode, improve the contact performance between the first doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the first doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell. Secondly, the beneficial effect that the recessed depth of the tower-like texture structure located on the first sub-surface can be greater than the recessed depth of the tower-like texture structure located on the second sub-surface can be referred to in the previous text and will not be repeated here.

[0100] Among them, the one-dimensional size of the bottom surface of the tower-like texture structure of the first sub-surface can refer to the one-dimensional size of the bottom surface of the first type of tower-like texture structure and the second type of tower-like texture structure mentioned above, which will not be repeated here.

[0101] As for the one-dimensional size of the bottom surface of the tower-like texture structure of the second sub-surface, illustratively, the one-dimensional size of the bottom surface of the tower-like texture structure located on the second sub-surface can be greater than or equal to 5μm and less than or equal to 30μm. For example: the one-dimensional size of the bottom surface of the tower-like texture structure located on the second sub-surface can be 5μm, 6μm, 8μm, 10μm, 15μm, 18μm, 20μm, 25μm or 30μm, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the one-dimensional size of the bottom surface of the first type of tower-like texture structure and / or the second type of tower-like texture structure being greater than or equal to 7μm and less than or equal to 15μm described above, which will not be repeated here.

[0102] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the solar cell of the first aspect and various implementations thereof.

[0103] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed by referring to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0104] In a third aspect, an embodiment of the present invention provides a semiconductor substrate, which includes a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of tower-like texture structures that are recessed into the semiconductor substrate. Among them, the plurality of tower-like texture structures include a first-type tower-like texture structure and a second-type tower-like texture structure. The corners in the bottom surface of the first-type tower-like texture structure are all quasi-rounded corners, and the bottom surface of the second-type tower-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-sharp corners. In the bottom surface of the same second-type tower-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

[0105] In one example, in the same target surface, the distribution density of the first type of tower base-shaped texture structure is greater than the distribution density of the second type of texture structure.

[0106] In one example, in the area surface of the target surface having the first type of tower base-like texture structure and the second type of tower base-like texture structure, and within the range of 1cm×1cm, the distribution density of the first type of tower base-like texture structure is greater than or equal to 80% and less than or equal to 99%.

[0107] In one example, in the target surface, the number of remaining first-type tower-like texture structures adjacent to the single first-type tower-like texture structure is greater than the number of second-type tower-like texture structures.

[0108] In one example, the target surface is a quasi-rectangular surface; in the quasi-rectangular surface, the corresponding areas of the four corners are the four-corner areas, the corresponding areas of the four contour edges are the peripheral areas, and the area located inside the four-corner areas and the peripheral areas is the middle area; wherein the recessed depth of the tower-like texture structure located in the peripheral area is greater than the recessed depth of the tower-like texture structure located in the middle area; and / or the recessed depth of the tower-like texture structure located in the four-corner areas is less than the recessed depth of the tower-like texture structure located in the middle area.

[0109] In one example, in the target surface, along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner regions is less than or equal to 2 cm.

[0110] In one example, in the target surface, along the direction from the edge of the quasi-rectangular surface to the geometric center, the width of the peripheral area is less than or equal to 3 cm.

[0111] In one example, in the target surface, along a direction parallel to the target surface, a concave depth of one side of at least one pyramid-like texture structure is smaller than a concave depth of the other side thereof.

[0112] In one example, in the target surface, a ratio between a concave depth on one side of at least one pyramid-like texture structure and a concave depth on the other side thereof is greater than or equal to 1.01 and less than 2.

[0113] In one example, in the target surface, at least one quasi-cusp angle is an angle formed by two intersecting straight line segments.

[0114] In one example, in the target surface, at least one quasi-sharp corner is a corner with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to one half of the fillet radius corresponding to the quasi-fillet corner.

[0115] In one example, one of the first surface and the second surface is a target surface; the target surface includes a first sub-surface and a second sub-surface that are alternately distributed; the first type of tower base-like texture structure and the second type of tower base-like texture structure are both distributed on the first sub-surface; the tower base-like texture structure also includes a third type of tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the third type of tower base-like texture structure is a surface with an arc-shaped contour.

[0116] In one example, in the target surface, the tower base-like texture structure further includes a fourth-type tower base-like texture structure distributed on the second sub-surface, and the bottom surface of the fourth-type tower base-like texture structure is a polygonal bottom surface.

[0117] In one example, in the target surface, a one-dimensional size of a bottom surface of a pyramid-like texture structure located on a first sub-surface is smaller than a one-dimensional size of a bottom surface of a pyramid-like texture structure located on a second sub-surface.

[0118] In one example, in the target surface, a one-dimensional size of the bottom surface of the pyramid-like texture structure located on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm.

[0119] In one example, in the target surface, a one-dimensional size of the bottom surface of the pyramid-like texture structure located on the second sub-surface is greater than or equal to 5 μm and less than or equal to 30 μm.

[0120] It should be noted that the semiconductor substrate provided in the third aspect of the embodiment of the present invention is used to manufacture the solar cell provided in the first aspect. The morphology of the multiple tower-like texture structures on the target surface of the semiconductor substrate, the size and distribution of the first tower-like texture structure and the second tower-like texture structure, etc. can refer to the morphology of the multiple tower-like texture structures on the side of the passivation layer away from the semiconductor substrate, the size and distribution of the first tower-like texture structure and the second tower-like texture structure, etc.

[0121] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0122] In a fourth aspect, an embodiment of the present invention provides a method for manufacturing a solar cell. The method for manufacturing a solar cell comprises the following steps:

[0123] First, a semiconductor substrate is provided; the semiconductor substrate includes a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. The material of the semiconductor substrate and whether the first surface and the second surface of the semiconductor substrate are target surfaces can be referred to in the previous text and will not be repeated here.

[0124] Next, a first polishing process is performed on the target surface of the semiconductor substrate to form a plurality of quasi-tower-shaped texture structures on the target surface. The plurality of quasi-tower-shaped texture structures include a first-type tower-shaped texture structure and a second-type tower-shaped texture structure. Each corner in the bottom surface of the first-type tower-shaped texture structure is a quasi-rounded corner, and the bottom surface of the second-type tower-shaped texture structure includes a portion of corners that are quasi-rounded corners and the remaining corners that are quasi-sharp corners. In the bottom surface of the same second-type tower-shaped texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

[0125] Specifically, the morphology, one-dimensional size and distribution of the tower-like texture structure on the target surface can refer to the morphology, one-dimensional size and distribution of the tower-like texture structure on the side of the passivation layer away from the semiconductor substrate in the solar cell provided by the first aspect described above, and will not be repeated here.

[0126] In the actual manufacturing process, a first alkaline solution can be used to perform a first polishing treatment on the target surface of the semiconductor substrate, and the first alkaline solution is a solution containing sodium hydroxide or potassium hydroxide. The concentration and temperature of the first alkaline solution, as well as the processing time of the first polishing treatment can be determined according to the requirements for the morphology and one-dimensional size of the tower-like texture structure in the actual application scenario, and are not specifically limited here.

[0127] Next, a passivation layer is formed on the target surface, wherein the passivation layer has a plurality of pyramid-like texture structures on a side facing away from the semiconductor substrate.

[0128] The specific formation process of the passivation layer can be determined according to the structure of the passivation layer and the distribution of the tower-like texture structure on the side of the passivation layer away from the semiconductor substrate.

[0129] Exemplarily, a process such as chemical vapor deposition can be used to form a passivation layer that is set as a whole layer on the target surface. If the passivation layer is only set in a local area of ​​the target surface, the passivation layer also needs to be patterned. If the passivation layer includes the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity type, after forming one of the first doped semiconductor layer and the second doped semiconductor layer, it is necessary to pattern the first doped semiconductor layer and the second doped semiconductor layer that are formed earlier; then, a process such as chemical vapor deposition is used to form the other of the first doped semiconductor layer and the second doped semiconductor layer that are set as a whole layer, and then the first doped semiconductor layer and the second doped semiconductor layer that are formed later are patterned.

[0130] The process of manufacturing the passivation layer is described below by taking the example that the passivation layer includes the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, and one of the first doped semiconductor layer and the second doped semiconductor layer formed first is a doped semiconductor layer of P-type conductivity type:

[0131] A first interface passivation layer and an intrinsic semiconductor layer are sequentially formed on the target surface by using processes such as chemical vapor deposition. Then, the intrinsic semiconductor layer is doped by using a doping process such as diffusion, so that the intrinsic semiconductor layer forms a P-type doped semiconductor layer. Wherein, when the material of the P-type doped semiconductor layer includes silicon, after the P-type doped semiconductor layer is formed, a borosilicate glass layer is also formed on the side of the P-type doped semiconductor layer away from the semiconductor substrate. Then, the borosilicate glass layer is locally heat-treated by using a laser irradiation process, so that the untreated portion of the borosilicate glass layer forms a mask layer. Then, a second alkaline solution is used to selectively remove the portion of the P-type doped semiconductor layer exposed outside the mask layer. The second alkaline solution is used to etch the portion of the P-type doped semiconductor layer exposed outside the mask layer. Because the doping concentration of the P-type impurities in the first interface passivation layer is lower and the density is higher than that of the heat-treated portion of the borosilicate glass layer, the portion of the first interface passivation layer exposed outside the mask layer is retained after being etched by the second alkaline solution. Among them, the type, concentration, temperature and processing time of the above-mentioned second alkaline solution can be set according to actual needs, and are not specifically limited here. Next, a third alkaline solution is used to remove the portion of the first interface passivation layer exposed outside the mask layer, and the portion of the semiconductor substrate exposed outside the mask layer is etched so that the surface of the portion of the semiconductor substrate exposed outside the mask layer is concave inward relative to the surface of the portion of the semiconductor substrate covered with the mask layer, and a third type of tower base texture structure and / or a fourth type of tower base texture structure are formed. In addition, compared with the second alkaline solution, because the third alkaline solution is to corrode the first interface passivation layer with higher density, the alkali concentration of the third alkaline solution is higher, and the corresponding etching time is shorter. Specifically, the type, concentration, temperature and processing time of the third alkaline solution can be set according to actual needs, and are not specifically limited here. Next, chemical vapor deposition and other processes can be used to sequentially form a second interface passivation layer and an N-type doped semiconductor layer set in a whole layer on the P-type doped semiconductor layer and on the target surface. Then, chemical slurry or laser etching is used to remove the second interface passivation layer and the portion of the N-type doped semiconductor layer at least covering the local area of ​​the P-type doped semiconductor layer.

[0132] It should be noted that when the passivation layer includes the above-mentioned N-type doped semiconductor layer and P-type doped semiconductor layer of opposite conductivity types, not only the P-type doped semiconductor layer can be formed first, but also the N-type doped semiconductor layer can be formed first. When the N-type doped semiconductor layer is formed first, the manufacturing process of the passivation layer can refer to the manufacturing process of the passivation layer when the P-type doped semiconductor layer is formed first in the above text, and will not be repeated here.

[0133] In addition, when the passivation layer includes the above-mentioned N-type doped semiconductor layer and P-type doped semiconductor layer of opposite conductivity types, the solar cell may not include the above-mentioned first interface passivation layer and / or second interface passivation layer. When the solar cell does not include the above-mentioned first interface passivation layer and / or second interface passivation layer, it is not necessary to perform the operations of forming and etching the first interface passivation layer and / or second interface passivation layer as described above.

[0134] In addition, when the N-type doped semiconductor layer and / or the P-type doped semiconductor layer does not include silicon material, and / or the N-type doped semiconductor layer and / or the P-type doped semiconductor layer is not formed by a diffusion process, a mask layer for performing patterning can be formed by combining chemical phase deposition and etching processes. The material of the mask layer can include materials such as silicon nitride or aluminum oxide.

[0135] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0136] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; A passivation layer, disposed on the target surface; A portion of the surface of the passivation layer on a side away from the semiconductor substrate is concave toward a side close to the semiconductor substrate, forming a plurality of tower-like texture structures; Among them, the multiple tower base-like texture structures include a first type of tower base-like texture structure and a second type of tower base-like texture structure; the corners in the bottom surface of the first type of tower base-like texture structure are all quasi-rounded corners, and the bottom surface of the second type of tower base-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-sharp corners; in the bottom surface of the same second type of tower base-like texture structure, the number of quasi-rounded corners is greater than or equal to the number of quasi-sharp corners.

2. The solar cell according to claim 1, characterized in that On the side of the same passivation layer facing away from the semiconductor substrate, the distribution density of the first type of tower-shaped texture structure is greater than the distribution density of the second type of texture structure; and / or, in the surface of the region having the first-type tower-shaped texture structure and the second-type tower-shaped texture structure on the side of the passivation layer away from the semiconductor substrate, and within the range of 1 cm×1 cm, the distribution density of the first-type tower-shaped texture structure is greater than or equal to 80% and less than or equal to 99%; And / or, in the side of the passivation layer facing away from the semiconductor substrate, the number of the remaining first-type tower-shaped texture structures adjacent to a single first-type tower-shaped texture structure is greater than the number of the second-type tower-shaped texture structures.

3. The solar cell according to claim 1, characterized in that The surface of the passivation layer facing away from the semiconductor substrate is a rectangular surface; in the rectangular surface, the corresponding areas of the four corners are the four corner areas, the corresponding areas of the four contour edges are the peripheral areas, and the area located inside the four corner areas and the peripheral areas is the middle area; Among them, the recessed depth of the tower-like texture structure located in the peripheral area is greater than the recessed depth of the tower-like texture structure located in the middle area; and / or the recessed depth of the tower-like texture structure located in the four corner areas is less than the recessed depth of the tower-like texture structure located in the middle area.

4. The solar cell according to claim 3, characterized in that: Along the direction from the four corner vertices of the quasi-rectangular surface to the geometric center of the quasi-rectangular surface, the width of the four corner areas is less than or equal to 2 cm; And / or, along the direction from the edge of the rectangular surface to the geometric center, the width of the peripheral area is less than or equal to 3 cm.

5. The solar cell according to claim 1, characterized in that: Along a direction parallel to the target surface, a concave depth on one side of at least one of the tower base-like texture structures is smaller than a concave depth on the other side thereof.

6. The solar cell according to claim 5, characterized in that: The ratio of the concave depth on one side of at least one of the tower base-like texture structures to the concave depth on the other side thereof is greater than or equal to 1.01 and less than 2.

7. The solar cell according to claim 1, characterized in that At least one of the quasi-pointed angles is an angle formed by two intersecting straight line segments; Alternatively, at least one of the quasi-sharp corners is an angle with a smooth transition, and the fillet radius corresponding to the quasi-sharp corner is less than or equal to half of the fillet radius corresponding to the quasi-fillet corner.

8. The solar cell according to claim 1, characterized in that One of the first surface and the second surface is a target surface; the passivation layer comprises first doped semiconductor layers and second doped semiconductor layers which are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are alternately distributed; A surface of the passivation layer corresponding to the first doped semiconductor layer and facing away from the semiconductor substrate is a first sub-surface, and a surface of the passivation layer corresponding to the second doped semiconductor layer and facing away from the semiconductor substrate is a second sub-surface; The first type of tower base-shaped texture structure and the second type of tower base-shaped texture structure are both distributed on the first sub-surface; The tower foundation-like texture structure also includes a third tower foundation-like texture structure distributed on the second sub-surface, and the bottom surface of the third tower foundation-like texture structure is a surface with an arc-shaped contour.

9. The solar cell according to claim 8, characterized in that The tower foundation-like texture structure also includes a fourth tower foundation-like texture structure distributed on the second sub-surface, and the bottom surface of the fourth tower foundation-like texture structure is a polygonal bottom surface.

10. The solar cell according to claim 8 or 9, characterized in that: The conductivity type of the first doped semiconductor layer is P type, and the conductivity type of the second doped semiconductor layer is N type; and / or, a one-dimensional size of the bottom surface of the tower-base-like texture structure located on the first sub-surface is smaller than a one-dimensional size of the bottom surface of the tower-base-like texture structure located on the second sub-surface; and / or, a one-dimensional size of the bottom surface of the tower-base-like texture structure located on the first sub-surface is greater than or equal to 7 μm and less than or equal to 15 μm; And / or, a one-dimensional size of a bottom surface of the tower base-like texture structure located on the second sub-surface is greater than or equal to 5 μm and less than or equal to 30 μm.

11. A photovoltaic module, characterized in that: The invention comprises a solar cell as claimed in any one of claims 1 to 10.

12. A semiconductor substrate, characterized in that: include: The semiconductor substrate comprises a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; The target surface has a plurality of tower-like texture structures recessed into the semiconductor substrate; Among them, the multiple tower base-like texture structures include a first type of tower base-like texture structure and a second type of tower base-like texture structure; the corners in the bottom surface of the first type of tower base-like texture structure are all quasi-rounded corners, and the bottom surface of the second type of tower base-like texture structure includes some corners that are quasi-rounded corners, and the remaining corners are quasi-sharp corners; in the bottom surface of the same second type of tower base-like texture structure, the number of quasi-rounded corners is greater than the number of quasi-sharp corners.

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