LED epitaxial structure and preparation method thereof, and light emitting diode

Abstract

The invention discloses an LED epitaxial structure and a preparation method thereof, and a light emitting diode. The LED epitaxial structure comprises a substrate; the first semiconductor layer, the multi-quantum well layer, the second semiconductor layer and the third semiconductor layer are arranged on the substrate and are sequentially arranged in the direction away from the substrate; the second semiconductor layer and the multi-quantum well layer both contain an In element, a Ga element and an N element; wherein the surface, far away from the substrate, of the second semiconductor layer is provided with a plurality of first grooves.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an LED epitaxial structure and a preparation method thereof, and a light emitting diode. Background Art

[0002] Micro-light-emitting diodes (Micro-LED) display technology is considered to be the next generation of display technology. Compared with the existing liquid crystal display (LCD) and organic light-emitting diodes (OLED) display technologies, it has obvious advantages in brightness, contrast, response speed, stability, etc. Full-color Micro-LED display products require high-efficiency red, green and blue primary color Micro-LEDs. Summary of the invention

[0003] The present disclosure provides an LED epitaxial structure and a preparation method thereof, and a light emitting diode.

[0004] In a first aspect, the present disclosure provides an LED epitaxial structure, comprising:

[0005] substrate substrate;

[0006] Disposed on the substrate and sequentially disposed in a direction away from the substrate: a first semiconductor layer, a multi-quantum well layer, a second semiconductor layer and a third semiconductor layer; the second semiconductor layer and the multi-quantum well layer both contain In element, Ga element and N element;

[0007] Wherein, a surface of the second semiconductor layer away from the base substrate has a plurality of first grooves.

[0008] In some embodiments, a surface of the multi-quantum well layer facing away from the substrate has a second groove, and an orthographic projection of the second groove on the substrate overlaps with an orthographic projection of the first groove on the substrate.

[0009] In some embodiments, the orthographic projection of the bottom of the first groove on the substrate is located within the orthographic projection range of the second groove on the substrate.

[0010] In some embodiments, the orthographic projection of the second groove on the base substrate is located within the orthographic projection range of the first groove on the base substrate.

[0011] In some embodiments, the first groove corresponds to the second groove one by one, the second semiconductor layer includes a first region and a second region, the orthographic projection of the first region on the substrate is located within the orthographic projection range of the second groove on the substrate, and the orthographic projection of the second region on the substrate is located outside the orthographic projection of the first groove on the substrate.

[0012] The first region and the second region have different defect densities.

[0013] In some embodiments, the defect density of the first region is higher than the defect density of the second region.

[0014] In some embodiments, the second groove is filled with the second semiconductor layer.

[0015] In some embodiments, the distribution density of the second grooves is 1×10 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2 between.

[0016] In some embodiments, the depth of the first groove is greater than the depth of the second groove.

[0017] In some embodiments, a surface of the second semiconductor layer away from the substrate is divided into a plurality of sub-surfaces spaced apart from each other by the plurality of first grooves.

[0018] In some embodiments, the thickness of the second semiconductor layer is between 200 nm and 300 nm.

[0019] In some embodiments, the first groove has a first longitudinal section parallel to the thickness direction of the substrate, and a width of the first longitudinal section gradually decreases along a direction approaching the substrate.

[0020] In some embodiments, the multi-quantum well layer includes: at least one film layer group, the film layer group includes a quantum well layer and a quantum barrier layer sequentially arranged in a direction away from the substrate, and the quantum well layer contains In, Ga, and N elements;

[0021] The quantum well layer and the quantum barrier layer are conformal.

[0022] In some embodiments, a content of the In element in the quantum well layer is greater than a content of the In element in the second semiconductor layer.

[0023] In some embodiments, the LED epitaxial structure further comprises:

[0024] An island growth layer is located between the first semiconductor layer and the substrate; the island growth layer includes a plurality of growth units arranged at intervals;

[0025] The closing layer is located between the island growth layer and the first semiconductor layer; the closing layer is a continuous film layer, and the closing layer and the island growth layer are made of the same material.

[0026] In some embodiments, the first groove is filled with the third semiconductor layer.

[0027] In some embodiments, the second semiconductor layer is configured to emit red light.

[0028] In a second aspect, the present disclosure provides a light emitting diode, comprising:

[0029] The epitaxial structure described above;

[0030] A first electrode and a second electrode, wherein the first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the third semiconductor layer.

[0031] In a third aspect, the present disclosure provides a method for preparing an LED epitaxial structure, comprising:

[0032] A first semiconductor layer, a multi-quantum well layer, a second semiconductor layer and a third semiconductor layer are sequentially grown on a substrate; the second semiconductor layer and the multi-quantum well layer both contain In element, Ga element and N element;

[0033] Wherein, a surface of the second semiconductor layer away from the base substrate has a plurality of first grooves.

[0034] In some embodiments, a surface of the multi-quantum well layer facing away from the substrate has a second groove, and an orthographic projection of the second groove on the substrate overlaps with an orthographic projection of the first groove on the substrate.

[0035] In some embodiments, the step of growing the multi-quantum well layer includes at least one film layer group growing step, and the film layer group growing step includes:

[0036] Growing a quantum well layer, wherein the surface of the quantum well layer away from the substrate has a plurality of depressions;

[0037] A quantum barrier layer is grown, wherein the quantum barrier layer is conformal to the quantum well layer.

[0038] In some embodiments, the growth temperature of the quantum well layer is between 600°C and 650°C, so that the distribution density of the depressions is between 1×10 9 Pieces / cm 2 ~1×10 10Pieces / cm 2 between;

[0039] The growth temperature of the quantum barrier layer is between 650°C and 700°C.

[0040] In some embodiments, the growth temperature of the second semiconductor layer is between 770°C and 830°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0042] Figure 1 Schematic diagram of film layer distribution of LED epitaxial structure provided in some embodiments of the present disclosure.

[0043] Figure 2A This is a SEM image of a longitudinal section of the second semiconductor layer and the multi-quantum well layer of the LED epitaxial structure provided in some embodiments of the present disclosure.

[0044] Figure 2B for Figure 2A Magnified view of area A.

[0045] Figure 3 The following are SEM images of the surface morphology of the second semiconductor layer and the multi-quantum well layer provided in some embodiments of the present disclosure.

[0046] Figure 4 A schematic comparison diagram of the first groove and the second groove provided in some embodiments of the present disclosure.

[0047] Figure 5 Schematic diagram of a second semiconductor layer and a multi-quantum well layer provided in some embodiments of the present disclosure.

[0048] Figure 6 : is the electroluminescence spectrum of the LED epitaxial structure in the embodiment of the present disclosure.

[0049] Figure 7 Schematic diagram of the peak wavelength shift of the LED epitaxial structure in the embodiment of the present disclosure when the current injection changes from 1 mA to 100 mA. DETAILED DESCRIPTION

[0050] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] As used herein, "parallel" and "perpendicular" include the described situation and the situation similar to the described situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.

[0054] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0055] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0056] In the embodiments of the present disclosure, the description of the numerical range "m1-m2" includes the endpoint values ​​m1 and m2.

[0057] The quantum well structure has a strong quantum confinement effect on carriers and has been widely used to prepare high-efficiency indium gallium nitride (InGaN)-based blue and green light-emitting diodes.

[0058] When the thickness of the InGaN film layer is large, the compressive stress on the film layer increases accordingly, thereby reducing the epitaxial quality of the InGaN film layer.

[0059] The embodiment of the present disclosure provides an LED epitaxial structure. Figure 1 Schematic diagram of film layer distribution of LED epitaxial structure provided in some embodiments of the present disclosure, such as Figure 1 As shown, the LED epitaxial structure includes a substrate 10 , and the following layers, which are arranged on the substrate 10 and in sequence in a direction away from the substrate 10 : a first semiconductor layer 40 , a multi-quantum well layer 50 , a second semiconductor layer 60 , and a third semiconductor layer 70 .

[0060] The material of the base substrate 10 is not limited. For example, the base substrate 10 may be a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0061] Among them, one of the first semiconductor layer 40 and the third semiconductor layer 70 is an N-type doped semiconductor layer, and the other is a P-type doped semiconductor layer. In one example, considering that the growth temperature of the N-type doped semiconductor layer is relatively high, the first semiconductor layer 40 is set as an N-type doped semiconductor layer, and the second semiconductor layer 60 is set as a P-type doped semiconductor layer, that is, in the preparation process, the N-type doped semiconductor layer is grown first to reduce the influence of high temperature on other semiconductor layers.

[0062] The second semiconductor layer 60 and the multi-quantum well layer 50 both contain indium (In) element, gallium (Ga) element and nitrogen (N) element. Figure 2A is a SEM image (scanning electron microscope image) of a longitudinal section of a second semiconductor layer and a multi-quantum well layer of an LED epitaxial structure provided in some embodiments of the present disclosure, Figure 2A The two SEM images in the figure are the same to more clearly illustrate the labels of each position. Figure 2B for Figure 2A A magnified view of area A. Figure 2A As shown, the surface of the second semiconductor layer 60 away from the base substrate 10 has a plurality of first grooves 60 v.

[0063] In the embodiment of the present disclosure, the surface of the second semiconductor layer 60 away from the base substrate 10 has a plurality of first grooves 60v, so that the compressive stress of the second semiconductor layer 60 can be effectively relaxed. In the state of stress relaxation, the second semiconductor layer 60 can achieve effective indium incorporation at a higher growth temperature, thereby greatly improving the crystal quality of the second semiconductor layer 60 and the In component (i.e., molar content).

[0064] In some embodiments, the second semiconductor layer 60 is a light emitting layer for emitting red light.

[0065] In some embodiments, the thickness of the second semiconductor layer 60 is between 200nm and 300nm. If the thickness of the second semiconductor layer 60 is insufficient, it is easy to cause electron leakage or holes to enter the multi-quantum well layer 50, causing the multi-quantum well layer 50 to emit light by mistake; if the thickness of the second semiconductor layer 60 is too large, it is easy to cause stress accumulation, thereby increasing the defect density of the second semiconductor layer 60; the embodiment of the present disclosure sets the thickness of the second semiconductor layer 60 between 200nm and 300nm, thereby preventing the multi-quantum well layer 50 from emitting light by mistake and facilitating the release of the stress of the second semiconductor layer 60.

[0066] For example, the thickness of the second semiconductor layer 60 is between 200 nm and 220 nm, or between 220 nm and 240 nm, or between 240 nm and 260 nm, or between 260 nm and 280 nm, or between 280 nm and 300 nm.

[0067] The inventors found that when preparing an InGaN-based light-emitting diode that emits red light, a higher content of In needs to be doped into the InGaN quantum well layer 51. However, there is a serious lattice mismatch between the InGaN quantum well layer 51 with a high In component and the GaN quantum barrier layer 52, which causes the quantum well layer 51 to produce too many defects during the growth process, resulting in serious non-radiative recombination. In addition, the strong lattice mismatch will introduce a strong polarization electric field in the quantum well layer 51, causing electrons and holes to separate in space, further reducing the luminous efficiency of the red light-emitting diode. In addition, when the current density injected into the quantum well layer 51 increases, the strong polarization electric field will cause the emission wavelength of the red light-emitting diode to blue-shift to the yellow light band, which will seriously affect the color accuracy of display applications.

[0068] In the embodiment of the present disclosure, a second semiconductor layer 60 with a large thickness is grown, and a plurality of first grooves 60v are formed on the second semiconductor layer 60. These first grooves 60v can effectively relax the compressive stress borne by the second semiconductor layer 60. In the state of compressive stress relaxation, the second semiconductor layer 60 can achieve effective In incorporation at a higher growth temperature, thereby greatly improving the crystal quality and In composition of the second semiconductor layer 60. That is, the In-rich phase structure in the second semiconductor layer 60 has the advantages of efficient In incorporation, high crystal quality and close to stress relaxation. Efficient In incorporation makes it easy for the luminous wavelength to reach the red light band. The high crystal quality helps to improve the luminous efficiency of the red light of the In-rich phase in the second semiconductor layer 60. The stress relaxation effect helps to reduce the wavelength shift effect caused by the change of the injected current. These advantages help to prepare a high-efficiency, low blue-shifted red light-emitting diode.

[0069] Furthermore, the thicker second semiconductor layer 60 can play a hole blocking role, effectively preventing the holes in the third semiconductor layer 70 from entering the multi-quantum well layer 50 , so that the holes are concentrated in the second semiconductor layer 60 for radiation recombination.

[0070] In some embodiments, when the thickness of the second semiconductor layer 60 is between 200 nm and 300 nm, the molar content of In is 8%, so that the second semiconductor layer 60 can emit red light. 0.08 Ga 0.92 N.

[0071] Figure 3 is a SEM image of the surface morphology of the second semiconductor layer and the multi-quantum well layer provided in some embodiments of the present disclosure, Figure 4 Schematic diagram of comparison between the first groove and the second groove provided in some embodiments of the present disclosure, Figure 5 Schematic diagram of a second semiconductor layer and a multi-quantum well layer provided in some embodiments of the present disclosure. Figure 5 Figure (a) is a schematic diagram of the longitudinal section of the multi-quantum well layer. Figure 5 Figure (b) is a schematic diagram of the surface of the multi-quantum well layer away from the substrate. Figure 5 Figure (c) is a schematic diagram of the longitudinal section of the multi-quantum well layer and the second semiconductor layer. Figure 5 Figure (d) is a schematic diagram of the multi-quantum well layer away from the substrate surface. Figures 2A to 5 As shown, in some embodiments, the surface of the multi-quantum well layer 50 facing away from the substrate 10 has a second groove 50 v , and the orthographic projection of the second groove 50 v on the substrate 10 overlaps with the orthographic projection of the first groove 60 v on the substrate 10 .

[0072] Among them, the second groove 50v on the multi-quantum well layer 50 is a defect structure induced by stacking faults in the multi-quantum well layer 50 system. There are surrounding mismatch boundaries around the stacking faults in the multi-quantum well layer 50, and these mismatch boundaries will produce a ring-shaped V-shaped pit structure in the process of extending upward, also known as a groove structure. The groove structure can play the role of carrier localization, stress relaxation and improving crystal quality for the multi-quantum well layer 50. In addition, the groove structure in the multi-quantum well layer 50 is easy to control, the growth process is simple, the stress relaxation effect is significant, and no additional substrate processing process is required, so it has excellent application value. The stress relaxation effect of the groove structure is combined with the growth of the second semiconductor layer 60 with a larger thickness, which is conducive to the second semiconductor layer 60 forming a first groove 60v corresponding to the second groove 50v during the growth process, thereby improving the epitaxial quality of the second semiconductor layer 60, so as to achieve high-efficiency, low-blue-shifted In-rich phase red light emission.

[0073] In some embodiments, the multi-quantum well layer 50 includes: at least one film layer group, the film layer group includes a quantum well layer 51 and a quantum barrier layer 52 (in the direction away from the substrate 10) arranged in sequence. Figure 2A and Figure 2B The quantum well layer 51 contains In, Ga, and N elements. The quantum well layer 51 and the quantum barrier layer 52 are conformal.

[0074] It should be noted that the conformal shape of the quantum well layer 51 and the quantum barrier layer 52 means that the morphologies of the two are basically the same, for example, a depression is formed at the same position. In other words, the second groove 50v is a second groove 50v formed on the entire multi-quantum well layer 50.

[0075] In one example, the number of film layer groups is 1 to 20, for example, between 1 and 5, or between 5 and 10, or between 10 and 15, or between 15 and 20.

[0076] In one example, the content of the In element in the quantum well layer 51 is greater than the content of the In element in the second semiconductor layer 60 (the content here refers to the molar content). For example, the quantum well layer 51 is a green light quantum well layer to ensure the formation of the second groove 50v and the first groove 60v and the release of stress. The quantum well layer 51 is a green light quantum well layer, which means that the quantum well layer 51 emits green light when radiation recombination of electrons and holes occurs inside it. For example, the thickness of the quantum well layer 51 is 2.5nm, and the In component is 25%. The thickness of the quantum barrier layer 52 is 10nm.

[0077] In some embodiments, the first groove 60v has a first longitudinal section parallel to the thickness direction of the base substrate 10, and the width of the first longitudinal section gradually decreases along the direction close to the base substrate 10. Figure 2AIn the embodiment, taking one of the first grooves 60v as an example, the widths of three positions of the first longitudinal section are d1, d2, and d3, respectively, and d1>d2>d3.

[0078] For example, the first longitudinal section of the first groove 60v is V-shaped, or W-shaped, or other shapes.

[0079] In some embodiments, the orthographic projection of the bottom of the first groove 60v on the substrate 10 is located within the orthographic projection range of the second groove 50v on the substrate 10. The multi-quantum well layer 50 can be used as the starting point for the growth of the trench-type second semiconductor layer 60, and therefore, the orthographic projection of the bottom of the first groove 60v falls within the orthographic projection range of the second groove 50v.

[0080] Among them, the bottom of the first groove 60v refers to the position where the first groove 60v is closest to the base substrate 10. For example, if the longitudinal section of the first groove 60v is V-shaped, then the longitudinal section of the first groove 60v is the tip position of the V-shaped groove; for another example, if the longitudinal section of the first groove 60v is W-shaped, then the bottom of the first groove 60v is the tip position of the W-shaped groove; for another example, if the longitudinal section of the first groove 60v is an inverted trapezoid, then the bottom of the first groove 60v is the bottom surface of the first groove 60v close to the base substrate 10.

[0081] In some embodiments, the second groove 50v is filled with the second semiconductor layer 60. Exemplarily, the second groove 50v is completely filled with the second semiconductor layer 60.

[0082] When it is necessary to detect whether a second groove 50v exists in a certain epitaxial structure and a longitudinal section of the second groove 50v, a TEM (Transmission Electron Microscope, abbreviated as TEM) detection method may be used for detection.

[0083] In some embodiments, the first groove 60v corresponds to the second groove 50v one-to-one, and the second semiconductor layer 60 includes a first region 61 and a second region 62. The orthographic projection of the first region 61 on the substrate substrate 10 is located within the orthographic projection range of the second groove 50v on the substrate substrate 10. The orthographic projection of the second region 62 on the substrate substrate 10 is located outside the orthographic projection of the first groove 60v on the substrate substrate 10. In some examples, the orthographic projection of the second groove 50v on the substrate substrate 10 is located within the orthographic projection range of the first groove 60v on the substrate substrate 10, then the orthographic projection of the second region 62 is also located outside the orthographic projection of the second groove 50v. The defect density of the first region 61 is different from that of the second region 62. For example, the defect density of the first region 61 is higher than that of the second region 62. From Figure 2A The SEM image shows different black and white contrast.

[0084] In some embodiments, the orthographic projection of the second groove 50v on the substrate 10 is a ring shape, and the second semiconductor layer 60 also includes a third region 63. The orthographic projection of the third region 63 on the substrate 10 is located in the area surrounded by the inner edge of the orthographic projection of the second groove 50v. The defect density of the third region 63 is different from that of the first region 61. For example, the defect density of the first region 61 is higher than the defect density of the third region 63.

[0085] In some embodiments, the distribution density of the second grooves 50v is 1×10 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2 Between (1×10 9 ~1×10 10 When the distribution density of the second grooves 50v is too low, the density of the first grooves 60v on the second semiconductor layer 60 is also reduced, making it difficult to release the compressive stress and to incorporate a high-component In element; when the distribution density of the second grooves 50v is too high, the second grooves 50v are easily connected to each other, making it difficult to form the second semiconductor layer 60 of the desired thickness. 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2 This is beneficial for forming a high-density first groove 60v on the second semiconductor layer 60, thereby improving the effect of alleviating the compressive stress of the second semiconductor layer 60.

[0086] In one example, the distribution density of the second grooves 50v is 1×10 9 Pieces / cm 2 ~3×10 9 Pieces / cm 2 Between, or between 3×10 9 Pieces / cm 2 ~5×10 9 Pieces / cm 2 Between, or between 5×10 9 Pieces / cm 2 ~7×10 9 Pieces / cm 2 Between, or between 7×10 9 Pieces / cm 2 ~9×10 9 Pieces / cm 2 Between, or between 9×10 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2For example, the distribution density of the second groove 50v is 5×10 9 Pieces / cm 2 .

[0087] In some embodiments, the depth of the first groove 60v is greater than the depth of the second groove 50v.

[0088] In some embodiments, the orthographic projection of the second groove 50v on the substrate 10 is within the orthographic projection range of the first groove 60v on the substrate 10. The multi-quantum well layer 50 serves as the starting point for the growth of the second semiconductor layer 60, and the thickness of the second semiconductor layer 60 is much greater than the thickness of the multi-quantum well layer 50, so that during the growth process of the second semiconductor layer 60, a first groove 60v that is deeper and wider than the second groove 50v is gradually formed.

[0089] In one example, at least a portion of the second groove 50v and at least a portion of the first groove 60v are shaped as follows: Figure 4 As shown in , the orthographic projection of the second groove 50v on the substrate 10 is annular, for example, the orthographic projection of the second groove 50v is a circular ring, or a polygonal ring such as a rectangular ring, a hexagonal ring, etc. The distance between the inner ring and the outer ring of the second groove 50v is relatively close. During the growth of the second semiconductor layer 60, the mismatch boundary from the inside of the multi-quantum well layer continues to extend upward during the growth of the second semiconductor layer 60, forming a deeper and wider first groove 60v. Therefore, the orthographic projection of the first groove 60v on the substrate 10 is similar in shape to the orthographic projection of the second groove 50v on the substrate 10, and the width of the first groove 60v is larger. At this time, the first longitudinal section of the first groove 60v passing through its own central axis is W-shaped.

[0090] In some embodiments, Figure 3 and Figure 5 As shown, the surface of the second semiconductor layer 60 away from the base substrate 10 is divided into multiple sub-surfaces 60a spaced apart from each other by multiple first grooves 60v, thereby further alleviating the compressive stress of the second semiconductor layer 60, improving the crystal quality, and enhancing the luminescence efficiency of the In-rich phase.

[0091] In some embodiments, Figure 1 As shown, the LED epitaxial structure also includes: a nucleation layer 20 and a closing layer 30. The nucleation layer 20 is an island growth layer, which is located between the first semiconductor layer 40 and the multi-quantum well layer 50. The island growth layer includes a plurality of growth units arranged at intervals. The closing layer 30 is located between the island growth layer and the first semiconductor layer 40. The closing layer 30 is a continuous film layer, and the closing layer 30 and the island growth layer are made of the same material.

[0092] The island growth layer and the closing layer 30 can both be unintentionally doped GaN layers. The island growth layer is used to reduce the dislocation density. By sequentially forming the island growth layer and the closing layer 30, the dislocations are bent, thereby reducing the dislocation density, which is beneficial to improving the quality of the first semiconductor layer 40 formed subsequently.

[0093] In some embodiments, the first groove 60 v is filled with the third semiconductor layer 70 . For example, the first groove 60 v is completely filled with the third semiconductor layer 70 .

[0094] In one example, the thickness of the third semiconductor layer 70 is between 100 nm and 200 nm, for example, 100 nm, 125 nm, 150 nm, 175 nm, or 200 nm. The surface of the third semiconductor layer 70 away from the substrate 10 may be a flat or approximately flat surface.

[0095] Since the material composition of the third semiconductor layer 70 and the second semiconductor layer 60v is quite different, in the SEM image of the epitaxial structure, the contrast of the third semiconductor layer 70 and the second semiconductor layer 60 is different, so the outline of the first groove 60v can be seen.

[0096] The present disclosure also provides a method for preparing the above LED epitaxial structure, including:

[0097] A first semiconductor layer 40 , a multi-quantum well layer 50 , a second semiconductor layer 60 and a third semiconductor layer 70 are sequentially grown on a base substrate 10 ; the second semiconductor layer 60 and the multi-quantum well layer 50 both contain In element, Ga element and N element.

[0098] The surface of the second semiconductor layer 60 away from the base substrate 10 has a plurality of first grooves 60 v.

[0099] The following is an introduction to the preparation method of the LED epitaxial structure with reference to a specific example. The preparation method of the LED epitaxial structure specifically includes:

[0100] S1. Provide a substrate 10. The substrate 10 may be a 4-inch, 6-inch, 8-inch or 12-inch substrate. In addition, the substrate 10 may be a sapphire substrate, a silicon substrate or a silicon carbide substrate.

[0101] S2. Place the substrate 10 in a MOCVD (Metal-organic Chemical Vapor Deposition) device, heat it to 1050° C. in a hydrogen atmosphere, and purge it for 10 minutes to clean the surface of the substrate 10 and expose the surface dangling bonds.

[0102] S3 . Growing an unintentionally doped GaN layer on the base substrate 10 .

[0103] Specifically, the temperature in the device is lowered to 540° C., and TMGa, NH 3 and H 2 are introduced to grow the nucleation layer 20 ; the temperature is then further raised to 1040° C. to grow a closing layer 30 with a thickness of 2 to 3 μm.

[0104] S4 , growing a first semiconductor layer 40 .

[0105] Specifically, the device temperature is further increased to 1060° C., and TMGa, NH 3 , SiH 4 and H 2 are introduced to grow an n-type doped GaN layer with a thickness of 1.5 to 2.5 microns on the unintentionally doped GaN layer.

[0106] S5 , growing a multi-quantum well layer 50 on the first semiconductor layer 40 .

[0107] Among them, the growth step of the multi-quantum well layer 50 includes at least one film layer group growth step, and the film layer group growth step includes: growing a quantum well layer 51, and the quantum well layer 51 has multiple depressions away from the surface of the substrate 10; then, growing a quantum barrier layer 52, and the quantum barrier layer 52 is conformal with the quantum well layer 51.

[0108] In one example, the growth temperature of the quantum well layer 51 is between 600° C. and 650° C., so that the distribution density of the depressions is between 1×10 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2 The growth temperature of the quantum barrier layer 52 is between 650°C and 700°C. For example, the growth temperature of the quantum well layer 51 is between 600°C and 620°C, or between 620°C and 640°C, or between 640°C and 650°C; for example, the growth temperature of the quantum barrier layer 52 is between 650°C and 670°C, or between 670°C and 690°C, or between 690°C and 700°C.

[0109] In one example, step S5 specifically includes: lowering the temperature, growing film layer groups, each film layer group including a quantum well layer 51 and a quantum barrier layer 52. The number of film layer groups is 1 to 20. The quantum well layer 51 is an InGaN layer with grooves, and the quantum barrier layer 52 is conformal to the quantum well layer 51 and is a GaN layer with grooves. Among them, the growth temperature of the InGaN quantum well layer 51 is 630°C, the gases introduced are TEGa, TMIn, NH3 and N2, the thickness is 2.5nm, and the indium component is 25%; and the growth temperature of the GaN quantum barrier layer 52 is 690°C, the gases introduced are TEGa, NH3 and N2, and the thickness is 10nm. Since the growth temperature of the multi-quantum well layer 50 is relatively low, a multi-quantum well layer 50 with a density of 1×10 9 Pieces / cm 2 ~1×10 10 Pieces / cm 2 The groove structure therebetween, ie, the second groove 50v.

[0110] S6 , further epitaxially growing a second semiconductor layer 60 on the multi-quantum well layer 50 .

[0111] In one example, the growth temperature of the second semiconductor layer 60 is between 770° C. and 830° C. For example, the growth temperature of the second semiconductor layer 60 is between 770° C. and 790° C., or between 790° C. and 810° C., or between 810° C. and 830° C.

[0112] In one example, step S6 specifically includes: raising the growth temperature to 800°C, introducing TEGa, TMIn, NH3 and N2, and growing an InGaN thick film with a thickness of 200nm to 300nm and an indium component of 8%. During the growth of the InGaN thick film, the high-density groove structure originating from the multi-quantum well layer 50 continues to extend upward to form a deeper and wider groove, that is, the first groove 60v. Under the spatial isolation effect of the high-density grooves, the surface of the InGaN thick film is no longer connected to each other, forming a plurality of discrete sub-surfaces 60a. This high-density groove significantly alleviates the compressive stress of the InGaN thick film, thereby improving the In incorporation ability. Although the growth temperature of the InGaN thick film is much higher than that of the trench-type multi-quantum well, effective In incorporation is still achieved, and high-quality In is successfully and continuously grown. 0.08 Ga 0.92 N thick film.

[0113] S7 . Growing the third semiconductor layer 70 on the second semiconductor layer 60 .

[0114] In one example, step S7 specifically includes: introducing TMGa, NH3, Cp2Mg and H2 to grow a P-type doped GaN layer with a thickness of about 150 nm at a growth temperature of 920°C.

[0115] Figure 6 is the electroluminescence spectrum of the LED epitaxial structure in the embodiment of the present disclosure, Figure 6 This is the electroluminescence spectrum of the LED epitaxial structure under 100mA current injection. Its peak wavelength is 643nm and the spectrum half-width is 70nm. Figure 7 is the peak wavelength shift of the LED epitaxial structure in the embodiment of the present disclosure when the current injection changes from 1 mA to 100 mA. Figure 6 and Figure 7 It can be seen that at 1 mA, the emission wavelength of the LED epitaxial structure is 648 nm. When the current changes from 1 mA to 100 mA, the wavelength shift of the LED epitaxial structure based on the second semiconductor layer 60 is only 5 nm, which is much smaller than the wavelength shift (>30 nm) of the traditional red light epitaxial wafer based on the quantum well structure. It can be seen that the internal polarization electric field of the In-rich phase in the InGaN thick film is much lower than that of the InGaN in the quantum well structure, mainly due to the fact that the stress of the In-rich phase is almost completely relaxed.

[0116] The present disclosure also provides a light emitting diode (LED), which may be a micro light emitting diode, comprising the LED epitaxial structure in the above embodiment, and a first electrode and a second electrode. The first electrode is electrically connected to the first semiconductor layer 40, and the second electrode is electrically connected to the second semiconductor layer 60.

[0117] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An LED epitaxial structure, characterized in that: include: substrate; Disposed on the substrate and sequentially arranged in a direction away from the substrate: a first semiconductor layer, a multi-quantum well layer, a second semiconductor layer, and a third semiconductor layer; the second semiconductor layer and the multi-quantum well layer both contain In, Ga, and N elements; Wherein, a surface of the second semiconductor layer away from the base substrate has a plurality of first grooves.

2. The LED epitaxial structure according to claim 1, characterized in that: A second groove is formed on a surface of the multi-quantum well layer facing away from the base substrate, and an orthographic projection of the second groove on the base substrate overlaps with an orthographic projection of the first groove on the base substrate.

3. The LED epitaxial structure according to claim 2, characterized in that: The orthographic projection of the bottom of the first groove on the base substrate is located within the orthographic projection range of the second groove on the base substrate.

4. The LED epitaxial structure according to claim 2, characterized in that: The orthographic projection of the second groove on the base substrate is located within the orthographic projection range of the first groove on the base substrate.

5. The LED epitaxial structure according to claim 2, characterized in that: The first groove corresponds to the second groove one by one, the second semiconductor layer includes a first region and a second region, the orthographic projection of the first region on the substrate is located within the orthographic projection of the second groove on the substrate, and the orthographic projection of the second region on the substrate is located outside the orthographic projection of the first groove on the substrate. The first region and the second region have different defect densities.

6. The LED epitaxial structure according to claim 5, wherein: The defect density of the first region is higher than the defect density of the second region.

7. The LED epitaxial structure according to claim 2, characterized in that: The second groove is filled with the second semiconductor layer.

8. The LED epitaxial structure according to claim 2, wherein: The distribution density of the second grooves is 1×10 9 pieces / cm 2 ~1×10 10 pieces / cm 2 between.

9. The LED epitaxial structure according to claim 2, characterized in that: The depth of the first groove is greater than the depth of the second groove.

10. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: A surface of the second semiconductor layer away from the base substrate is divided into a plurality of sub-surfaces spaced apart from each other by the plurality of first grooves.

11. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The thickness of the second semiconductor layer is between 200 nm and 300 nm.

12. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The first groove has a first longitudinal section parallel to the thickness direction of the base substrate, and a width of the first longitudinal section gradually decreases in a direction approaching the base substrate.

13. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The multi-quantum well layer comprises: at least one film layer group, the film layer group comprises a quantum well layer and a quantum barrier layer sequentially arranged in a direction away from the substrate, the quantum well layer contains In, Ga, and N elements; The quantum well layer and the quantum barrier layer are conformal.

14. The LED epitaxial structure according to claim 13, characterized in that: The content of the In element in the quantum well layer is greater than the content of the In element in the second semiconductor layer.

15. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The LED epitaxial structure further includes: an island growth layer located between the first semiconductor layer and the substrate; the island growth layer comprises a plurality of growth units arranged at intervals; The closing layer is located between the island growth layer and the first semiconductor layer; the closing layer is a continuous film layer, and the closing layer and the island growth layer are made of the same material.

16. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The first groove is filled with the third semiconductor layer.

17. The LED epitaxial structure according to any one of claims 1 to 9, characterized in that: The second semiconductor layer is used for emitting red light.

18. A light emitting diode, characterized in that: include: The LED epitaxial structure according to any one of claims 1 to 17; A first electrode and a second electrode, the first electrode is electrically connected to the first semiconductor layer, and the second electrode is electrically connected to the third semiconductor layer.

19. A method for preparing an LED epitaxial structure, characterized in that: include: A first semiconductor layer, a multi-quantum well layer, a second semiconductor layer and a third semiconductor layer are sequentially grown on a substrate; the second semiconductor layer and the multi-quantum well layer both contain In, Ga and N elements; Wherein, a surface of the second semiconductor layer away from the base substrate has a plurality of first grooves.

20. The preparation method according to claim 19, characterized in that A second groove is formed on a surface of the multi-quantum well layer facing away from the base substrate, and an orthographic projection of the second groove on the base substrate overlaps with an orthographic projection of the first groove on the base substrate.

21. The preparation method according to claim 20, characterized in that The step of growing the multi-quantum well layer includes at least one film layer group growth step, and the film layer group growth step includes: Growing a quantum well layer, wherein the surface of the quantum well layer away from the substrate has a plurality of depressions; A quantum barrier layer is grown, wherein the quantum barrier layer is conformal to the quantum well layer.

22. The preparation method according to claim 21, characterized in that The growth temperature of the quantum well layer is between 600°C and 650°C, so that the distribution density of the depressions is 1×10 9 pieces / cm 2 ~1×10 10 pieces / cm 2 between; The growth temperature of the quantum barrier layer is between 650° C. and 700° C.

23. The preparation method according to claim 19, characterized in that The growth temperature of the second semiconductor layer is between 770° C. and 830° C.

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