Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a method of manufacturing the same. The display panel includes: a base substrate; a circuit element layer provided on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light emitting opening; a light emitting element disposed on the circuit element layer and including a first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; the metal pattern layer is arranged on the pixel defining layer; and a low thermal conductive layer disposed between the pixel defining layer and the metal pattern layer, thereby having excellent display quality.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117412, filed on September 5, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a display panel and a method of manufacturing the display panel, and more particularly, to a display panel including a light emitting element having a common layer and a method of manufacturing the display panel. Background Art

[0004] Various display devices are being developed for multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation systems, game consoles, and wearable devices. Such display devices may include a display panel that displays an image. The display panel uses a so-called self-luminous display element to display an image by emitting light from a light-emitting material including an organic compound, quantum dots, etc. in a light-emitting layer provided between electrodes facing each other.

[0005] For example, recently, as demands for high definition and portability of multimedia electronic devices increase, a display panel capable of being reduced in size and providing excellent high-resolution display quality is required. Summary of the invention

[0006] This embodiment provides a display panel with excellent display quality.

[0007] Embodiments also provide a high-resolution display panel with excellent display quality.

[0008] Embodiments also provide a method of manufacturing a display panel capable of improving display quality by not only minimizing damage to a light emitting layer and a common layer in a light emitting region but also effectively disconnecting an organic film provided as a common layer in adjacent light emitting regions.

[0009] However, the embodiments are not limited to the embodiments set forth herein.The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0010] One embodiment provides a display panel, comprising: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and comprising a light-emitting opening; a light-emitting element disposed on the circuit element layer and comprising a first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer disposed on the pixel defining layer; and a low thermal conductivity layer disposed between the pixel defining layer and the metal pattern layer.

[0011] In one embodiment, the low thermal conductivity layer may have a thermal conductivity of about 1.0 W / mK or less.

[0012] In one embodiment, the functional layer may not overlap with the metal pattern layer.

[0013] In one embodiment, the functional layer may include a light-emitting layer and an organic layer disposed on at least one of an upper portion and a lower portion of the light-emitting layer, wherein the organic layer may overlap with the light-emitting opening and a portion of the pixel defining layer adjacent to the light-emitting opening and be spaced apart from the metal pattern layer.

[0014] In one embodiment, the low thermal conductivity layer may include a polymer amorphous carbon film.

[0015] In one embodiment, the polymer amorphous carbon film has sp 3 The ratio of carbon bonds may be in the range of about 50% to about 70%.

[0016] In one embodiment, the low thermal conductivity layer may have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a thermal conductivity of about 1.2 g / cm 3 To about 1.6g / cm 3 density within the range of .

[0017] In one embodiment, in a cross section perpendicular to the base substrate, a first width of the metal pattern layer in one direction may be smaller than a second width of the pixel defining layer in the direction.

[0018] In an embodiment, the first width may be about 1 / 2 or less of the second width.

[0019] In one embodiment, the width of the metal pattern layer in one direction may be smaller than the width of the low thermal conductivity layer in the direction.

[0020] In one embodiment, the low thermal conductivity layer may cover the upper surface and the side surface of the pixel defining layer.

[0021] In one embodiment, the low thermal conductivity layer may be disposed on an upper surface of the pixel defining layer, and a side surface of the pixel defining layer may be covered by the functional layer.

[0022] In an embodiment, a concave portion may be formed on an upper surface of the pixel defining layer, and the low thermal conductive layer may be disposed in the concave portion.

[0023] In one embodiment, a first concave portion may be formed on an upper surface of the pixel defining layer, the low thermal conductivity layer may be disposed in the first concave portion, a second concave portion may be formed on an upper surface of the low thermal conductivity layer, and the metal pattern layer may be disposed in the second concave portion.

[0024] In one embodiment, a display panel divided into a plurality of light-emitting areas spaced apart from each other and a peripheral area disposed between the plurality of light-emitting areas in a plan view may include: a base substrate; a circuit element layer disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light-emitting opening overlapping each of the plurality of light-emitting areas; a plurality of light-emitting elements including a first electrode disposed on the circuit element layer, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer corresponding to the peripheral area and disposed on the pixel defining layer; and a low thermal conductivity layer disposed directly between the pixel defining layer and the metal pattern layer.

[0025] In one embodiment, the first electrode of the multiple light-emitting elements may overlap with each of the multiple light-emitting regions, the second electrode may be set as a common layer throughout the multiple light-emitting elements, and the functional layer may not overlap with the metal pattern layer and may be set in the multiple light-emitting regions and the peripheral region adjacent to the multiple light-emitting regions.

[0026] In one embodiment, the functional layer may include: a light-emitting layer; a hole transport region disposed between the first electrode and the light-emitting layer; and an electron transport region disposed between the light-emitting layer and the second electrode, wherein the light-emitting layer may be disposed in the light-emitting opening, and at least one of the hole transport region and the electron transport region may be disposed in the light-emitting opening and extend above the upper surface of the pixel defining layer adjacent to the light-emitting opening.

[0027] In one embodiment, the multiple light-emitting regions may include a first light-emitting region, a second light-emitting region, and a third light-emitting region emitting light in different wavelength ranges, and the multiple light-emitting elements may include a first light-emitting layer overlapping with the first light-emitting region, a second light-emitting layer overlapping with the second light-emitting region, and a third light-emitting layer overlapping with the third light-emitting region, wherein the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer may contain different light-emitting materials, and the multiple light-emitting elements may include the hole transport region that is identical to each other and the electron transport region that is identical to each other.

[0028] In an embodiment, at least one edge portion of the hole transport region and the electron transport region disposed to extend over the upper surface of the pixel defining layer may be spaced apart from the metal pattern layer.

[0029] In an embodiment, in a plan view, a metal layer boundary line defined by the edge portion and an edge portion of the metal pattern layer may be located in the peripheral region, and the edge portion may be closer to the plurality of light emitting regions than the metal layer boundary line.

[0030] In one embodiment, the low thermal conductivity layer may include a polymer amorphous carbon film.

[0031] In one embodiment, the polymer amorphous carbon film has sp 3 The ratio of the carbon bond may be in the range of about 50% to about 70%, and the low thermal conductivity layer may have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a thermal conductivity of about 1.2 g / cm 3 To about 1.6g / cm 3 density within the range of .

[0032] In one embodiment, in a cross section perpendicular to the base substrate, a first width of the metal pattern layer in one direction may be smaller than each of a second width of an upper surface of the pixel defining layer adjacent to the metal pattern layer in the direction and a third width of an upper surface of the low thermal conductivity layer adjacent to the metal pattern layer in the direction.

[0033] In one embodiment, in a plan view, a size of the metal pattern layer may be smaller than a size of the pixel defining layer.

[0034] In one embodiment, a method for manufacturing a display panel may include: forming a first electrode on a circuit element layer; forming a pixel defining layer on the circuit element layer; forming a low thermal conductivity layer on the pixel defining layer; forming a metal pattern layer on the low thermal conductivity layer to overlap with the pixel defining layer; providing a preliminary functional layer to overlap with the pixel defining layer and the first electrode; forming a functional layer by providing current to the metal pattern layer to remove a portion of the preliminary functional layer overlapping with the metal pattern layer; forming a second electrode to cover the functional layer and the metal pattern layer; and forming an encapsulation layer on the second electrode.

[0035] In one embodiment, the metal pattern layer may be a Joule heating wire, and forming the functional layer by removing the portion of the preliminary functional layer may include: removing the portion of the preliminary functional layer by sublimating the portion of the preliminary functional layer using heat generated in the metal pattern layer.

[0036] In one embodiment, the forming of the low thermal conductivity layer may include forming a polymeric amorphous carbon film using a hydrocarbon gas using a deposition facility.

[0037] In one embodiment, the metal pattern layer may have a width in one direction that is smaller than a width of the low thermal conductive layer.

[0038] In one embodiment, the functional layer may be formed so as not to overlap with the metal pattern layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of the specification. The accompanying drawings illustrate embodiments and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0040] Figure 1A is a schematic perspective view of an electronic device according to an embodiment;

[0041] Figure 1B is an exploded schematic perspective view of an electronic device according to an embodiment;

[0042] Figure 2A is a schematic perspective view of an electronic device according to an embodiment;

[0043] Figure 2B is an exploded schematic perspective view of an electronic device according to an embodiment;

[0044] Figure 3 is a schematic cross-sectional view of a display panel according to an embodiment;

[0045] Figure 4 is a schematic plan view of a display panel according to an embodiment;

[0046] Figure 5 is a schematic plan view of a portion of a display panel according to an embodiment;

[0047] Figure 6 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0048] Figure 7 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0049] Fig. 8A is a schematic cross-sectional view of a light emitting element according to an embodiment;

[0050] Figure 8B is a schematic cross-sectional view of a light emitting element according to an embodiment;

[0051] Fig. 9is a schematic cross-sectional view illustrating a portion of a display panel according to an embodiment;

[0052] Fig.10 is a schematic cross-sectional view illustrating a portion of a display panel according to an embodiment;

[0053] Fig.11 is a schematic plan view of a portion of a display panel according to an embodiment;

[0054] Fig.12 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0055] Fig.13 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0056] Fig.14 is a schematic cross-sectional view of a portion of a display panel according to an embodiment;

[0057] Fig.15 is a schematic cross-sectional view of a portion of a display panel according to an embodiment; and

[0058] 16A to 16H The steps of a method for manufacturing a display panel according to an embodiment are respectively illustrated. Specific embodiments

[0059] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments need not be exclusive, nor do they limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment.

[0060] Unless otherwise specified, the illustrated embodiments should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the present invention.

[0061] The use of cross-hatching and / or shading in the drawings is generally used to clarify the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading does not convey or illustrate any preference or requirement for a particular material, material property, size, ratio, commonality between the illustrated elements, and / or any other characteristics, attributes, characteristics, etc. of the elements, unless otherwise stated. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order. Moreover, the same reference numerals represent the same elements.

[0062] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. For the purposes of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Moreover, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] Although the terms "first", "second", etc. can be used in this article to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0064] Spatially relative terms such as "below," "below," "below," "above," "on," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes to describe the relationship of one element to another element as illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" can cover both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and, for this reason, the spatially relative descriptors used herein should be interpreted accordingly.

[0065] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be restrictive. As used herein, the "one" and "the" in the singular are intended to also include plural forms, unless the context clearly states otherwise. In addition, the terms "including" and / or "comprising" when used in this specification clearly indicate the presence of stated features, integers, steps, operations, elements, parts and / or their groups, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and just for this reason, are used to explain the inherent deviations of the measured values, calculated values ​​and / or the values ​​provided that will be recognized by those of ordinary skill in the art.

[0066] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments disclosed herein are not necessarily to be construed as limited to the specific illustrated shapes of the regions, but rather include shape deviations caused by, for example, manufacturing. In this manner, the regions illustrated in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0067] According to the practice in the art, some embodiments are described and illustrated in the form of functional blocks, units and / or modules in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of implementing blocks, units and / or modules by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuits) that perform other functions. Moreover, each block, unit and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the present invention. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0068] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0069] Figure 1A is a schematic perspective view of an electronic device according to an embodiment. Figure 1B is an exploded schematic perspective view of an electronic device according to an embodiment. Figure 2A is a schematic perspective view of an electronic device according to an embodiment, and Figure 2B is an exploded schematic perspective view of an electronic device according to an embodiment.

[0070] The electronic device DD according to an embodiment can be activated according to an electrical signal and display an image. For example, the electronic device DD may be small and medium-sized devices such as monitors, laptop computers, personal digital terminals, car navigation units, game consoles, smart phones, tablet computers, and cameras, as well as large devices such as televisions and external billboards. However, these are presented only as examples and are not limited to any one embodiment as long as they do not depart from the concept of the present invention.

[0071] exist Figure 1A and Figure 1B In the embodiment, the electronic device DD according to one embodiment is illustrated as a smart phone. Figure 2A and Figure 2B Example The electronic device HMD according to an embodiment is a wearable display device.

[0072] The electronic device DD according to an embodiment may be rigid or flexible. The term "flexible" refers to a bendable property. For example, the flexible electronic device DD may include a bendable device, a rollable device, or a foldable device.

[0073] Figure 1A The following drawings illustrate the first direction DR1 to the third direction DR3, and the directions represented by the first direction to the third direction DR1, DR2 and DR3 described in this document are relative concepts and can be converted into other directions. In the description, the first direction DR1 and the second direction DR2 can be orthogonal to each other, and the third direction DR3 can be a normal direction relative to the plane defined by the first direction DR1 and the second direction DR2.

[0074] The thickness direction of the electronic device DD may be parallel to a third direction DR3, which is a normal direction relative to a plane defined by the first direction DR1 and the second direction DR2. In the description, the front (or upper) surface and the rear (or lower) surface of the component of the electronic device DD may be defined based on the third direction DR3. The front (or upper) surface and the rear (or lower) surface of each component of the electronic device DD may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be substantially parallel to the third direction DR3. The separation distance between the front surface and the rear surface defined along the third direction DR3 may correspond to the thickness of the component.

[0075] In the description, the expression "on a plane" or "in a plan view" may be defined as being observed in the third direction DR3. In the description, the expression "in a cross section" may be defined as being observed in the first direction DR1 or the second direction DR2. The directions indicated by the first direction to the third directions DR1, DR2, and DR3 are relative concepts and may be converted to other directions.

[0076] refer to Figure 1A and Figure 1B According to an embodiment, the electronic device DD may display an image IM through the display surface FS. The image IM may include a still image and a dynamic image. Figure 1A A viewing window and an icon are illustrated as examples of the image IM. The display surface FS displaying the image IM may correspond to a front surface of the electronic device DD.

[0077] refer to Figure 1B , the electronic device DD according to an embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to form the exterior of the electronic device DD.

[0078] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define (or form) a display surface FS of the electronic device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may have a visible light transmittance of about 90% or more.

[0079] The frame area BZA may have a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define (or form) the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. In another example, the frame area BZA may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, but the embodiment is not limited thereto.

[0080] The display module DM may be disposed below the window WP. The display module DM may generate an image IM. The image IM generated by the display module DM may be displayed on a display surface IS of the display module DM and may be visually recognized by a user from the outside through the transmission area TA.

[0081] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated according to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be covered by the frame area BZA and may not be visually recognized from the outside.

[0082] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide an inner space. The display module DM may be accommodated in the inner space.

[0083] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a frame and / or a plate made of glass, plastic, or metal, or a combination thereof. The housing HAU may reliably protect the components of the electronic device DD housed in the internal space from external impacts.

[0084] refer to Figure 1B According to an embodiment, the display module DM may include a display panel DP and an input sensor ISL. For example, the electronic device DD may further include a protective member disposed on the lower surface of the display panel DP, or an anti-reflection member and / or an optical member disposed on the upper surface of the input sensor ISL.

[0085] The input sensor ISL may obtain coordinate information of an external input. The input sensor ISL may have a multi-layer structure. The input sensor ISL may include a single conductive layer or multiple conductive layers. The input sensor ISL may include a single insulating layer or multiple insulating layers. The input sensor ISL may sense the external input, for example, in a capacitive manner. In the present invention, the operation mode of the input sensor ISL is not limited thereto, and in one embodiment, the input sensor ISL may sense the external input in an electromagnetic induction manner or a pressure sensing manner. The input sensor ISL may be disposed (for example, directly disposed) in an encapsulation layer TFE (see FIG. 2 ) of a display panel DP to be described later. Figure 3 ). In the description, the expression “component A is directly disposed on component B” means that no adhesive layer is disposed between component A and component B. In another embodiment, the input sensor ISL may be omitted.

[0086] Figure 2A is a schematic perspective view of an electronic device HMD according to an embodiment. Figure 2B is an exploded schematic perspective view of a portion of an electronic device HMD according to an embodiment.

[0087] exist Figure 2A and Figure 2B The electronic device HMD according to an embodiment illustrated in can be activated according to an electrical signal and is a wearable device. The wearable device may be a device worn on the user's body and may include a head mounted display (HMD) device that implements extended reality (XR). Figure 2A and Figure 2B The exemplary electronic device HMD is a head mounted display device, but embodiments are not limited thereto.

[0088] exist Figure 2A and Figure 2B The electronic device HMD according to one embodiment illustrated in FIG. 1 is a display device worn on the head of a user. The electronic device HMD can provide an image in a state where the actual peripheral vision of the user is blocked. The user wearing the electronic device HMD can be immersed in virtual reality more easily.

[0089] The electronic device HMD may include a main body unit HS, a belt STR, a pad portion PP, and a display panel DP. For example, the electronic device HMD may include various sensors and a camera.

[0090] The main body unit HS can be worn on the user's head. A display panel DP that displays an image, an acceleration sensor, etc. can be accommodated in the main body unit HS. The acceleration sensor can detect the movement of the user and send the detected signal to the display panel DP. Accordingly, the display panel DP can provide an image corresponding to the change of the user's gaze. Therefore, the user can experience a virtual reality similar to actual reality.

[0091] In the main unit HS, components having various functions other than those described above may be accommodated. For example, a control unit for adjusting the volume or screen brightness may be additionally provided outside the main unit HS. The control unit may be provided in the form of a physical button, a touch sensor, etc. For example, a proximity sensor for determining whether a user is wearing the device may be accommodated in the main unit HS. For example, an external display panel may be further provided in the main unit HS.

[0092] The body unit HS may be divided into a body portion HS-1 and a cover portion HS-2. Figure 2B The body portion HS-1 and the cover portion HS-2 are illustrated as being separated from each other, but the embodiment is not limited thereto. For example, the body portion HS-1 and the cover portion HS-2 may be provided as an integral unit and may not be separated from each other.

[0093] The display panel DP may be disposed between the body portion HS-1 and the cover portion HS-2. Each of the display panels DP may provide an image through the display area DA. Each of the display panels DP may include a non-display area NDA surrounding the display area DA. In an embodiment, the non-display area NDA may be disposed only on one side of the display area DA, or may be omitted.

[0094] exist Figure 2B In the example of displaying the left eye image and the right eye image by separate display panels DP, the embodiment is not limited thereto. In another example, the left eye image and the right eye image may be displayed by a single display panel. The display panel DP may be driven by separate drive units. However, not limited thereto, the display panel DP may be driven by a single drive unit. The display panel DP may generate an image corresponding to the input image data.

[0095] The band STR may be coupled to the main body unit HS so that the main body unit HS may be easily worn by the user. The band STR may include a main band portion STR1 and an upper band portion STR2.

[0096] The main belt portion STR1 can be worn along the circumference of the user's head. The main belt portion STR1 can fix the main body unit HS to the user so that the main body unit HS can be in close contact with the user's head. The upper belt portion STR2 can connect the main body unit HS and the main belt portion STR1 to each other along the upper part of the user's head. The upper belt portion STR2 can prevent the main body unit HS from falling. For example, the upper belt portion STR2 can distribute the load of the main body unit HS to further improve the wearing comfort of the user.

[0097] As long as the main unit HS is fixed to the user, the belt STR can be modified to Figure 2AIn another embodiment, the upper band portion STR2 may be omitted. In another embodiment, the band STR may be modified into various forms, such as a helmet connected to the main body unit HS or a temple of glasses connected to the main body unit HS.

[0098] The cushion part PP may be provided between the main body unit HS and the user's head. The cushion part PP may be made of a material having a freely deformable shape. For example, the cushion part PP may be formed of a polymer resin (e.g., polyurethane, polycarbonate, polypropylene, and polyethylene) or a sponge made by foaming and molding a rubber solution, a urethane material, or an acrylic material. However, the embodiment is not limited thereto.

[0099] The pad part PP can play a role in close contact between the main body unit HS and the user, thereby improving the wearing comfort of the user. The pad part PP can be removed from the main body unit HS. In another embodiment, the pad part PP can be omitted.

[0100] The optical system OL may be disposed inside the main body portion HS-1 of the main body unit HS. The optical system OL may magnify an image provided from the display panel DP. Each of the display panels DP may display an image in a third direction DR3 through a display area DA parallel to a plane defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The optical system OL may be spaced apart from the display panel DP in the third direction DR3. The optical system OL may be disposed between the display panel DP and the user's eyes. The optical system OL may include a right-eye optical system OL_R and a left-eye optical system OL_L. The left-eye optical system OL_L may magnify an image and provide the image to the left pupil of the user, and the right-eye optical system OL_R may magnify an image and provide the image to the right pupil of the user.

[0101] The left-eye optical system OL_L and the right-eye optical system OL_R may be spaced apart from each other in the first direction DR1. The distance between the right-eye optical system OL_R and the left-eye optical system OL_L may be adjusted in response to the distance between the two eyes of the user. For example, the distance between the optical system OL and the display panel DP may be adjusted according to the user's vision.

[0102] The optical system OL may be a convex aspherical lens. For example, the optical system OL may be a pancake-shaped lens, but the embodiment is not limited thereto. In this embodiment, each of the left-eye optical system OL_L and the right-eye optical system OL_R is described as being composed of only one lens, but the embodiment is not limited thereto. For example, each of the left-eye optical system OL_L and the right-eye optical system OL_R may include a plurality of lenses.

[0103] Included in the reference Figures 1A to 2B The display panel DP in the electronic device DD and the electronic device HMD of the described embodiment may be an organic light emitting display panel, an inorganic light emitting display panel, an organic-inorganic light emitting display panel, a quantum dot display panel, a micro LED display panel, or a nano LED display panel. In this embodiment, the display panel DP is described as an organic light emitting display panel, but the embodiment is not limited thereto.

[0104] Figure 3 is a schematic cross-sectional view of a display panel DP according to an embodiment. The display panel DP according to an embodiment may include a base substrate BL, a circuit element layer D-CL disposed on the base substrate BL, a display element layer D-OL, and an encapsulation layer TFE. The display panel DP may include a display area DA and a non-display area NDA. The display element layer D-OL may be disposed to correspond to the display area DA (or may overlap the display area DA). However, the embodiment is not limited thereto, and at least a portion of the display element layer D-OL may be disposed in the non-display area NDA.

[0105] The base substrate BL may be a supporting substrate on which a circuit element layer D-CL and a display element layer D-OL are provided. The base substrate BL may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc. The base substrate BL may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. For example, the base substrate BL may be a single crystal silicon substrate, but the embodiment is not limited thereto. In the description, the display area DA and the non-display area NDA may be considered to be defined on the base substrate BL, and a component provided on the base substrate BL may also be considered to be provided to overlap with the display area DA or the non-display area NDA.

[0106] The circuit element layer D-CL may include at least one insulating layer and a circuit element. The circuit element may include a signal line, a pixel driving circuit, etc. The circuit element layer D-CL may be formed by a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and then patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process.

[0107] The display element layer D-OL may include a light emitting element, and the light emitting element may include a light emitting layer that emits light.

[0108] The encapsulation layer TFE may include thin films, some of which may be provided to improve optical efficiency, and other thin films may be provided to protect the light emitting element.

[0109] The encapsulation layer TFE may be a thin film encapsulation layer. The encapsulation layer TFE may be a single layer or multiple layers stacked on each other. The encapsulation layer TFE may include at least one insulating layer. The encapsulation layer TFE according to an embodiment may include at least one inorganic film (hereinafter referred to as an inorganic encapsulation film). For example, the encapsulation layer TFE according to an embodiment may include at least one organic film (hereinafter referred to as an organic encapsulation film) and at least one inorganic encapsulation film.

[0110] Inorganic encapsulation film can protect the light-emitting element ED (see Figure 6 ) from moisture / oxygen, and the organic encapsulation film can protect the light-emitting element ED (see Figure 6 ) from foreign substances such as dust particles. The inorganic encapsulation film may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, but the embodiment is not limited thereto. The organic encapsulation film may include an acrylic compound, an epoxy compound, etc. The organic encapsulation film may include a photopolymerizable organic material, but the embodiment is not limited thereto.

[0111] Figure 4 1 is a schematic plan view of a display panel DP according to an embodiment. The display panel DP may include a base substrate BL divided into a display area DA and a non-display area NDA, as shown in FIG. Figure 3 Described.

[0112] The display panel DP may include pixels PX disposed in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD disposed in the non-display area NDA.

[0113] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include pixel rows extending in the first direction DR1 and arranged in the second direction DR2, and pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0114] The signal lines SGL may include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. Each of the gate lines GL may be connected to a corresponding pixel in the pixels PX, and each of the data lines DL may be connected to a corresponding pixel in the pixels PX. The power lines PL may be electrically connected to the pixels PX. The control signal lines CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0115] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and output the generated gate signal to the gate line GL in sequence. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0116] The pad portion PLD may be a portion to which the flexible circuit board is connected. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line in the signal line SGL. The pixel pad D-PD may be connected to the corresponding pixel PX through the signal line SGL. For example, any one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0117] For example, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor ISL (see Figure 1B However, without limitation thereto, the input pad may be provided at the input sensor ISL (see Figure 1B ) and connected to the pixel pad D-PD and a separate circuit board. In another example, the input sensor ISL (see Figure 1B ) and may not include input pads.

[0118] Figure 5 is an enlarged schematic plan view of a portion of a display panel DP according to an embodiment. Figure 5 Example from the display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) observed display area DA (see Figure 1B ) part. Figure 5 The display panel DP according to an embodiment is shown in FIG. Figure 3 ) in the arrangement of the light-emitting areas PXA-R, PXA-G and PXA-B.

[0119] The display panel DP according to an embodiment may include light emitting regions PXA-R, PXA-G, and PXA-B spaced apart from each other in a plan view and a peripheral region NPXA disposed between the light emitting regions PXA-R, PXA-G, and PXA-B.

[0120] The display panel DP according to an embodiment may include three types of light emitting areas PXA-R, PXA-G, and PXA-B that are distinguished from each other. Figure 5 The three types of light emitting regions PXA-R, PXA-G, and PXA-B illustrated in FIG. 4 may be repeatedly disposed in the entire display area DA. The light emitting regions PXA-R, PXA-G, and PXA-B may also be referred to as pixel regions.

[0121] The display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B that emit light of different wavelength ranges and are spaced apart from each other on a plane (or in a plan view). For example, the display area DA may include a peripheral area NPXA. The peripheral area NPXA may be referred to as a non-light emitting area. Figure 5 , the first light emitting area PXA-R may correspond to a red pixel R, the second light emitting area PXA-G may correspond to a green pixel G, and the third light emitting area PXA-B may correspond to a blue pixel B.

[0122] The peripheral area NPXA may be disposed around the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The peripheral area NPXA may set (or define) boundaries of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The peripheral area NPXA may surround the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. In the peripheral area NPXA, a structure (such as a pixel defining layer PDL (see FIG. 1 ) that prevents color mixing in the first to third light-emitting areas (e.g., the first to third pixel areas) PXA-R, PXA-G, and PXA-B) may be disposed. Figure 6 )) so as to correspond to the peripheral area NPXA.

[0123] Since the display panel DP according to an embodiment includes the metal pattern layer JHL (see Figure 7 ) and a low thermal conductivity layer PTL (see FIG. 1 ) disposed below the metal pattern layer JHL to be described later. Figure 7 ), and the functional layer FL (see Figure 6 ) may not be connected to each other at a portion corresponding to the peripheral region NPXA, so that leakage current may be prevented from being transmitted to the adjacent light emitting regions PXA-R, PXA-G, and PXA-B. For example, the functional layer FL (see FIG. 1 ) provided in the light emitting regions PXA-R, PXA-G, and PXA-B Figure 6 ) may have excellent film characteristics to prevent damage. Therefore, the display panel DP according to an embodiment may have excellent display quality.

[0124] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may correspond to the light emitting elements ED1, ED2, and ED3 (see FIG. Figure 7 ) provided by the light. The first to third light emitting areas PXA-R, PXA-G and PXA-B can be arranged according to the light emitted by the display module DM (see Figure 1B ) to classify (or differentiate) the color of the externally emitted light.

[0125] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color lights are not limited thereto.

[0126] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be defined as a region in which the first electrode AE ​​of the light emitting element (see Figure 6 ) through a light emitting opening OH (see Figure 6 ) exposed areas.

[0127] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be provided in plural and may be repeatedly arranged in a specific arrangement in the display area DA. For example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged with each other along the second direction DR2.

[0128] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0129] Figure 5 The arrangement form of the first to third light emitting regions PXA-R, PXA-G, and PXA-B is illustrated, but the embodiment is not limited thereto. For example, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be arranged in various forms. In one embodiment, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have In another example, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have a stripe arrangement or a diamond pixel arrangement. (Diamond )Layout form.

[0130] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane (or in a plan view). For example, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have a polygonal, circular, or elliptical shape. Figure 5 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a diamond shape) and the second light emitting region PXA-G having an octagonal shape are illustrated on a plane (or in a plan view).

[0131] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape on a plane (or in a plan view), or at least some of them may have a shape different from the others. Figure 5 The first and third light emitting regions PXA-R and PXA-B having the same shape and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are illustrated on a plane (or in a plan view).

[0132] At least some of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas (or sizes) from each other on a plane (or in a plan view). In one embodiment, the area (or size) of the first light-emitting region PXA-R emitting red light may be larger than the area (or size) of the second light-emitting region PXA-G emitting green light and smaller than the area (or size) of the third light-emitting region PXA-B emitting blue light. However, the size relationship between the areas (or sizes) of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B emitting light of different colors is not limited thereto, and may vary according to the design of the display panel DP of one embodiment. For example, without limitation thereto, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have the same area (or the same size) on a plane (or in a plan view).

[0133] For example, the shapes, areas (or sizes), and arrangements of the first to third light emitting regions PXA-R, PXA-G, and PXA-B of the display panel DP according to an embodiment may be designed in various ways according to the color of emitted light or the size and configuration of the display panel DP included in the electronic device, and the embodiment is not limited thereto. Figure 5 For example, in one embodiment, in addition to the first to third light emitting areas PXA-R, PXA-G, and PXA-B, the display panel DP may further include a light emitting area emitting white light.

[0134] Figure 6is a schematic cross-sectional view of a partial area of ​​a display panel DP according to an embodiment. Figure 7 is a schematic cross-sectional view of a partial region of a display panel DP according to an embodiment, and illustrates portions corresponding to light emitting regions PXA-R, PXA-G, and PXA-B. Figure 6 It can be corresponding to Figure 5 A schematic cross-sectional view of a portion of line II', and Figure 7 It can be corresponding to Figure 5 Schematic cross-sectional view of a portion along line II-II'.

[0135] Figure 6 The example corresponds to the first light emitting region PXA-R (see Figure 5 ) and a cross section of a portion of the periphery of the first light emitting region PXA-R. However, Figure 6 The cross section illustrated in FIG. 5 is not limited to the first light emitting region PXA-R and the peripheral region thereof, and may be a portion corresponding to any one of the light emitting regions included in the display panel DP.

[0136] refer to Figure 6 , the display panel DP may include a base substrate BL, a circuit element layer D-CL, a display element layer D-OL, and an encapsulation layer TFE.

[0137] The circuit element layer D-CL may include a buffer layer BFL, a transistor TR, a signal transmission region SCL, first to fifth insulating layers 10 , 20 , 30 , 40 , and 50 , an upper electrode pattern EE, and connection electrodes CNE1 and CNE2 .

[0138] The buffer layer BFL may be disposed on the base substrate BL. The buffer layer BFL may improve the bonding strength between the base substrate BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0139] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 6 Only a portion of the semiconductor pattern is illustrated, and the semiconductor pattern may be further provided in the light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 5 ). The semiconductor pattern may be arranged throughout the light emitting regions PXA-R, PXA-G, and PXA-B in a specific rule. The semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0140] The first region may have a higher conductivity than the second region and may be substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (or channel region) of a transistor. For example, a portion of the semiconductor pattern may be an active region of a transistor, another portion of the semiconductor pattern may be a source region or a drain region of the transistor, and another portion of the semiconductor pattern may be a conductive region.

[0141] The source region SD, the active region AD, and the drain region DD of the transistor TR may be formed of a semiconductor pattern. Figure 6 A portion of the signal transmission region SCL formed of the semiconductor pattern is illustrated. For example, the signal transmission region SCL may be connected to the drain region DD of the transistor TR on a plane (or in a plan view).

[0142] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed over the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, and 50 may be inorganic layers or organic layers.

[0143] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source region SD, the active region AD, the drain region DD, and the signal transmission region SCL of the transistor TR disposed on the buffer layer BFL. The gate GD of the transistor TR may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate GD. The upper electrode pattern EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode pattern EE.

[0144] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0145] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0146] The display element layer D-OL may be disposed on the circuit element layer D-CL. The display element layer D-OL may include a light emitting element ED, a pixel defining layer PDL, a metal pattern layer JHL, and a low thermal conductivity layer PTL.

[0147] The light emitting element ED may include a first electrode AE, a second electrode CE facing the first electrode AE, and a functional layer FL disposed between the first electrode AE ​​and the second electrode CE.

[0148] The first electrode AE ​​may be disposed on the circuit element layer D-CL. The first electrode AE ​​may overlap each of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B. In one embodiment, the first electrode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer D-CL. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined in the fifth insulating layer 50 (or through the fifth insulating layer 50). Accordingly, the first electrode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2, thereby being electrically connected to the corresponding circuit element. The first electrode AE ​​may include a single-layer structure or a multi-layer structure.

[0149] The first electrode AE ​​may be an anode or a cathode. For example, the first electrode AE ​​may be a pixel electrode. The second electrode CE may be a cathode or an anode. The second electrode CE may be a common electrode. For example, in the case where the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and in the case where the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0150] The functional layer FL may include a light emitting layer and an organic layer disposed on at least one of an upper portion and a lower portion of the light emitting layer. The functional layer FL may include at least one light emitting structure. The functional layer FL may include an organic layer provided in common in the light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ) in at least one organic layer. For example, the functional layer FL may include at least one organic layer provided to the light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ) and patterned so as to correspond to the light emitting layer of each of the light emitting regions PXA-R, PXA-G, and PXA-B. The common layer may be at least one organic layer that may overlap the light emitting opening OH and a portion of the pixel defining layer PDL adjacent to the light emitting opening OH and be spaced apart from the metal pattern layer JHL, and, for example, the common layer may perform a hole transport function or an electron transport function. The configuration of the functional layer FL will be described in more detail later.

[0151] For example, the light emitting element ED according to an embodiment may further include a capping layer disposed on the second electrode CE. The capping layer may include a plurality of layers or a single layer.

[0152] The display element layer D-OL may include a pixel defining layer PDL disposed on the circuit element layer D-CL. The light emitting opening OH may be defined in the pixel defining layer PDL (or may pass through the pixel defining layer PDL). The light emitting opening OH of the pixel defining layer PDL may expose at least a portion of the first electrode AE. In an embodiment, the pixel defining layer PDL may cover an edge portion of the first electrode AE.

[0153] The pixel defining layer PDL may have a single-layer structure or a multi-layer structure. The pixel defining layer PDL may be formed of a polymer resin. For example, the pixel defining layer PDL may be formed by including a polyacrylate resin or a polyimide resin. For example, in addition to the polymer resin, the pixel defining layer PDL may be formed by further including an inorganic material. For example, the pixel defining layer PDL may be formed by including a light absorbing material, or may be formed by including a black pigment or a black dye. The pixel defining layer PDL formed by including a black pigment or a black dye may realize a black pixel defining layer. In the case of forming the pixel defining layer PDL, carbon black or the like may be used as a black pigment or a black dye, but the embodiment is not limited thereto.

[0154] For example, the pixel defining layer PDL may be formed of an inorganic material. For example, the pixel defining layer PDL may be formed of a silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) is formed by inorganic materials.

[0155] The encapsulation layer TFE may be disposed on the second electrode CE of the light emitting element ED. In another example, when the light emitting element ED includes a capping layer, the encapsulation layer TFE may be disposed on the capping layer. The encapsulation layer TFE may cover the light emitting element ED.

[0156] Figure 7 1 is a schematic cross-sectional view of a portion of a display panel DP according to an embodiment. The display panel DP may include a base substrate BL, a circuit element layer D-CL, a display element layer D-OL, and an encapsulation layer TFE stacked in a third direction DR3. The base substrate BL, the circuit element layer D-CL, the display element layer D-OL, and the encapsulation layer TFE will not be described in detail. Figure 6 The contents described in overlap, and for the sake of convenience of description, the differences will be described.

[0157] refer to Figure 7, the display panel DP may include first to third light emitting areas PXA-R, PXA-G, and PXA-B distinguished from each other and a peripheral area NPXA disposed between the first to third light emitting areas PXA-R, PXA-G, and PXA-B.

[0158] The light emitting regions PXA-R, PXA-G and PXA-B may be defined by being divided by the pixel defining layer PDL. In one embodiment, the first to third light emitting regions PXA-R, PXA-G and PXA-B of the display panel DP may be defined to correspond to partial regions of the first electrode AE ​​exposed by the light emitting opening OH, respectively.

[0159] The display element layer D-OL may include a pixel defining layer PDL and light emitting elements ED1, ED2, and ED3 divided by the pixel defining layer PDL. The display element layer D-OL may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. The first light emitting element ED1 may emit red light, the second light emitting element ED2 may emit green light, and the third light emitting element ED3 may emit blue light.

[0160] The first light emitting element ED1 may include a first pixel electrode AE1, a first functional layer FL1, and a second electrode CE, the second light emitting element ED2 may include a second pixel electrode AE2, a second functional layer FL2, and a second electrode CE, and the third light emitting element ED3 may include a third pixel electrode AE3, a third functional layer FL3, and a second electrode CE. Each of the first to third pixel electrodes AE1, AE2, and AE3 may be referred to as a first electrode.

[0161] Fig. 8A and Figure 8B Each of is a schematic cross-sectional view illustrating a light emitting element according to an embodiment. Figure 7 Each of the first to third light emitting elements ED1, ED2, and ED3 in the embodiment may have Fig. 8A or Figure 8B The composition of the embodiment of the light-emitting element illustrated in FIG.

[0162] refer to Fig. 8A According to an embodiment, the light emitting element ED may include a first electrode AE, a functional layer FL, and a second electrode CE, and the functional layer FL may include a hole transport region HTR, an emission layer EML, and an electron transport region ETR. According to an embodiment, the light emitting element ED may include a single light emitting structure, which is a stacked structure of the hole transport region HTR, the emission layer EML, and the electron transport region ETR. For example, Figure 7Each of the first to third functional layers FL1, FL2 and FL3 of the first to third light emitting elements ED1, ED2 and ED3 illustrated in the drawings may include a single light emitting structure which is a stacked structure of a hole transport region HTR, an emission layer EML and an electron transport region ETR.

[0163] In the light emitting element ED, the first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. The first electrode AE ​​may be formed of a metal material, a metal alloy or a conductive compound. The first electrode AE ​​may include at least one selected from the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn and Zn, a compound selected from two or more thereof, a mixture selected from two or more thereof or an oxide thereof.

[0164] In the case where the first electrode AE ​​is a transmissive electrode, the first electrode AE ​​may be composed of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO). In the case where the first electrode AE ​​is a semi-transmissive electrode or a reflective electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). In another example, the first electrode AE ​​may have a multilayer structure including: a reflective film or a semi-transmissive film formed of the above materials; and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but the embodiment is not limited thereto. For example, the embodiment is not limited thereto, and the first electrode AE ​​may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, an oxide of the above-described metal material, or the like.

[0165] The second electrode CE may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. In the case where the second electrode CE is a transmissive electrode, the second electrode CE may be made of a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO).

[0166] In the case where the second electrode CE is a transmissive electrode or a reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, or a compound or mixture thereof (e.g., AgMg, AgYb, or MgYb). In another example, the second electrode CE may have a multilayer structure including: a reflective film or a semi-transmissive film formed of the above materials; and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the second electrode CE may include the metal material described above, a combination of two or more metal materials selected from the metal materials described above, an oxide of the metal material described above, etc.

[0167] The light-emitting layer EML may include a light-emitting material. The light-emitting layer EML may have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multilayer structure consisting of a plurality of layers made of different materials. The light-emitting layer may include a fluorescent or phosphorescent material. In the light-emitting element ED according to an embodiment, the light-emitting layer EML may include an organic light-emitting material, an organic metal complex, a quantum dot, etc. as the light-emitting material.

[0168] For example, the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in the light emitting layer EML can emit light in different wavelength ranges. The first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) may include a light-emitting layer EML including different light-emitting materials.

[0169] Fig. 8A The exemplary light emitting element ED includes a single light emitting layer EML, but the light emitting element ED may further include an auxiliary light emitting layer for improving light emitting efficiency in addition to a main light emitting layer including a light emitting material emitting light of a selected color. For example, in one embodiment, the light emitting layer EML may have a stacked structure of sub-light emitting layers having different light emitting material compositions.

[0170] The light emitting element ED may include a hole transport region HTR disposed between the first electrode AE ​​and the light emitting layer EML. The hole transport region HTR may include at least one of a hole injection layer HIL, a hole transport layer HTL, an auxiliary light emitting layer, and an electron blocking layer. For example, the hole transport region HTR may include a hole injection layer HIL and a hole transport layer HTL sequentially stacked on the first electrode AE.

[0171] For example, the first to third functional layers FL1, FL2 and FL3 (see Figure 7) can be formed simultaneously in the same process step. The first to third functional layers FL1, FL2 and FL3 (see Figure 7 The hole transport region HTR in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the hole transport region HTR can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in each of them.

[0172] The light emitting element ED may include an electron transport region ETR disposed between the light emitting layer EML and the second electrode CE. The electron transport region ETR may include at least one of a hole blocking layer, an electron transport layer ETL, and an electron injection layer EIL. For example, the electron transport region ETR may include an electron transport layer ETL and an electron injection layer EIL disposed on the light emitting layer EML, but the embodiment is not limited thereto. The electron transport region ETR may have a single-layer structure made of a single material, a single-layer structure made of different materials, or a multilayer structure consisting of a plurality of layers made of different materials.

[0173] For example, the first to third functional layers FL1, FL2 and FL3 (see Figure 7 The electron transport region ETR in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 The electron transport region ETR in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the electron transport region ETR can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in each of them.

[0174] refer to Figure 8B According to an embodiment, a light-emitting element ED-a may include a first electrode AE, a functional layer FL-a, and a second electrode CE, and the functional layer FL-a may include light-emitting structures EU-B and EU-T. The light-emitting structures EU-B and EU-T may include light-emitting layers EML-B and EML-T, respectively. Accordingly, the functional layer FL-a may include light-emitting layers EML-B and EML-T. For example, a light-emitting element ED-a according to an embodiment may be a light-emitting element having a series structure including light-emitting layers EML-B and EML-T separated from each other.

[0175] The light-emitting element ED-a according to an embodiment may further include a charge generation layer CGL. When a voltage is applied to the light-emitting element ED-a, the charge generation layer CGL may generate charges (electrons and holes) by forming a complex through an oxidation-reduction reaction. The charge generation layer CGL may provide the generated charges to each of the adjacent light-emitting structures EU-B and EU-T. The charge generation layer CGL may improve the efficiency of the current generated in each of the adjacent light-emitting structures EU-B and EU-T, and may play a role in controlling the charge balance between the adjacent light-emitting structures EU-B and EU-T.

[0176] The charge generation layer CGL may have a layer structure in which an n-type charge generation layer n-CGL and a p-type charge generation layer p-CGL are combined with each other.

[0177] The n-type charge generation layer n-CGL may provide electrons to the adjacent light emitting structures EU-B and EU-T. The n-type charge generation layer n-CGL may be a layer in which a base material is doped with an n-dopant. The p-type charge generation layer p-CGL may provide holes to the adjacent light emitting structures EU-B and EU-T. The p-type charge generation layer p-CGL may be a layer in which a base material is doped with a p-dopant.

[0178] The light emitting element ED-a may include a first light emitting structure EU-B and a second light emitting structure EU-T disposed on the first light emitting structure EU-B. A charge generation layer CGL may be disposed between the first light emitting structure EU-B and the second light emitting structure EU-T.

[0179] The first light emitting structure EU-B may include a first hole transport region HTR-B, a first light emitting layer EML-B, and a first electron transport region ETR-B, and the second light emitting structure EU-T may include a second hole transport region HTR-T, a second light emitting layer EML-T, and a second electron transport region ETR-T.

[0180] refer to Fig. 8A The description of the hole transport region HTR provided may be equally applied to the first hole transport region HTR-B and the second hole transport region HTR-T. For example, in the light emitting element ED-a according to an embodiment, the first hole transport region HTR-B and the second hole transport region HTR-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first hole transport region HTR-B and the second hole transport region HTR-T may have different stacking structures, or the first hole transport region HTR-B and the second hole transport region HTR-T may contain different hole transport materials.

[0181] refer to Fig. 8AThe description of the light-emitting layer EML provided may also be applied to the first light-emitting layer EML-B and the second light-emitting layer EML-T. For example, in the light-emitting element ED-a according to an embodiment, the first light-emitting layer EML-B and the second light-emitting layer EML-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first light-emitting layer EML-B and the second light-emitting layer EML-T may have different stacking structures, or the first light-emitting layer EML-B and the second light-emitting layer EML-T may include different light-emitting materials. For example, each of the first light-emitting layer EML-B and the second light-emitting layer EML-T may include a stacked sub-light-emitting layer or a stacked auxiliary light-emitting layer.

[0182] refer to Fig. 8A The description of the electron transport region ETR provided may also be applied to the first electron transport region ETR-B and the second electron transport region ETR-T. For example, in the light-emitting element ED-a according to an embodiment, the first electron transport region ETR-B and the second electron transport region ETR-T may have the same structure and be formed of the same material. However, the embodiment is not limited thereto, and the first electron transport region ETR-B and the second electron transport region ETR-T may have different stacking structures, or the first electron transport region ETR-B and the second electron transport region ETR-T may contain different electron transport materials.

[0183] For example, the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in the light emitting structures EU-B and EU-T can emit light in different wavelength ranges. The first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) may include light-emitting layers EML-B and EML-T, each of the light-emitting layers EML-B and EML-T containing different light-emitting materials.

[0184] The first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the first hole transport region HTR-B can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ). For example, including the first to third functional layers FL1, FL2 and FL3 (see Figure 7) can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the second hole transport region HTR-T can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in each of them.

[0185] For example, the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The first electron transport region ETR-B can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the first electron transport region ETR-B can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ). For example, including the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) can be formed simultaneously in the same process step. The second electron transport region ETR-T can be provided in the same process step by using the same material and then disconnected by the metal pattern layer JHL, so that the second electron transport region ETR-T can be separately provided in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in each of them.

[0186] The first to third functional layers FL1, FL2 and FL3 (see Figure 7 The charge generation layer CGL in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 The charge generation layer CGL in the embodiment of the present invention can be formed by using the same material in the same process step and then disconnected by the metal pattern layer JHL, so that the charge generation layer CGL can be separately disposed in the first to third functional layers FL1, FL2 and FL3 (see Figure 7 ) in each of them.

[0187] Reference again Figure 7, the functional layers FL1, FL2, and FL3 of the light emitting elements ED1, ED2, and ED3 may extend to the light emitting regions PXA-R, PXA-G, and PXA-B and the peripheral region NPXA adjacent to the light emitting regions PXA-R, PXA-G, and PXA-B. For example, the functional layers FL1, FL2, and FL3 of the light emitting elements ED1, ED2, and ED3 may be disposed in portions of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B and the peripheral region NPXA adjacent to the plurality of light emitting regions PXA-R, PXA-G, and PXA-B.

[0188] The display panel DP according to an embodiment may include a metal pattern layer JHL. The metal pattern layer JHL may overlap with the pixel defining layer PDL. The metal pattern layer JHL may not overlap with the upper surface (eg, the entire upper surface) of the pixel defining layer PDL, and may overlap only with a portion of the upper surface of the pixel defining layer PDL.

[0189] The metal pattern layer JHL may be a Joule heating wire that generates heat when current is supplied. When current flows through the metal pattern layer JHL, heat of about 400°C or more may be generated. The metal pattern layer JHL may be formed of a metal material having a high resistance characteristic. For example, the metal pattern layer JHL may contain molybdenum (Mo), titanium (Ti), or tungsten (W). For example, the metal pattern layer JHL may be formed of a metal material containing molybdenum (Mo). However, the embodiment is not limited thereto, and any metal material may be used for the metal pattern layer JHL without limitation, as long as it is a metal material that generates heat of about 90°C or more, which is capable of removing organic materials when current is supplied.

[0190] Figure 7 In the display panel DP according to an embodiment, the metal pattern layers JHL may be provided to correspond to the peripheral areas NPXA, respectively, and may be spaced apart from each other in a cross section. However, the embodiment is not limited thereto, and in order to easily supply current to the metal pattern layer JHL, at least a portion of the metal pattern layers JHL provided to correspond to the peripheral areas NPXA, respectively, may be connected to each other. For example, the metal pattern layer JHL may overlap with the peripheral area NPXA and be provided as an integral part connected to each other.

[0191] The metal pattern layer JHL may be provided in such a manner that the organic layers provided as common layers in the adjacent light emitting regions PXA-R, PXA-B, and PXA-G are disconnected from each other in some regions. In one embodiment, the common layer may be the hole transport regions HTR, HTR-T, and HTR-B (see Fig. 8A and Figure 8B ), electron transport regions ETR, ETR-T and ETR-B (see Fig. 8A and Figure 8B ) or charge generation layer CGL (see Figure 8B ).

[0192] In the case where the common layer is connected to each other between the light-emitting areas PXA-R, PXA-B, and PXA-G, leakage current may occur through the common layer. Therefore, color mixing may occur between the light-emitting areas PXA-R, PXA-B, and PXA-G. Therefore, by disconnecting the common layer, the display quality can be improved. For example, for the disconnection of the common layer, there is a method of using the step difference of the structure by providing a structure separately on the pixel defining layer PDL, but in one embodiment, by using a metal pattern layer JHL that generates heat by a Joule heating method without introducing (or forming) a separate structure, a structure in which the common layers are disconnected from each other can be easily formed.

[0193] For example, since the organic layer is patterned by using the metal pattern layer JHL without introducing (or forming) a separate structure, although the size of the light emitting region (e.g., the pixel region) is small, a disconnected organic layer can be provided, and thus, the display panel DP according to an embodiment can have high-resolution characteristics. The display panel DP according to an embodiment can be used in a miniaturized electronic device, etc., and can have ultra-high-resolution characteristics.

[0194] The display panel DP according to an embodiment may include a low thermal conductivity layer PTL disposed below the metal pattern layer JHL. The low thermal conductivity layer PTL may be disposed (e.g., directly disposed) below the metal pattern layer JHL. The low thermal conductivity layer PTL may overlap the metal pattern layer JHL (e.g., the entire metal pattern layer JHL). The low thermal conductivity layer PTL may be disposed (e.g., directly disposed) between the pixel defining layer PDL and the metal pattern layer JHL.

[0195] The low thermal conductivity layer PTL can prevent the heat generated in the metal pattern layer JHL from being transferred to the light emitting regions PXA-R, PXA-G, and PXA-B. The low thermal conductivity layer PTL can inhibit the heat generated in the metal pattern layer JHL from being transferred to the functional layer FL disposed in the light emitting regions PXA-R, PXA-G, and PXA-B, and can prevent the functional layer FL from being damaged, thereby being able to improve the light emitting efficiency and quality of the light emitting elements ED1, ED2, and ED3.

[0196] The low thermal conductivity layer PTL may have a thermal conductivity of about 1.0 W / mK or less. For example, the thermal conductivity of the low thermal conductivity layer PTL may be about 0.5 W / mK or less. For example, the thermal conductivity of the low thermal conductivity layer PTL may be about 0.28 W / mK.

[0197] The low thermal conductivity layer PTL may include a polymer amorphous carbon film. 3The ratio of carbon bonds may be in the range of about 50% to about 70%. For example, the sp 3 The ratio of carbon bonds may be about 60%. For example, the low thermal conductivity layer PTL may have a refractive index of about 1.75 or less at a wavelength of about 550 nm and a thermal conductivity of about 1.2 g / cm 3 To about 1.6g / cm 3 For example, the low thermal conductivity layer PTL may be composed of a sp 3 carbon bonds, a refractive index of about 1.64 at a wavelength of about 550 nm, and about 1.3 g / cm 3 A polymer-type amorphous carbon film of high density is formed.

[0198] In one embodiment, the low thermal conductivity layer PTL may be formed of a sp 3 carbon bonds, a refractive index of about 1.75 or less at a wavelength of about 550 nm, and about 1.2 g / cm 3 To about 1.6g / cm 3 A polymer-type amorphous carbon film with a high density is formed, thereby having low thermal conductivity characteristics.

[0199] In one embodiment, a deposition facility may be used to form the low thermal conductivity layer PTL. The low thermal conductivity layer PTL may be formed by providing hydrocarbon gas and using a chemical vapor deposition (CVD) facility. For example, a C 2 H 4 The gas is used as a source to form the low thermal conductivity layer PTL.

[0200] In the display panel DP according to an embodiment, the functional layers FL1, FL2, and FL3 of the light emitting elements ED1, ED2, and ED3 may not overlap with the metal pattern layer JHL. The functional layers FL1, FL2, and FL3 may be disposed in the light emitting openings OH corresponding to the light emitting areas PXA-R, PXA-G, and PXA-B, respectively, and may be partially disposed to extend over the pixel defining layer PDL adjacent to the light emitting openings OH.

[0201] The first to third functional layers FL1, FL2, and FL3 disposed in the light emitting regions PXA-R, PXA-G, and PXA-B may be disconnected by the metal pattern layer JHL and may be separated from each other. The first to third functional layers FL1, FL2, and FL3 may be disposed in the light emitting regions PXA-R, PXA-G, and PXA-B, respectively, and overlap at least a portion of the peripheral region NPXA adjacent to the light emitting regions PXA-R, PXA-G, and PXA-B, but may not overlap with the metal pattern layer JHL.

[0202] Fig. 9 yes Figure 7The region "AA" is selected from the second light emitting region PXA-G and the peripheral region NPXA adjacent to the second light emitting region PXA-G, but Fig. 9 The structure illustrated in FIG. 4 can be similarly applied to other light-emitting regions and their adjacent regions.

[0203] Fig. 9 The case where the functional layer FL includes a hole transport region HTR, a light emitting layer EML, and an electron transport region ETR is exemplified. The light emitting layer EML of the functional layer FL may be provided by patterning in the light emitting opening OH. For example, the light emitting layer EML may be patterned and provided in the light emitting opening OH, which is defined to correspond to Figure 7 Each of the light emitting areas PXA-R, PXA-G and PXA-B illustrated in FIG.

[0204] Reference again Fig. 9 , the hole transport region HTR and the electron transport region ETR of the functional layer FL may be disposed in the light emitting opening OH, and may be partially disposed above the pixel defining layer PDL by extending from a portion of the functional layer FL disposed in the light emitting opening OH. In one embodiment, at least one of the hole transport region HTR and the electron transport region ETR may be disposed in the light emitting opening OH and extend above the upper surface US-PD of the pixel defining layer PDL adjacent to the light emitting opening OH. The hole transport region HTR and the electron transport region ETR extending above the pixel defining layer PDL may be on the low thermal conductivity layer PTL. In one embodiment, at least one edge portion of the hole transport region HTR and the electron transport region ETR disposed to extend above the upper surface US-PD of the pixel defining layer PDL may be spaced apart from the metal pattern layer JHL.

[0205] Fig.10 is an enlarged schematic cross-sectional view of a portion of a display panel DP according to an embodiment. Fig.10 The example includes the light emitting element ED and a partial region of the pixel defining layer PDL adjacent to the light emitting element ED.

[0206] In one embodiment, the low thermal conductivity layer PTL may cover the pixel defining layer PDL. The low thermal conductivity layer PTL may cover the upper surface US-PD and the side surface SS-PD of the pixel defining layer PDL.

[0207] In one embodiment, in a cross section perpendicular to the base substrate BL, the metal pattern layer JHL has a first width W in a direction (eg, a horizontal direction) of JH may be smaller than the second width W of the pixel defining layer PDL in the direction PD For example, the first width W of the metal pattern layer JHL is JH The second width W of the pixel defining layer PDL may bePD For example, the second width W of the pixel defining layer PDL is about 1 / 2 or less. PD The first width W of the metal pattern layer JHL may be in the range of about 4 μm to about 5 μm, and JH It may be in the range of about 1 μm to about 2 μm. For example, in one embodiment, the second width W of the pixel defining layer PDL is PD may be about 2 μm, and the first width W of the metal pattern layer JHL may be about 2 μm. JH For example, the second width W of the pixel defining layer PDL compared thereto is about 1 μm or less. PD It may be the width of an upper portion of the pixel defining layer PDL disposed adjacent to the metal pattern layer JHL.

[0208] In one embodiment, since the metal pattern layer JHL has a width smaller than that of the pixel defining layer PDL, although heat is generated from the metal pattern layer JHL, the heat transferred to the organic layer disposed in the light emitting regions PXA-R, PXA-B, and PXA-G separated by the pixel defining layer PDL can be reduced. For example, in the display panel DP according to one embodiment, since the low thermal conductivity layer PTL is disposed in contact with (e.g., in direct contact with) the metal pattern layer JHL so as to overlap with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), damage to the organic layer in the light emitting region can be minimized while including a common layer disconnected by the metal pattern layer JHL, thereby having excellent display quality. For example, the organic layer may be a hole transport region, an electron transport region, a charge generation layer, etc.

[0209] refer to Fig.10 , the edge portion EDP of the functional layer FL extending to be disposed above the pixel defining layer PDL may be disposed (e.g., directly disposed) on the low thermal conductivity layer PTL. For example, the edge portion EDP of the functional layer FL may be spaced apart from the metal pattern layer JHL. For example, the shape and arrangement position of the edge portion EDP of the functional layer FL are not limited to Fig.10 The shape and arrangement position illustrated in FIG. 1 and FIG. 2 may adjust the shape and arrangement position of the edge portion EDP of the functional layer FL by changing the Joule heating conditions in the metal pattern layer JHL.

[0210] The upper surface of the low thermal conductive layer PTL that is not covered by the functional layer FL and is exposed may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0211] In one embodiment, each of the metal pattern layer JHL and the low thermal conductivity layer PTL may be formed to have a thickness of several kiloangstroms. For example, each of the metal pattern layer JHL and the low thermal conductivity layer PTL may have a thickness of about However, the embodiment is not limited thereto.

[0212] Fig.11 is a schematic plan view briefly illustrating a portion of a display panel DP according to an embodiment. Fig.11 A portion of the display area is illustrated.

[0213] Fig.11 The arrangement relationship of the light emitting area PXA, the metal pattern layer JHL, the low thermal conductivity layer PTL, and the edge portion EDP of the functional layer FL on a plane (or in a plan view) is illustrated. Fig.11 In the embodiment, the outer peripheral portion of the light emitting region PXA may correspond to the peripheral region NPXA (see Figure 5 The metal pattern layer JHL and the low thermal conductivity layer PTL may be disposed in the peripheral area NPXA (see Figure 5 )middle.

[0214] In one embodiment, the low thermal conductive layer PTL may overlap with the region (e.g., the entire region) where the metal pattern layer JHL is provided, and may be provided to a region further extended toward the light emitting region PXA. When viewed on a plane defined by the first direction DR1 and the second direction DR2 (or in a plan view), the area (or size) of the low thermal conductive layer PTL may be greater than the area (or size) of the metal pattern layer JHL.

[0215] When viewed on a plane (or in a plan view), a metal layer boundary line JBL defined by edge portions EDP of the functional layer FL and the metal pattern layer JHL may be located in the peripheral region, and the edge portion EDP may be closer to the light emitting region PXA than the metal layer boundary line JBL.

[0216] For example, in Fig.11 In the embodiment, the outer portion of the light emitting area PXA may be provided with a pixel defining layer PDL (see Figure 7 ), and the area (or size) of the metal pattern layer JHL in a plan view may be smaller than the area (or size) of the pixel defining layer PDL. For example, the metal pattern layer JHL may be spaced apart from the light emitting area PXA, and the area (or size) of the metal pattern layer JHL may be smaller than the area (or size) of the pixel defining layer PDL (see Figure 7 ) area (or size), the metal pattern layer JHL can be aligned with the pixel definition layer PDL (see Figure 7 ) overlaps, thereby preventing the organic layer in the light emitting region PXA from being damaged. For example, because the edge portion EDP of the functional layer FL is set not to overlap with the metal pattern layer JHL, and the functional layer FL overlaps with the peripheral region NPXA (see Figure 5 ) are separated, so the quality degradation due to the leakage current can be prevented, and the display panel DP can have excellent display quality.

[0217] Figures 12 to 15 Each of them is a schematic cross-sectional view illustrating a portion of a display panel DP according to an embodiment. Figures 12 to 15 In the description of the display panel DP according to an embodiment, the description of the display panel DP according to the embodiment will not be provided. Figures 1A to 11 Descriptions that are similar (or substantially the same) are provided, and the differences will be explained for convenience of description.

[0218] Fig.12 The display panel DP-a according to one embodiment illustrated in the figure may include a low thermal conductivity layer PTL-a, which is arranged on the upper surface US-PD of the pixel defining layer PDL and is arranged (for example, directly arranged) between the upper surface US-PD of the pixel defining layer PDL and the metal pattern layer JHL.

[0219] In one embodiment, in a cross section perpendicular to the base substrate BL, the metal pattern layer JHL has a first width W in a direction (eg, a horizontal direction) of JH The second width W in the direction of the upper surface US-PD of the pixel definition layer PDL adjacent to the metal pattern layer JHL may be less than that of the upper surface US-PD of the pixel definition layer PDL adjacent to the metal pattern layer JHL. PD and a third width W of the upper surface of the low thermal conductive layer PTL-a adjacent to the metal pattern layer JHL in the direction PT .

[0220] In the display panel DP-a according to an embodiment, the side surface SS-PD of the pixel defining layer PDL may be covered by the functional layer FL. For example, a portion of the upper surface US-PD of the pixel defining layer PDL not covered by the low thermal conductivity layer PTL-a may also be covered by the functional layer FL.

[0221] In one embodiment, the third width W of the low thermal conductivity layer PTL-a is PT The second width W may be smaller than the upper surface US-PD of the pixel defining layer PDL. PD For example, the low thermal conductive layer PTL-a having a width sufficiently greater than that of the metal pattern layer JHL may overlap the metal pattern layer JHL (eg, the entire metal pattern layer JHL), and thus, heat generated from the metal pattern layer JHL may be prevented from being transferred to the functional layer FL.

[0222] Fig.13The illustrated display panel DP-b according to an embodiment may include a low thermal conductivity layer PTL-b, which is disposed (e.g., directly disposed) between the upper surface US-PD of the pixel defining layer PDL and the metal pattern layer JHL. The low thermal conductivity layer PTL-b may overlap with the upper surface US-PD of the pixel defining layer PDL (e.g., the entire upper surface US-PD). For example, in the display panel DP-b according to an embodiment, the side surface SS-PD of the pixel defining layer PDL may be covered by the functional layer FL.

[0223] In an embodiment, the low thermal conductive layer PTL-b may cover the upper surface US-PD (eg, the entire upper surface US-PD) of the pixel defining layer PDL, thereby preventing heat generated from the metal pattern layer JHL from being transferred to the functional layer FL.

[0224] exist Fig.12 and Fig.13 In the embodiment illustrated in , the low thermal conductivity layers PTL-a and PTL-b may be deposited on the pixel defining layer PDL and then patterned together with the pixel defining layer PDL in the same process step. Fig.12 and Fig.13 In the embodiment illustrated in , the second electrode CE may be disposed (eg, directly disposed) on portions of the low thermal conductive layers PTL-a and PTL-b that are not covered by the functional layer FL.

[0225] exist Fig.14 In the display panel DP-c according to an embodiment illustrated in FIG. 1 , the concave portion UH-PD may be defined (or formed) on the upper surface US-PD of the pixel defining layer PDL. In an embodiment, the low thermal conductivity layer PTL-c may be disposed in the concave portion UH-PD.

[0226] In one embodiment, the first width W of the metal pattern layer JHL is JH It may be smaller than the third width W of the low thermal conductivity layer PTL-c PT . An edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL and disposed on the low thermal conductivity layer PTL-c. For example, unlike the illustration in the accompanying drawings, an edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL, not overlap the low thermal conductivity layer PTL-c, and be disposed on the pixel defining layer PDL. The upper surface of the low thermal conductivity layer PTL-c that is not covered by the functional layer FL and is exposed may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0227] In the display panel DP-c according to one embodiment, because the low thermal conductivity layer PTL-c has a width sufficiently larger than that of the metal pattern layer JHL and overlaps with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), the heat generated from the metal pattern layer JHL can be prevented from being transferred to the functional layer FL, thereby having excellent display quality.

[0228] exist Fig.15 In the display panel DP-d according to an embodiment illustrated in FIG, the first concave portion UH-PD may be defined (or formed) on the upper surface US-PD of the pixel defining layer PDL. In an embodiment, the low thermal conductivity layer PTL-d may be disposed in the first concave portion UH-PD. For example, the second concave portion UH-PT may be defined (or formed) on the upper surface of the low thermal conductivity layer PTL-d, and the metal pattern layer JHL may be disposed in the second concave portion UH-PT.

[0229] The low thermal conductive layer PTL-d may cover the lower surface and the side surfaces of the metal pattern layer JHL so that the metal pattern layer JHL may not contact the pixel defining layer PDL.

[0230] The edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL and disposed on the low thermal conductivity layer PTL-d. For example, unlike the illustration in the drawings, the edge portion of the functional layer FL may be spaced apart from the metal pattern layer JHL, not overlapped with the low thermal conductivity layer PTL-d, and disposed on the pixel defining layer PDL. The upper surface of the low thermal conductivity layer PTL-d that is not covered by the functional layer FL and exposed may be covered by the second electrode CE. The second electrode CE may cover the functional layer FL and the metal pattern layer JHL.

[0231] In the display panel DP-d according to one embodiment, because the low thermal conductivity layer PTL-d has a width sufficiently larger than that of the metal pattern layer JHL and overlaps with the metal pattern layer JHL (e.g., the entire metal pattern layer JHL), the heat generated from the metal pattern layer JHL can be prevented from being transferred to the functional layer FL, thereby having excellent display quality.

[0232] In the following, reference will be made to 16A to 16H A method of manufacturing a display device according to an embodiment is described. 16A to 16H The steps of the method for manufacturing the display panel DP according to an embodiment are illustrated. 16A to 16H The same / similar reference numerals will be used when referring to Figures 1A to 15 The same / similar parts are described, and redundant description will be omitted for convenience of description.

[0233] According to one embodiment, a method for manufacturing a display panel DP may include: forming a first electrode AE ​​on a circuit element layer D-CL; forming a pixel defining layer PDL on the circuit element layer D-CL; forming a low thermal conductivity layer PTL on the pixel defining layer PDL; forming a metal pattern layer JHL overlapping the pixel defining layer PDL on the low thermal conductivity layer PTL; providing a preliminary functional layer P-FL so as to overlap the pixel defining layer PDL and the first electrode AE; forming a functional layer FL by supplying current to the metal pattern layer JHL to remove a portion of the preliminary functional layer P-FL overlapping the metal pattern layer JHL; forming a second electrode CE so as to cover the functional layer FL and the metal pattern layer JHL; and forming an encapsulation layer TFE on the second electrode CE.

[0234] Fig.16A It is illustrated that the first electrode AE ​​is formed on the circuit element layer D-CL and the pixel defining layer PDL is formed on the circuit element layer D-CL.

[0235] The circuit element layer D-CL may be formed on the base substrate BL, and the first electrode AE ​​may be formed on the circuit element layer D-CL. The first electrode AE ​​may be patterned and provided on the base substrate BL.

[0236] After forming the first electrode AE, a pixel defining layer PDL may be formed on the circuit element layer D-CL. Light emission openings OH may be defined / formed in (or through) the pixel defining layer PDL. The upper surface of the patterned first electrode AE ​​may be exposed through each of the light emission openings OH.

[0237] Fig. 16B It is exemplified that the low thermal conductive layer PTL is formed on the pixel defining layer PDL. Fig. 16B Example in Figure 7 The low thermal conductivity layer PTL covers an embodiment of the pixel defining layer PDL illustrated in FIG. However, the embodiment is not limited thereto, and the low thermal conductivity layer is provided in a different shape. Figures 12 to 15 In the case of the embodiment, the low thermal conductive layer may be formed to at least partially overlap the pixel defining layer PDL.

[0238] The low thermal conductivity layer PTL may be formed of a polymer amorphous carbon film. The formation of the low thermal conductivity layer PTL may include forming the polymer amorphous carbon film using a hydrocarbon gas by using a deposition facility. For example, the low thermal conductivity layer PTL may be formed by using a chemical vapor deposition (CVD) facility and providing a C 2 H 4 Gas is used to form a low thermal conductivity layer PTL.

[0239] The low thermal conductive layer PTL may not be provided on the upper surface of the first electrode AE ​​disposed in the light emitting opening OH, and may be formed on the pixel defining layer PDL.

[0240] Fig. 16C The metal pattern layer JHL is exemplified as being formed. The metal pattern layer JHL may overlap the pixel defining layer PDL and be formed on the low thermal conductive layer PTL.

[0241] The metal pattern layer JHL may be a Joule heating wire. When current is supplied to the metal pattern layer JHL, heat may be generated in the metal pattern layer JHL.

[0242] The metal pattern layer JHL may be disposed (e.g., directly disposed) on the low thermal conductivity layer PTL. The metal pattern layer JHL may be formed to have a width smaller than that of the low thermal conductivity layer PTL. By forming the metal pattern layer JHL so that its lower surface is fully covered by the low thermal conductivity layer PTL, the transfer of heat generated from the metal pattern layer JHL may be blocked by the low thermal conductivity layer PTL having low thermal conductivity.

[0243] Fig.16D The preliminary functional layer P-FL is provided as an example. The preliminary functional layer P-FL may be provided / formed to overlap with the first electrode AE ​​and the pixel defining layer PDL. The preliminary functional layer P-FL may be provided so as to overlap with the light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 7 ) and the peripheral region NPXA (see Figure 7 ) overlap (eg, completely overlap). For example, the preliminary functional layer P-FL may include a hole transport region HTR (see Fig. 9 ) and the electron transport region ETR (see Fig. 9 ) at least one of. For example, the light emitting element ED (see Fig. 9 ) of the light-emitting layer EML (see Fig. 9 ) may not be provided as a common layer like the preliminary functional layer P-FL, but may be patterned and provided to be disposed in each of the light emitting openings OH. Figure 8B In the case of a structure of Figure 8B ) can also be provided as a preliminary functional layer P-FL.

[0244] The hole transport region HTR (see Fig. 9 ), a preliminary functional layer P-FL patterned and provided to be disposed in each of the light emitting openings OH, and an electron transport region ETR formed (see Fig. 9 ) of the preliminary functional layer P-FL. For example, in the light emitting element having Figure 8BIn the case of a structure of the present invention, a preliminary functional layer P-FL forming a hole transport region HTR-B or HTR-T, a light emitting layer EML-B or EML-T patterned and provided to be disposed in each of the light emitting openings OH, and a preliminary functional layer P-FL forming an electron transport region ETR-B or ETR-T may be sequentially provided in each of the first light emitting structure EU-B and the second light emitting structure EU-T. For example, a charge generation layer CGL (see FIG. 1 ) may also be provided after providing the first light emitting structure EU-B. Figure 8B ) as the preliminary functional layer P-FL.

[0245] Fig.16E and Fig.16F Forming the functional layer is illustrated. After providing / forming the preliminary functional layer P-FL, the formation of the functional layer FL may be performed by supplying a current to the metal pattern layer JHL to remove a portion of the preliminary functional layer P-FL overlapping the metal pattern layer JHL.

[0246] When current is supplied to the metal pattern layer JHL, heat HT may be generated in the metal pattern layer JHL. The heat HT generated in the metal pattern layer JHL may be transferred to the adjacent preliminary functional layer P-FL, and a portion of the preliminary functional layer P-FL may be removed by the heat HT. A portion of the preliminary functional layer P-FL may be sublimated and removed by the heat generated from the metal pattern layer JHL.

[0247] A portion of the preliminary functional layer P-FL overlapping the metal pattern layer JHL and a portion of the preliminary functional layer P-FL adjacent to the metal pattern layer JHL may be removed. A partial region of the preliminary functional layer P-FL may be removed through the metal pattern layer JHL, and a functional layer FL may be formed.

[0248] The functional layer FL may be formed so as not to overlap with the metal pattern layer JHL. For example, in one embodiment, the functional layer FL may be formed so as to be spaced apart from the metal pattern layer JHL by a selected distance.

[0249] The shape and size of the separation portion SPP between the metal pattern layer JHL and the functional layer FL may vary according to the process conditions used to remove the preliminary functional layer P-FL, such as the amount of current supplied to the metal pattern layer JHL, the time for supplying the current to the metal pattern layer JHL, and the resistance characteristics of the metal material used for the metal pattern layer JHL.

[0250] Since the method of manufacturing the display panel DP according to an embodiment includes forming the functional layer FL by using the metal pattern layer JHL generating heat by a Joule heating method to remove a portion of the preliminary functional layer P-FL adjacent to the metal pattern layer JHL, patterning can be easily performed so that the functional layer FL can be formed in adjacent light emitting areas PXA-R, PXA-G, and PXA-B (see FIG. Figure 7 ) are not connected to each other. Since the method of manufacturing a display panel DP according to an embodiment includes providing a metal pattern layer JHL and a low thermal conductivity layer PTL, the preliminary functional layer P-FL can be easily disconnected, and damage to the functional layer FL can be minimized or prevented. Therefore, the method can be used to manufacture a display panel DP capable of preventing damage due to adjacent light emitting areas PXA-R, PXA-G, and PXA-B (see Figure 7 ) due to leakage current in the display panel DP, which may cause degradation of display quality and color mixing.

[0251] Figure 16G The second electrode CE is formed as an example. The second electrode CE may be formed to cover the functional layer FL and the metal pattern layer JHL. The second electrode CE may also be disposed in the separation portion SPP between the metal pattern layer JHL and the functional layer FL. The second electrode CE may be provided as the light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 7 ) and a common layer in the peripheral area NPXA. In one embodiment, the second electrode CE may be provided as a common layer throughout the plurality of light emitting elements ED.

[0252] Fig.16H The encapsulation layer TFE is formed as an example. The encapsulation layer TFE may cover the light emitting element ED. Fig.16H , the encapsulation layer TFE is exemplified as one layer, but the encapsulation layer TFE may be formed to include a plurality of layers including at least one inorganic layer and at least one organic layer.

[0253] The display panel DP according to an embodiment may include a metal pattern layer JHL disposed on a pixel defining layer PDL, a low thermal conductivity layer PTL disposed (e.g., directly disposed) between the pixel defining layer PDL and the metal pattern layer JHL, and a light emitting element ED including a functional layer FL disposed so as not to overlap with the metal pattern layer JHL. Therefore, the light emitting regions PXA-R, PXA-B, and PXA-G may have excellent light emitting characteristics due to the good quality functional layer FL, and no leakage current occurs between adjacent light emitting regions PXA-R, PXA-B, and PXA-G due to the disconnected functional layer, thereby having excellent display quality.

[0254] For example, a method for manufacturing a display panel DP according to an embodiment may include: forming a low thermal conductivity layer PTL disposed on a pixel defining layer PDL, forming a metal pattern layer JHL on the low thermal conductivity layer PTL, and forming a functional layer FL by removing a preliminary functional layer P-FL disposed on the metal pattern layer JHL using heat generated in the metal pattern layer JHL. Therefore, the functional layer FL can be easily formed to be disconnected between adjacent light emitting regions, and the film quality of the functional layer disposed in the light emitting regions PXA-R, PXA-B, and PXA-G can be maintained excellent. Accordingly, the method can be used to manufacture a display panel DP having excellent display quality.

[0255] The display panel DP according to an embodiment may include a disconnected organic layer in a non-light emitting region, thereby preventing current leakage between adjacent light emitting regions and having excellent display quality.

[0256] The method of manufacturing a display panel DP according to an embodiment may include forming a low thermal conductivity layer PTL between a metal pattern layer JHL and a pixel defining layer PDL and disconnecting an organic film by using the metal pattern layer JHL, and thus, the method may be used to manufacture a display panel DP having excellent display quality.

[0257] In summarizing the detailed description, those skilled in the art will recognize that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display panel, comprising: base substrate; A circuit element layer is disposed on the base substrate; a pixel defining layer, disposed on the circuit element layer and comprising a light emitting opening; A light emitting element is disposed on the circuit element layer, and the light emitting element comprises: The first electrode, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer, disposed on the pixel defining layer; and The low thermal conductivity layer is arranged between the pixel defining layer and the metal pattern layer. 2 . The display panel according to claim 1 , wherein the low thermal conductivity layer has a thermal conductivity of 1.0 W / mK or less. The display panel according to claim 1 , wherein the functional layer does not overlap with the metal pattern layer.

4. The display panel according to claim 3, wherein The functional layer comprises: Luminescent layer; and an organic layer disposed on at least one of the upper portion and the lower portion of the light emitting layer, The organic layer overlaps the light emitting opening and a portion of the pixel defining layer adjacent to the light emitting opening, and is spaced apart from the metal pattern layer. The display panel according to claim 1 , wherein the low thermal conductivity layer comprises a polymer type amorphous carbon film.

6. The display panel according to claim 5, wherein the polymer-based amorphous carbon film has sp 3 The ratio of carbon bonds ranges from 50% to 70%.

7. The display panel according to claim 5, wherein the low thermal conductivity layer has a refractive index of 1.75 or less at a wavelength of 550 nm and a thermal conductivity of 1.2 g / cm 3 Up to 1.6g / cm 3 density within the range of . 8 . The display panel according to claim 1 , wherein in a cross section perpendicular to the base substrate, a first width of the metal pattern layer in one direction is smaller than a second width of the pixel defining layer in the direction. 9 . The display panel according to claim 8 , wherein the first width is ½ or less of the second width. 10 . The display panel according to claim 1 , wherein a width of the metal pattern layer in a direction is smaller than a width of the low thermal conductivity layer in the direction. 11 . The display panel according to claim 1 , wherein the low thermal conductivity layer covers an upper surface and a side surface of the pixel defining layer.

12. The display panel according to claim 1, wherein: The low thermal conductivity layer is disposed on the upper surface of the pixel defining layer; and A side surface of the pixel defining layer is covered by the functional layer.

13. The display panel according to claim 1, wherein: A concave portion is formed on an upper surface of the pixel defining layer; and The low thermal conductive layer is disposed in the concave portion.

14. The display panel according to claim 1, wherein: A first concave portion is formed on an upper surface of the pixel defining layer; The low thermal conductivity layer is disposed in the first concave portion; A second concave portion is formed on an upper surface of the low-thermal-conductivity layer; and The metal pattern layer is disposed in the second concave portion.

15. A display panel, divided into a plurality of light-emitting areas spaced apart from each other and a peripheral area disposed between the plurality of light-emitting areas, the display panel comprising: base substrate; A circuit element layer is disposed on the base substrate; a pixel defining layer disposed on the circuit element layer and including a light emitting opening overlapping each of the plurality of light emitting regions; Multiple light-emitting elements, including: A first electrode disposed on the circuit element layer, a second electrode facing the first electrode, and a functional layer disposed between the first electrode and the second electrode; a metal pattern layer disposed in the peripheral region and on the pixel defining layer; and The low thermal conductivity layer is arranged between the pixel defining layer and the metal pattern layer.

16. The display panel according to claim 15, wherein: The first electrode of the plurality of light emitting elements overlaps with each of the plurality of light emitting regions; The second electrode is provided as a common layer throughout the plurality of light emitting elements; and The functional layer does not overlap the metal pattern layer and is disposed in the plurality of light emitting regions and a portion of the peripheral region adjacent to the plurality of light emitting regions.

17. The display panel according to claim 16, wherein The functional layer comprises: Luminescent layer; A hole transport region, disposed between the first electrode and the light-emitting layer; as well as an electron transport region, disposed between the light-emitting layer and the second electrode, The light emitting layer is disposed in the light emitting opening; and At least one of the hole transport region and the electron transport region is disposed in the light emitting opening and extends over an upper surface of the pixel defining layer adjacent to the light emitting opening.

18. The display panel according to claim 17, wherein: The plurality of light emitting regions include a first light emitting region, a second light emitting region, and a third light emitting region that emit light in different wavelength ranges; The plurality of light emitting elements include a first light emitting layer overlapping the first light emitting region, a second light emitting layer overlapping the second light emitting region, and a third light emitting layer overlapping the third light emitting region. The first light-emitting layer, the second light-emitting layer and the third light-emitting layer include different light-emitting materials; and The plurality of light emitting elements include the hole transporting regions that are identical to each other and the electron transporting regions that are identical to each other. 19 . The display panel of claim 17 , wherein at least one edge portion of the hole transport region and the electron transport region disposed to extend over the upper surface of the pixel defining layer is spaced apart from the metal pattern layer.

20. The display panel according to claim 19, wherein: In a plan view, a metal layer boundary line defined by the edge portion and an edge portion of the metal pattern layer is disposed in the peripheral region; and The edge portion is closer to the plurality of light emitting regions than the metal layer boundary line.

21. The display panel according to claim 15, wherein the low thermal conductivity layer comprises a polymer type amorphous carbon film.

22. The display panel according to claim 21, wherein: The polymer amorphous carbon film has sp 3 The proportion of carbon bonds is in the range of 50% to 70%; and The low thermal conductivity layer has a refractive index of 1.75 or less at a wavelength of 550 nm and a thermal conductivity of 1.2 g / cm 3 Up to 1.6g / cm 3 density within the range of .

23. The display panel according to claim 15, wherein in a cross section perpendicular to the base substrate, a first width of the metal pattern layer in one direction is smaller than each of a second width of an upper surface of the pixel defining layer adjacent to the metal pattern layer in the direction and a third width of an upper surface of the low thermal conductivity layer adjacent to the metal pattern layer in the direction. 24 . The display panel of claim 15 , wherein in a plan view, a size of the metal pattern layer is smaller than a size of the pixel defining layer.

25. A method for manufacturing a display panel, the method comprising: forming a first electrode on the circuit element layer; forming a pixel defining layer on the circuit element layer; forming a low thermal conductivity layer on the pixel defining layer; forming a metal pattern layer on the low thermal conductivity layer to overlap with the pixel defining layer; providing a preliminary functional layer to overlap the pixel defining layer and the first electrode; forming a functional layer by supplying a current to the metal pattern layer to remove a portion of the preliminary functional layer overlapping the metal pattern layer; forming a second electrode to cover the functional layer and the metal pattern layer; and An encapsulation layer is formed on the second electrode.

26. The method of claim 25, wherein: The metal pattern layer is a Joule heating wire; and Forming the functional layer by removing the portion of the preliminary functional layer includes removing the portion of the preliminary functional layer by sublimating the portion of the preliminary functional layer using heat generated in the metal pattern layer. 27 . The method of claim 25 , wherein the forming of the low thermal conductivity layer comprises forming a polymeric amorphous carbon film using a deposition facility with a hydrocarbon gas. 28 . The method according to claim 25 , wherein the metal pattern layer has a width in one direction that is smaller than a width of the low-thermal-conductivity layer. 29 . The method of claim 25 , the functional layer is formed so as not to overlap with the metal pattern layer.

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