Array substrate and display panel

Abstract

The embodiment of the present disclosure provides an array substrate and a display panel. Wherein, the array substrate comprises: a substrate, the substrate comprises a display area and a peripheral area surrounding the display area, a plurality of pixel unit groups arranged along a first direction are arranged on the display area, the pixel unit group comprises a plurality of pixel units arranged along a second direction, and the pixel unit comprises a thin film transistor; the array substrate further comprises: a plurality of gate lines arranged along the first direction, the gate line extends along the second direction, the gate line comprises a first conductive pattern and a first conductive connection line arranged alternately along the second direction, the first conductive connection line is connected with the adjacent first conductive pattern, and the first conductive pattern is multiplexed as a gate electrode of the thin film transistor; and a common electrode, the orthogonal projection of the common electrode on the substrate at least covers the orthogonal projection of the first conductive connection line on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] In a liquid crystal display (LCD) device, the array substrate is a key component. Within the array substrate, pixel units are arranged in an array. Each pixel unit may contain a thin-film transistor (TFT) and a pixel electrode, and is connected to the TFT via data lines and gate lines to drive the pixel electrode in each pixel unit.

[0003] The array substrate also includes a common electrode. When an electric field is generated between the pixel electrode and the common electrode, it drives the liquid crystal in the pixel unit where the pixel electrode is located to deflect. However, the edge region of the orthogonal projection of the common electrode on the substrate overlaps with the orthogonal projection of the gate line on the substrate. That is, electric field disturbance is generated at the edge of the common electrode and near the gate line, causing the liquid crystal in this area to be disordered. It is not easy to recover after being pressed, thus resulting in a trace mura defect. Summary of the Invention

[0004] This disclosure provides an array substrate and a display panel.

[0005] In a first aspect, embodiments of this disclosure provide an array substrate comprising: a substrate, the substrate comprising a display area and a peripheral area surrounding the display area, the display area being provided with a plurality of pixel unit groups arranged along a first direction, the pixel unit groups comprising a plurality of pixel units arranged along a second direction, and the pixel units comprising thin film transistors;

[0006] The array substrate further includes:

[0007] Multiple gate lines are arranged along a first direction, the gate lines extend along a second direction, the gate lines include first conductive patterns and first conductive connecting lines arranged alternately along the second direction, the first conductive connecting lines are connected to adjacent first conductive patterns, and the first conductive patterns are multiplexed as the gate of the thin film transistor;

[0008] A common electrode, the orthographic projection of which on the substrate at least covers the orthographic projection of the first conductive connection line on the substrate.

[0009] In some embodiments, the common electrode includes a plurality of first vias corresponding one-to-one with at least a portion of the thin-film transistors; the thin-film transistors also include an active layer located on one side of the gate.

[0010] The orthographic projection of the first via on the substrate falls within the area covered by the orthographic projection of the active layer pattern of the corresponding thin-film transistor on the substrate.

[0011] In some embodiments, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the active layer pattern corresponding to the thin-film transistor on the substrate.

[0012] In some embodiments, the pixel unit further includes a pixel electrode, the pixel electrode including a body electrode and a connection electrode, the thin film transistor including a first electrode and a second electrode, and the connection electrode connecting the corresponding body electrode and the second electrode of the thin film transistor;

[0013] The minimum distance between the orthographic projection of the first through hole on the substrate and the orthographic projection of any of the body electrodes on the substrate in the first direction is 3-10 μm.

[0014] In some embodiments, two gate lines are provided between adjacent pixel unit groups;

[0015] The array substrate further includes: multiple data lines extending along the first direction;

[0016] Within the pixel unit group, every two adjacent pixel units form a pixel unit subgroup, and the pixel unit subgroup corresponds one-to-one with the data line. The pixel unit is connected to the data line corresponding to its pixel unit subgroup.

[0017] Two pixel units located in the same pixel unit subgroup are connected by different gate lines.

[0018] In some embodiments, a first spacing region is formed between two gate lines located between adjacent pixel unit groups;

[0019] The orthographic projection of the common electrode on the substrate covers the orthographic projection of the portion of the data line located in the first interval region on the substrate.

[0020] In some embodiments, a first spacing region is formed between two gate lines located between adjacent pixel unit groups;

[0021] The orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the first interval region on the substrate.

[0022] In some embodiments, a third spacing region is formed between adjacent groups of pixel units.

[0023] The ratio of the overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the third interval region on the substrate to the area of ​​the orthographic projection of the third interval region on the substrate is 0.8-0.9.

[0024] In some embodiments, the gate of the thin-film transistor is connected to a corresponding gate line, the first electrode of the thin-film transistor is connected to a data line corresponding to the pixel unit, and the second electrode of the thin-film transistor is connected to the pixel electrode in the same pixel unit.

[0025] The two pixel electrodes of two pixel units located within the same pixel unit subgroup are arranged along the second direction;

[0026] The two thin-film transistors of two pixel units located within the same pixel unit subgroup are arranged along the first direction.

[0027] In some embodiments, each pixel unit group corresponds to two gate lines, and the two gate lines are respectively located on opposite sides of the corresponding pixel unit group in the first direction;

[0028] The pixel unit subgroup includes a first pixel unit and a second pixel unit, wherein the first pixel unit is located on the side of the second pixel unit away from the data line corresponding to the pixel unit subgroup;

[0029] The thin-film transistor of the first pixel unit is a first thin-film transistor, the pixel electrode of the first pixel unit is a first pixel electrode, the thin-film transistor of the second pixel unit is a second thin-film transistor, and the pixel electrode of the second pixel unit is a second pixel electrode.

[0030] The first pixel electrode includes a first body electrode and a first connection electrode, wherein the first connection electrode is connected to the corresponding first body electrode and the second electrode of the first thin film transistor;

[0031] The second pixel electrode includes a second body electrode and a second connection electrode, wherein the second connection electrode is connected to the corresponding second body electrode and the second electrode of the second thin film transistor;

[0032] The first thin-film transistor and the second thin-film transistor are located on opposite sides of the second body electrode in the first direction;

[0033] The first body electrode and the second body electrode are arranged along the second direction, the first connecting electrode and the first thin film transistor are located on the same side of the second body electrode, and the second connecting electrode and the second thin film transistor are located on the same side of the second body electrode.

[0034] In some embodiments, the area of ​​the first connecting electrode projected onto the substrate is larger than the area of ​​the second connecting electrode projected onto the substrate.

[0035] The common electrode further includes a plurality of second through holes corresponding one-to-one with at least a portion of the first connecting electrodes, wherein the orthographic projection of the second through holes on the substrate overlaps with the orthographic projection of the first connecting electrodes on the substrate.

[0036] In some embodiments, the first connection electrode includes a first connection portion and a second connection portion, the orthographic projection of the second connection portion on the substrate and the orthographic projection of the gate of the first thin film transistor on the substrate are arranged along a second direction, the first connection portion connects the first body electrode and the second connection portion, and the second connection portion is connected to the second electrode of the first thin film transistor.

[0037] The orthographic projection of the second through hole on the substrate overlaps with the orthographic projection of the second connecting portion on the substrate.

[0038] In some embodiments, the orthographic projection of the second connection portion on the substrate covers the orthographic projection of the corresponding second through hole on the substrate.

[0039] In some embodiments, the minimum distance between the edge of the orthographic projection of the second through hole on the substrate and the edge of the orthographic projection of the second connection portion on the substrate on the same side is 1.5-5 μm.

[0040] In some embodiments, the orthographic projection of the second through-hole on the substrate, the orthographic projection of the second electrode of the first thin-film transistor on the substrate, and the orthographic projection of the second connection portion on the substrate overlap.

[0041] In some embodiments, the overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the first connecting electrode on the substrate is equal to the overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the second connecting electrode on the substrate.

[0042] In some embodiments, the average diameter of the second through hole is 2.5-10 μm.

[0043] In some embodiments, the common electrode includes a plurality of first through holes corresponding one-to-one with the thin-film transistor;

[0044] The orthographic projection of the first via on the substrate is located within the area covered by the orthographic projection of the active layer pattern corresponding to the thin-film transistor on the substrate.

[0045] The minimum distance between the second through hole and the first through hole corresponding to the first thin-film transistor connected to the first connecting electrode in the second direction is 5-10 μm.

[0046] In some embodiments, two adjacent pixel unit subgroups include a first pixel unit subgroup and a second pixel unit subgroup;

[0047] In the first pixel unit subgroup, the first thin-film transistor is located on the first side of the second body electrode in the first direction, and the second thin-film transistor is located on the second side of the second body electrode in the first direction.

[0048] In the first pixel unit subgroup, the first connecting electrode of the first pixel unit is located on the first side of the first body electrode in the first direction, and the second connecting electrode of the second pixel unit in the first pixel unit subgroup is located on the second side of the second body electrode in the first direction;

[0049] In the second pixel unit subgroup, the first thin-film transistor is located on the second side of the second body electrode in the first direction, and in the first pixel unit subgroup, the second thin-film transistor is located on the first side of the second body electrode in the first direction;

[0050] In the second pixel unit subgroup, the first connecting electrode of the first pixel unit is located on the second side of the first body electrode in the first direction, and the second connecting electrode of the second pixel unit in the second pixel unit subgroup is located on the first side of the second body electrode in the first direction;

[0051] Wherein, the first side and the second side are opposite sides in the first direction.

[0052] In some embodiments, the array substrate further includes: a plurality of common voltage line groups corresponding one-to-one with the pixel unit groups;

[0053] The common voltage line group includes a second common voltage line extending along the second direction and a plurality of first common voltage lines extending along the first direction;

[0054] A second spacing region is formed between the first body electrode and the second body electrode located in the same pixel unit subgroup, and the first common voltage line is located in the second spacing region;

[0055] Both the first body electrode and the second body electrode are dual-domain electrodes. The dual-domain electrode includes a first domain region and a second domain region arranged along the first direction. The orthogonal projection of the second common voltage line on the substrate covers the boundary between the first domain region and the second domain region.

[0056] In some embodiments, the end of the first common voltage line near the second connection electrode is electrically connected to the common electrode through a via.

[0057] In some embodiments, the difference between the storage capacitance corresponding to the first pixel unit and the storage capacitance corresponding to the second pixel unit is less than 1.5fF.

[0058] In some embodiments, the difference between the voltage drop generated by the first pixel unit and the voltage drop generated by the second pixel unit is less than 0.005V.

[0059] In a second aspect, embodiments of this disclosure provide a display panel including the array substrate described in the first aspect.

[0060] In the array substrate provided in this embodiment, the gate line includes the gate of the thin film transistor and the connection line, i.e., the first conductive pattern and the first conductive connection line, which are alternately arranged along the row direction. By increasing the area of ​​the common electrode, its orthogonal projection on the substrate covers the orthogonal projection of the first conductive connection line on the substrate, thereby avoiding electric field disturbance between the edge position of the common electrode and the gate line, improving the stability of the liquid crystal, and effectively improving the phenomenon of trace mura on the display panel. Attached Figure Description

[0061] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0062] Figure 1 This is a top view schematic diagram of an array substrate provided in related technologies.

[0063] Figure 2 This is a layout of a common electrode provided in related technologies.

[0064] Figure 3 This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure.

[0065] Figure 4 for Figure 3 A top-down view of area A in the middle.

[0066] Figure 5 For along Figure 4 A cross-sectional view of line AA' in the middle.

[0067] Figure 6 A layout of the common electrode layer provided in an embodiment of this disclosure.

[0068] Figure 7 A layout of the first metal layer provided for an embodiment of this disclosure.

[0069] Figure 8 The layout of the active layer pattern of the thin-film transistor provided in the embodiments of this disclosure.

[0070] Figure 9 This is an overlay pattern of the first metal layer and the active layer pattern of the thin-film transistor provided in an embodiment of this disclosure.

[0071] Figure 10 The layout of the pixel electrodes provided in the embodiments of this disclosure.

[0072] Figure 11 The superimposed layout of the first metal layer, the active layer pattern of the thin-film transistor, and the pixel electrode is provided for embodiments of this disclosure.

[0073] Figure 12 A layout of the second metal layer provided in an embodiment of this disclosure.

[0074] Figure 13 The overlay layout of the first metal layer, the active layer pattern of the thin-film transistor, the pixel electrode, and the data line provided in the embodiments of this disclosure.

[0075] Figure 14 The layout of the passivation layer provided in the embodiments of this disclosure.

[0076] Figure 15 The superimposed layout of the first metal layer, the active layer pattern of the thin-film transistor, the pixel electrode, the data line, and the passivation layer provided in the embodiments of this disclosure.

[0077] Explanation of reference numerals in the attached figures:

[0078] The block-shaped common electrode COM' and the outer edge L' of the block-shaped common electrode;

[0079] Substrate 1, first spacing region N1, second spacing region N2;

[0080] The structure consists of a first metal layer M1, a gate insulating layer GI, an active layer Act, a pixel electrode layer Pix10, a second metal layer M2, a passivation layer PVX, and a common electrode layer COM10.

[0081] Gate: First conductive pattern G1, first conductive connecting line G2, first part g1, second part g2, third part g3, second protruding pattern z2; Data line;

[0082] Pixel unit group PG, pixel unit subgroup pg, first pixel unit subgroup pg1, second pixel unit subgroup pg2, first pixel unit 10, second pixel unit 20;

[0083] Pixel electrode Pix: Body electrode p1, connecting electrode p2;

[0084] First pixel electrode pix1: First body electrode p11, first connecting electrode p21, first connecting part p211, second connecting part p212;

[0085] Second pixel electrode pix2: Second body electrode p12, second connecting electrode p22, third connecting part p221, fourth connecting part p222;

[0086] Common electrode COM: First through hole k1, second through hole k2;

[0087] Thin Film Transistor (TFT): First electrode 41, Second electrode 42, Gate 43, Active layer pattern 44;

[0088] First thin-film transistor T1, second thin-film transistor T2;

[0089] Passivation layer PVX: via k3;

[0090] Common voltage line group Lcom: First common voltage line L1, second common voltage line L2, first protruding pattern z1;

[0091] First direction Y, second direction X. Detailed Implementation

[0092] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0093] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0094] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0095] In a liquid crystal display (LCD) device, the array substrate is a key component. Within the array substrate, pixel units are arranged in an array. Each pixel unit may contain a thin-film transistor (TFT) and a pixel electrode, and is connected to the TFT via data lines and gate lines to drive the pixel electrode in each pixel unit.

[0096] Figure 1 This is a top view schematic diagram of an array substrate provided in related technologies. Figure 2 This is a layout of a common electrode provided in related technologies. For example... Figure 1 , Figure 2 As shown, the array substrate includes a block-shaped common electrode COM'. Generally, one block-shaped common electrode COM' corresponds to one pixel unit group PG. The pixel unit group PG includes a row of pixel units. When an electric field is generated between the pixel electrode and the common electrode, it drives the liquid crystal in the pixel unit where the pixel electrode is located to deflect. However, the inventors discovered in their research that the orthographic projection of the block-shaped common electrode COM' on the substrate overlaps with the orthographic projection of the gate line on the substrate, and the orthographic projection of the outer edge L' of the block-shaped common electrode COM' on the substrate is partially covered by the orthographic projection of the gate line Gate on the substrate. For example... Figure 1 As shown in regions a and b, the electric field disturbance between the outer edge L' of the blocky common electrode COM' and the vicinity of the gate line (e.g., in regions a and b) causes the liquid crystal arrangement in that region to become disordered and difficult to recover after being pressed. Since the aforementioned electric field disturbance area is close to the opening area of ​​the pixel unit, it will affect the deflection of the liquid crystal near the position of the electric field disturbance area in the opening area, thus resulting in a Trace Mura defect.

[0097] To address at least one of the aforementioned technical problems, this disclosure provides an array substrate that, by increasing the area of ​​the common electrode, avoids electric field disturbances between the edge of the common power supply and the gate, thereby effectively improving the phenomenon of trace mura on the display panel.

[0098] Figure 3 This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure. Figure 4 for Figure 3 A top-down view of area A in the middle. Figure 5 For along Figure 4 A cross-sectional diagram of line AA' in the middle. Figure 6 This is a layout of the common electrode layer provided in an embodiment of the present disclosure. Figure 7 A layout of the first metal layer provided for an embodiment of this disclosure.

[0099] like Figures 3-7 As shown, the array substrate includes: a substrate 1, which is divided into a display area (not shown in the figure) and a peripheral area (not shown in the figure) surrounding the display area. The display area is provided with a plurality of pixel unit groups PG arranged along a first direction Y. The pixel unit group PG includes a plurality of pixel units arranged along a second direction X. The pixel unit includes a thin film transistor (TFT).

[0100] The array substrate further includes: a plurality of gate lines arranged along the first direction Y and a common electrode COM, wherein: the gate lines extend along the second direction X, and the gate lines include first conductive patterns G1 and first conductive connection lines G2 arranged alternately along the second direction X, the first conductive connection lines G2 are connected to adjacent first conductive patterns G1, and the first conductive patterns G1 are multiplexed as the gate 43 of a thin film transistor; the orthographic projection of the common electrode COM on the substrate 1 at least covers the orthographic projection of the first conductive connection lines G2 on the substrate 1.

[0101] It should be understood that the first direction Y intersects with the second direction X. Preferably, the first direction Y is the column direction and the second direction X is the row direction.

[0102] In the array substrate provided in this embodiment, the gate line includes the gate of the thin film transistor and the connection line, i.e., the first conductive pattern and the first conductive connection line, which are alternately arranged along the row direction. By increasing the area of ​​the common electrode, its orthographic projection on the substrate covers the orthographic projection of the first conductive connection line on the substrate. That is, the orthographic projection of the outer edge of the common electrode on the substrate will not be covered by the orthographic projection of the gate line on the substrate, thereby avoiding electric field disturbance between the edge position of the common electrode and the gate line, improving the stability of the liquid crystal, and effectively improving the phenomenon of trace mura on the display panel.

[0103] It should be noted that in a single-gate line array substrate, assuming the array substrate structure has N*M pixel units, the single-gate line array substrate can include N gate lines and M data lines. Pixel units are disposed at the intersections of the gate lines and data lines, and different combinations of gate lines and data lines can drive different pixel units. To reduce product cost, a dual-gate line array substrate is provided in the prior art. Compared with the single-gate line array substrate described above, the number of data lines in the dual-gate line array substrate can be reduced by approximately half, and the cost of the driving circuit connecting the data lines is also reduced accordingly, thus lowering the product cost.

[0104] Meanwhile, the increased number of gate lines exacerbates the electric field disturbance caused by the overlap between the edge of the common electrode and the gate line position, resulting in liquid crystal alignment disorder and affecting display performance. Therefore, the array substrate provided in this disclosure is not only applicable to single-gate line array substrates, but also particularly suitable for dual-gate line array substrates.

[0105] In the embodiments disclosed herein, such as Figure 5 As shown, a first metal layer M1, a gate insulating layer GI, an active layer Act, a pixel electrode layer Pix10, a second metal layer M2, a passivation layer PVX, and a common electrode layer COM10 are sequentially disposed in the direction away from the substrate 1. The common electrode layer COM10 includes a common electrode COM. The first metal layer M1 includes a gate line Gate and a common voltage line group Lcom. The gate line Gate includes a first conductive pattern G1 (the gate 43 of the thin-film transistor) and a first conductive connection line G2. The common voltage line in the common voltage line group is connected to the common electrode COM through a via k3 that at least penetrates the passivation layer PVX. The second metal layer M2 includes a data line Data, a first electrode 41 of the thin-film transistor TFT, and a second electrode 42.

[0106] It should be understood that one of the first electrode 41 and the second electrode 42 of the thin-film transistor TFT is the source electrode of the thin-film transistor TFT, and the other is the drain electrode of the thin-film transistor TFT. The pixel electrode layer Pix10 includes pixel electrodes corresponding to each pixel unit, and the body electrode of the pixel electrode has a dual-domain structure. The common electrode COM is a slit electrode extending along the second direction X, and the slits are uniformly distributed.

[0107] And, with Figure 2 The related technology shown differs from the one in that the common electrode layer includes multiple spaced-apart block-shaped common electrodes COM', as... Figure 6 As shown, the common electrode COM included in the common electrode layer COM10 in this embodiment of the present disclosure is a planar electrode.

[0108] In some embodiments, Figure 8This is a layout of the active layer pattern of a thin-film transistor provided in an embodiment of this disclosure. Figure 9 This is a superimposed layout of the first metal layer and the active layer pattern of the thin-film transistor provided for embodiments of this disclosure. (See attached image.) Figures 3-8 As shown, the common electrode COM includes a plurality of first vias k1 corresponding to at least a portion of the thin-film transistors (TFTs); the orthographic projection of the first vias k1 on the substrate 1 is located within the area covered by the orthographic projection of the active layer pattern 44 of the corresponding thin-film transistor TFT on the substrate 1.

[0109] Preferably, the common electrode COM includes a plurality of first vias k1 corresponding one-to-one with each thin-film transistor TFT.

[0110] A thin-film transistor (TFT) is configured to generate a drive signal and provide it to the pixel electrode in a pixel unit. Specifically, the TFT includes a gate, a source, a drain, and an active layer. The active layer includes a channel portion and source and drain connection portions located on both sides of the channel portion. The source connection portion connects to the source, and the drain connection portion connects to the drain. The channel portion faces the gate. When the voltage signal applied to the gate reaches a certain value, a carrier path is formed in the channel portion, causing the source and drain of the TFT to conduct.

[0111] When a portion of the common electrode COM directly aligns with the active layer pattern 44 of the thin-film transistor (TFT), it interferes with the formation of carrier pathways in the channel portion of the TFT's active layer, thereby affecting the generation of the drive signal. Therefore, the portion of the pattern on the common electrode COM directly aligning with the active layer pattern 44 of the TFT is removed to form a first via k1, exposing the active layer pattern 44 of the TFT in the first via k1 to avoid affecting the drive signal.

[0112] Preferably, in some embodiments, such as Figure 3 , Figure 4 As shown, the orthographic projection of the first via k1 on the substrate 1 overlaps with the orthographic projection of the active layer pattern 44 of the corresponding thin-film transistor on the substrate 1, so as to avoid the phenomenon that the electric field between the edge position of the first via k1 and the first conductive connection line G2 in the gate line is disordered due to the first via k1 being too large.

[0113] Figure 10 This is a layout of pixel electrodes provided in an embodiment of this disclosure. Figure 11 The superimposed layout of the first metal layer, the active layer pattern of the thin-film transistor, and the pixel electrode is provided for embodiments of this disclosure. In one embodiment, such as Figure 3 , Figure 6 , Figure 10 , Figure 11As shown, the pixel unit also includes a pixel electrode Pix, which includes a body electrode p1 and a connecting electrode p2. The connecting electrode p2 connects the corresponding body electrode p1 and the second electrode 42 of the thin film transistor TFT. The orthographic projection of the first through hole k1 on the substrate 1 and the orthographic projection of any body electrode p1 on the substrate 1 are d1 apart in the first direction Y, where d1 is 3-10μm.

[0114] It should be noted that each pixel unit has a corresponding opening region, which refers to the area where light emitted from the pixel unit can exit the display panel. In the pixel electrode Pix, the main electrode p1 is located in the opening region. An electric field is generated between the main electrode p1 and the common electrode COM, causing the liquid crystal to deflect and thus allowing light to exit.

[0115] Based on this, the first through hole k1 is set outside the opening area, and the distance d1 between the first through hole k1 and the body electrode p1 in the first direction Y is at least 3μm, so as to avoid affecting the display effect.

[0116] Figure 12 This is a layout of the second metal layer provided in an embodiment of the present disclosure. Figure 13 The overlay layout of the first metal layer, the active layer pattern of the thin-film transistor, the pixel electrode, and the data lines provided for embodiments of this disclosure. In some embodiments, such as Figure 3 , Figure 12 , Figure 13 As shown, two gate lines (Gates) are provided between adjacent pixel unit groups (PGs). The array substrate also includes multiple data lines (Data), which extend along the first direction Y. Within each pixel unit group (PG), every two adjacent pixel units form a pixel unit subgroup, and each pixel unit subgroup corresponds one-to-one with a data line (Data). The pixel unit is connected to the corresponding data line (Data) of its subgroup. Two pixel units located in the same pixel unit subgroup (PG) are connected to different gate lines (Gates). In other words, the array substrate has a dual-gate structure. By increasing the number of gate lines (Gates) and reducing the number of data lines (Data), the cost of the driving circuit connecting the data lines (Data) is reduced, further reducing the cost of the display product.

[0117] like Figures 3-13 As shown, a first spacing region N1 is formed between two gate lines located between adjacent pixel unit groups PG. In some embodiments, the orthogonal projection of the common electrode COM on the substrate 1 covers the portion of the data line Data located in the first spacing region N1, thereby avoiding the phenomenon of electric field disturbance between the edge of the common electrode COM and the data line Data, which affects the display effect.

[0118] In some embodiments, the orthographic projection of the common electrode COM on the substrate 1 covers the orthographic projection of the first spacing region N1 on the substrate 1, so as to avoid electric field interference between the edge of the common electrode COM and other signal lines, thereby causing liquid crystal arrangement disorder and the phenomenon of trace mura on the display panel, and improving the display effect.

[0119] In some embodiments, such as Figures 3-13 As shown, a pixel unit includes a pixel electrode and a corresponding thin-film transistor (TFT). The gate 43 of the TFT is connected to the corresponding gate line, the first electrode 41 of the TFT is connected to the data line Data corresponding to the pixel unit, and the second electrode 42 of the TFT is connected to the pixel electrode in the same pixel unit. The two pixel electrodes of two pixel units located in the same pixel unit subgroup pg are arranged along the second direction X; the two TFTs of two pixel units located in the same pixel unit subgroup pg are arranged along the first direction Y.

[0120] Specifically, such as Figures 3-13 As shown, each pixel unit group PG corresponds to two gate lines, and the two gate lines are located on opposite sides of the corresponding pixel unit group PG in the first direction Y. The pixel unit subgroup includes a first pixel unit 10 and a second pixel unit 20, with the first pixel unit 10 located on the side of the second pixel unit 20 away from the data line Data corresponding to the pixel unit subgroup.

[0121] In this design, the thin-film transistor of the first pixel unit 10 is a first thin-film transistor T1, and the pixel electrode of the first pixel unit 10 is a first pixel electrode pix1. The thin-film transistor of the second pixel unit 20 is a second thin-film transistor T2, and the pixel electrode of the second pixel unit 20 is a second pixel electrode pix2. The first pixel electrode pix1 includes a first body electrode p11 and a first connecting electrode p21, and the first connecting electrode p21 is connected to the corresponding first body electrode p11 and the second electrode 42 of the first thin-film transistor T1. The second pixel electrode pix2 includes a second body electrode p12 and a second connecting electrode p22, and the second connecting electrode p22 is connected to the corresponding second body electrode p12 and the second electrode 42 of the second thin-film transistor T2.

[0122] like Figures 3-13As shown, the first thin-film transistor T1 and the second thin-film transistor T2 are located on opposite sides of the second body electrode p12 in the first direction Y. That is, the first thin-film transistor T1, the second body electrode p12, and the second thin-film transistor T2 are arranged along the first direction Y. The first body electrode p11 and the second body electrode p12 are arranged along the second direction X. The first connecting electrode p21 and the first thin-film transistor T1 are located on the same side of the second body electrode p12, and the second connecting electrode p22 and the second thin-film transistor T2 are located on the same side of the second body electrode p12.

[0123] Since the first thin-film transistor T1 and the second thin-film transistor T2 are located on opposite sides of the second body electrode p12 in the first direction Y, and the first body electrode p11 is located on the side of the second body electrode p12 away from the data line Data in the second direction X, the area of ​​the first connecting electrode p21 used to connect the first body electrode p11 and the first thin-film transistor T1 is greater than the area of ​​the second connecting electrode p22 used to connect the second body electrode p12 and the second thin-film transistor T2. That is, the area of ​​the first connecting electrode p21 projected onto the substrate 1 is greater than the area of ​​the second connecting electrode p22 projected onto the substrate 1.

[0124] In some embodiments, such as Figure 4 As shown, a third spacing region N3 is formed between adjacent pixel unit groups PG. The ratio of the overlapping area of ​​the orthographic projection of the common electrode COM on the substrate 1 and the orthographic projection of the third spacing region N3 on the substrate 1 to the area of ​​the third spacing region N3 is 0.8-0.9. In some embodiments, the ratio of the orthographic projection of the portion of the common electrode COM located in the opening region on the substrate 1 to the area of ​​the opening region is 0.65-0.75.

[0125] In this embodiment of the present disclosure, by increasing the area of ​​the common electrode COM on the third spacing region N3 between adjacent pixel units, the orthogonal projection of its outer edge on the substrate will not be covered by the orthogonal projection of the gate line on the substrate, thereby avoiding electric field disturbance between the edge position of the common electrode and the gate line, improving the stability of the liquid crystal, and effectively improving the phenomenon of trace mura on the display panel.

[0126] Based on the structure of the aforementioned common electrode COM, the difference between the storage capacitance Cst corresponding to the first pixel unit 10 and the second pixel unit 20 is less than 1.5fF; and the difference between the voltage drops generated on the first pixel unit 10 and the second pixel unit 20 is less than 0.005V. See Table 1 below for details.

[0127] It should be understood that, for a single pixel unit, the voltage drop ΔVp across the pixel electrode can be calculated using Equation 1:

[0128] △Vp=(Cgs+Cpg)×(Vgh-Vgl) / (Cgs+Cpg+Cst+Clc) Formula 1

[0129] Wherein, Cgs is the parasitic capacitance (gate-source capacitance) generated between the gate and source of the thin-film transistor, Cpg is the parasitic capacitance generated between the pixel electrode and the gate 43, Cst is the storage capacitance generated between the common electrode COM and the pixel electrode, Clc is the liquid crystal capacitor, and Vgh and Vgl are the high-level voltage signal and low-level voltage signal received on the pixel electrode, respectively.

[0130] Within a pixel unit subgroup pg, because the sizes of the first connecting electrode p21 in the first pixel unit 10 and the second connecting electrode p22 in the second pixel unit 20 are different, the areas of the first pixel electrode pix1 and the second pixel electrode pix2 facing the common electrode COM are different. Therefore, the storage capacitors Cst corresponding to the first pixel unit 10 and the second pixel unit 20 are different, resulting in different voltage drops on the pixel electrodes in the first pixel unit 10 and the second pixel unit 20. This leads to a brightness difference between the first pixel unit 10 and the second pixel unit 20, producing a "head wrinkle" phenomenon on the entire display panel and affecting the display effect.

[0131] Table 1

[0132]

[0133] Table 1 shows the capacitance difference between the first pixel unit 10 and the second pixel unit 20 in the same pixel unit subgroup pg in the comparative example and the array substrate in Embodiment 1 of this disclosure. The structure of the common electrode COM on the array substrate in the comparative example is as follows: Figure 2 As shown, in Embodiment 1 of this disclosure, the common electrode COM on the array substrate covers the spacing region between adjacent pixel unit groups PG, excluding the active layer pattern 44 of the thin-film transistor. Furthermore, the array substrates in the comparative example and Embodiment 1 of this disclosure are identical in structure except for the common electrode COM; both employ the same type of thin-film transistor and the same driving method, and the driving voltage provided to the pixel electrodes is also the same.

[0134] The aforementioned "common electrode COM on the array substrate covers the spacing area between adjacent pixel unit groups PG, excluding the active layer pattern 44 of the thin-film transistor" refers to the following: in addition to the opening area of ​​the pixel unit, the common electrode COM also covers the area between adjacent pixel unit groups PG, and a first via k1 is provided on the common electrode COM. The orthographic projection of the first via k1 in the direction of the substrate 1 overlaps with the orthographic projection of the active layer pattern 44 of the thin-film transistor on the substrate 1. The main difference between the array substrate in the comparative example and the first embodiment of this disclosure lies in the structure and position of the common electrode layer COM10. As shown in Table 1, regardless of whether it is the first pixel unit 10 or the second pixel unit 20, the storage capacitance Cst of the array substrate in the first embodiment of this disclosure is significantly larger than that of the array substrate in the comparative example. In addition, there is no significant difference in the gate-source capacitance Cgs, the parasitic capacitance Cpg generated between the pixel electrode and the gate 43, and the liquid crystal capacitance Clc, which will not be described in detail in this disclosure.

[0135] Specifically, for the array substrate in the comparative example, due to its common electrode COM structure as... Figure 2 As shown, the common electrode COM covers both the opening and edge regions of the pixel unit. In other words, the common electrode COM essentially does not cover the gap region between adjacent pixel unit groups PG. Simultaneously, the first connecting electrode p21 and the second connecting electrode p22 corresponding to the first pixel unit 10 and the second pixel unit 20, respectively, are located within the gap region. Therefore, the differences in the pixel electrode structures corresponding to the first pixel unit 10 and the second pixel unit 20 will not significantly affect the overlap area of ​​the pixel electrodes and the common electrode COM in the direction perpendicular to the substrate 1. The aforementioned "edge region" refers to the boundary between the opening region of the pixel unit and the first gap region N1 between adjacent pixel unit groups PG, specifically the side closer to the opening region.

[0136] It should also be noted that there is a small difference in the storage capacitance Cst between the first pixel unit 10 and the second pixel unit 20 in the comparative example. This is because: in the second direction X, a via k3 is provided on the side of the second connecting electrode p22 away from the second thin film transistor T2. The common voltage line and the common electrode COM, which are disposed on the same layer as the gate line, are connected through the via k3. The via k3 is located on the edge region of the second pixel unit 20. The orthographic projection of the common electrode COM in the direction of the substrate 1 partially overlaps with the orthographic projection of the via k3 on the substrate 1. However, the via k3 is not provided in the first pixel unit 10, thereby causing the difference in the storage capacitance Cst between the first pixel unit 10 and the second pixel unit 20.

[0137] Similarly, the shape of the second through hole k2 can be any one of the following: circular, near-circular, square, or rounded square. This embodiment does not impose any limitation on this shape.

[0138] In the array substrate of Embodiment 1 of this disclosure, since the common electrode COM covers not only the opening area of ​​the pixel unit but also the third spacing area N3 between adjacent pixel unit groups PG, the area of ​​the common electrode COM is significantly increased. Furthermore, the overlap area between the common electrode COM and the pixel electrode in the direction perpendicular to the substrate 1 is also increased. Therefore, the storage capacitance Cst of the array substrate in the comparative example is significantly increased. However, since the common electrode COM extends into the spacing area, and the electrodes of the pixel electrodes corresponding to the first pixel unit 10 and the second pixel unit 20 are not the same, and the area of ​​the first connecting electrode p21 is larger than that of the second connecting electrode p22, the overlap area of ​​the common electrode COM and the first pixel electrode pix1 in the first pixel unit 10 in the direction perpendicular to the substrate 1 is greater than the overlap area of ​​the common electrode COM and the second pixel electrode pix2 in the second pixel unit 20 in the direction perpendicular to the substrate 1. This further leads to a significant difference in the storage capacitance Cst corresponding to the first pixel unit 10 and the second pixel unit 20.

[0139] Based on the above analysis and in conjunction with Table 1, it can be seen that although the electric field disturbance between the edge area of ​​the common electrode COM and the gate line is avoided by increasing the coverage area of ​​the common electrode COM in the embodiments of this disclosure, the voltage drop difference on the pixel electrode of the first pixel unit 10 and the second pixel unit 20 calculated by the above formula 1 in the comparative example and the first embodiment of this disclosure is basically the same, which will lead to the display defect of "forehead wrinkles" on the display panel.

[0140] To address the technical problem of "brow lines" appearing on display panels, this disclosure provides an array substrate that adjusts the storage capacitor Cst by setting multiple second through holes on the common electrode and adjusting the facing area of ​​the common electrode and the pixel electrode.

[0141] like Figures 3-13 As shown, the common electrode COM further includes a plurality of second vias k2 corresponding to at least a portion of the first connecting electrodes p21, wherein the orthographic projection of the second vias k2 on the substrate 1 overlaps with the orthographic projection of the first connecting electrodes p21 on the substrate 1. Preferably, the common electrode COM includes a plurality of second vias k2 corresponding to each of the first connecting electrodes p21.

[0142] In this embodiment of the array substrate, a second through-hole k2 is provided on the common electrode COM in the area directly opposite to the first connecting electrode p21, thereby reducing the area of ​​the portion directly opposite the common electrode COM and the first connecting electrode p21, that is, reducing the overlap area between the common electrode COM and the first pixel electrode pix1, further reducing the difference in the overlap area between the first pixel electrode pix1 and the second pixel electrode pix2 and the common electrode COM, improving the difference in the storage capacitance Cst on the first pixel unit 10 and the second pixel unit 20, so as to improve the phenomenon of "head wrinkles" appearing on the display panel and improve the display effect.

[0143] The aforementioned overlapping area refers to the area of ​​the overlapping portion of the orthographic projection of the pixel electrode (first pixel electrode pix1 / second pixel electrode pix2) on the substrate 1 and the orthographic projection of the common electrode COM on the substrate 1.

[0144] In some embodiments, such as Figure 10 , Figure 11 As shown, the first connecting electrode p21 includes a first connecting portion p211 and a second connecting portion p212. The orthographic projection of the second connecting portion p212 on the substrate 1 and the orthographic projection of the gate 43 of the first thin film transistor T1 on the substrate 1 are arranged along the second direction X. The first connecting portion p211 connects the first body electrode p11 and the second connecting portion p212. The second connecting portion p212 is connected to the second electrode 42 of the first thin film transistor T1. The orthographic projection of the second through hole k2 on the substrate 1 overlaps with the orthographic projection of the second connecting portion p212 on the substrate 1.

[0145] It should be understood that the second connecting portion p212 is wider and has a larger overall area than the first connecting portion p211. In this case, if a second through hole k2 is provided on the common electrode COM opposite to the first connecting portion p211, the width of the first connecting portion p211 may be smaller than the diameter of the second through hole k2. In this case, the orthographic projection of the first connecting portion p211 on the substrate 1 cannot completely cover the orthographic projection of the second hole diameter on the substrate 1. That is to say, even if the second through hole k2 is provided, the hollow portion of the second through hole k2 cannot be fully utilized to reduce the overlap area between the common electrode COM and the first connecting electrode p21. Therefore, providing the second through hole k2 on the common electrode COM corresponding to the second connecting portion p212 can ensure the effective reduction of the overlap area between the common electrode COM and the first connecting electrode p21.

[0146] Furthermore, since the second connecting portion p212 is located on the side of the first connecting portion p211 that is far from the first body electrode p11, and the first body electrode p11 is located on the opening area of ​​the first pixel unit 10, the second connecting portion p212 is farther away from the opening area than the first connecting portion p211. Therefore, by setting the second through hole k2 on the common electrode COM corresponding to the second connecting portion p212, it can be ensured that the formation of the second through hole k2 will not affect the display effect. In addition, the second connecting portion p212 has a larger area than the first connecting portion p211, which can reduce the difficulty of the hole-cutting process and improve the accuracy of the hole-cutting, ensuring the effective formation of the second through hole k2.

[0147] Preferably, in some embodiments, the orthographic projection of the second connecting portion p212 on the substrate 1 covers the orthographic projection of the corresponding second through hole k2 on the substrate 1, so as to fully utilize the hollow portion of the second through hole k2 to reduce the overlap area between the common electrode COM and the first connecting electrode p21, ensuring the effective reduction of the overlap area, that is, reducing the difference in the overlap area between the first pixel electrode pix1 and the second pixel electrode pix2 and the common electrode COM, improving the difference in the storage capacitance Cst corresponding to the first pixel unit 10 and the second pixel unit 20, and further reducing the voltage drop difference on the pixel electrodes corresponding to the first pixel unit 10 and the second pixel unit 20, thereby avoiding the phenomenon of "head wrinkles" on the display panel and improving the display effect.

[0148] In some embodiments, the overlap area of ​​the common electrode COM and the first connecting electrode p21 in the direction perpendicular to the substrate 1 is equal to the overlap area of ​​the common electrode COM and the second connecting electrode p22 in the direction perpendicular to the substrate 1. Simultaneously, the area of ​​the first body electrode p11 projected onto the substrate 1 is the same as the area of ​​the second body electrode p12 projected onto the substrate 1. Therefore, the overlap area of ​​the common electrode COM and the first pixel electrode pix1 in the direction perpendicular to the substrate 1 is equal to the overlap area of ​​the common electrode COM and the second pixel electrode pix2 in the direction perpendicular to the substrate 1. This ensures that the storage capacitance Cst on the first pixel unit 10 and the second pixel unit 20 is substantially the same, further reducing the voltage drop difference on the pixel electrodes corresponding to the first pixel unit 10 and the second pixel unit 20, thereby avoiding the "head wrinkle" phenomenon on the display panel and improving the display effect.

[0149] Referring again to Table 1, which also shows the capacitance difference between the first pixel unit 10 and the second pixel unit 20 within the same pixel unit subgroup pg in Embodiment 2, the structure of the common electrode COM of the array substrate in Embodiment 2 is as follows. Figure 6As shown, the common electrode COM covers not only the opening area of ​​the pixel unit but also the area between adjacent pixel unit groups PG. A first through-hole k1 and a second through-hole k2 are provided on the common electrode COM. The orthographic projection of the first through-hole k1 onto the substrate 1 overlaps with the orthographic projection of the active layer pattern 44 of the thin-film transistor onto the substrate 1. The orthographic projection of the second connection portion p212 of the first pixel electrode pix1 onto the substrate 1 covers the orthographic projection of the corresponding second through-hole k2 onto the substrate 1. The array substrates of the comparative examples, Embodiment 1, and Embodiment 2 of this disclosure are identical in structure except for the common electrode COM.

[0150] Specifically, as shown in Table 1, by setting a second through-hole k2 on the common electrode COM and adjusting the overlap area between the first pixel electrode pix1 and the second pixel electrode pix2 and the common electrode COM, the difference between the storage capacitors Cst corresponding to the first pixel unit 10 and the second pixel unit 20 is significantly reduced compared to Embodiment 1. Furthermore, the voltage drop difference on the pixel electrodes of the first pixel unit 10 and the second pixel unit 20 calculated by Formula 1 above is only 0.002V, which is also significantly reduced compared to Embodiment 1, thereby avoiding the phenomenon of "head wrinkles" on the display panel and improving the display effect.

[0151] In addition, the array substrates of the comparative examples, Embodiment 1 and Embodiment 2 of this disclosure are identical in structure except for the common electrode COM; and all three use the same type of thin-film transistor and the same driving method, as well as the same driving voltage provided to the pixel electrode.

[0152] In some embodiments, such as Figure 10 As shown, the second connection electrode p22 includes a third connection portion p221 and a fourth connection portion p222. The orthographic projection of the fourth connection portion p222 on the substrate 1 and the orthographic projection of the gate 43 of the second thin film transistor T2 on the substrate 1 are arranged along the second direction X. The third connection portion p221 connects the second body electrode p12 and the fourth connection portion p222, and the fourth connection portion p222 is connected to the second electrode 42 of the second thin film transistor T2.

[0153] In some embodiments, such as Figure 4 As shown, the distance d2 between the edge of the orthographic projection of the second through hole k2 on the substrate 1 and the edge of the orthographic projection of the second connecting part p212 on the substrate 1 on the same side is 1.5-5μm. For example, d2 can be any one of 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, or other distances. No specific limitation is made in this disclosure.

[0154] In some embodiments, such as Figure 6As shown, the average aperture D of the second through hole k2 is 2.5-10 μm. For example, D can be any one of 2.5 μm, 3 μm, 4 μm, 5 μm, 6 μm, and 7 μm, or other aperture sizes. This disclosure does not impose specific limitations. It should be understood that the shape of the second through hole can be any one of circular, near-circular, square, or rounded square shapes. The aforementioned average aperture refers to the average of the maximum and minimum aperture distances passing through the geometric center of the hole. For example, when the second through hole is circular, the average aperture is the diameter of the circle; when the second through hole is square, the maximum aperture distance is the distance between its diagonals, and the minimum aperture distance is the distance between its sides, so the average aperture is the average of the two; when the second through hole is elliptical, the average aperture is the average of the major and minor axes of the ellipse. This disclosure does not impose any limitations on this aspect.

[0155] In some embodiments, the orthographic projection of the second through hole k2 on the substrate 1, the orthographic projection of the second electrode 42 of the first thin film transistor T1 on the substrate 1, and the orthographic projection of the second connection portion p212 on the substrate 1 overlap.

[0156] In some embodiments, the common electrode COM includes a plurality of first vias k1 corresponding one-to-one with the thin-film transistors;

[0157] The orthographic projection of the first via k1 on the substrate 1 is located within the area covered by the orthographic projection of the active layer pattern 44 of the corresponding thin film transistor on the substrate 1; the minimum distance d3 between the second via k2 and the first via k1 corresponding to the first thin film transistor T1 connected to the first connecting electrode p21 in the second direction X is 5-10μm.

[0158] In some embodiments, two adjacent pixel unit subgroups include a first pixel unit subgroup pg1 and a second pixel unit subgroup pg2.

[0159] In the first pixel unit subgroup pg1, the first thin film transistor T1 is located on the first side of the second body electrode p12 in the first direction Y, and the second thin film transistor T2 is located on the second side of the second body electrode p12 in the first direction Y; in the first pixel unit subgroup pg1, the first connecting electrode p21 of the first pixel unit 10 is located on the first side of the first body electrode p11 in the first direction Y, and the second connecting electrode p22 of the second pixel unit 20 is located on the second side of the second body electrode p12 in the first direction Y.

[0160] In the second pixel unit subgroup pg2, the first thin film transistor T1 is located on the second side of the second body electrode p12 in the first direction Y, and the second thin film transistor T2 is located on the first side of the second body electrode p12 in the first direction Y; in the second pixel unit subgroup pg2, the first connecting electrode p21 of the first pixel unit 10 is located on the second side of the first body electrode p11 in the first direction Y, and the second connecting electrode p22 of the second pixel unit 20 is located on the first side of the second body electrode p12 in the first direction Y.

[0161] The first side and the second side are opposite sides in the first direction Y.

[0162] Figure 14 The layout of the passivation layer provided in the embodiments of this disclosure. Figure 15 This is a superimposed layout of a first metal layer, an active layer pattern of a thin-film transistor, a pixel electrode, a data line, and a passivation layer, provided for embodiments of this disclosure. In some embodiments, such as Figure 3 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 As shown, in some embodiments, the array substrate further includes a plurality of common voltage line groups Lcom corresponding one-to-one with the pixel unit group PG, and the common voltage line groups Lcom are disposed on the same layer as the gate line. The common voltage line group Lcom includes a second common voltage line L2 extending along the second direction X and a plurality of first common voltage lines L1 extending along the first direction Y.

[0163] Specifically, such as Figure 11 As shown, a second spacing region N2 is formed between the first body electrode p11 and the second body electrode p12 located in the same pixel unit subgroup pg, and the first common voltage line L1 is located in the second spacing region N2; the first body electrode p11 and the second body electrode p12 are both dual-domain electrodes, and the dual-domain electrode includes a first domain region and a second domain region arranged along the first direction Y, and the orthogonal projection of the second common voltage line L2 on the substrate 1 covers the boundary between the first domain region and the second domain region.

[0164] By setting a horizontal common voltage line that runs through the opening area of ​​the pixel unit, and a column-oriented common voltage line between two columns of pixel units located between adjacent data lines, the uniformity of the common voltage applied to each pixel unit can be improved.

[0165] In some embodiments, such as Figure 7 , Figure 14 , Figure 15As shown, the first common voltage line L1 near the second connecting electrode p22 includes a first protruding pattern z1, which is electrically connected to the common electrode COM through a via k3 penetrating the gate insulating layer GI and the passivation layer PVX.

[0166] like Figure 15 As shown, the first conductive connection line G2 includes a first portion g1, a second portion g2, and a third portion g3 arranged and connected sequentially along the second direction X. The first portion g1 and the third portion g3 extend along the second direction X and are connected to different first conductive patterns G1. In the second direction X, the orthographic projection of the via k3 onto the substrate 1 lies between the orthographic projection of the second portion g2 onto the substrate 1 and the orthographic projection of the second connecting electrode p22 onto the substrate 1.

[0167] In addition, such as Figure 7 As shown, a second protruding pattern z2 is provided on the second part g2. The second protruding pattern z2 is used to compensate for the gate-source capacitance Cgs generated on the corresponding thin-film transistor. Specifically, the second electrode 42 of the thin-film transistor is connected to the first connection electrode p21 on the first pixel electrode pix1, and the second electrode 42 extends to the region opposite to the second protruding pattern z2, thereby increasing the facing area of ​​the second electrode 42 and the gate line in the direction perpendicular to the substrate. Based on this setting, even if the position of the gate 43 (first conductive pattern G1) is offset, it can still be ensured that the facing area of ​​the gate line Gate and the second electrode 42 in the direction perpendicular to the substrate will not decrease, ensuring the consistency of the gate-source capacitance Cgs, thereby avoiding voltage drop differences on the pixel electrode. The aforementioned second electrode 42 refers to the source electrode of the thin-film transistor.

[0168] Based on the same inventive concept, this disclosure also provides a display panel including an array substrate, which includes the array substrate provided in the previous embodiments. For a description of the array substrate, please refer to the content in the previous embodiments, and it will not be repeated here.

[0169] The display panel provided in this embodiment may further include a cell-to-cell substrate disposed with the array substrate. A liquid crystal layer and a plurality of spacers are disposed between the array substrate and the cell-to-cell substrate. The spacers are located in the interval area between the opening areas of adjacent pixel units and are used to support the thickness of the liquid crystal cell and prevent the display panel from deforming. The spacers can be fabricated on the array substrate or on the cell-to-cell substrate.

[0170] The substrate may include a base and a black matrix and a color filter matrix located on the base. The color filter pattern in the color filter matrix corresponds one-to-one with the pixel unit to achieve color display.

[0171] This disclosure also provides a display device, including the above-described display panel.

[0172] The display device provided in this embodiment can be any product or component with display function, such as wearable devices, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, and navigators. Other essential components of this display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0173] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a peripheral area surrounding the display area, the display area having a plurality of pixel unit groups arranged along a first direction, the pixel unit groups including a plurality of pixel units arranged along a second direction, the pixel units including thin film transistors; The array substrate further includes: Multiple gate lines are arranged along a first direction, the gate lines extend along a second direction, the gate lines include first conductive patterns and first conductive connecting lines arranged alternately along the second direction, the first conductive connecting lines are connected to adjacent first conductive patterns, and the first conductive patterns are multiplexed as the gate of the thin film transistor; A common electrode, wherein the orthographic projection of the common electrode on the substrate at least covers the orthographic projection of the first conductive connection line on the substrate; The pixel unit further includes a pixel electrode, which includes a body electrode and a connection electrode. Each pixel unit group corresponds to two gate lines, and the two gate lines are respectively located on opposite sides of the corresponding pixel unit group in the first direction; Within each pixel unit group, every two adjacent pixel units form a pixel unit subgroup, and each pixel unit subgroup corresponds one-to-one with a data line. The pixel unit subgroup includes a first pixel unit and a second pixel unit, wherein the first pixel unit is located on the side of the second pixel unit away from the data line corresponding to the pixel unit subgroup; The thin-film transistor of the first pixel unit is a first thin-film transistor, the pixel electrode of the first pixel unit is a first pixel electrode, the thin-film transistor of the second pixel unit is a second thin-film transistor, and the pixel electrode of the second pixel unit is a second pixel electrode. The first pixel electrode includes a first body electrode and a first connection electrode, wherein the first connection electrode is connected to the corresponding first body electrode and the second electrode of the first thin film transistor; The second pixel electrode includes a second body electrode and a second connection electrode, wherein the second connection electrode is connected to the corresponding second body electrode and the second electrode of the second thin film transistor; The area of ​​the first connecting electrode projected onto the substrate is larger than the area of ​​the second connecting electrode projected onto the substrate. The common electrode further includes: a plurality of second through holes corresponding one-to-one with at least a portion of the first connecting electrodes, wherein the orthographic projection of the second through holes on the substrate overlaps with the orthographic projection of the first connecting electrodes on the substrate; by providing the second through holes, the difference in the overlap area between the first pixel electrode and the second pixel electrode and the common electrode is reduced.

2. The array substrate according to claim 1, wherein, The common electrode includes a plurality of first vias corresponding one-to-one with at least a portion of the thin-film transistors; the thin-film transistors also include an active layer located on one side of the gate. The orthographic projection of the first via on the substrate falls within the area covered by the orthographic projection of the active layer corresponding to the thin-film transistor on the substrate.

3. The array substrate according to claim 2, wherein, The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the active layer pattern corresponding to the thin-film transistor on the substrate.

4. The array substrate of claim 2, wherein, The thin-film transistor includes a first electrode and a second electrode, and the connecting electrode connects the corresponding body electrode and the second electrode of the thin-film transistor; The minimum distance between the orthographic projection of the first through hole on the substrate and the orthographic projection of any of the body electrodes on the substrate in the first direction is 3-10 μm.

5. The array substrate according to claim 4, wherein, Two gate lines are provided between adjacent pixel unit groups; The array substrate further includes: multiple data lines extending along the first direction; The pixel unit is connected to the data line corresponding to its pixel unit subgroup; Two pixel units located in the same pixel unit subgroup are connected by different gate lines.

6. The array substrate according to claim 5, wherein, A first spacing region is formed between the two gate lines located between adjacent pixel unit groups; The orthographic projection of the common electrode on the substrate covers the orthographic projection of the portion of the data line located in the first interval region on the substrate.

7. The array substrate according to claim 5, wherein, A first spacing region is formed between the two gate lines located between adjacent pixel unit groups; The orthogonal projection of the common electrode on the substrate covers the orthogonal projection of the first interval region on the substrate.

8. The array substrate of claim 5, wherein, A third spacing region is formed between adjacent pixel unit groups. The ratio of the overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the third interval region on the substrate to the area of ​​the orthographic projection of the third interval region on the substrate is 0.8-0.

9.

9. The array substrate according to any one of claims 5 to 8, wherein, The gate of the thin-film transistor is connected to the corresponding gate line, the first electrode of the thin-film transistor is connected to the data line corresponding to the pixel unit, and the second electrode of the thin-film transistor is connected to the pixel electrode in the same pixel unit. The two pixel electrodes of two pixel units located within the same pixel unit subgroup are arranged along the second direction; The two thin-film transistors of two pixel units located within the same pixel unit subgroup are arranged along the first direction.

10. The array substrate according to claim 9, wherein, The first thin-film transistor and the second thin-film transistor are located on opposite sides of the second body electrode in the first direction; The first body electrode and the second body electrode are arranged along the second direction, the first connecting electrode and the first thin film transistor are located on the same side of the second body electrode, and the second connecting electrode and the second thin film transistor are located on the same side of the second body electrode.

11. The array substrate of claim 1, wherein, The first connection electrode includes a first connection portion and a second connection portion. The orthographic projection of the second connection portion on the substrate and the orthographic projection of the gate of the first thin film transistor on the substrate are arranged along a second direction. The first connection portion connects the first body electrode and the second connection portion, and the second connection portion is connected to the second electrode of the first thin film transistor. The orthographic projection of the second through hole on the substrate overlaps with the orthographic projection of the second connecting portion on the substrate.

12. The array substrate of claim 11, wherein, The orthographic projection of the second connecting portion on the substrate covers the orthographic projection of the corresponding second through hole on the substrate.

13. The array substrate of claim 12, wherein, The minimum distance between the edge of the orthographic projection of the second through hole on the substrate and the edge of the orthographic projection of the second connection portion on the substrate on the same side is 1.5-5 μm.

14. The array substrate according to any one of claims 11 to 13, wherein, The orthographic projection of the second through hole on the substrate, the orthographic projection of the second electrode of the first thin film transistor on the substrate, and the orthographic projection of the second connection portion on the substrate overlap.

15. The array substrate of claim 1, wherein, The overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the first connecting electrode on the substrate is equal to the overlapping area of ​​the orthographic projection of the common electrode on the substrate and the orthographic projection of the second connecting electrode on the substrate.

16. The array substrate of claim 1, wherein, The average diameter of the second through hole is 2.5-10 μm.

17. The array substrate of claim 1, wherein, The common electrode includes a plurality of first through holes corresponding one-to-one with the thin-film transistor; The orthographic projection of the first via on the substrate is located within the area covered by the orthographic projection of the active layer pattern corresponding to the thin-film transistor on the substrate. The minimum distance between the second through hole and the first through hole corresponding to the first thin-film transistor connected to the first connecting electrode in the second direction is 5-10 μm.

18. The array substrate of claim 10, wherein, Two adjacent pixel unit subgroups include a first pixel unit subgroup and a second pixel unit subgroup; In the first pixel unit subgroup, the first thin-film transistor is located on the first side of the second body electrode in the first direction, and the second thin-film transistor is located on the second side of the second body electrode in the first direction. In the first pixel unit subgroup, the first connecting electrode of the first pixel unit is located on the first side of the first body electrode in the first direction, and the second connecting electrode of the second pixel unit in the first pixel unit subgroup is located on the second side of the second body electrode in the first direction; In the second pixel unit subgroup, the first thin-film transistor is located on the second side of the second body electrode in the first direction, and in the first pixel unit subgroup, the second thin-film transistor is located on the first side of the second body electrode in the first direction; In the second pixel unit subgroup, the first connecting electrode of the first pixel unit is located on the second side of the first body electrode in the first direction, and the second connecting electrode of the second pixel unit in the second pixel unit subgroup is located on the first side of the second body electrode in the first direction; Wherein, the first side and the second side are opposite sides in the first direction.

19. The array substrate according to claim 10, wherein, The array substrate further includes: a plurality of common voltage line groups that correspond one-to-one with the pixel unit groups; The common voltage line group includes a second common voltage line extending along the second direction and a plurality of first common voltage lines extending along the first direction; A second spacing region is formed between the first body electrode and the second body electrode located in the same pixel unit subgroup, and the first common voltage line is located in the second spacing region; Both the first body electrode and the second body electrode are dual-domain electrodes. The dual-domain electrode includes a first domain region and a second domain region arranged along the first direction. The orthogonal projection of the second common voltage line on the substrate covers the boundary between the first domain region and the second domain region.

20. The array substrate according to claim 19, wherein, The end of the first common voltage line near the second connecting electrode is electrically connected to the common electrode through a via.

21. The array substrate according to claim 10, wherein, The difference between the storage capacitance corresponding to the first pixel unit and the storage capacitance corresponding to the second pixel unit is less than 1.5fF.

22. The array substrate according to claim 10, wherein, The difference between the voltage drop generated by the first pixel unit and the voltage drop generated by the second pixel unit is less than 0.005V.

23. A display panel, wherein, Includes the array substrate as described in any one of claims 1 to 22.

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