Storage system, method of operating a storage system, and computer-readable storage medium

Abstract

The application discloses a storage system, an operation method of the storage system and a computer readable storage medium, and relates to the technical field of storage. The storage system comprises a memory and a memory controller. The memory comprises a storage array. The storage array is coupled with n word lines. The n word lines are arranged in a physical word line identification order, and n is greater than or equal to 2. The memory controller is configured to map the n physical word line identifications into n virtual word line identifications. Adjacent m virtual word line identifications correspond to physical word line identifications that are spaced from each other, and 2 is less than or equal to m and m is less than or equal to n. Check data is generated based on data corresponding to the adjacent m virtual word line identifications. The check data is generated based on data corresponding to multiple adjacent virtual word line identifications, that is, the check data is generated based on data corresponding to multiple non-adjacent physical word line identifications. The influence of the mutual influence between adjacent physical word lines on the check data is reduced, the success rate of data recovery is improved, and the reliability of data storage and reading is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a storage system, a method of operating the storage system, and a computer-readable storage medium. Background Technology

[0002] In a 3D memory, the memory cells are coupled to word lines, and data is written to the memory cells by the programming voltage applied to the word lines.

[0003] When writing data to a 3D memory, to prevent errors during subsequent data reads, checksum data can be generated based on the written data. This way, when reading data from the memory, the read data is verified against the checksum data. If the verification fails, the correct data can be recovered from the checksum data. Ensuring successful data recovery in the event of verification failure is currently a hot research topic. Summary of the Invention

[0004] This application provides a storage system, a method for operating the storage system, and a computer-readable storage medium, which can improve programming efficiency. The technical solution is as follows:

[0005] On one hand, a storage system is provided, characterized in that the storage system includes: one or more memories, and a memory controller coupled to the memories and configured to control the memories; the memories include a memory array coupled to n word lines, the n word lines being arranged in physical word line identification order, where n≥2;

[0006] The memory controller is configured to acquire multiple copies of data to be written to the memory array;

[0007] The memory controller is configured to map the n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the m adjacent virtual word line identifiers are spaced apart from each other, and 2≤m≤n;

[0008] The memory controller is configured to generate verification data based on the data corresponding to the adjacent m virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the adjacent m virtual word line identifiers.

[0009] In an optional embodiment, the memory controller is configured to obtain a pre-set mapping table, which includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; and to match the n physical word line identifiers with the mapping table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0010] In an optional embodiment, the memory controller is configured to retrieve the pre-set mapping table from static random access memory.

[0011] In an optional embodiment, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

[0012] In an optional embodiment, the memory controller is configured to obtain a preset algorithm for mapping physical word line identifiers to virtual word line identifiers; and to substitute the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0013] In an optional embodiment, the memory controller is configured to process the data corresponding to the adjacent m virtual word line identifiers using a first operator to obtain the verification data. The verification data is used to verify and recover the failed data by using a second operator when there is a data read failure in the data corresponding to the adjacent m virtual word line identifiers. The first operator and the second operator are operators with opposite operational logic.

[0014] In an optional embodiment, the memory controller is configured to send a first read instruction to the memory, the first read instruction including a first physical word line identifier corresponding to a first piece of data to be read; and receive a data read result returned by the memory;

[0015] The memory controller is configured to, when the data read result indicates that the first data read corresponding to the first physical word line identifier has failed, determine a first virtual word line identifier corresponding to the first physical word line identifier; and obtain target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read.

[0016] In an optional embodiment, the memory controller is configured to acquire the target verification data corresponding to the first virtual word line identifier, and acquire a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data; and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0017] The memory controller is configured to send a second read instruction to the memory, the second read instruction including a second physical word line identifier, the second read instruction being used to instruct the memory to read data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; receive second data returned by the memory corresponding to the second physical word line identifier, and recover the first data that failed to be read based on the target check data and the second data.

[0018] In an optional embodiment, the memory controller is configured to, when reading the first data corresponding to the first physical word line identifier, determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; obtain a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0019] Send a read instruction to the memory, the read instruction being used to instruct the reading of data stored in the memory cell row coupled to the word line corresponding to the first physical word line identifier and the second physical word line identifier;

[0020] The memory controller is configured to receive the data read result returned by the memory; if the data read result indicates that the first data read failed, it calls the target verification data and the second data corresponding to the second physical word line identifier to recover the first data that failed to be read.

[0021] On the other hand, a method for operating a storage system is provided, the storage system including a memory with a storage array coupled to n word lines, the n word lines being arranged in physical word line identification order, where n≥2;

[0022] The method includes:

[0023] Acquire multiple copies of data to be written to the storage array;

[0024] Verification data is written to the memory. The verification data is generated based on the data corresponding to the physical word lines that are spaced apart from each other. The verification data is used to verify and recover the data.

[0025] In an optional embodiment, before writing the verification data to the memory, the method further includes:

[0026] The n physical word line identifiers are mapped to n virtual word line identifiers, wherein the physical word line identifiers corresponding to the m adjacent virtual word line identifiers are spaced apart from each other, and 2≤m≤n;

[0027] The verification data is generated based on the data corresponding to the m adjacent virtual character line identifiers. The verification data is used to verify and recover the data corresponding to the m adjacent virtual character line identifiers.

[0028] In an optional embodiment, mapping the n physical word line identifiers to n virtual word line identifiers includes:

[0029] Obtain a pre-set mapping table, which includes the mapping correspondence between physical word line identifiers and virtual word line identifiers;

[0030] Match the n physical word line identifiers with the mapping table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0031] In an optional embodiment, obtaining the pre-set mapping table includes:

[0032] Retrieve the pre-set mapping table from the static random access memory.

[0033] In an optional embodiment, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

[0034] In an optional embodiment, mapping the n physical word line identifiers to n virtual word line identifiers includes:

[0035] A preset algorithm is obtained, which is used to map physical character line identifiers to virtual character line identifiers;

[0036] Substitute the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

[0037] In an optional embodiment, generating verification data based on the data corresponding to the adjacent m virtual character line identifiers includes:

[0038] The first operator processes the data corresponding to the m adjacent virtual word line identifiers to obtain the verification data. The verification data is used to verify and recover the failed data when there is a data reading failure in the data corresponding to the m adjacent virtual word line identifiers, by means of a second operator. The first operator and the second operator are operators with opposite operation logic.

[0039] In an optional embodiment, after writing the verification data to the memory, the method further includes:

[0040] Send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read;

[0041] Receive the data read result returned by the memory;

[0042] If the data reading result indicates that the first data reading corresponding to the first physical word line identifier has failed, a first virtual word line identifier corresponding to the first physical word line identifier is determined;

[0043] Obtain the target verification data corresponding to the first virtual character line identifier to recover the first data that failed to be read.

[0044] In an optional embodiment, the step of obtaining the target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read includes:

[0045] Obtain the target verification data corresponding to the first virtual character line identifier, and obtain the second virtual character line identifier that is used in conjunction with the first virtual character line identifier to generate the target verification data;

[0046] Determine the second physical word line identifier corresponding to the second virtual word line identifier;

[0047] Send a second read instruction to the memory, the second read instruction including the second physical word line identifier, the second read instruction being used to instruct the memory to read the data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier;

[0048] The system receives the second data returned by the memory, which corresponds to the second physical word line identifier, and recovers the first data that failed to be read based on the target verification data and the second data.

[0049] In an optional embodiment, after generating the verification data based on the data corresponding to the adjacent m virtual word line identifiers, the method further includes:

[0050] Send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read;

[0051] Determine the first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier;

[0052] Obtain a second virtual word line identifier that is paired with the first virtual word line identifier to generate the target verification data, and determine the second physical word line identifier corresponding to the second virtual word line identifier;

[0053] Send a second read instruction to the memory, the second read instruction including the second physical word line identifier, the second read instruction being used to instruct the memory to read the data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier;

[0054] Receive the data read result returned by the memory;

[0055] If the data reading result indicates that the first data reading failed, the first data that failed to be read is recovered by calling the target verification data and the second data corresponding to the second physical word line identifier.

[0056] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a memory controller, implement the operation method of the storage system as described in any of the above embodiments.

[0057] The technical solution provided in this application may include the following beneficial effects:

[0058] By setting a mapping relationship between physical word line identifiers and virtual word line identifiers, virtual word line identifiers corresponding to physical word line identifiers are generated. This ensures that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Verification data is generated using data corresponding to multiple adjacent virtual word line identifiers, which in turn generates verification data using data corresponding to multiple non-adjacent physical word line identifiers. This reduces the impact of mutual interference between adjacent physical word lines on the verification data, improves the success rate of data recovery, and enhances the reliability of data storage and retrieval. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0061] Figure 2 This is a schematic diagram of an integrated scenario of a storage system provided in an exemplary embodiment of this application;

[0062] Figure 3 This is a schematic diagram of an integrated scenario of a storage system provided in another exemplary embodiment of this application;

[0063] Figure 4 This is a schematic diagram of a memory provided in an embodiment of this application;

[0064] Figure 5 This is a cross-sectional schematic diagram of a storage array including storage strings provided in an embodiment of this application;

[0065] Figure 6 This is a schematic diagram of the peripheral circuit provided in the embodiments of this application;

[0066] Figure 7 This is a flowchart of an operation method of a storage system provided in an exemplary embodiment of this application;

[0067] Figure 8 This is a schematic diagram of a mapping table provided in an exemplary embodiment of this application;

[0068] Figure 9 This is a schematic diagram of a verification data generation process provided in an exemplary embodiment of this application;

[0069] Figure 10 This is a flowchart of an operation method of a storage system provided in another exemplary embodiment of this application;

[0070] Figure 11 This is a schematic diagram illustrating the data verification and recovery process provided in an exemplary embodiment of this application;

[0071] Figure 12 This is a schematic diagram of the structure of a memory controller provided in an exemplary embodiment of this application. Detailed Implementation

[0072] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0073] The operation method of the storage system provided in this application embodiment can be applied to a storage system. This storage system may include 3D memory, such as 3D NAND flash memory.

[0074] Figure 1 This is a schematic diagram of a storage system 10 provided in an embodiment of this application. For example... Figure 1 As shown, the storage system 10 includes: one or more memories 100, and a memory controller 200 coupled to the memories 100 and configured to control the memories 100.

[0075] The memory controller 200 can be configured to control operations performed by the memory 100, such as read, erase, and program operations. The memory controller 200 can also be configured to manage various functions related to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical address to physical address translation, and wear leveling. Optionally, the memory controller 200 can also be configured to handle error correcting codes (ECCs) for data read from or written to the memory 100. The memory controller 200 can also perform any other suitable functions, such as formatting the memory 100.

[0076] The memory controller 200 can also communicate with external devices according to a specific communication protocol. For example, the memory controller 200 can communicate with external devices through at least one of various interface protocols. These interface protocols can include Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Development Environment (IDE), FireWire, etc.

[0077] In some embodiments, the memory controller 200 and one or more memories 100 can be integrated into various types of electronic devices. These electronic devices may be mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. In such a scenario, such as... Figure 1As shown, the storage system 10 also includes a host 300. A memory controller 200 is coupled to the host 300. The memory controller 200 can manage the data stored in the memory 100 and communicate with the host 300 to perform the functions of the aforementioned electronic device.

[0078] In other embodiments, the memory controller 200 and one or more memories 100 may be integrated into various types of storage devices.

[0079] As an example, such as Figure 2 As shown, the memory controller 200 and the single memory 100 can be integrated into the memory card 400. The memory card 400 may include PCMCIA (PC) cards, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multi-Media Cards (MMC), RS-MMC, micro-MMC, Secure Digital (SD) cards, Universal Flash Storage (UFS), etc. Figure 2 As shown, the memory card 400 may also include a connector 410 for coupling the memory card 400 to the host.

[0080] As another example, such as Figure 3 As shown, the memory controller 200 and multiple memories 100 can be integrated into a solid-state drive (SSD) 500. The solid-state drive 500 may also include a connector 510 for coupling the solid-state drive 500 to the host. The storage capacity and / or operating speed of the solid-state drive 500 is greater than that of the memory card 400.

[0081] also, Figures 1 to 3 The memory 100 can be any memory involved in the embodiments of this application. For example, it can be a 3D NAND (NAND gate) memory. The structure of the memory 100 will be explained below.

[0082] Figure 4 This is a schematic diagram of a memory 100 provided in an embodiment of this application. Figure 4 As shown, the memory 100 includes:

[0083] Storage array 110, which includes multiple rows of storage cells;

[0084] Multiple word lines 120 are coupled to multiple rows of memory cells;

[0085] Peripheral circuitry 130 is coupled to a plurality of word lines 120 and configured to perform a verification operation or a programming operation on a selected memory cell line among a plurality of memory cell lines, wherein the selected memory cell line is a memory cell line coupled to the selected word line, wherein, in order to perform the verification operation or programming operation, peripheral circuitry 130 is configured to perform the memory operation method provided in the embodiments of this application.

[0086] Storage array 110 can be a NAND flash memory storage array. For example... Figure 1 As shown, the NAND flash memory array includes a plurality of memory strings 111 arranged in an array on a substrate, each memory string 111 extending vertically above the substrate (not shown). In some embodiments, each memory string 111 includes a plurality of memory cells 112 that are coupled in series and stacked vertically.

[0087] like Figure 4 As shown, each memory string 111 may further include a source select gate (SSG) 113 at the bottom and a drain select gate (DSG) 114 at the top. The source select gate is also called the bottom select gate (BSG) or source selector, and the drain select gate is also called the top select gate (TSG) or drain selector. The source select gate 113 and the drain select gate 114 can be configured to activate the selected memory string 111 during read and program operations.

[0088] In some embodiments, the drain selection gate 114 of each memory string 111 is coupled to a corresponding bit line 115, and data can be read from or written to the bit line 115 via an output bus (not shown).

[0089] In some embodiments, each memory string 111 is configured to apply a selection voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 116. And / or, in some embodiments, each memory string 111 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 117.

[0090] like Figure 4As shown, the storage string 111 can be organized into multiple blocks 140. For any one of the multiple blocks 140, the block 140 can have a source line (SL) 118. The sources of all storage strings 111 in the block 140 are coupled through the source line 118. The source line is also called the common source line or array common source (ACS).

[0091] The source line 118 can be used for grounding, so that the source of each memory cell in the memory string of block 140 can be grounded in some subsequent operations. Optionally, in some other operations, the source of each memory cell in the memory string of block 140 can also be connected to a high voltage through the source line 118.

[0092] Each block 140 is the basic data unit used for the erase operation, meaning that all memory cells 112 on the same block 140 are erased simultaneously. To erase memory cells 112 in a selected block, an erase voltage (Vers) (e.g., a high positive voltage (20V or higher)) can be biased and coupled to the source line of the selected block.

[0093] It should be understood that, in other embodiments, erasure operations may be performed at the half-block level, at the quarter-block level, or at any suitable fractional level with any suitable number of blocks or blocks.

[0094] like Figure 4 As shown, the same layer of storage cells 112 of adjacent storage strings 111 in the same block 140 can be coupled through word lines 120. Word lines 120 are used to select which layer of storage cells 112 in the block 140 is affected by read and program operations.

[0095] In some embodiments, each word line 120 is coupled to the page to which the memory cell 112 belongs, and the page is the basic unit of data used for programming operations. The size of the page may be related to the number of memory strings 111 coupled by word lines 120 in a block 140. Each word line 120 may be coupled to the control gate (i.e., gate electrode) of each memory cell 112 in the corresponding page. It is understood that...

[0096] It should be noted that within a block of 140, storage units at the same level correspond to the same word line, but storage units at the same level can be divided into one or more pages. That is, a word line can couple to one or more pages. For example, for SLC, a word line couples to one page, and for MLC, a word line couples to two pages.

[0097] Figure 5 This is a cross-sectional schematic diagram of a storage array 110 including storage strings 111, provided in an embodiment of this application. Figure 5As shown, the storage string 111 may extend vertically over the substrate 101 and through the stacked layer 102. The substrate 101 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0098] The stacked layer 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in the stacked layer 102 can determine the number of memory cells 112 in the memory array 110.

[0099] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In other embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Furthermore, each gate conductive layer 103 may include a control gate surrounding the memory cell 112, and may extend laterally at the top of the stacked layer 102 as a DSG line 116, at the bottom of the stacked layer 102 as an SSG line 117, or between the DSG line 116 and the SSG line 117 as a word line 120.

[0100] like Figure 5 As shown, the memory string 111 includes a channel structure 105 extending vertically through the stacked layer 102. In some embodiments, the channel structure 105 includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). The semiconductor channel includes silicon, such as polycrystalline silicon. The memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer.

[0101] In some embodiments, the channel structure 105 has a cylindrical shape (e.g., a pillar shape). The layers in the semiconductor channel and the memory film are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order.

[0102] It should be understood that, despite Figure 5 As not shown, the memory array 110 may also include other additional components, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0103] Return to reference Figure 4The peripheral circuitry 130 can be coupled to the memory array 110 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116. The peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 110 by applying voltage and / or current signals to and sensing voltage and / or current signals from the memory cells 112 via bit line 115, word line 120, source line 118, SSG line 117, and DSG line 116.

[0104] Peripheral circuitry 130 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry 130 is shown, including a page buffer / sensor amplifier 131, a column decoder / bit line (BL) driver 132, a row decoder / word line (WL) driver 133, a voltage generator 134, a control logic unit 135, a register 136, an interface 137, and a data bus 138. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0105] Page buffer / sensor amplifier 131 can be configured to read data from memory array 110 and program (write) data to memory array 110 according to control signals from control logic unit 135. For example, page buffer / sensor amplifier 131 can store a page of programming data (write data) to be programmed into a page 130 of memory array 110. Page buffer / sensor amplifier 131 can also perform a verification operation to ensure that data has been correctly programmed into memory cell 112 coupled to selected word line 120. Page buffer / sensor amplifier 131 can also sense a low-power signal from bit line 115, which represents a data bit stored in memory cell 112, and amplify a small voltage swing to a recognizable logic level during read operations.

[0106] The column decoder / bit line driver 132 can be configured to be controlled by the control logic unit 135 and to select one or more memory strings 111 by applying a bit line voltage generated from the voltage generator 134.

[0107] The row decoder / word line driver 133 can be configured to be controlled by the control logic unit 135 and to select / deselect block 140 of the memory array 110 and to select / deselect word lines 120 of block 140. The row decoder / word line driver 133 can also be configured to drive word lines 120 using word line voltages (VWL) generated from a voltage generator 134. In some embodiments, the row decoder / word line driver 133 can also select / deselect and drive SSG lines 117 and DSG lines 116. As described in detail below, the row decoder / word line driver 133 is configured to perform erase operations on memory cells 112 coupled to one or more selected word lines 120.

[0108] Voltage generator 134 can be configured to be controlled by control logic unit 135 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 110.

[0109] The control logic unit 135 can be coupled to various circuits in the peripheral circuitry described above and is configured to control the operation of each circuit.

[0110] Register 136 can be coupled to control logic unit 135. The register may include a status register, a command register, and an address register to store status information, command opcodes (OP codes), and command addresses for controlling the operation of each circuit in the peripheral circuitry.

[0111] Interface (I / F) 137 can be coupled to control logic unit 135 and act as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 135, as well as to buffer status information received from control logic unit 135 and relay it to the host. Interface 137 can also be coupled to column decoder / bit line driver 132 via data bus 138 and act as a data I / O interface and data buffer to buffer data and relay it to or from memory array 110.

[0112] The above description of the memory-related hardware embodiments has similar beneficial effects to the method embodiments described below. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0113] by Figure 1 Taking the illustrated storage system as an example, the storage system includes one or more memories, and a memory controller coupled to the memories and configured to control the memories; the memories include a storage array coupled to n word lines, the n word lines being arranged in physical word line identification order, where n≥2.

[0114] In this embodiment, the memory controller is configured to acquire multiple copies of data to be written to the memory array, map n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to adjacent m virtual word line identifiers are spaced apart from each other, and 2≤m≤n; and the memory controller is configured to generate verification data based on the data corresponding to the adjacent m virtual word line identifiers, the verification data being used to verify and recover the data corresponding to the adjacent m virtual word line identifiers.

[0115] In some embodiments, the memory controller is configured to obtain a pre-set mapping table, which includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; and to match n physical word line identifiers with the mapping table to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0116] In some embodiments, the memory controller is configured to retrieve a pre-set mapping table from static random access memory.

[0117] In some embodiments, a reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

[0118] In some embodiments, the memory controller is configured to obtain a preset algorithm for mapping physical word line identifiers to virtual word line identifiers; and to substitute n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0119] In some embodiments, the memory controller is configured to process the data corresponding to adjacent m virtual word line identifiers using a first operator to obtain verification data. The verification data is used to verify and recover the failed data by using a second operator when there is a data read failure among the data corresponding to adjacent m virtual word line identifiers. The first operator and the second operator are operators with opposite operational logic.

[0120] In some embodiments, the memory controller is configured to send a first read instruction to the memory, the first read instruction including a first physical word line identifier corresponding to first data to be read; and receive a data read result returned by the memory;

[0121] The memory controller is configured to, when the data read result indicates that the first data read corresponding to the first physical word line identifier has failed, determine the first virtual word line identifier corresponding to the first physical word line identifier; and obtain the target verification data corresponding to the first virtual word line identifier to recover the first data that failed to be read.

[0122] In some embodiments, the memory controller is configured to acquire target verification data corresponding to a first virtual word line identifier, and acquire a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data; and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0123] The memory controller is configured to send a second read instruction to the memory, the second read instruction including a second physical word line identifier, the second read instruction being used to instruct the memory to read data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; receive second data returned by the memory corresponding to the second physical word line identifier, and recover the first data that failed to be read based on the target check data and the second data.

[0124] In some embodiments, the memory controller is configured to, when reading first data corresponding to a first physical word line identifier, determine a first virtual word line identifier corresponding to the first physical word line identifier, and obtain target verification data corresponding to the first virtual word line identifier; obtain a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data, and determine a second physical word line identifier corresponding to the second virtual word line identifier;

[0125] Send a read instruction to the memory. The read instruction is used to instruct the reading of data stored in the memory cell row coupled to the word line corresponding to the first physical word line identifier and the second physical word line identifier.

[0126] The memory controller is configured to receive the data read result returned by the memory; if the data read result indicates that the first data read failed, it calls the target check data and the second data corresponding to the second physical word line identifier to recover the first data that failed to be read.

[0127] Figure 7 This is a flowchart of an operation method of a storage system provided in an exemplary embodiment of this application. Taking the application of this method in a storage system as an example, such as... Figure 7 As shown, the method includes:

[0128] Step 701: Obtain multiple copies of data to be written to the storage array.

[0129] The multiple data sets are data to be written to the memory array. In some embodiments, the memory array includes n rows of memory cells, each of which is coupled to n word lines, where the i-th row of memory cells is coupled to the i-th word line, and i is a positive integer less than or equal to n. The multiple data sets are data to be written to the n rows of memory cells. The n word lines coupled to the n rows of memory cells are arranged in physical word line identifier order; that is, each of the n word lines corresponds to a physical word line identifier, used to uniquely indicate the word line according to its arrangement order.

[0130] In some embodiments, the memory controller in the storage system receives multiple copies of data to be written to the storage array; or, the memory controller periodically and actively acquires multiple copies of data to be written to the storage array.

[0131] In some embodiments, after acquiring multiple copies of data, the memory controller writes the multiple copies of data into the memory array based on the physical word line identifier.

[0132] Step 702: Write verification data to the memory. The verification data is generated based on the data corresponding to the physical word lines that are spaced apart from each other. The verification data is used to verify and recover the data.

[0133] The memory controller first determines the arrangement of multiple data entries written to the memory cell row, that is, the physical word line identifier corresponding to the memory cell row to which the data is written, such as: data a, data b, data c and data d. Among them, data a is written to the memory cell row coupled to word line 1, data b is written to the memory cell row coupled to word line 2, data c is written to the memory cell row coupled to word line 3, and data d is written to the memory cell row coupled to word line 4.

[0134] The memory controller generates check data based on the arrangement of multiple data entries written in the storage cell rows, and writes the check data to the memory. The check data is generated based on the data corresponding to the physical word line identifiers of the intervals. That is, taking the above data a, data b, data c and data d as an example, since there is a word line 2 between word line 1 and word line 3, and a word line 3 between word line 2 and word line 4, check data is generated based on data a and data c, while check data is generated based on data b and data d.

[0135] In some embodiments, when generating verification data based on the data corresponding to the physical word line identifiers based on the interval, n physical word line identifiers are first mapped to n virtual word line identifiers. The physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart, where 2 ≤ m ≤ n. Verification data is generated based on the data corresponding to the m adjacent virtual word line identifiers. This verification data is used to verify and recover the data corresponding to the m adjacent virtual word line identifiers. For illustration, m=2 is used as an example, meaning that verification data is generated based on the data corresponding to two adjacent virtual word line identifiers, and the physical word line identifiers corresponding to two adjacent virtual word line identifiers are spaced apart.

[0136] Optionally, the m virtual word line identifiers include adjacent first virtual word line identifiers and second virtual word line identifiers, wherein the first virtual word line identifier maps to a first physical word line identifier, the second virtual word line identifier maps to a second physical word line identifier, and at least one physical word line identifier is distributed between the first physical word line identifier and the second physical word line identifier.

[0137] In some embodiments, one physical word line identifier is distributed between the first physical word line identifier and the second physical word line identifier. That is, check data is generated for the data corresponding to the separated physical word lines by means of a physical word line interval. Alternatively, multiple physical word line identifiers are distributed between the first physical word line identifier and the second physical word line identifier, such as a reference number of physical word line identifiers distributed between the physical word line identifiers corresponding to each of the m adjacent virtual word line identifiers. That is, check data is generated for the data corresponding to the separated physical word lines by means of a multiple physical word line interval. Alternatively, the number of physical word line identifiers distributed between the first physical word line identifier and the second physical word line identifier is an uncertain number determined by an algorithm. That is, check data is generated for the data corresponding to the separated physical word lines by means of a one or more physical word line interval.

[0138] Schematic representation: When mapping between physical and virtual word line identifiers, at least one of the following methods is included:

[0139] First, obtain a pre-set mapping table, which includes the mapping relationship between physical word line identifiers and virtual word line identifiers; match n physical word line identifiers with the mapping table to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0140] In some embodiments, the mapping table is stored in static random-access memory (SRAM), in which case the pre-set mapping table is retrieved from the SRAM; or, the mapping table is stored in 3D NAND memory, in which case the memory controller retrieves the pre-set mapping table from the 3D NAND.

[0141] In some embodiments, the mapping table stores the correspondence between physical word line identifiers and virtual word line identifiers in the form of key-value pairs. For example, physical word line identifier 1 is stored as a key and the virtual word line identifier 1 corresponding to physical word line identifier 1 is stored as a value; physical word line identifier 2 is stored as a key and the virtual word line identifier 6 corresponding to physical word line identifier 1 is stored as a value. Figure 8 The diagram illustrates a mapping table provided in an exemplary embodiment of this application, as shown below. Figure 8As shown, virtual word line identifiers 810, numbered 1-5, correspond to physical word line identifiers 820, numbered 1 / 6 / 11 / 16 / 21 respectively, and the corresponding data 830 are Data1 / Data6 / Data11 / Data16 / Data21 respectively, generating parity data 840 as Parity1; virtual word line identifiers 810, numbered 6-10, correspond to physical word line identifiers 820, numbered 26 / 31 / 36 / 41 / 46 respectively, and the corresponding data 830 are Data26 / Data31 / Data36 / Data41 / Data46 respectively, generating parity data 840 as Parity2, and so on.

[0142] It is worth noting that the above mapping table uses an example where the physical word line identifiers corresponding to two adjacent virtual word line identifiers are spaced four physical word line identifiers apart. However, the above interval is only an illustrative example. In some embodiments, taking five word lines to generate one check data as an example, virtual word line identifiers 1-5 can also correspond to physical word line identifiers 1 / 3 / 5 / 7 / 9, virtual word line identifiers 6-10 can correspond to physical word line identifiers 2 / 4 / 6 / 8 / 10, and so on. That is, the physical word line identifiers corresponding to two adjacent virtual word line identifiers are spaced one physical word line identifier apart. The virtual character line identifiers can be: 1 / 4 / 7 / 10 / 13, 6 / 10, and 14, respectively; or, the virtual character line identifiers 1-5 can correspond to the physical character line identifiers 1 / 4 / 7 / 10 / 13, and vice versa. That is, there is a two-physical-line-line-identity interval between the physical character line identifiers corresponding to two adjacent virtual character line identifiers. Alternatively, while ensuring a one-to-one correspondence between virtual and physical character line identifiers, there can be any number of physical character line identifiers between the physical character line identifiers corresponding to two adjacent virtual character line identifiers. This application does not limit the number of intervals. In some embodiments, the number of intervals between the physical character line identifiers corresponding to different sets of adjacent virtual character line identifiers can be different.

[0143] Second, obtain a preset algorithm, which is used to map physical word line identifiers to virtual word line identifiers; substitute n physical word line identifiers into the preset algorithm to obtain n virtual word line identifiers corresponding to the n physical word line identifiers.

[0144] In some embodiments, a pre-stored preset algorithm is retrieved from SRAM.

[0145] Optionally, the preset algorithm includes a parameter substitution bit for the physical word line identifier. After substituting the physical word line identifier into this parameter substitution bit, the algorithm is processed by the preset algorithm to output the virtual word line identifier corresponding to the physical word line identifier.

[0146] To illustrate, taking 50 physical character line identifiers as an example, the physical character line identifiers are numbered 1-50 in sequence. The preset algorithm is as follows: when the physical character line identifier is odd, the virtual character line identifier is equal to the physical character line identifier; when the physical character line identifier is even, the virtual character line identifier is equal to 50 minus the value of the physical character line identifier.

[0147] It is worth noting that the above-described method for mapping between physical and virtual character line identifiers is merely an illustrative example, and the embodiments of this application do not limit it.

[0148] In some embodiments, generating verification data includes at least one of the following methods:

[0149] 1. The verification data is obtained by performing an XOR algorithm on the data corresponding to the m adjacent virtual character line identifiers.

[0150] In some embodiments, the check data can be generated using a parity check. For example, for any given set of data, the total number of bits that are 1 in the binary encoding is determined, and check data is generated to record the parity of this total number. This allows for subsequent verification of the read data based on the check data.

[0151] 2. The data corresponding to the m adjacent virtual word line identifiers is processed by the first operator to obtain the verification data. The verification data is used to verify and recover the failed data when there is a data reading failure in the data corresponding to the m adjacent virtual word line identifiers. The first operator and the second operator are operators with opposite operation logic.

[0152] Figure 9 This is a schematic diagram illustrating the verification data generation process provided in an exemplary embodiment of this application. For example... Figure 9 As shown, firstly, K pieces of data 900 to be written to the memory are acquired. Data 1 is written to physical word lines 1-5, data 2 to physical word lines 6-10, and so on, with data K written to physical word lines k-k+4. First, the physical word line identifiers are mapped to virtual word line identifiers via mapping 910. Physical word line identifiers 1-5 are mapped to virtual word line identifiers 1 / 6 / 11 / 16 / 21, and physical word line identifiers 6-10 are mapped to virtual word line identifiers 2 / 7 / 12 / 17 / 22. After mapping between the virtual and physical word line identifiers, data 920 for consecutive virtual word line identifiers is acquired. For example, data for virtual word line identifiers 1-5 is acquired and, through integration 930, checksum data 1 is obtained; data for virtual word line identifiers 6-10 is acquired and, through integration 930, checksum data 2 is obtained, and so on.

[0153] In some embodiments, a logic analyzer is used to perform sequential write operations on the memory, and it is observed whether the NAND write address sent by the memory controller on the logic analyzer is a non-sequential WL number. If it is a non-sequential WL number, it proves that the operation method of the storage system provided in the embodiments of this application is used.

[0154] In summary, the method provided in this application establishes a mapping relationship between physical word line identifiers and virtual word line identifiers to generate virtual word line identifiers corresponding to physical word line identifiers. This ensures that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Verification data is generated using data corresponding to multiple adjacent virtual word line identifiers, which in turn generates verification data using data corresponding to multiple non-adjacent physical word line identifiers. This reduces the impact of mutual influence between adjacent physical word lines on the verification data, improves the success rate of data recovery, and enhances the reliability of data storage and retrieval.

[0155] The method provided in this embodiment, by pre-setting a mapping relationship table, intuitively maps physical character line identifiers to virtual character line identifiers, thereby mapping physical character line identifiers to virtual character line identifiers through the mapping relationship table, which improves the efficiency of determining virtual character line identifiers.

[0156] The method provided in this embodiment matches physical character line identifiers with virtual character line identifiers using a pre-set algorithm, thereby mapping physical character line identifiers to virtual character line identifiers through a preset algorithm, which improves the efficiency of determining virtual character line identifiers.

[0157] In an optional embodiment, after generating and storing the verification data, the process of reading the stored data is further included. Figure 10 This is a flowchart of an operation method of a storage system provided in another exemplary embodiment of this application. The method is applied to, for example... Figure 1 In the storage system shown, and executed in such a way Figure 7 Taking step 702 as an example, the method includes:

[0158] Step 1001: Send a first read instruction to the memory. The first read instruction includes the first physical word line identifier corresponding to the first data to be read.

[0159] Since data is still accessed through physical word line identifiers from the memory's perspective, when reading data, a first read instruction with the first physical word line identifier is sent to the memory to read data from the memory cell row coupled to the word line corresponding to the first physical word line identifier.

[0160] In some embodiments, when the computer device where the storage system is located receives a data read operation, it sends a first read instruction to the memory through the memory controller to read the first data stored in the storage cell row coupled to the word line corresponding to the first physical word line identifier.

[0161] In some embodiments, the data reading process corresponding to the first read instruction includes at least one of the following:

[0162] The first method involves identifying the virtual character line identifier and obtaining verification data in the event of a data reading failure.

[0163] Step 1021: Receive the data read result returned by the memory.

[0164] Specifically, if the first data can be read normally, the data reading result includes the first data read from the storage cell row coupled to the word line corresponding to the first physical word line identifier. If the first data cannot be read normally, such as if the storage cell row coupled to the word line corresponding to the first physical word line identifier is damaged, the first data cannot be read correctly, and the data reading result includes an indication that the first data reading failed.

[0165] That is, the data reading result includes: 1. the data read; 2. an indication of reading failure, at least one of the above two items.

[0166] In some embodiments, the first read instruction is used to read a plurality of first physical word lines. The first data includes sub-data corresponding to the plurality of physical word lines respectively. The data read result may also include an indication of partial data read failure. In some embodiments, the data read result includes the first physical word line identifier corresponding to the data that was read failed, as well as other data that was read successfully.

[0167] Step 1031: If the data reading result indicates that the first data reading corresponding to the first physical word line identifier has failed, determine the first virtual word line identifier corresponding to the first physical word line identifier.

[0168] Optionally, when generating verification data, it is generated by mapping physical word line identifiers to virtual word line identifiers. Therefore, the first physical word line identifier is mapped using the same mapping method to determine the corresponding first virtual word line identifier. For example, when generating verification data, if the physical word line identifier is mapped to a virtual word line identifier using a mapping table, then in the event of a first data read failure, the first virtual word line identifier corresponding to the first physical word line identifier is determined using the mapping table. Alternatively, when generating verification data, if the physical word line identifier is mapped to a virtual word line identifier using a preset algorithm, then in the event of a first data read failure, the first virtual word line identifier corresponding to the first physical word line identifier is determined using the preset algorithm.

[0169] Step 1041: Obtain the target verification data corresponding to the first virtual character line identifier to recover the first data that failed to be read.

[0170] In some embodiments, target verification data corresponding to a first virtual word line identifier is read from a memory to verify the first data.

[0171] In some embodiments, target verification data corresponding to the first virtual character line identifier is obtained, and a second virtual character line identifier that is used in conjunction with the first virtual character line to generate the target verification data is obtained. Optionally, during the storage of verification data, the physical character line identifiers and virtual character line identifiers corresponding to the verification data and the data that generates the verification data are stored accordingly. Then, the second virtual character line identifier corresponding to the first virtual character line identifier in the target verification data is obtained, and the second physical character line identifier corresponding to the second virtual character line identifier is determined. Optionally, when generating verification data, if the physical character line identifier is mapped to the virtual character line identifier through mapping, then the second virtual character line identifier is mapped to the corresponding second physical character line identifier through inverse mapping. Illustratively, when generating verification data, if the physical character line identifier is mapped to the virtual character line identifier through a mapping relationship table, then the second virtual character line identifier is still mapped to the second physical character line identifier through the mapping relationship table. When generating verification data, if the physical character line identifier is mapped to the virtual character line identifier through a preset algorithm, then the corresponding second physical character line identifier is determined by substituting the second virtual character line identifier into the preset algorithm.

[0172] Send a second read instruction to the memory, the second read instruction including a second physical word line identifier, the second read instruction is used to instruct the memory to read the data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; receive the second data returned by the memory corresponding to the second physical word line identifier, and recover the first data that failed to be read based on the target check data and the second data.

[0173] Indicative, Figure 11 This is a schematic diagram illustrating the data verification and recovery process provided in an exemplary embodiment of this application, as shown below. Figure 11 As shown, when memory controller 1101 sends a read command to memory 1102, instructing it to read the data corresponding to physical word line identifiers 1-5, memory 1102 reports back to memory controller 1101 that the data read corresponding to physical word line identifier 5 failed. Therefore, memory controller 1101 first determines the virtual word line identifier 21 corresponding to physical word line identifier 5 through mapping 1110, and determines the check data n corresponding to virtual word line identifier 21 through check data lookup 1120. It then obtains other virtual word line identifiers p that make up the check data n through check data generation lookup 1130, and determines the physical word line identifier q corresponding to virtual word line identifier p through mapping 1140. Memory controller 1101 sends a read command to memory 1102, instructing it to read the data corresponding to physical word line identifier q. After memory 1102 reports back data q to memory controller 1101, memory controller 1101 performs verification and recovery on the data corresponding to physical word line identifier 5.

[0174] The second method involves pre-acquiring target verification data and second data, and then performing verification using the target verification data and second data when the first data reading fails.

[0175] Step 1022: Determine the first virtual character line identifier corresponding to the first physical character line identifier, and obtain the target verification data corresponding to the first virtual character line identifier.

[0176] In some embodiments, when generating verification data, a virtual word line identifier is mapped to a physical word line identifier through a mapping table. In the event of a first data reading failure, a first virtual word line identifier corresponding to the first physical word line identifier is determined through the mapping table. When generating verification data, a virtual word line identifier is mapped to a physical word line identifier through a preset algorithm. In the event of a first data reading failure, a first virtual word line identifier corresponding to the first physical word line identifier is determined through the preset algorithm.

[0177] Step 1032: Obtain the second virtual character identifier that is used in conjunction with the first virtual character identifier to generate the target verification data, and determine the second physical character identifier corresponding to the second virtual character identifier.

[0178] In some embodiments, target verification data corresponding to the first virtual word line identifier is obtained, and a second virtual word line identifier that is used in conjunction with the first virtual word line to generate the target verification data is obtained. Optionally, during the storage of verification data, the physical word line identifier and virtual word line identifier corresponding to the verification data and the data that generates the verification data are stored accordingly. Then, the second virtual word line identifier corresponding to the target verification data containing the first virtual word line identifier is obtained, and the second physical word line identifier corresponding to the second virtual word line identifier is determined. Optionally, when generating verification data, the physical word line identifier is mapped to the virtual word line identifier through mapping, and the second virtual word line identifier is mapped to the corresponding second physical word line identifier through inverse mapping.

[0179] Step 1042: Send a second read instruction to the memory, the second read instruction including a second physical word line identifier.

[0180] The second read instruction is used to instruct the memory to read the data stored in the row of memory cells coupled to the word line corresponding to the second physical word line identifier.

[0181] Step 1052: Receive the data read result returned by the memory.

[0182] Optionally, the data reading result includes the result of reading the storage cell row coupled to the word line corresponding to the first physical word line identifier, and the result of reading the storage cell row coupled to the word line corresponding to the second physical word line identifier.

[0183] In this embodiment of the application, in the case where the first data reading fails but the second data reading succeeds, the first data is verified and recovered.

[0184] Step 1062: If the data reading result indicates that the first data reading failed, the target verification data and the second data corresponding to the second physical word line identifier are called to recover the first data that failed to be read.

[0185] In summary, the method provided in this application establishes a mapping relationship between physical word line identifiers and virtual word line identifiers to generate virtual word line identifiers corresponding to physical word line identifiers. This ensures that the physical word line identifiers corresponding to adjacent virtual word line identifiers are spaced apart, i.e., not adjacent. Verification data is generated using data corresponding to multiple adjacent virtual word line identifiers, which in turn generates verification data using data corresponding to multiple non-adjacent physical word line identifiers. This reduces the impact of mutual influence between adjacent physical word lines on the verification data, improves the success rate of data recovery, and enhances the reliability of data storage and retrieval.

[0186] The method provided in this embodiment verifies and recovers data by verifying the data in the event of a data reading failure. On the one hand, it avoids the problem that adjacent word lines affect each other and the verification data cannot be used to verify and recover the data. On the other hand, it improves the security and accuracy of data storage.

[0187] Figure 12 This is a schematic diagram of the structure of a memory controller provided in an exemplary embodiment of this application. The memory system operation method provided in this embodiment is mainly implemented by the memory controller. Figure 12 As shown, the memory controller 1200 includes a memory interface 1210, a memory controller 1220, a configuration register 1230, and a bus interface 1240.

[0188] The memory interface 1210 is used to connect to the memory and convert the data exchange on the bus into data exchange that conforms to the storage timing of the storage medium.

[0189] The memory controller 1220 is used to control the functions of the entire memory controller, control the memory interface to correctly complete the data exchange between the memory and the internal bus of the microcontroller unit (MCU), and is responsible for the management of interrupt signals.

[0190] Configuration register 1230 is used to configure the functions of the memory controller, such as the timing configuration of the memory interface.

[0191] The bus interface 1240 is used to connect to the internal bus of the MCU, and is typically used for: 1. transmitting configuration information of the memory controller; 2. transmitting storage data that conforms to the memory controller interface.

[0192] In some embodiments, the memory controller 1200 includes at least two interfaces, wherein at least one of the at least two interfaces is used to communicate with the memory, and at least one front-end interface is used to communicate with the host.

[0193] This application provides a control circuit, which includes programmable logic circuits and / or program instructions. The control circuit can be used to implement the operation method of the storage system provided in the foregoing embodiments of this application.

[0194] This application provides a computer-readable storage medium storing instructions that, when executed on a memory controller, implement the operation method of the storage system provided in the foregoing embodiments of this application.

[0195] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0196] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0197] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A storage system, characterized in that, The storage system includes: one or more memories, and a memory controller coupled to the memories and configured to control the memories; the memories include a memory array coupled to n word lines, the n word lines being arranged in physical word line identifier order, where n≥2; The memory controller is configured to acquire multiple copies of data to be written to the memory array; The memory controller is configured to map n physical word line identifiers to n virtual word line identifiers, wherein the physical word line identifiers corresponding to adjacent m virtual word line identifiers are spaced apart from each other, and 2≤m≤n; The memory controller is configured to generate verification data based on the data corresponding to the adjacent m virtual word line identifiers, and the verification data is used to verify and recover the data corresponding to the adjacent m virtual word line identifiers.

2. The system according to claim 1, characterized in that, The memory controller is configured to acquire a pre-set mapping table, which includes a mapping correspondence between physical word line identifiers and virtual word line identifiers; and to match the n physical word line identifiers with the mapping table to acquire the n virtual word line identifiers corresponding to the n physical word line identifiers.

3. The system according to claim 2, characterized in that, The memory controller is configured to retrieve the pre-set mapping table from the static random access memory.

4. The system according to claim 1, characterized in that, A reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

5. The system according to claim 1, characterized in that, The memory controller is configured to acquire a preset algorithm, which is used to map physical word line identifiers to virtual word line identifiers; Substitute the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

6. The system according to claim 1, characterized in that, The memory controller is configured to process the data corresponding to the adjacent m virtual word line identifiers using a first operator to obtain the verification data. The verification data is used to verify and recover the failed data by using a second operator when there is a data read failure in the data corresponding to the adjacent m virtual word line identifiers. The first operator and the second operator are operators with opposite operation logic.

7. The system according to any one of claims 1 to 6, characterized in that, The memory controller is configured to send a first read instruction to the memory, the first read instruction including a first physical word line identifier corresponding to the first data to be read; and receive the data read result returned by the memory; The memory controller is configured to determine a first virtual word line identifier corresponding to the first physical word line identifier when the data read result indicates that the first data read corresponding to the first physical word line identifier has failed. Obtain the target verification data corresponding to the first virtual character line identifier to recover the first data that failed to be read.

8. The system according to claim 7, characterized in that, The memory controller is configured to acquire the target verification data corresponding to the first virtual word line identifier, and acquire a second virtual word line identifier that is used in conjunction with the first virtual word line identifier to generate the target verification data; Determine the second physical word line identifier corresponding to the second virtual word line identifier; The memory controller is configured to send a second read instruction to the memory, the second read instruction including a second physical word line identifier, the second read instruction being used to instruct the memory to read data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; receive second data returned by the memory corresponding to the second physical word line identifier, and recover the first data that failed to be read based on the target check data and the second data.

9. The system according to any one of claims 1 to 6, characterized in that, The memory controller is configured to, when reading the first data corresponding to the first physical word line identifier, determine the first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; Obtain a second virtual word line identifier that is paired with the first virtual word line identifier to generate the target verification data, and determine the second physical word line identifier corresponding to the second virtual word line identifier; Send a read instruction to the memory, the read instruction being used to instruct the reading of data stored in the memory cell row coupled to the word line corresponding to the first physical word line identifier and the second physical word line identifier; The memory controller is configured to receive the data read result returned by the memory; if the data read result indicates that the first data read failed, it calls the target verification data and the second data corresponding to the second physical word line identifier to recover the first data that failed to be read.

10. A method for operating a storage system, characterized in that, The storage system includes a memory with a storage array coupled to n word lines, the n word lines being arranged in physical word line identification order, where n≥2; The method includes: Acquire multiple copies of data to be written to the storage array; Map n physical word line identifiers to n virtual word line identifiers, where the physical word line identifiers corresponding to the m adjacent virtual word line identifiers are spaced apart from each other, and 2≤m≤n; Verification data is generated based on the data corresponding to the m adjacent virtual character line identifiers. The verification data is used to verify and recover the data corresponding to the m adjacent virtual character line identifiers. The verification data is written to the memory.

11. The method according to claim 10, characterized in that, The process of mapping n physical word line identifiers to n virtual word line identifiers includes: Obtain a pre-set mapping table, which includes the mapping correspondence between physical word line identifiers and virtual word line identifiers; Match the n physical word line identifiers with the mapping table to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

12. The method according to claim 11, characterized in that, The step of obtaining the pre-set mapping table includes: Retrieve the pre-set mapping table from the static random access memory.

13. The method according to claim 10, characterized in that, A reference number of physical word line identifiers are distributed between the physical word line identifiers corresponding to the adjacent m virtual word line identifiers.

14. The method according to claim 10, characterized in that, The process of mapping n physical word line identifiers to n virtual word line identifiers includes: A preset algorithm is obtained, which is used to map physical character line identifiers to virtual character line identifiers; Substitute the n physical word line identifiers into the preset algorithm to obtain the n virtual word line identifiers corresponding to the n physical word line identifiers.

15. The method according to claim 10, characterized in that, The step of generating verification data based on the data corresponding to the m adjacent virtual character line identifiers includes: The first operator processes the data corresponding to the m adjacent virtual word line identifiers to obtain the verification data. The verification data is used to verify and recover the failed data when there is a data reading failure in the data corresponding to the m adjacent virtual word line identifiers, by means of a second operator. The first operator and the second operator are operators with opposite operation logic.

16. The method according to any one of claims 10 to 15, characterized in that, After writing the verification data to the memory, the method further includes: Send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read; Receive the data read result returned by the memory; If the data reading result indicates that the first data reading corresponding to the first physical word line identifier has failed, a first virtual word line identifier corresponding to the first physical word line identifier is determined; Obtain the target verification data corresponding to the first virtual character line identifier to recover the first data that failed to be read.

17. The method according to claim 16, characterized in that, The step of obtaining the target verification data corresponding to the first virtual character identifier to recover the first data that failed to be read includes: Obtain the target verification data corresponding to the first virtual character line identifier, and obtain the second virtual character line identifier that is used in conjunction with the first virtual character line identifier to generate the target verification data; Determine the second physical word line identifier corresponding to the second virtual word line identifier; Send a second read instruction to the memory, the second read instruction including the second physical word line identifier, the second read instruction being used to instruct the memory to read the data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; The system receives the second data returned by the memory, which corresponds to the second physical word line identifier, and recovers the first data that failed to be read based on the target verification data and the second data.

18. The method according to any one of claims 10 to 15, characterized in that, After generating the verification data based on the data corresponding to the adjacent m virtual character line identifiers, the method further includes: Send a first read instruction to the memory, wherein the first read instruction includes a first physical word line identifier corresponding to the first data to be read; Determine the first virtual word line identifier corresponding to the first physical word line identifier, and obtain the target verification data corresponding to the first virtual word line identifier; Obtain a second virtual word line identifier that is paired with the first virtual word line identifier to generate the target verification data, and determine the second physical word line identifier corresponding to the second virtual word line identifier; Send a second read instruction to the memory, the second read instruction including the second physical word line identifier, the second read instruction being used to instruct the memory to read the data stored in the memory cell row coupled to the word line corresponding to the second physical word line identifier; Receive the data read result returned by the memory; If the data reading result indicates that the first data reading failed, the first data that failed to be read is recovered by calling the target verification data and the second data corresponding to the second physical word line identifier.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a memory controller, implement the operation method of the storage system as described in any one of claims 1 to 9.

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