On-chip automation of clock-to-Q access time measurements for memory devices

Abstract

An integrated circuit (IC) may include a memory device and circuitry coupled with the memory device. The circuitry may pre-process the memory device to maintain oscillations, initiate a first oscillation in a first loop including the memory device, and initiate a second oscillation in a second loop not including the memory device.

Description

[0001] Inventor: T.B. Chadwick Jr.

[0002] Related Applications

[0003] This application claims the benefit of U.S. Provisional Application Serial No. 63 / 335,483, filed on April 27, 2022, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0004] The present disclosure relates to integrated circuits (ICs). More particularly, the present disclosure relates to on-chip automation of clock-to-Q access time measurements of memory devices. Background Art

[0005] A computer system may store information in a memory device. The performance of a computer system may depend on the access time of the memory device, for example, the amount of time used to write to and / or read from the memory device. Accurately measuring the access time of the memory device is very important. Summary of the invention

[0006] An integrated circuit (IC) may include a memory device and a circuit coupled to the memory device. The circuit may precondition the memory device to maintain oscillation, initiate a first oscillation in a first loop including the memory device, and initiate a second oscillation in a second loop not including the memory device.

[0007] In some embodiments described herein, the circuit may include a set of multiplexers, wherein a set of outputs of the set of multiplexers may be coupled to a set of inputs of a memory device. The circuit may include a finite state machine (FSM) that provides a set of selection signals to the set of multiplexers, wherein the memory device and the FSM are clocked using a clock signal.

[0008] In some embodiments described herein, the FSM may include a first state in which the FSM writes a first value to a first memory address, wherein the FSM transitions from an idle state to the first state when an enable signal is asserted. The FSM may include a second state in which the FSM writes a second value to a second memory address, wherein the second value is the complement of the first value (e.g., the first value may be a logical 0 and the second value may be a logical 1), and wherein the FSM transitions from the first state to the second state after one clock cycle of a clock signal.

[0009] In some embodiments described herein, the FSM may include a third state in which the FSM reads the first value from the first memory address, wherein the FSM transitions from the second state to the third state after one clock cycle of the clock signal.

[0010] In some embodiments described herein, the FSM may include a fourth state in which the FSM reads a second value from a second memory address, wherein the FSM transitions from the third state to the fourth state after one clock cycle of the clock signal.

[0011] In some embodiments described herein, the FSM may include a fifth state, in which the FSM provides an oscillating signal to a clock input of the memory device, wherein the oscillating signal corresponds to the first oscillation or the second oscillation, and wherein the FSM transitions from the fourth state to the fifth state after one clock cycle of the clock signal.

[0012] In some embodiments described herein, the FSM may transition from the fifth state to the idle state when the enable signal is deasserted.

[0013] In some embodiments described herein, the circuit may initiate the first oscillation or the second oscillation based on the calibration signal.

[0014] In some embodiments described herein, the circuit may include a clock divider, wherein an oscillation signal corresponding to the first oscillation or the second oscillation may be provided as an input to the clock divider, and wherein an output of the clock divider may be provided as an output of the circuit.

[0015] In some embodiments described herein, a first cycle time of a first oscillation may be measured. A second cycle time of a second oscillation may be measured. A clock-to-Q access time of a memory device may be calculated based on the first cycle time and the second cycle time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure can be understood from the detailed description and accompanying drawings given below. These drawings are for illustrative purposes and do not limit the scope of the present disclosure. In addition, these drawings are not necessarily drawn to scale.

[0017] Figure 1 The McLeod loop is shown.

[0018] Figure 2 The waveform generated by the MacLeod loop is shown.

[0019] Figure 3 A MacLeod loop with a calibration circuit is shown.

[0020] Figure 4 An IC including a MacLeod loop and calibration circuitry and a memory device according to some embodiments described herein is illustrated.

[0021] Figure 5An implementation of a MacLeod loop and calibration circuitry according to some embodiments described herein is illustrated.

[0022] Figure 6 A state transition diagram is illustrated according to some embodiments described herein.

[0023] Figure 7 A process for preconditioning a memory device using on-chip circuitry and performing MacLeod loop oscillation according to some embodiments described herein is illustrated.

[0024] Figure 8 An example flow of design, verification, and fabrication of an integrated circuit according to some embodiments described herein is illustrated.

[0025] Fig. 9 An example machine of a computer system is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. DETAILED DESCRIPTION

[0026] Various aspects of the present disclosure relate to on-chip automation of clock-to-Q access time measurements of memory devices. A technique called a "McLeod loop" can be used to measure the clock-to-Q access time of synchronous memory devices. The term "clock-to-Q" refers to the duration between a clock transition in a clock signal provided to a memory device and data available at a data pin of the memory device.

[0027] These measurements may require proper preconditioning of the memory device via writes and reads to achieve free-running oscillations. The preconditioning requirements of the memory device under test can vary from device to device and can be difficult to properly configure, set up, and execute via the chip pins driven by the tester.

[0028] Some embodiments described herein provide a technique for measuring the clock-to-Q access time of a synchronous memory device that can be controlled by a tester via two low-frequency signals (e.g., a "Calibrate" signal and an "Enable" signal). Specifically, in response to the assertion of the "Enable" signal, the on-chip logic in some embodiments described herein can configure the memory device under test and other MacLeod loop-specific on-chip logic for a certain number of cycles, resulting in free-running oscillations.

[0029] The technical advantages of the embodiments described herein include, but are not limited to: (1) eliminating the complexity of setting up and triggering the McLeod loop oscillation from the tester itself, and (2) providing on-chip logic for setting up and triggering the McLeod loop oscillation with little interference to the normal operation of the memory device and with low logic overhead.

[0030] Figure 1 A MacLeod loop is illustrated. The MacLeod loop utilizes an inverted address-to-Q path through a synchronous memory device to generate a clock pulse and a new address each time the Q output of the memory device switches. The result is a free-running oscillation that can be buffered to a chip output pin where its frequency can be measured by an off-chip tester. A circuit 100 implementing a MacLeod loop may include a memory device 102, an AND gate 104, a delay element 106, and an exclusive NOR gate 108. To simplify the illustration, the additional inputs to the memory are shown in FIG. Figure 1 Not shown are additional address input pins, such as read / write control signals, data inputs, and so on.

[0031] The MacLeod loop may operate as follows. Assume that the memory has been previously written so that when the memory is read with input A[j] of logic 0, the memory output Q[i] will output logic 1, and when the memory is read with input A[j] of logic 1, the memory output Q[i] will output logic 0. To establish an initial steady state, the ENABLE signal may be externally held at logic 0. Via the previous read, the output Q[i] of the memory device 102 is at logic 1. Therefore, the output of the AND gate 104 is logic 0, the output of the delay element 106 is logic 0, the output of the XOR gate 108 is logic 0, the input CLK of the memory device 102 is logic 0, and the input A[j] of the memory device 102 is logic 1.

[0032] Now, if the ENABLE signal is asserted to logic 1, the output of AND gate 104 will transition to logic 1. The output of delay element 106 will transition to logic 1; the output of XOR gate 108 will transition to logic 1, and the CLK input of memory device 102 will transition to 1. The rising edge of the CLK input will trigger a read of memory device 102, and after the clock-to-Q delay inherent to memory device 102, output Q[i] will transition to logic 0, as will memory input A[j]. As the output of delay element 106 remains at logic 1, the output of XOR gate 108 will transition to logic 0. After a period of time, the output of delay element 106 will transition to logic 0, causing the output of XOR gate 108 to transition to logic 1, as will the input CLK of memory device 102. This rising edge of the CLK input will trigger another read of memory device 102. Thereafter, the loop may enter into a continuous oscillation of the CLK, A[j], and Q[i] pins of memory device 102 as long as ENABLE remains at logic 1.

[0033] Figure 2The waveform generated by the MacLeod loop is illustrated. The ENABLE signal (shown as "ENABLE"), the output of AND gate 104 (shown as "AND_OUT"), the output of delay element 106 (shown as "DELAY_OUT"), the output of XNOR gate 108 (shown as "XNOR_OUT") (which is also the clock input of memory device 102), the Q0 output of memory device 102 (shown as "MEM_Q0"), and the address A0 of memory device 102 (shown as "MEM_A0") are shown. After time T1, the continued oscillation of the CLK, A[j], and Q[i] pins of memory device 102 is shown. The arrows illustrate the cause-effect relationship between different signal transitions. For example, at time T1, a transition of AND_OUT causes a corresponding transition of DELAY_OUT, which causes a corresponding transition of XNOR_OUT, and so on.

[0034] The oscillation at the CLK pin of the memory device 102 can be buffered to an off-chip pin where its cycle time can be measured by an off-chip tester. The cycle time of the oscillation can be equal to the sum of the delays through the memory device 102, AND gate 104, delay element 106, and XOR gate 108. However, the goal is to measure the clock-to-Q delay of the memory device 102, which is only a portion of the cycle time of the oscillation. To extract the clock-to-Q delay of the memory device 102, the Figure 1 The circuit shown, Figure 3 shown.

[0035] Figure 3 A MacLeod loop with calibration circuitry is illustrated. The MacLeod loop in circuit 300 may include a memory device 302, an AND gate 304, a delay element 306, and an XNOR gate 308. The calibration logic in circuit 300 may include a CALIBRATE signal, an inverter 310, an AND gate 312, and a multiplexer 314. The CALIBRATE signal may be provided to a select input of multiplexer 314 such that when CALIBRATE is at a logic 0, the output Q[i] of memory device 302 is output by multiplexer 314, and when CALIBRATE is at a logic 1, the CLK input signal of memory device 302 (which is the output of XNOR gate 308) is output by multiplexer 314.

[0036] If CALIBRATE is held at logic 0, the operation of circuit 300 may be similar to Figure 1The operation of the circuit 100 shown is the same. However, the loop delay may be slightly different because the circuit 300 includes a multiplexer 314 in the loop. Therefore, the cycle time of the oscillation in the circuit 300 may be equal to the sum of the delays through the memory device 302, the AND gate 304, the delay element 306, the XOR gate 308, and the multiplexer 314.

[0037] If CALIBRATE remains at logic 1, the operation of circuit 300 can be similar to Figure 1 304, 306, 308 and multiplexer 314. When CALIBRATE is maintained at a static value, the outputs of inverter 310 and AND gate 312 also remain static. Therefore, these circuit elements do not contribute to the propagation delay of the loop. The cycle time of the oscillating loop (as measured off-chip) can be twice the sum of the delays of the circuit elements AND gate 304, delay element 306, XOR gate 308 and multiplexer 314.

[0038] Therefore, by measuring the cycle time of two different oscillations generated when CALIBRATE is held at logic 0 and when CALIBRATE is held at logic 1, the clock to Q access time of the memory device 302 can be calculated using the following expression: t_acc = t_cyc0-t_cyc1 / 2, where t_acc is the access time, t_cyc0 is the cycle time of the oscillation measured when CALIBRATE is held at logic 0, and t_cyc1 is the cycle time of the oscillation measured when CALIBRATE is held at logic 1.

[0039] An off-chip tester may be used to test different memory devices, where each memory device may use a different process to initiate oscillation and measure the clock to Q access time. Thus, in these approaches, the off-chip tester may implement complex logic that is difficult to debug and maintain.

[0040] Figure 4 An IC including a MacLeod loop and calibration circuitry and a memory device according to some embodiments described herein is illustrated.

[0041] The memory device 402 and the MacLeod loop and calibration circuitry 404 may be implemented on the same IC chip. The MacLeod loop and calibration circuitry 404 may receive a signal 406 from an external source (e.g., a tester). The MacLeod loop and calibration circuitry 404 may precondition the memory device 402 and initiate an oscillation that, when measured, may be used to determine the clock-to-Q access time of the memory device 402. Embodiments described herein may use the MacLeod loop and calibration circuitry 404 to mitigate the complexity of an off-chip tester process to precondition a memory device to initiate oscillations in a MacLeod loop.

[0042] Signal CLK may be a clock signal that may be provided to memory device 402 and may be used to time read and write requests. Signal CE may be a chip enable signal that may allow the system to select memory device 402. Signal WE may be a write enable signal that may indicate to memory device 402 that a write operation is being performed. Signal D[i] may contain data bits to be written to memory device 402 during a write operation. Address signal set A[m:0] may specify a memory address corresponding to a read or write operation. Signal Q[i] may be a data bit read from memory device 402 that corresponds to memory address A[m:0] provided to memory device 402 as input.

[0043] In some embodiments described herein, signal 406 may include signals A0[m:0], A1[m:0], ENABLE, and CALIBRATE. Address signal set A0[m:0] and A1[m:0] may be used to precondition memory device 402. The ENABLE signal may be used to instruct MacLeod loop and calibration circuitry 404 to precondition memory device 402 and initiate oscillation. The CALIBRATE signal may be used to instruct MacLeod loop and calibration circuitry 404 to include (or not include) memory device 402 in an oscillation loop. In embodiments described herein, complex operations for preconditioning memory devices and initiating oscillation may be performed by MacLeod loop and calibration circuitry 404 as part of an IC that includes memory device 402.

[0044] Figure 5 An implementation of a MacLeod loop and calibration circuitry according to some embodiments described herein is illustrated.

[0045] The inputs CLK, CE, WE, D[i], and A[m:0] to the memory device 502 may be multiplexed between a signal 506 (which may be received from an external source such as a tester) and corresponding signals generated by the MacLeod loop and calibration circuitry 504. The embodiments described herein may use write and read operations to precondition the memory device 502 and then initiate oscillations in the MacLeod loop. Specifically, a finite state machine (FSM) 508 may execute a cycle-by-cycle sequence of events for preconditioning the memory device 502 and initiating MacLeod loop oscillations. The FSM 508 may receive a clock signal MEMCLKIN, which may be used by the FSM 508 to transition between different states (the connection from MEMCLKIN to the FSM 508 is in Figure 5 not shown).

[0046] The circuit system 514 may correspond to Figure 3 The circuit system shown includes AND gate 304, delay element 306, XOR gate 308, inverter 310 and AND gate 312. Multiplexer 518 may correspond to Figure 3 Multiplexer 518 may receive the MEMCLKOUT signal at the bottom input and the MEMQIN signal (which is the Q[i] output of memory device 502) at the top input. The operation of circuit system 514 and multiplexer 518 may correspond to Figure 3 Operation of the circuit system shown. Specifically, when the CALIBRATE signal (which can be provided to the multiplexer 518 as a select signal) is maintained at a logic 0, an oscillation loop passing through the memory device 502 can be created (e.g., by selecting the top input of the multiplexer 518 as the output), and when the CALIBRATE signal is maintained at a logic 1, an oscillation loop bypassing the memory device 502 can be created (e.g., by selecting the bottom input of the multiplexer 518 as the output). The cycle time of the oscillation loop can be twice the sum of the delays through the circuit elements. The clock to Q access time of the memory device 502 can be calculated using the following expression: t_acc = t_cyc0-t_cyc1 / 2, where t_acc is the access time, t_cyc0 is the cycle time of the oscillation measured when CALIBRATE is maintained at a logic 0, and t_cyc1 is the cycle time of the oscillation measured when CALIBRATE is maintained at a logic 1.

[0047] The FSM 508 can provide a select input signal to the multiplexers 510 and 516, which can enable the FSM 508 to control the input provided to the memory device 502. Specifically, the FSM 508 can precondition the memory device 502 and initiate oscillation based on the ENABLE signal. The clock divider 512 can generate a divided version of the oscillation signal. The output of the clock divider 512 can be used to calculate the clock to Q access time of the memory device 502.

[0048] Signal 506 may include signals MEMCLKIN (which may be a clock signal), MEMCEIN (which may be a chip enable signal), MEMEWEIN (which may be a write enable signal), MEMDIN (which may be a data bit), and MEMAIN[m:0] (which may be a memory address). Signal 506 may also include signals A0[m:0] (which may be a first address for pre-processing memory device 502), A1[m:0] (which may be a second address for pre-processing memory device 502), CALIBRATE (which may be a write enable signal), MEMDIN (which may be a data bit), and MEMAIN[m:0] (which may be a memory address). Figure 5 ”, which may specify the oscillation loop to be activated) and ENABLE (which may be used to instruct the MacLeod loop and calibration circuitry 504 to precondition and initiate oscillation).

[0049] FSM 508 can generate signals corresponding to signals MEMCLKIN, MEMCEIN, MEMEWEIN, and MEMDIN. In addition, FSM 508 can generate select signals that multiplex between signals MEMCLKIN, MEMCEIN, MEMEWEIN, and MEMDIN and corresponding signals generated by FSM 508. Specifically, some multiplexers in multiplexer 510 can be used for this purpose. The multiplexed output signals are shown as MEMCLKOUT, MEMCEOUT, MEMWEOUT, and MEMDOUT, which can be provided to the CLK, CE, WE, and D[i] pins of memory device 502.

[0050] Signal MEMAIN[m:0] may be multiplexed with signals A0[m:0] and A1[m:0], and the output (shown as MEMAOUT) may be provided to address port A[m:0] of memory device 502. The select signal for the multiplexer may be generated by FSM 508. Specifically, the FSM may select between A0[m:0] and A1[m:0] using multiplexer 522, and then select between MEMAIN[m:0] and the output of multiplexer 522 using multiplexer 524. The output of multiplexer 520 may be provided to multiplexer 522 as the select signal. The FSM 508 may precondition the memory device 502 using multiplexers 520, 522, and 524 by writing a first logic value (e.g., “0”) to a first memory address (e.g., memory address A0[m:0]) and a second logic value (e.g., “1”) to a second memory address (e.g., memory address A1[m:0]). To initiate oscillation, the FSM 508 may provide a select signal to the multiplexer 520 such that the top input of the multiplexer 520 is connected to the output of the multiplexer 520. In this state, the output of the multiplexer 520 (which is the select signal of the multiplexer 522) may cause the multiplexer 522 to switch between A0[m:0] and A1[m:0] in consecutive cycles, which may sustain the oscillation in the loop.

[0051] Figure 6 A state transition diagram 600 is illustrated according to some embodiments described herein. The state transition diagram 600 may be implemented by the FSM 508 .

[0052] State 0 may be an initial default state. This initial default state may be entered when ENABLE is at logic 0. Figure 6 In FIG. 5 , the symbol “ / ENABLE” indicates that the ENABLE signal is at logic 0, and the symbol “ENABLE” indicates that the ENABLE signal is at logic 1. In this state, FSM 508 can control the select inputs of multiplexers 510 and 516 so that the off-chip tester ( Figure 5 ) controls the memory device and the McLeod loop does not work.

[0053] When ENABLE transitions to high, i.e., ENABLE is asserted, State 1 may be entered. The FSM 508 may remain in State 1 for 1 clock cycle before unconditionally transitioning to State 2. In State 1, the FSM 508 may use the multiplexer 510 to provide appropriate signals to the input pins CE, WE, D[i], and A[m:0] of the memory device 502 so that appropriate data is written to the address A0[m:0] of the memory device 502. Specifically, CE may be asserted (which may cause the memory device 502 to be selected) and WE may be asserted (which may cause the memory device to write data to a specified memory location). In addition, D[i] may be provided with a logic-zero value and A[m:0] may be provided with the address A0[m:0], which may cause the memory device 502 to write a logic-zero value at the address A0[m:0].

[0054] In the cycle following state 1, state 2 may be entered. FSM 508 may stay in this state 2 for 1 clock cycle before unconditionally moving to state 3. In state 2, FSM 508 may use multiplexer 510 to provide appropriate signals to input pins CE, WE, D[i], and A[m:0] of memory device 502 so that appropriate data is written to address A1[m:0] of memory device 502. Specifically, CE may be asserted (which may cause memory device 502 to be selected) and WE may be asserted (which may cause the memory device to write data to a specified memory location). In addition, D[i] may be provided with a logic 1 value and A[m:0] may be provided with address A1[m:0], which may cause memory device 502 to write a logic 1 value at address A1[m:0].

[0055] In the cycle following state 2, state 3 may be entered. FSM 508 may remain in this state 3 for 1 clock cycle before unconditionally moving to state 4. In state 3, FSM 508 may use multiplexer 510 to provide appropriate signals to input pins CE, WE, D[i], and A[m:0] of memory device 502 so that memory device 502 performs a read of address A0[m:0]. Specifically, CE may be asserted (which may cause memory device 502 to be selected) and WE may be deasserted (which may cause the memory device to read data from the specified memory location). In addition, A[m:0] may be provided with address A0[m:0], which may cause memory device 502 to read the value from address A0[m:0] (e.g., a logical 0 if this was the value written to that address in state 1) and output that value at the Q[i] output pin.

[0056] In the cycle following state 3, state 4 may be entered. FSM 508 may stay in this state 4 for 1 clock cycle before unconditionally moving to state 5. In state 4, FSM 508 may use multiplexer 510 to provide appropriate signals to input pins CE, WE, D[i], and A[m:0] of memory device 502 so that memory device 502 performs a read of address A1[m:0]. Specifically, CE may be asserted (which may cause memory device 502 to be selected) and WE may be deasserted (which may cause the memory device to read data from the specified memory location). In addition, A[m:0] may be provided with address A1[m:0], which may cause memory device 502 to read the value from address A1[m:0] (e.g., a logical 1 if this is the value written to that address in state 2) and output that value at the Q[i] output pin.

[0057] In the cycle following state 4, state 5 may be entered. FSM 508 may stay in this state for 1 clock cycle before unconditionally moving to state 6. In state 5, FSM 508 may change the value of the select input of multiplexer 516 so that the off-chip tester ( Figure 5 502. Instead, the MacLeod loop logic controls the CLK input to the memory device 502. Specifically, by using multiplexer 516, the output of circuit system 514 can be provided to the memory device 502 as the CLK input.

[0058] In the cycle following state 5, state 6 may be entered. FSM 508 may remain in this state until the ENABLE signal is deasserted to logic 0. In state 6, FSM 508 may assert the input of the AND gate, which feeds the delay element in circuit system 514 to a logic 1 value, which may enable the MacLeod loop oscillation to begin. An off-chip tester may use the CALIBRATE signal to select whether the oscillation loop includes memory device 502 (as shown in FIG. 1 ). Figure 3 described above).

[0059] An oscillating signal is observed at the output of circuit system 514 (eg Figure 5 The clock divider 512 can be used to reduce the clock frequency of the oscillation signal. The output of the clock divider 512 (in Figure 5 ”) may be provided as an output signal of the MacLeod loop and calibration circuitry 504. The oscillation signal CALCKIN or the output signal DIVCLKOUT may be used to measure the cycle time of two oscillations and calculate the clock to Q access time.

[0060] Some embodiments described herein feature an IC that can include a memory device (e.g., memory device 502) and circuitry coupled to the memory device (e.g., MacLeod loop and calibration circuitry 504). The circuitry can precondition the memory device to maintain oscillation, initiate a first oscillation in a first loop that includes the memory device, and initiate a second oscillation in a second loop that does not include the memory device.

[0061] In some embodiments described herein, the circuit may include a set of multiplexers (e.g., multiplexers 510, 516, and 518), wherein a set of outputs of the set of multiplexers may be coupled to a set of inputs of a memory device. The circuit may include a FSM (e.g., FSM 508) that provides a set of select signals to the set of multiplexers, wherein the memory device and the FSM are clocked using a clock signal.

[0062] In some embodiments described herein, the circuit can be based on a calibration signal (e.g., Figure 5 In some embodiments described herein, the circuit may include a clock divider (e.g., clock divider 512), wherein an oscillation signal corresponding to the first oscillation or the second oscillation (e.g., signal “CALCKIN”) may be provided as an input to the clock divider, and a clock divider output (e.g., “DIVCLKOUT”) may be provided as an output of the circuit.

[0063] In some embodiments described herein, a first cycle time of a first oscillation may be measured. A second cycle time of a second oscillation may be measured. A clock-to-Q access time of a memory device may be calculated based on the first cycle time and the second cycle time.

[0064] Figure 7 A process for preconditioning a memory device using on-chip circuitry and performing MacLeod loop oscillation according to some embodiments described herein is illustrated.

[0065] An enable signal may be received at an IC including a circuit and a memory device (at 702). Next, the circuit may write data to at least two memory addresses in the memory device (at 704). The circuit may initiate a first oscillation in a first loop including the memory device (at 706). A first signal corresponding to the first oscillation may be provided (at 706). A first cycle time of the first oscillation may be measured based on the first signal corresponding to the first oscillation (e.g., by an on-chip or off-chip measurement device). The circuit may initiate a second oscillation in a second loop not including the memory device (at 710). A second signal corresponding to the second oscillation may be provided (at 712). A second cycle time of the second oscillation may be measured based on the second signal corresponding to the second oscillation (e.g., by an on-chip or off-chip measurement device). A clock-to-Q access time of the memory device may be calculated based on the first cycle time and the second cycle time.

[0066] Figure 8 An example flow 800 for design, verification, and fabrication of integrated circuits according to some embodiments described herein is illustrated. EDA processes 812 (the abbreviation "EDA" refers to "electronic design automation") can be used to transform and verify design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations.

[0067] Flow 800 may begin with creating a product idea 810 using information provided by a designer, which is transformed and verified using an EDA process 812. When the design is finalized, the design is taped out 834, which is when the artwork (e.g., geometric pattern) for the integrated circuit is sent to a manufacturing facility to make a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die 836 is manufactured, and packaging and assembly 838 is performed to produce a manufactured IC chip 840.

[0068] The specification of a circuit or electronic structure can range from low-level transistor material layout to a high-level description language. High-level representations can be used to design circuits and systems using hardware description languages ​​("HDLs") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level ("RTL") description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation as a more specific description adds more detail to the design description. The lower-level representations as more specific descriptions can be computer-generated, derived from a design library, or created by another design automation process. SPICE (which stands for "Simulation Program for Emphasized Integrated Circuits") is an example of a lower-level specification language for specifying a more detailed description of the representation language. The description of each representation level contains enough detail for the corresponding tools (e.g., formal verification tools) at that level to use.

[0069] During system design 814, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. The design may be divided into different types of modules or components at this stage.

[0070] During logic design and functional verification 816, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of the specifications is checked. For example, the components of a circuit can be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0071] During synthesis and design for testing 818, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph structure represent components of the circuit, and the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0072] During netlist verification 820, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 822, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0073] During layout or physical implementation 824, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components through multiple conductors) occur, and selection of cells from the library to enable specific logic functions can be performed. As used herein, the term "cell" can specify a group of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (such as flip-flops or latches). As used herein, a circuit "block" can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components, and are enabled as both physical structures and simulations. Parameters (based on "standard cells"), such as size, are specified for the selected cell, and it is made accessible in a database for use by EDA products.

[0074] During analysis and extraction 826, circuit functionality is verified at the layout level, which allows the layout design to be refined. During physical verification 828, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithography constraints, and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 830, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0075] During tape-out, data is created to be used to produce lithography masks (after applying lithography enhancements where appropriate). During mask data preparation 832, the "tape-out" data is used to produce lithography masks, which are used to produce finished integrated circuits.

[0076] Computer systems (such as Fig. 9 The storage subsystem of the computer system 900) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and physical and logical design products that use the libraries.

[0077] Fig. 9 An example machine of a computer system 900 is illustrated in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequence, etc.) that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

[0080] The processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 902 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 902 can be configured to execute instructions 926 for performing the operations and steps described herein.

[0081] The computer system 900 may also include a network interface device 908 for communicating over a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generating device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0082] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein. During execution of the instructions 926 by the computer system 900, the instructions may also reside completely or at least partially within the main memory 904 and / or within the processing device 902, which also constitute machine-readable storage media.

[0083] In some implementations, the instructions 926 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 924 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode instruction sets for machine execution and cause the machine and processing device 902 to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0084] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. Operations are those that require physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0085] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise clearly indicated from this disclosure, it should be understood that throughout the description certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0086] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program in accordance with the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0088] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, and the instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.

[0089] In the foregoing disclosure, implementations of the present disclosure have been described with reference to specific example implementations thereof. It is clear that various modifications may be made thereto without departing from the scope of implementation of the present disclosure as set forth in the following claims. Where the present disclosure relates to some elements in the singular tense, more than one element may be depicted in the accompanying drawings, and similar elements are marked with similar numbers. Therefore, the present disclosure and the accompanying drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit (IC), comprising: Memory devices; as well as A circuit coupled to the memory device and configured to: preconditioning the memory device to maintain oscillation; initiating a first oscillation in a first loop including the preconditioned memory device, and A second oscillation is initiated in a second loop that does not include the memory device.

2. The IC of claim 1 , wherein the circuit comprises: a set of multiplexers, wherein a set of outputs of the set of multiplexers are coupled to a set of inputs of the memory device; as well as A finite state machine (FSM) provides a set of select signals to the set of multiplexers, wherein the memory device and the FSM are clocked using a clock signal.

3. The IC of claim 2, wherein the FSM includes a first state in which the FSM writes a first value to a first memory address, wherein the FSM transitions from an idle state to the first state when an enable signal is asserted.

4. The IC of claim 3 , wherein the FSM includes a second state in which the FSM writes a second value to a second memory address, wherein the second value is the complement of the first value, and wherein the FSM transitions from the first state to the second state after one clock cycle of the clock signal.

5. The IC of claim 4, wherein the FSM includes a third state in which the FSM reads the first value from the first memory address, wherein the FSM transitions from the second state to the third state after one clock cycle of the clock signal.

6. The IC of claim 5, wherein the FSM includes a fourth state in which the FSM reads the second value from the second memory address, wherein the FSM transitions from the third state to the fourth state after one clock cycle of the clock signal.

7. The IC of claim 6 , wherein the FSM comprises a fifth state, in which the FSM provides an oscillating signal to a clock input of the memory device, wherein the oscillating signal corresponds to the first oscillation or the second oscillation, and wherein the FSM transitions from the fourth state to the fifth state after one clock cycle of the clock signal.

8. The IC of claim 7, wherein the FSM transitions from the fifth state to the idle state when the enable signal is de-asserted.

9. The IC of claim 1, wherein the circuit initiates the first oscillation or the second oscillation based on a calibration signal.

10. The IC of claim 1, wherein the circuit includes a clock divider, wherein an oscillation signal corresponding to the first oscillation or the second oscillation is provided as an input to the clock divider, and wherein an output of the clock divider is provided as an output of the circuit.

11. A method comprising: writing data to at least two memory addresses in a memory device by a circuit, wherein the circuit and the memory device are part of an integrated circuit (IC); initiating, by the circuit, a first oscillation in a first loop including the memory device; generating, by the circuit, a first signal corresponding to the first oscillation; initiating, by the circuit, a second oscillation in a second loop that does not include the memory device; as well as A second signal corresponding to the second oscillation is generated by the circuit.

12. The method according to claim 11, further comprising: measuring a first cycle time of the first oscillation based on the first signal; measuring a second cycle time of the second oscillation based on the second signal; as well as A clock-to-Q access time of the memory device is calculated based on the first cycle time and the second cycle time.

13. The method of claim 11, wherein the writing data to the at least two memory addresses in the memory device comprises writing a first value to a first memory address and writing a second value to a second memory address. The method of claim 13 , wherein the second value is the complement of the first value.

15. The method of claim 13, wherein the first value and the second value are written in consecutive clock cycles.

16. An integrated circuit (IC), comprising: Memory devices; as well as Circuit, including: a set of multiplexers, wherein a set of outputs of the set of multiplexers are coupled to a set of inputs of the memory device; as well as a finite state machine (FSM) that provides a set of selection signals to the set of multiplexers, wherein the memory device and the FSM are clocked using a clock signal, and wherein the FSM preconditions the memory device to maintain oscillation, initiates a first oscillation in a first loop that includes the preconditioned memory device, and initiates a second oscillation in a second loop that does not include the memory device.

17. The IC of claim 16, wherein the FSM includes a first state in which the FSM writes a first value to a first memory address, wherein the FSM transitions from an idle state to the first state when an enable signal is asserted, wherein the FSM includes a second state in which the FSM writes a second value to a second memory address, wherein the second value is the complement of the first value, and wherein the FSM transitions from the first state to the second state after one clock cycle of the clock signal.

18. The IC of claim 17, wherein the FSM comprises a third state in which the FSM reads the first value from the first memory address, wherein the FSM transitions from the second state to the third state after one clock cycle of the clock signal, wherein the FSM comprises a fourth state in which the FSM reads the second value from the second memory address, and wherein the FSM transitions from the third state to the fourth state after one clock cycle of the clock signal.

19. The IC of claim 18, wherein the FSM includes a fifth state, in which the FSM provides an oscillating signal to a clock input of the memory device, wherein the oscillating signal corresponds to the first oscillation or the second oscillation, wherein the FSM transitions from the fourth state to the fifth state after one clock cycle of the clock signal, and wherein the FSM transitions from the fifth state to the idle state when the enable signal is deasserted.

20. The IC of claim 16, wherein the circuit comprises a clock divider, wherein an oscillation signal corresponding to the first oscillation or the second oscillation is provided as an input to the clock divider, and wherein an output of the clock divider is provided as an output of the circuit.

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