Semiconductor device and manufacturing method thereof, memory and memory system

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a memory and a storage system. The semiconductor device includes a plurality of semiconductor pillars; a grid strip and a shielding strip are arranged between the adjacent semiconductor columns in the second direction; and the barrier strip extends along the first direction, is connected with one end of the shielding strip in the third direction, and is positioned on the same side of the shielding strip and the grid strip in the third direction. According to the invention, the yield and reliability can be improved.

Description

Semiconductor device and manufacturing method thereof, memory and storage system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a memory, and a storage system. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D structured memories to approach an upper limit.

[0003] To overcome the limitations of 2D structured memories, the industry has developed memories with three-dimensional structures to increase storage density.

[0004] However, as the integration requirements for memories increase, how to properly arrange the layout of various gates to reduce mutual interference between gates remains a problem to be overcome.

[0005] Summary of the Invention

[0006] The present application provides a semiconductor device and a manufacturing method thereof, a memory and a storage system, which can improve the yield and reliability of the memory.

[0007] In a first aspect, the present application provides a semiconductor device, comprising:

[0008] a semiconductor pillar array, the semiconductor pillar array comprising a plurality of semiconductor pillars arranged in an array along a first direction and a second direction and extending in a third direction, wherein the first direction, the second direction, and the third direction intersect each other;

[0009] A gate bar and a shield bar are provided between adjacent semiconductor columns along the second direction, the gate bar and the shield bar extend along the first direction and are spaced apart in the second direction; and

[0010] A barrier bar extends along the first direction, is connected to one end of the shielding bar in the third direction, and is located on the same side of the shielding bar and the gate bar in the third direction.

[0011] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, comprising:

[0012] forming a plurality of semiconductor pillars, and arranging the plurality of semiconductor pillars in an array in a first direction and a second direction and extending in a third direction, wherein the first direction, the second direction, and the third direction intersect each other;

[0013] forming a gate bar and a shield bar between the adjacent semiconductor columns of the first row and the second row, and extending the gate bar and the shield bar along the first direction and spaced apart in the second direction; and

[0014] A barrier strip is formed at one end of the shielding strip along the third direction. The barrier strip extends along the first direction and is located on the same side of the shielding strip and the gate strip in the third direction.

[0015] In a third aspect, the present application further provides a memory, comprising:

[0016] An array storage structure, comprising the semiconductor device according to the first aspect; and

[0017] A peripheral circuit is connected to the array storage structure to control the bias voltage of the array storage structure.

[0018] In a fourth aspect, the present application further provides a storage system, comprising: the memory as described in the third aspect; and a controller coupled to the memory, the controller being used to control the memory to perform data writing and reading operations.

[0019] Beneficial effects of the present application: The present application forms two electrodes, namely a first electrode and a second electrode, between adjacent semiconductor columns, and forms a barrier strip extending along the first direction and connected to the second electrode at the same end of the first electrode and the second electrode in the third direction, so that the first electrode can be used as a gate strip and the second electrode can be used as a shielding strip. The shielding strip is formed at the same time as the gate strip, so that the shielding strip can prevent interference between adjacent semiconductor columns, thereby reducing the coupling effect between adjacent semiconductor columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] FIG1 is an equivalent circuit diagram of a memory cell in a semiconductor device according to an embodiment of the present application;

[0022] FIG2 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0023] FIG3 is a top view of a substrate provided in an embodiment of the present application;

[0024] FIG4 is a cross-sectional view of a substrate provided in an embodiment of the present application;

[0025] FIG5 is a top view of forming an isolation trench according to an embodiment of the present application;

[0026] FIG6 is a cross-sectional view of the isolation trench formed along the AA′ cutting line in FIG5 according to an embodiment of the present application;

[0027] FIG7 is a top view of a dielectric material deposited in an isolation trench according to an embodiment of the present application;

[0028] FIG8 is a cross-sectional view of the isolation trench along the BB′ cutting line in FIG7 provided by an embodiment of the present application;

[0029] FIG9 is a top view of a gate trench formed according to an embodiment of the present application;

[0030] FIG10 is a cross-sectional view of the CC' cutting line in FIG9 in forming the gate trench according to an embodiment of the present application;

[0031] FIG11 is a top view of a first oxide layer formed on the sidewall of a gate trench according to an embodiment of the present application;

[0032] FIG12 is a cross-sectional view of a first oxide layer formed on the sidewall of a gate trench according to an embodiment of the present application, taken along the DD′ cutting line in FIG11 ;

[0033] 13 is a top view of a conductive layer formed on a first oxide layer according to an embodiment of the present application;

[0034] 14 is a cross-sectional view of a conductive layer formed on a first oxide layer along a cutting line EE' in FIG. 13 according to an embodiment of the present application;

[0035] FIG15 is a cross-sectional view of the semiconductor device provided in an embodiment of the present application taken along the BB′ cutting line in FIG12 ;

[0036] FIG16 is a top view of an embodiment of the present application showing an isolation material being filled into the inner wall of a gate trench;

[0037] FIG17 is a cross-sectional view of the FF′ cutting line in FIG16 , showing an embodiment of the present application where an isolation material is filled into the inner wall of the gate trench;

[0038] FIG18 is a cross-sectional view of an embodiment of the present application showing an isolation material being filled into the inner wall of a gate trench to cover a gate bar and a shielding bar;

[0039] FIG19 is a cross-sectional view of a capacitor array formed according to an embodiment of the present application;

[0040] 20 to 26 are multiple cross-sectional views of a production process for forming a barrier layer according to an embodiment of the present application;

[0041] FIG27 is a top view of a barrier strip and gate conductive structure formed according to an embodiment of the present application;

[0042] FIG28 is a cross-sectional view of a barrier strip and a gate conductive structure formed along the GG′ cutting line in FIG27 according to an embodiment of the present application;

[0043] 29 to 30 are multiple cross-sectional views of a process for forming a gate lead contact according to an embodiment of the present application;

[0044] FIG31 is a top view of a method for forming a gate lead contact and a shield lead contact provided in an embodiment of the present application;

[0045] FIG32 is a cross-sectional view of forming gate lead contacts and shield lead contacts along the HH′ cutting line in FIG31 according to an embodiment of the present application;

[0046] 33 and 34 are multiple top views of another manufacturing process for forming gate lead contacts and shield lead contacts provided by an embodiment of the present application;

[0047] FIG35 is a top view of a semiconductor column lead-out contact formed according to an embodiment of the present application;

[0048] 36 is a cross-sectional view of forming a gate lead contact, a shield lead contact, and a semiconductor pillar lead contact according to an embodiment of the present application;

[0049] FIG37 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0050] Figure 38 is a structural diagram of the storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0052] Transistors are used in dynamic random access memory (DRAM) to control the capacitance within each memory cell. The basic DRAM cell structure consists of a transistor and a storage capacitor. Its primary function is to use the amount of charge stored in the capacitor to represent whether a binary bit is a 1 or a 0.

[0053] With the development of dynamic random access memory technology, the size of storage cells is getting smaller and smaller, and its array architecture is composed of 8F 2 Go to 6F 2 Then go to 4F 2 In addition, based on the requirements for ions and leakage current in dynamic random access memory, the memory architecture has evolved from planar array transistor to recessed gate array transistor, from recessed gate array transistor to buried saddle fin array transistor, and then from buried saddle fin array transistor to vertical gate transistor.

[0054] In practical applications, whether using planar transistors, recessed gate array transistors, buried transistors, or vertical gate transistors, dynamic random access memory (DRAM) is composed of multiple memory cell structures. Each memory cell structure primarily consists of a transistor and a storage capacitor controlled by the transistor. In other words, a DRAM consists of one transistor (T) and one capacitor (C), a 1T1C architecture. Its primary operating principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0055] Figure 1 is a circuit connection diagram of a 1T1C architecture provided in an embodiment of the present application. As shown in Figure 1, the drain of the transistor T is electrically connected to the bit line (BL), the source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C is grounded through the ground terminal (GND), and the gate of the transistor T is connected to the word line (WL). A voltage is applied through the word line WL to control the conduction or cut-off of the transistor T. The bit line BL is used to perform a read or write operation on the capacitor C when the transistor T is turned on.

[0056] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure 200 provided in an embodiment of the present application. The embodiment of the present application provides a semiconductor structure, as shown in Figure 2, the semiconductor structure includes: a first transistor 210 and a second transistor 220 arranged in parallel along the Y-axis direction and separated by a first isolation structure 206, the first isolation structure 206 includes an air gap 205 (Airgap); the first transistor 210 and the second transistor 220 both include: a gate 201 extending along the Z-axis direction, a channel region 204 extending along the Z-axis direction, a gate oxide layer (Gate oxide layer) 202 located between the gate 201 and the channel region 204 and extending along the Z-axis direction, and a source (not shown in the figure) and a drain (not shown in the figure) respectively located at opposite ends of the channel region 204 along the Z-direction. The gate 201 is located on one side of the channel region 204; wherein, the gate 201 of the first transistor 210 is located on one side of the channel region 204 away from the first isolation structure 206, and the gate 201 of the second transistor 220 is located on one side of the channel region 204 away from the first isolation structure 206.

[0057] When the gate vertical transistor structure shown in FIG2 is adopted, an air gap 205 is formed in the middle of the first isolation structure 206 to improve the problem of coupling effect between the adjacent first transistor 210 and the second transistor 220 in the semiconductor structure. However, the semiconductor structure has high requirements for process control and is prone to dumping problems.

[0058] To improve the above-mentioned problems, with reference to Figures 3 to 38, some embodiments of the present application provide a semiconductor device 100 and a method for manufacturing the same, a memory 320, and a storage system 300. The present application forms two electrodes, namely a first electrode and a second electrode, between adjacent semiconductor pillars 10. At the same end of the first electrode and the second electrode in the third direction Z, a barrier strip 90 extending along the first direction X and connected to the second electrode is formed. In this way, the first electrode can serve as a gate strip 30, and the second electrode can serve as a shield strip 20. The shield strip 20 is formed simultaneously with the gate strip 30, thereby preventing interference between adjacent semiconductor pillars 10 through the shield strip 20, thereby reducing the coupling effect between adjacent semiconductor pillars 10.

[0059] Please refer to Figures 3 to 36, which are schematic diagrams of a manufacturing process of a semiconductor device 100 provided in some embodiments of the present application. First, the semiconductor device 100 will be described. Figure 27 is a top view of a semiconductor structure provided in an embodiment of the present application, Figure 28 is a cross-sectional view of the semiconductor structure provided in an embodiment of the present application taken along the GG' cutting line in Figure 27, and Figure 30 is another cross-sectional view of the semiconductor structure provided in an embodiment of the present application taken along the GG' cutting line in Figure 27. As shown in Figures 27, 28 and 30, the semiconductor device 100 includes:

[0060] A semiconductor pillar array, comprising a plurality of semiconductor pillars 10 arranged in an array along a first direction and a third direction and extending in the third direction, wherein the first direction, the second direction, and the third direction intersect each other;

[0061] A gate bar 30 and a shield bar 20 are provided between adjacent semiconductor pillars 10 along the second direction Y, the gate bar 30 and the shield bar 20 extend along the first direction X and are spaced apart in the third direction Y; and

[0062] The barrier strip 90 extends along the first direction X, is connected to one end of the shielding strip 20 in the third direction Z, and is located on the same side of the shielding strip 20 and the gate strip 30 in the third direction Z.

[0063] In some specific examples, the first direction and the third direction have an angle therebetween, and the third direction has an angle therebetween with the plane containing the first and third directions, wherein the angle is less than or equal to 90 degrees. For example, in some embodiments of the present application, the first direction is the X direction, the second direction is the Y direction, and the third direction is the Z direction.

[0064] As shown in FIG27 , the plurality of semiconductor pillars 10 include a first row of semiconductor pillars 10 a and a second row of semiconductor pillars 10 b arranged along a first direction X and adjacent to each other in a second direction Y. The semiconductor pillars 10 are used to transfer charge or stop the transfer of charge under the action of an applied electric field, thereby turning the transistor on or off. The extension direction of each semiconductor pillar 10 is the direction of current flow when the transistor is on. For example, as shown in FIG28 and FIG30 , the extension direction of the semiconductor pillars 10 is the third direction Z, and the plurality of semiconductor pillars 10 are arranged in an array along the first direction X and the third direction Y to form a semiconductor pillar array.

[0065] In some specific examples, as shown in Figures 27, 28, and 30, a gate bar 30 and a shield bar 20 are provided between two adjacent semiconductor pillars 10 along the second direction Y. In addition, as shown in Figure 27, the gate bar 30 between the adjacent semiconductor pillars 10 along the second direction Y extends along the first direction X, and the shield bar 20 between the adjacent semiconductor pillars 10 along the second direction Y extends along the first direction X. Moreover, the gate bar 30 and the shield bar 20 between every two adjacent semiconductor pillars 10 along the second direction Y are spaced apart from each other, that is, the gate bar 30 and the shield bar 20 between adjacent semiconductor pillars 10 do not contact or have a spacing therebetween.

[0066] In some specific examples, as shown in FIG28 and FIG30 , the semiconductor structure further includes a barrier strip 90 extending along the first direction X. The barrier strip 90 contacts or connects to one end of the shielding strip 20 in the third direction Z. Furthermore, the barrier strip 90 is located on the same side as the shielding strip 20 and the gate strip 30 in the third direction Z, that is, the barrier strip 90, the end of the shielding strip 20 connected to the barrier strip 90 in the third direction Z, and the end of the gate strip 30 connected to the gate conductive structure 31 formed in the later embodiment in the third direction Z. In this way, the barrier strip 90 can isolate the gate strip 30 and the shielding strip 20 between adjacent semiconductor pillars 10 in the second direction Y. Furthermore, because the barrier strip 90 has an insulating function, the barrier strip 90 can better isolate the shielding strip 20 from the gate strip 30.

[0067] In some specific examples, as shown in Figures 28 and 30, the barrier strip 90 is located between the shielding strip 20 and the gate strip 30 and is in contact with one end of the shielding strip 20 in the third direction Z (for example, the end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the barrier strip 90 and the gate strip 30 are spaced apart in the second direction Y.

[0068] In some specific examples, the blocking strip 90 can also be located at the same end of the shielding strip 20 and the semiconductor column 10 in the third direction Z. For example, as shown in Figures 28 and 30, the first blocking portion 90a of the blocking strip 90 is located at the same end of the shielding strip 20 and the gate strip 30 between adjacent semiconductor columns 10 in the third direction Z, that is, the first blocking portion 90a is connected to one end of the shielding strip 20 in the third direction Z, and the second blocking portion 90b of the blocking strip 90 is located at the same end of the adjacent semiconductor columns 10 in the third direction Z, that is, the second blocking portion 90b is connected to one end of the semiconductor column 10 in the third direction Z, and the first blocking portion 90a connected to one end of the shielding strip 20 in the third direction Z and the second blocking portion 90b connected to one end of the semiconductor column 10 in the third direction Z are located on the same side in the third direction Z.

[0069] In some examples, as shown in Figures 28 and 30, the first barrier portion 90a and the second barrier portion 90b. As shown in Figure 28, the cross-sectional shape of the second barrier portion 90b can be a sector, and as shown in Figure 30, the cross-sectional shape of the second barrier portion 90b can be a rectangle. Of course, the cross-sectional shape of the second barrier portion 90b can also be an inverted trapezoid, an arc, etc.

[0070] In some embodiments, the first blocking portion 90 a may be removed as shown in FIG. 28 to connect the bit line BL in the following embodiments.

[0071] In some specific examples, the barrier strip 90 may be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane, or polysilazane. Silicon oxide refers to silicon oxide compounds such as SixOy, and silicon nitride refers to silicon nitrogen compounds such as SixNy.

[0072] In some embodiments, the semiconductor device 100 further includes: a gate conductive structure 31, wherein the gate conductive structure 31 extends along the first direction X and is located between the end of the gate bar 30 in the third direction Z and the barrier bar 90, and is at least partially parallel to the barrier bar 90.

[0073] In some specific examples, as shown in Figures 28 to 30 , one end of the gate strip 30 in the third direction Z is connected to a gate conductive structure 31. In the third direction Z, the gate conductive structure 31 is located between the gate strip 30 and the barrier strip 90. The gate conductive structure 31 is in contact with and connected to one end of the gate strip 30 in the third direction Z (e.g., the end of the semiconductor pillar 10 in the third direction Z that is away from the capacitor structure 70 in the embodiments below), and the gate conductive structure 31 is adjacent to the barrier strip 90. In other words, the gate conductive structure 31 connected to the gate strip 30 and the barrier strip 90 contacted by the shielding strip 20 are on the same side in the third direction Z, and the gate conductive structure 31 is adjacent to the barrier strip 90 along the second direction Y.

[0074] In some specific examples, the gate conductive structure 31 may be made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

[0075] In some embodiments, the semiconductor device 100 further includes a gate lead contact 32 located at one end of the semiconductor pillar array in the third direction Z, and the gate lead contact 32 is connected to the gate conductive structure 31 .

[0076] In some specific examples, as shown in Figures 30 and 32, each gate conductive structure 31 is connected to a gate lead contact 32 at one end away from the gate bar 30 in the third direction Z, that is, the gate lead structure is located between the gate lead contact 32 and the gate bar 30 in the third direction Z.

[0077] In some specific examples, the gate lead contact 32 may be formed of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The gate lead contact 32 and the gate conductive structure 31 may be made of the same or different materials. The present application utilizes the gate lead contact 32 and the gate conductive structure 31 to connect the gate strip 30, facilitating process flow and improving reliability.

[0078] In some embodiments, the semiconductor device 100 further includes: a shielding lead-out contact 21 located at the one end of the semiconductor pillar array in the third direction Z, wherein the shielding lead-out contact 21 is connected to the shielding bar 20 .

[0079] In some specific examples, as shown in Figures 31, 32, and 34, one end of the shielding strip 20 in the third direction Z is connected to a shielding lead-out contact 21. In some examples, such as when located at a non-end portion of the shielding strip 20, the shielding lead-out contact 21 passes through the barrier strip 90 along the third direction Z, and the shielding lead-out contact 21 is in contact with and connected to one end of the shielding strip 20 in the third direction Z (for example, the end of the semiconductor pillar 10 in the third direction Z away from the capacitor structure 70 in the embodiment below) through the barrier strip 90. In other words, the shielding lead-out contact 21 connected to the shielding strip 20 and the barrier strip 90 connected to the shielding strip 20 are on the same side in the third direction Z, and the shielding lead-out contact 21 and the shielding strip 20 are located on opposite sides of the barrier strip 90 along the third direction Z.

[0080] In some specific examples, the component material of the shielding lead-out contact 21 may include a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof. The shielding lead-out contact 21 and the shielding bar 20 may be made of the same material or different materials. The shielding lead-out contact 21 of the present application is electrically interconnected with the shielding bar 20, and a fixed voltage is applied to the shielding bar 20 through the shielding lead-out contact 21, that is, the shielding lead-out contact 21 can be connected to the common end to enable the shielding bar 20 to perform a shielding function.

[0081] In some specific examples, the common terminal may include a low voltage terminal and a ground terminal, wherein the low voltage may include -0.5V, -1V, etc. In some embodiments, the shielding bar 20 is connected to the common terminal. In actual application, the shielding bar 20 can be set to be powered separately and not connected to the common terminal as required. In some embodiments of the present application, a low voltage is applied to the shielding bar 20 or the shielding bar 20 is grounded so that the shielding bar 20 can shield interference between adjacent semiconductor pillars 10.

[0082] In some embodiments, the semiconductor device 100 further includes: a semiconductor pillar lead-out contact 11 located at the one end of the semiconductor pillar array in the third direction Z, and the semiconductor pillar lead-out contact 11 is connected to the semiconductor pillar 10 .

[0083] In some specific examples, as shown in Figures 35 and 36, one end of the semiconductor pillar 10 in the third direction Z is connected to a semiconductor pillar lead-out contact 11. The semiconductor pillar lead-out contact 11 passes through a barrier strip 90 covering the semiconductor pillar 10 along the third direction Z, such that the semiconductor pillar lead-out contact 11 passes through the barrier strip 90 and is in contact with and connected to one end of the semiconductor pillar 10 in the third direction Z (for example, the end of the semiconductor pillar 10 in the third direction Z that is away from the capacitor structure 70 in the embodiment below). That is, the semiconductor pillar lead-out contact 11 connected to the semiconductor pillar 10 and the barrier strip 90 connected to the semiconductor pillar 10 are on the same side in the third direction Z, and the semiconductor pillar lead-out contact 11 is connected to one end of the shielding strip 20 along the third direction Z.

[0084] In some embodiments, the first blocking portion 90 a connected to one end of the semiconductor pillar 10 along the third direction Z shown in FIG. 28 may be removed.

[0085] In some specific examples, the constituent material of the semiconductor pillar lead-out contact 11 may include a conductive material, and the conductive material includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof. The material of the semiconductor pillar lead-out contact 11 and the semiconductor pillar 10 may be the same or different. The semiconductor pillar lead-out contact 11 of the present application is electrically interconnected with the semiconductor pillar 10, and the semiconductor pillar lead-out contact 11 can connect one end of multiple semiconductor pillars 10 along the third direction Z to the same bit line BL. Of course, in some embodiments, the semiconductor pillar lead-out contact 11 can also be replaced to form a bit line BL, that is, the embodiment of the present application can lead out the connection of the bit line BL through the semiconductor pillar lead-out contact 11, or can not lead out the connection of the bit line BL through the semiconductor pillar lead-out contact 11, that is, the bit line BL adjacent to the end of the multiple semiconductor pillars 10 along the third direction Z can be formed directly.

[0086] For example, as shown in FIG35 , a semiconductor pillar lead-out contact 11 is formed at the bottom of each of the plurality of semiconductor pillars 10 arranged in an array. The corresponding semiconductor pillars 10 can be led out through the plurality of semiconductor pillar lead-out contacts 11 arranged at intervals along the first direction X and the second direction Y as shown in FIG35 . That is, eight columns of semiconductor pillar lead-out contacts 11 are sequentially connected to the first bit line BL1 through the eighth word line BL8 . It should be noted that the number of semiconductor pillar lead-out contacts 11 shown in the embodiment of this application is merely an example, and other numbers of semiconductor pillar lead-out contacts 11 are also within the scope of protection of this application.

[0087] In some specific examples, the semiconductor device 100 may further include an insulating layer 91 extending along the second direction Y and located at the one end of the semiconductor pillar array in the third direction Z. As shown in FIG32 , in the third direction Z, the insulating layer 91 covers the barrier strips 90 , the gate conductive structure 31 , the gate lead contact 32 , the shield lead contact 21 , and the semiconductor pillar lead contact 11 .

[0088] In some specific examples, the semiconductor device 100 may further include an isolation layer 80 extending along the second direction Y and located at the one end of the semiconductor pillar array in the third direction Z. As shown in FIG32 , in the third direction Z, the isolation layer 80 covers the end of the semiconductor pillar 10 in the third direction Z that is away from the capacitor structure 70 of the following embodiment. That is, as shown in FIG32 , in the third direction Z, the isolation layer 80 and the insulating layer 91 are respectively located on opposite sides of the barrier strip 90, and the isolation layer 80 covers each semiconductor pillar 10, and the insulating layer 91 covers the barrier strip 90, the gate conductive structure 31, the gate lead contact 32, the shield lead contact 21, and the semiconductor pillar lead contact 11 located on the same side in the third direction Z.

[0089] In some specific examples, the constituent materials of the isolation layer 80 and the insulating layer 91 may both include any one or a combination of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane. In the embodiment of the present application, the materials of the isolation layer 80 and the insulating layer 91 may be the same or different.

[0090] In some embodiments, the semiconductor device 100 further includes:

[0091] A plurality of gate bars 30 arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y;

[0092] a plurality of shielding bars 20 arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y and arranged alternately with the plurality of gate bars 30;

[0093] a plurality of the barrier strips 90 arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y; and

[0094] The gate conductive structures 31 are arranged at intervals between the rows of semiconductor pillars 10 along the third direction Y.

[0095] In some specific examples, as shown in FIG27 , multiple semiconductor pillars 10 are arranged at intervals along a first direction X, and multiple semiconductor pillars 10 are arranged at intervals along a second direction Y, i.e., multiple semiconductor pillars 10 are arranged in an array along the first direction X and the second direction Y. As shown in FIG27 , FIG28 , and FIG31 , multiple semiconductor pillars 10 are arranged in an array along the first direction X and the second direction Y, and gate strips 30 in semiconductor pillars 10 adjacent to each other in the second direction Y are located on one side of each semiconductor pillar 10, i.e., multiple gate strips 30 are arranged at intervals along the third direction Y between rows of semiconductor pillars 10, and multiple gate strips 30 are located on one side of the semiconductor pillars 10 in the second direction Y. Shield strips 20 in semiconductor pillars 10 adjacent to each other in the second direction Y are located on the other side of each semiconductor pillar 10, i.e., multiple shield strips 20 are arranged at intervals along the third direction Y between rows of semiconductor pillars 10, and multiple shield strips 20 are located on the other side of the semiconductor pillars 10 in the second direction Y. In addition, the plurality of gate bars 30 and the plurality of shield bars 20 are arranged alternately along the second direction Y, and there is a gap between the gate bars 30 and the shield bars 20 in adjacent semiconductor pillars 10 along the second direction Y.

[0096] In some specific examples, as shown in Figures 28 and 30, the semiconductor structure is further provided with a plurality of barrier strips 90 extending along the first direction X, each shielding strip 20 is connected to its own barrier strip 90 at one end in the third direction Z, and the barrier strips 90 to which the plurality of shielding strips 20 are connected are all located at the same end in the third direction Z. Among them, the blocking strip 90 is in contact with one end of the shielding strip 20 in the third direction Z (for example, the end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the blocking strip 90 is located on the same side of the shielding strip 20 and the gate strip 30 in the third direction Z, and the blocking strip 90 and the gate strip 30 are spaced apart in the second direction Y. In this way, the gate strip 30 and the shielding strip 20 between adjacent semiconductor columns 10 along the second direction Y can be isolated by the blocking strip 90, and because the blocking strip 90 has an insulating function, the shielding strip 20 in contact with the blocking strip 90 can play a shielding role, thereby improving the coupling effect between adjacent transistors in the second direction Y, reducing interference between adjacent transistors, and improving the yield and reliability of the memory.

[0097] In some specific examples, as shown in FIG30 , a plurality of barrier strips 90 may be located on one side of the semiconductor pillar 10 along the second direction Y. Of course, as shown in FIG28 , a plurality of barrier strips 90 may be located on the other side of the semiconductor pillar 10 along the second direction Y. It should be noted that the constituent materials of the barrier strips 90 can be referred to in the above embodiments and will not be described in detail here.

[0098] Exemplarily, as shown in Figure 28, the first transistor T1 includes a gate bar 30a and a semiconductor column 10a, and the second transistor T2 includes a gate bar 30b and a semiconductor column 10b. A shielding bar 20 connected to the barrier bar 90 is provided between the semiconductor column 10a and the semiconductor column 10b. In this way, the shielding bar 20 connected to the barrier bar 90 can improve the coupling effect between the first transistor T1 and the second transistor T2. That is, when the first transistor T1 is turned on, the semiconductor column 10a region of the first transistor T1 becomes a high voltage, and the shielding bar 20 located between the first transistor T1 and the second transistor T2 will shield the interference between the electrons in the semiconductor column 10a of the first transistor T1 and the electrons in the semiconductor column 10b of the second transistor T2, thereby reducing the interference problem of the turned-on first transistor T1 on the second transistor T2.

[0099] In some specific examples, as shown in Figures 28 to 30 and Figures 32 to 33, each gate bar 30 is connected to a gate conductive structure 31 at one end in the third direction Z, and the gate conductive structures 31 to which the multiple gate bars 30 are respectively connected are all located at the same end in the third direction Z, wherein the gate conductive structure 31 is located between the gate bar 30 and the barrier bar 90 along the third direction Z, the gate conductive structure 31 is in contact with and connected to one end of the gate bar 30 in the third direction Z (for example, the end of the semiconductor column 10 in the third direction Z away from the capacitor structure 70 in the embodiment below), and the gate conductive structure 31 is adjacent to the barrier bar 90 along the second direction Y.

[0100] In some specific examples, as shown in FIG28 , multiple gate conductive structures 31 may be located on one side between adjacent semiconductor pillars 10 along the second direction Y, while multiple barrier strips 90 are located on the other side between adjacent semiconductor pillars 10 along the second direction Y. Alternatively, as shown in FIG30 , multiple gate conductive structures 31 may be located on the other side of the semiconductor pillars 10 along the second direction Y, while multiple barrier strips 90 are located on one side between adjacent semiconductor pillars 10 along the second direction Y. In summary, the gate conductive structures 31 and barrier strips 90 are located on the same side of the semiconductor pillars 10 along the third direction Z, and the gate conductive structures 31 and barrier strips 90 are located on different sides of adjacent semiconductor pillars 10 along the second direction Y. It should be noted that the materials used for the gate conductive structures 31 can be found in the above embodiments and will not be detailed here.

[0101] In some embodiments, the semiconductor device 100 further includes a plurality of gate lead contacts 32 , one gate lead contact 32 corresponds to one gate conductive structure 31 , and the plurality of gate lead contacts 32 are synchronously spaced along the first direction X and the second direction Y in a stepped distribution.

[0102] In some embodiments, the semiconductor device 100 further includes a plurality of shielding lead contacts 21 , one shielding lead contact 21 corresponds to one shielding bar 20 , and the plurality of shielding lead contacts 21 are synchronously spaced and distributed in a stepped manner along the first direction X and the second direction Y.

[0103] In a specific example, as shown in FIG30, FIG34 and FIG32, the semiconductor device 100 includes gate lead contacts 32a, gate lead contacts 32b, gate lead contacts 32c and gate lead contacts 32d arranged simultaneously or synchronously in the order of arrangement of the four gate strips 30 in the examples shown in FIG30 and FIG32, thereby forming a stepped arrangement. The semiconductor device 100 includes gate lead contacts 32a, gate lead contacts 32b, gate lead contacts 32c and gate lead contacts 32d arranged simultaneously or synchronously in the order of arrangement of the four gate strips 30 in the examples shown in FIG30 and FIG32, thereby forming a stepped arrangement. The arrangement order of the four shielding strips 20 in the embodiment is such that the shielding lead contacts 21a, 21b, 21c, and 21d are arranged simultaneously or synchronously at intervals, thereby forming a stepped arrangement. In addition, the gate lead contact 32 is located on a gate strip 30 between adjacent semiconductor pillars 10, away from one end of the capacitor structure 70 in the embodiment below along the third direction Z, and the shielding lead contact 21 is located on a shielding strip 20 between adjacent semiconductor pillars 10, away from one end of the capacitor structure 70 in the embodiment below along the third direction Z. It should be noted that the constituent materials of the gate lead contact 32 and the shielding lead contact 21 can be referred to the above embodiment and will not be repeated here.

[0104] In some embodiments, as shown in Figures 31 and 32, the semiconductor device 100 further includes a plurality of gate lead-out contacts 32 and a plurality of shield lead-out contacts 21, one gate lead-out contact 32 corresponds to one gate conductive structure 31, one shield lead-out contact 21 corresponds to one shielding bar 20, and the plurality of gate lead-out contacts 32 and the plurality of shield lead-out contacts 21 are staggered and arranged along the second direction Y.

[0105] For example, as shown in FIG31 , four gate strips 30 extending along the first direction X are arranged at intervals along the second direction Y. Each gate strip 30 is connected to a gate conductive structure 31 on a side close to the isolation structure 50 in the following embodiment along the second direction Y. One of the gate conductive structures 31 is connected to a corresponding gate lead contact 32. Four gate strips 30 are led out through the four spaced-apart gate lead contacts 32 and their respective connected gate conductive structures 31. That is, the four gate strips 30 are connected to the first word line WL1, the second word line WL2, the third word line WL3, and the fourth word line WL4, respectively, in sequence. Similarly, four shielding bars 20 extending along the first direction X are arranged at intervals along the second direction Y. Each shielding bar 20 is connected to a barrier bar 90 on one side of the second direction near the isolation structure 50 in the following embodiment. Each shielding bar is connected to a corresponding shielding lead contact 21. The four shielding bars 20 are connected to the first plate line PL1, the second plate line PL2, the third plate line PL2, and the fourth plate line PL4, respectively, through the four spaced shielding lead contacts 21. A fixed voltage can be applied to the shielding bars 20 connected to the plate line PL, so that the shielding bars 20 can shield interference between adjacent semiconductor pillars 10. It should be noted that the number of gate lead contacts 32 and shield lead contacts 21 shown in the embodiment of this application is only an example, and other numbers of semiconductor pillar lead contacts 11 are also within the scope of protection of this application.

[0106] In some embodiments, as shown in Figures 32 and 34, the semiconductor device 100 further includes a plurality of gate lead contacts 32 and a plurality of shield lead contacts 21, one gate lead contact 32 corresponds to one gate conductive structure 31, one shield lead contact 21 corresponds to one shield bar 20, and the plurality of gate lead contacts 32 and the plurality of shield lead contacts 21 are synchronously staggered and arranged along the first direction X and the second direction Y in a stepped distribution.

[0107] For example, as shown in FIG34 , four gate bars 30 and four shield bars 20 can also be led out with reference to FIG31 . The difference between FIG34 and FIG31 is that the multiple gate lead-out contacts 32 and the multiple shield lead-out contacts 21 in FIG34 are staggered and arranged in a stepped manner along the second direction Y.

[0108] In some embodiments, a cross-sectional dimension of the semiconductor pillar 10 in the second direction Y is equal to a spacing dimension between two adjacent semiconductor pillars 10 .

[0109] In some specific examples, as shown in FIG32 , the cross-sectional dimension L2 of each semiconductor pillar 10 along the second direction Y is equal to the spacing dimension L1 between adjacent semiconductor pillars 10. Due to process precision control, the term "equal" in this embodiment includes approximately equal to or approximately equal to. In some embodiments of the present application, two electrodes, namely a first electrode and a second electrode, are formed between adjacent semiconductor pillars 10. At the same end of the first and second electrodes in the third direction Z, a barrier strip 90 extending along the first direction X and connected to the second electrode is formed. In this way, the first electrode can function as the gate strip 30, and the second electrode can function as the shield strip 20. There is no need to directly form an air gap or other shielding isolation structure 50 between adjacent semiconductor pillars 10. The barrier strip 90 allows the shield strip 20 to be formed simultaneously with the gate strip 30, thereby shielding the gate strip 30 from interfering with adjacent semiconductor pillars 10 and reducing coupling effects between adjacent semiconductor pillars 10. Furthermore, the cross-sectional dimension L2 of each semiconductor pillar 10 along the second direction Y is equal to the spacing dimension L1 between adjacent semiconductor pillars 10, thereby reducing loading effects and simplifying process control.

[0110] In some embodiments, a difference between a cross-sectional dimension of the semiconductor pillar 10 in the second direction Y and a spacing dimension between two adjacent semiconductor pillars 10 is smaller than a preset value.

[0111] In some specific examples, as shown in Figure 32, the cross-sectional dimension L2 of each semiconductor column 10 along the second direction Y is equal to the spacing dimension L1 between adjacent semiconductor columns 10, and the size difference is less than the set value based on the precision requirements of the process or equipment, or the product requirements. For example, the absolute value of the difference between the spacing dimension L1 and the cross-sectional dimension L2 is less than and other feasible values, that is, |L1-L2|<△L, △L refers to the preset value.

[0112] In some embodiments, the semiconductor device 100 further includes:

[0113] a first oxide layer 41 located between the semiconductor pillar 10 and the gate strip 30 and between the semiconductor pillar 10 and the shield strip 20;

[0114] An isolation structure 50 is located between the gate strips 30 and the shield strips 20 .

[0115] In some specific examples, as shown in Figures 18 to 26, 28 to 30, and 32, the semiconductor device 100 further includes a first oxide layer 41 and an isolation structure 50. The first oxide layer 41 is provided between the semiconductor pillar 10 and the gate strip 30 along the second direction Y, and the first oxide layer 41 is provided between the semiconductor pillar 10 and the shield strip 20 along the second direction Y. Furthermore, the isolation structure 50 is provided between the gate strip 30 and the shield strip 20 along the second direction Y. As shown in Figures 18 to 26, 28 to 30, and 32, the semiconductor pillar 10, the first oxide layer 41, the gate strip 30, the isolation structure 50, the shield strip 20, the first oxide layer 41, and the semiconductor pillar 10 are arranged in sequence along the second direction Y.

[0116] In some embodiments, a gate strip 30 and a shield strip 20 are disposed between adjacent semiconductor pillars 10 in the second direction Y, and the spacing between the semiconductor pillars 10 and the shield strip 20 is the same as the spacing between adjacent semiconductor pillars 10 and the gate strip 30. In other words, in the second direction Y, a gate strip 30 and a shield strip 20 are located on different sidewalls of adjacent semiconductor pillars 10, and the shield strips 20 and the gate strips 30 are positioned in mirror symmetry.

[0117] As shown in Figure 2, the first isolation structure 206 is located in the middle position between two adjacent gates 201 along the second direction Y, and a first isolation structure 206 is provided in the middle position of the adjacent channel region 204 in the second direction Y. That is, the distance between the first isolation structure 206 and the adjacent channel region 204 in the second direction Y is the same, and the distance between the first isolation structure 206 and the adjacent gate 201 in the second direction Y is the same. Unlike that shown in FIG2 , the present application forms a gate trench K2 simultaneously as shown in FIG11 to FIG28 , deposits a first electrode and a second electrode on different side walls of the gate trench along the second direction Y, and forms a barrier strip 90 on one side of the second electrode located on one side wall along the third direction Z, so that the second electrode connected to the barrier strip 90 forms a shielding strip 20 with a shielding effect, and the first electrode not connected to the barrier strip 90 forms a gate strip. Compared with FIG2 , an isolation groove for forming a first isolation structure 206 is obtained by additionally digging grooves between adjacent transistors. The present application directly uses a plurality of equally spaced gate grooves to form a mirror-symmetrically arranged conductive layer to cooperate with the barrier strip to form a gate strip 30 and a shielding strip 20, thereby reducing the difficulty of process control, and can also enhance the strength of the semiconductor column 10 and improve the anti-tilting ability of the semiconductor device 100.

[0118] In some specific examples, the constituent material of the first oxide layer 41 may include silicon oxide, silicon oxynitride, etc.

[0119] In some specific examples, the constituent material of the isolation structure 50 may include any one or a combination of multiple insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, polysiloxane or polysilazane.

[0120] In some embodiments, the semiconductor device 100 further includes: a capacitor array 71 located at the other end of the semiconductor pillar array in the third direction Z, the capacitor array 71 including a plurality of capacitor structures 70 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z, the capacitor structure 70 including a first electrode layer (not shown in the figure) connected to the other end of the semiconductor pillar 10 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located within the first electrode layer.

[0121] In some specific examples, as shown in Figures 28, 30, and 32, the semiconductor device 100 further includes a capacitor array 71, which includes a plurality of capacitor structures 70 extending in the third direction Z. The plurality of capacitor structures 70 are arranged in an array along the first direction X and the second direction Y. In addition, a capacitor structure 70 is connected to the other end of each semiconductor pillar 10 along the third direction Z (i.e., the opposite ends of the semiconductor pillar 10 connected to the barrier strip 90 and the gate conductive structure 31 in the above embodiment along the third direction Z). In addition, each capacitor structure 70 includes a first electrode layer connected to the source of the semiconductor pillar 10.

[0122] A gate strip 30 is formed on the sidewall of each semiconductor pillar 10 of the semiconductor array. The gate strips 30 of each semiconductor pillar 10 in the same column (i.e., each semiconductor pillar 10 arranged at intervals along the second direction Y) are connected to form a word line. A source electrode (not shown in the figure) is formed at one end of each semiconductor pillar 10 in the transistor array along the third direction Z. The source electrode is connected to the first electrode layer of the capacitor structure 70. A drain electrode (not shown in the figure) is formed at the other end of each semiconductor pillar 10 in the transistor array along the third direction Z. The drain electrodes of each semiconductor pillar 10 in the same row (i.e., each semiconductor pillar 10 arranged at intervals along the first direction X) are connected to form a bit line BL (not shown in the figure). In the above-mentioned semiconductor device 100, the semiconductor pillars 10 extend along the third direction Z, and the source and drain electrodes are respectively formed at opposite ends of the semiconductor pillar 10 along the third direction Z. The capacitor structure 70 and the bit line BL are respectively located on opposite sides of the semiconductor pillar 10 along the third direction Z. In this way, the semiconductor pillars 10 can be manufactured separately on both sides of the substrate 1, thereby improving process manufacturing efficiency.

[0123] It can be understood that the source and drain of the semiconductor pillar 10 are relative concepts, and the source and drain can be any surface of the semiconductor pillar 10 along the third direction Z.

[0124] Among them, a capacitor structure 70 and a transistor constitute a DRAM storage unit. By turning the transistor on and off, the connected capacitor structure 70 is selected and deselected, and the selected storage unit can be read, written, or erased. The embodiment of the present application does not limit the number of capacitor structures 70 and transistors. A capacitor array 71 can be coupled with a transistor array (including multiple transistors arranged in a first direction X and a second direction Y) to form a DRAM array storage structure.

[0125] It is understandable that the source and drain of a transistor are relative concepts, which are related to the way the transistor is actually connected to the circuit, and have nothing to do with the physical location of the source and drain in the transistor. In some examples, when the transistor is connected to the circuit, the input end of the transistor connected to the circuit can be used as the source, and the output end can be used as the drain, and carriers flow from the source to the drain. In order to better explain the coupling relationship between the capacitor structure 70 and the transistor in the embodiment of the present application, the end of the transistor coupled to the capacitor structure 70 is used as the drain, and the source of the transistor can be coupled to the bit line BL to which the operating voltage is applied.

[0126] The present invention also provides a method for manufacturing a semiconductor device 100. The semiconductor device 100 in the above embodiment can be manufactured by the following method for manufacturing a semiconductor device 100. FIG37 is a flow chart of the method for manufacturing a semiconductor device 100 in the embodiment of the present invention, as shown in FIG37, including:

[0127] S100 , forming a plurality of semiconductor pillars 10 , and arranging the plurality of semiconductor pillars 10 in an array in a first direction X and a third direction Y and extending in a third direction Z, wherein the first direction X, the second direction Y, and the third direction Z intersect with each other.

[0128] In some embodiments, the step of forming the plurality of semiconductor pillars 10 includes:

[0129] S110 , providing a substrate 1 .

[0130] In some specific examples, substrate 1 is a material used to manufacture semiconductor device 100. The material of substrate 1 may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. Substrate 1 may include a wafer formed by grinding, polishing, and slicing cylindrical single crystal silicon.

[0131] In some specific examples, before forming the isolation trench K1 in step S120, a first dielectric layer 14 covering the substrate 1 is first deposited along the third direction Z, and then a second oxide layer (liner oxide) 13 covering the first dielectric layer 14 is deposited along the third direction Z under high temperature conditions to repair the surface of the substrate 1, so as to form a structure in which the substrate 1, the first dielectric layer 14, and the second oxide layer 13 are stacked in sequence along the third direction Z as shown in Figures 3 and 4.

[0132] In some specific examples, the constituent materials of the second oxide layer 13 and the first dielectric layer 14 may include any one or more of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.

[0133] S120, forming a plurality of isolation trenches K1 extending along the third direction Y and spaced apart along the first direction X in the substrate 1 as shown in FIG5 and FIG6, and filling the inner walls of the isolation trenches K1 with a dielectric material 42;

[0134] In some specific examples, multiple isolation trenches K1 may be formed in the substrate 1, or multiple isolation trenches K1 may be formed in the structure shown in Figures 3 and 4 as shown in Figures 5 and 6. As shown in Figures 5 and 6, the multiple isolation trenches K1 extend along the second direction Y and are arranged at intervals along the first direction X, and the isolation trenches K1 extend along the third direction Z but do not penetrate the substrate 1.

[0135] The step of forming the isolation trench K1 includes etching the surface of the second oxide layer 13 as shown in FIG4 to form isolation trenches K1 extending along the third direction Y and spaced apart along the first direction X. The isolation trenches K1 may extend along the third direction Z to the substrate 1 but do not penetrate the substrate 1. As shown in FIG5 and FIG6 , during the etching process, a mask (not shown) may be used to cover portions of the surface of the substrate 1 or the second oxide layer 13, i.e., the areas where the isolation trenches K1 are to be formed. The surface of the substrate 1 is then etched along the thickness direction of the substrate 1 (i.e., the third direction Z). Outside the areas covered by the mask, portions of the substrate 1, the first dielectric layer 14, and the second oxide layer 13 are etched away, forming grooves of a certain depth, i.e., the isolation trenches K1 described above. It should be noted that the etching depth for forming the isolation trenches K1 is less than the initial thickness of the substrate 1, i.e., the etching process does not penetrate the substrate 1.

[0136] In some specific examples, etching can be performed using processes such as photolithography (PH) or dry etching (ET), for example, electron beam lithography, plasma etching, or reactive ion etching, which is not limited in some embodiments of the present application.

[0137] In some embodiments of the present application, by etching the entire surface of the substrate 1 to simultaneously form a plurality of isolation trenches K1 having the same depth, the manufacturing process can be simplified and the efficiency can be improved.

[0138] In some specific examples, FIG7 is a top view of a dielectric material 42 deposited in an isolation trench K1 according to some embodiments of the present application, and FIG8 is a cross-sectional view of a dielectric material 42 deposited in an isolation trench K1 according to some embodiments of the present application. After forming the isolation trench K1 as shown in FIG5 and FIG6 , as shown in FIG7 and FIG8 , a dielectric material 42 is deposited in the isolation trench K1 using a deposition process.

[0139] In some embodiments, dielectric material 42 includes but is not limited to any one of silicon nitride, silicon oxide, or silicon oxynitride, or any combination thereof. Silicon oxide herein refers to a silicon oxide compound, such as SixOy, and silicon nitride refers to a silicon nitrogen compound, such as SixNy.

[0140] Since isolation trenches K1 are formed as shown in Figures 5 and 6, and multiple isolation trenches K1 are arranged at intervals along the first direction X, there will be a raised structure 211 between the isolation trenches K1 formed by removing a portion of the semiconductor material in the substrate 1, which is used to separate two adjacent isolation trenches K1. It should be noted that during the actual deposition of the dielectric material 42, the dielectric material 42 will cover the surface of the raised structure 211. As shown in Figure 7, the dielectric material 42 is filled around each raised structure 211. In addition, after the deposition is completed, a chemical mechanical polishing (CMP) process can be used to polish away excess dielectric material 42 to achieve planarization.

[0141] In some embodiments of the present application, the deposition method of the dielectric material 42, the first dielectric layer 14, and the second oxide layer 13 can be, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0142] S130 , as shown in FIG. 9 and FIG. 10 , a plurality of gate trenches K2 extending along the first direction X and spaced apart along the third direction Y are formed, and the plurality of semiconductor pillars 10 extending along the first direction X and spaced apart along the third direction Y and extending in the third direction Z are formed.

[0143] In some specific examples, after the dielectric material 42 is filled in the isolation trench K1, as shown in Figures 9 and 10, gate trenches K2 extending along the first direction X and arranged at intervals along the second direction Y are formed in the substrate 1, and the semiconductor pillars 10 are located between adjacent gate trenches K2 along the second direction Y. Since the isolation trench K1 filled with the dielectric material 42 extends along the second direction Y and is arranged at intervals along the first direction X, and the gate trenches K2 extend along the first direction X and are arranged at intervals in the second direction Y, the isolation trench K1 filled with the dielectric material 42 can be divided into a plurality of semiconductor pillars 10 arranged in an array in the first direction X and the third direction Y and extending in the third direction Z through the gate trenches K2.

[0144] In some specific examples, the dimensions of the plurality of gate trenches K2 spaced apart in the second direction Y along the first direction X may be the same or different. For example, as shown in FIG9 and FIG10 , the gate trenches K2a and the gate trenches K2b are spaced apart and staggered along the third direction Y, and the dimension of the gate trench K2a along the first direction X is greater than the dimension of the gate trench K2b along the first direction X.

[0145] In some specific examples, the size of the gate trench K2 formed by etching along the second direction Y is equal to the size of the semiconductor pillar 10 along the third direction Y.

[0146] S200, forming a gate bar 30 and a shield bar 20 between adjacent semiconductor pillars 10, and making the gate bar 30 and the shield bar 20 extend along the first direction X and be spaced apart in the third direction Y; and

[0147] In some embodiments, the step of forming a gate strip 30 and a shield strip 20 includes:

[0148] S210 , as shown in FIG. 11 and FIG. 12 , forming a first oxide layer 41 in the sidewall of the gate trench K2 .

[0149] In some specific examples, as shown in Figures 9 and 10, after the gate trench K2 is formed, a first oxide layer 41 can be formed in the sidewalls of the gate trench K2, as shown in Figures 11 and 12. The first oxide layer 41 can be a silicon oxide layer formed using a thermal oxidation method (RTO, Rapid Thermal Oxidation) or an in-situ steam generation method (ISSG, In-situ Stream Generation). As shown in Figures 11 and 12, the exposed sidewalls of the semiconductor pillar 10 are oxidized through the gate trench K2 to form the first oxide layer 41 in the sidewalls of the semiconductor pillar 10, i.e., the sidewalls of the gate trench K2. The process of oxidizing the sidewalls of the semiconductor pillar 10 exposed in the gate trench K2 includes, but is not limited to, direct oxidation, alkaline oxidation, or acidic oxidation.

[0150] In some embodiments of the present application, direct oxidation is performed by heating, causing the silicon on the sidewalls of the semiconductor pillar 10 to chemically react with a gas containing an oxidizing substance at high temperature, thereby producing a dense silicon dioxide film on the silicon surface, forming a first oxide layer 41 located on the sidewalls of the semiconductor pillar 10. The first oxide layer 41 includes an insulating material such as silicon oxide or silicon oxynitride.

[0151] S220 , as shown in FIG. 13 and FIG. 14 , forming a conductive layer 66 on the sidewall of the first oxide layer 41 .

[0152] In some specific examples, a conductive layer 66 is deposited on the sidewalls of the first oxide layer 41 , and the material of the conductive layer includes but is not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof.

[0153] In some embodiments, the conductive material may be deposited by methods including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0154] S230, as shown in Figures 15 and 16, remove the portion of the conductive layer 66 located on the side wall of the first oxide layer 41 and close to the substrate 1 along the third direction Z, and the connecting portions located at the two ends of the gate trench K2 in the first direction X, to form the separated gate bars 30 and the shielding bars 20.

[0155] S300 , forming a barrier strip 90 at one end of the shielding strip 20 along the third direction Z. The barrier strip 90 extends along the first direction X and is located on the same side of the shielding strip 20 and the gate strip 30 in the third direction Z.

[0156] In some specific examples, the gate strip 30 and the shield strip 20 formed in the gate trench K2 are adjacent in the third direction Y, and the gate strip 30 and the shield strip 20 are respectively located on one side of the adjacent semiconductor pillar 10. For example, as shown in FIG28 , a semiconductor pillar 10a is adjacent to a semiconductor pillar 10b in the third direction Y. A gate strip 30 and a shield strip 20 are provided between the semiconductor pillars 10a and 10b, and the gate strip 30 is located on a side closer to the semiconductor pillar 10b along the third direction Y. The shield strip 20 of the gate strip 30 is located on a side closer to the semiconductor pillar 10a along the third direction Y.

[0157] The steps of forming the barrier strip 90 specifically include: as shown in Figure 23, depositing an isolation layer 80 along the third direction Z at the end of the semiconductor column 10 away from the capacitor array 71; as shown in Figure 24, doping the exposed gate strip 30 and the shield strip 20 with N-type doping, for example, by a process such as ion implantation (IMP Process). The above-mentioned N-type doping may include any suitable N-type dopant (for example, phosphorus (P), arsenic (Ar) or antimony (Sb)) to contribute free electrons and increase the conductivity of the gate strip 30 and the shield strip 20. As shown in Figure 25, a barrier layer 92 covering the semiconductor column 10, the gate bar 30 and the shielding bar 20 is formed based on a deposition process. The barrier layer 92 extends along the second direction Y. The portion of the barrier layer 92 in Figure 25 connected to the shielding bar 20 is removed to form a groove K3 as shown in Figure 26. After removing the portion connected to the shielding bar 20, the remaining barrier layer 92 forms a barrier bar 90 extending along the first direction X as shown in Figure 26. In the third direction Z, the barrier bar 90 is connected to one end of the shielding bar 20, and the barrier bar 90 is at the same end of the shielding bar 20 and the gate bar 30 in the third direction Z.

[0158] In some embodiments of the present application, two electrodes, namely a first electrode and a second electrode, are formed between adjacent semiconductor pillars 10. At the same end of the first electrode and the second electrode in the third direction Z, a barrier strip 90 extending along the first direction X and connected to the second electrode is formed. In this way, the first electrode can serve as the gate strip 30, and the second electrode can serve as the shielding strip 20. The barrier strip 90 can be used to form the shielding strip 20 at the same time as the gate strip 30, so that the interference of the gate strip 30 on the adjacent semiconductor pillars 10 can be shielded, thereby reducing the coupling effect between the adjacent semiconductor pillars 10.

[0159] In some embodiments, the manufacturing method further includes: as shown in FIG. 15 , FIG. 17 and FIG. 18 , filling the gate trench K2 with an isolation material 55 , and allowing the isolation material 55 to cover the gate strip 30 and the shielding strip 20 to form an isolation structure 50 .

[0160] In some specific examples, the material of the isolation material 55 includes, but is not limited to, any one of silicon nitride, silicon oxide, or silicon oxynitride, or any combination thereof. The deposition method of the isolation material 55 can be, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD).

[0161] In some embodiments, the manufacturing method further comprises:

[0162] As shown in FIG19 , a capacitor array 71 is formed at the other end of the semiconductor pillar array in the third direction Z, and the capacitor array 71 includes a plurality of capacitor structures 70 arranged in an array along the first direction X and the second direction Y and extending in the third direction Z. The capacitor structure 70 includes a first electrode layer (not shown in the figure) connected to the other end of the semiconductor pillar 10 in the third direction Z, and a capacitor dielectric layer (not shown in the figure) and a second electrode layer (not shown in the figure) located within the first electrode layer.

[0163] In some specific examples, as shown in FIG19 , a capacitor array 71 is formed at the other end of the semiconductor pillar array in the third direction Z. As shown in FIG20 , a portion of the substrate 1 away from the capacitor array 71 along the third direction Z is removed.

[0164] In some embodiments, the manufacturing method further comprises:

[0165] As shown in Figures 21 and 22, the end of the substrate 1 in the third direction Z away from the capacitor array 71 and the isolation structure 50 at the bottom of the gate trench K2 are removed, thereby exposing one end of the gate bar 30 in the third direction Z and one end of the shielding bar 20 in the third direction Z.

[0166] In some specific examples, as shown in FIG21 , a process such as photolithography (PH) or dry etching (ET) can be used to remove the end of the substrate 1 away from the capacitor array 71 in the third direction Z. Then, as shown in FIG22 , a portion of the isolation material 55 in the isolation structure 50 away from the capacitor array 71 along the third direction Z, i.e., the bottom portion 56 of the isolation structure 50, can be removed by dry etching or wet etching. The bottom portion 56 of the isolation structure 50 covers the end of the gate strip 30 away from the capacitor array 71 in the third direction Z, and covers the end of the shield strip 20 away from the capacitor array 71 in the third direction Z. Therefore, removing the bottom portion 56 of the isolation structure 50 can expose the end of the gate strip 30 in the third direction Z and the end of the shield strip 20 in the third direction Z.

[0167] In some embodiments, the manufacturing method further comprises:

[0168] A gate conductive structure 31 is formed at the bottom of the gate trench K2. The gate conductive structure 31 extends along the first direction X and is located at one end of the gate strip 30 and the isolation structure 50 in the third direction Z, and is spaced apart from the one end of the shielding strip 20 in the third direction Z.

[0169] In some specific examples, the groove K3 is located at an end of the gate strip 30 and the isolation structure 50 away from the capacitor structure 70 in the third direction Z, and the groove K3 is spaced apart from the end of the shielding strip 20 away from the capacitor structure 70 in the third direction Z. In this way, a gate conductive structure 31 is formed in the groove K3 as shown in FIG26 , and the gate conductive structure 31 as shown in FIG28 can be formed. The material of the gate conductive structure 31 can be found in the above embodiments and will not be described in detail here.

[0170] In some embodiments, the manufacturing method further comprises:

[0171] As shown in FIG. 26 to FIG. 28 , a gate lead contact 32 is formed at one end of the semiconductor pillar array in the third direction Z. The gate lead contact 32 is connected to the gate conductive structure 31 .

[0172] In some specific examples, as shown in FIG29 , an insulating layer 91 is deposited and formed at one end of the semiconductor pillar array, away from the capacitor array 71, in the third direction Z. The insulating layer 91 covers the barrier strips 90 and the gate conductive structure 31. A portion of the insulating layer 91 is removed to form a first trench K4, and a gate lead contact 32 is formed in the first trench K4. The material of the gate lead contact 32 can be found in the above-mentioned embodiments and will not be further described here.

[0173] In some embodiments, the manufacturing method further comprises:

[0174] As shown in Figures 31 and 32, or in Figures 33, 34, and 36, a shielding lead-out contact 21 is formed at one end of the semiconductor pillar array in the third direction Z, and the shielding lead-out contact 21 is connected to the shielding bar 20. A portion of the insulating layer 91 is removed to form a second trench K5, and the shielding lead-out contact 21 is formed in the second trench K5. The material of the shielding lead-out contact 21 can be found in the above-mentioned embodiment and will not be described in detail here.

[0175] In some embodiments, the manufacturing method further comprises:

[0176] As shown in Figures 35 and 36, semiconductor pillar lead-out contacts 11 are formed at one end of the semiconductor pillar array in the third direction Z, and are connected to the semiconductor pillars 10. A portion of the insulating layer 91 is removed to form a third trench K6, and the semiconductor pillar lead-out contacts 11 are formed in the third trench K6. The materials for the semiconductor pillar lead-out contacts 11 can be found in the above-mentioned embodiments and will not be described in detail here.

[0177] As shown in FIG. 26 to FIG. 29 and FIG. 33 to FIG. 34 , in some embodiments, the step of forming a gate lead contact 32 at one end of the semiconductor pillar array in the third direction Z includes:

[0178] A plurality of gate lead contacts 32 are formed, one gate lead contact 32 corresponds to one gate conductive structure 31 , and the plurality of gate lead contacts 32 are synchronously spaced and distributed in a stepped manner along the first direction X and the second direction Y.

[0179] As shown in FIG. 26 to FIG. 29 and FIG. 33 to FIG. 34 , in some embodiments, the step of forming the shielding lead contact 21 at the one end of the semiconductor pillar array in the third direction Z includes:

[0180] A plurality of shielding lead-out contacts 21 are formed, one shielding lead-out contact 21 corresponds to one shielding bar 20 , and the plurality of shielding lead-out contacts 21 are synchronously spaced and distributed in a stepped manner along the first direction X and the second direction Y.

[0181] As shown in Figures 26 to 29 and Figures 33 to 34, in some embodiments, the manufacturing method also includes forming a plurality of gate lead-out contacts 32 and a plurality of shield lead-out contacts 21, one gate lead-out contact 32 corresponds to one gate conductive structure 31, and one shield lead-out contact 21 corresponds to one shielding bar 20, and the plurality of gate lead-out contacts 32 and the plurality of shield lead-out contacts 21 are synchronously staggered and arranged along the first direction X and the second direction Y in a stepped distribution.

[0182] As shown in Figures 31 to 32, in some embodiments, the manufacturing method also includes forming a plurality of gate lead-out contacts and a plurality of shield lead-out contacts, one gate lead-out contact corresponds to one gate conductive structure, and one shield lead-out contact corresponds to one shield strip, and the plurality of gate lead-out contacts and the plurality of shield lead-out contacts are synchronously staggered and arranged along the first direction and the second direction.

[0183] In some embodiments, as shown in FIG. 32 , the step of forming a plurality of semiconductor pillars 10 includes ensuring that a difference between a cross-sectional dimension of the semiconductor pillar 10 in the second direction Y and a spacing dimension between two adjacent semiconductor pillars 10 is smaller than a preset value.

[0184] In some specific examples, before forming the first trench K4 for forming the gate lead contact 32 and the second trench K5 for forming the shield lead contact 21 as shown in FIG33 , a patterned first mask layer (not shown) is formed on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z. The first mask layer has a plurality of first openings (not shown) and second openings (not shown). The first openings are used to form the first trenches K4, and the second openings are used to form the second trenches K5. Openings corresponding to the first trenches K4 and the second trenches K5 are formed in the patterned first mask layer. The openings expose the positions of the first trenches K4 and the second trenches K5 to be etched in a subsequent etching process. That is, the vertical projection of the first openings on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z may at least substantially overlap with the position of the first trench K4, and the vertical projection of the second openings on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z may at least substantially overlap with the position of the second trench K5. By setting the first mask layer, the etching positions of the first trench K4 and the second trench K5 can be quickly and accurately determined, which facilitates etching of the insulating layer 91, thereby forming the gate lead contact 32 in the first trench K4 and the shield lead contact 21 in the second trench K5.

[0185] In some specific examples, before forming the third trench K6 for forming the semiconductor pillar lead contact 11 as shown in FIG34 , a patterned second mask layer (not shown) is formed on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z. The second mask layer has a plurality of third openings (not shown), and the third openings are used to form the third trench K6. Openings corresponding to the second trench K5 are formed in the patterned second mask layer. The openings expose the locations of the third trenches K6 to be etched in a subsequent etching process. That is, the vertical projection of the first openings on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z may at least substantially overlap with the locations of the third trenches K6. The vertical projection of the third openings on the surface of the insulating layer 91 facing away from the capacitor array 71 along the third direction Z may at least substantially overlap with the locations of the third trenches K6. By providing the second mask layer, the etching position of the third trench K6 can be quickly and accurately determined, so as to facilitate etching the insulating layer 91 to form the third trench K6 and further form the semiconductor column lead contact 11 in the third trench K6.

[0186] Some embodiments of the present application provide a semiconductor device 100 and a manufacturing method thereof. Shielding strips 20 are formed between adjacent semiconductor pillars 10 in the semiconductor device 100 formed by the manufacturing method. The shielding strips 20 can prevent interference between adjacent semiconductor pillars 10, thereby reducing the coupling effect between adjacent semiconductor pillars 10.

[0187] Based on the above-mentioned semiconductor device 100 and its manufacturing method, referring to FIG. 38 , an embodiment of the present application further provides a memory 320 , wherein the memory 320 includes:

[0188] The array storage structure 321 includes the semiconductor device 100 of the embodiment shown in Figures 3 to 36; and a peripheral circuit 322, which is connected to the array storage structure 321 to control the bias voltage of the array storage structure 321.

[0189] Based on the above-mentioned semiconductor device 100 and its manufacturing method, referring to Figure 38, an embodiment of the present application also provides a storage system 300, which includes a memory 320 as shown in Figure 38, and a controller coupled to the memory 320, and the controller is used to control the memory to perform data writing and reading operations.

[0190] Specifically, as shown in FIG38 , the storage system 300 includes a controller 310 and one or more memories 320, wherein the memory 320 (3D NAND Flash) includes an array storage structure 321 (array) and a peripheral circuit 322 (periphery circuit), wherein the array storage structure 321 includes any of the semiconductor devices 100 described above. The storage system 300 can communicate with the host 400 through the controller 310, wherein the controller 310 can be connected to the one or more memories 320 via channels in the one or more memories 320. Each memory 320 can be managed by the controller 310 via the channels in the memory 320.

[0191] Specifically, the array storage structure 321 is used to store information, and the peripheral circuit 322 can be located above or below the array storage structure 321, or can be located around the array storage structure 321. The peripheral circuit 322 is used to control the corresponding array storage structure 321. In addition, the semiconductor device 100 can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., without specific limitation. In addition, the semiconductor device 100 of the embodiment of the present application can be a memory 320, or can be part of a peripheral memory, without special limitation.

[0192] The above is a detailed introduction to a semiconductor device 100 and its manufacturing method, memory and storage system 300 provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, wherein: include: A semiconductor column array, the semiconductor column array comprising a plurality of semiconductor columns arranged in an array along a first direction and a second direction and extending in a third direction, wherein the first direction, the second direction, and the third direction intersect each other; A gate bar and a shielding bar are provided between adjacent semiconductor columns along the second direction, and the gate bar and the shielding bar extend along the first direction and are spaced apart in the second direction; as well as, A barrier bar extending along the first direction, connected to one end of the shielding bar in the third direction, and located on the same side of the shielding bar and the gate bar in the third direction.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a gate conductive structure extending along the first direction and located between the one end of the gate bar in the third direction and the barrier bar, and at least partially parallel to the barrier bar.

3. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: a gate lead-out contact located at one end of the semiconductor pillar array in the third direction, wherein the gate lead-out contact is connected to the gate conductive structure.

4. The semiconductor device according to claim 3, wherein: The semiconductor device further includes: a shielding lead-out contact located at the one end of the semiconductor pillar array in the third direction, wherein the shielding lead-out contact is connected to the shielding bar.

5. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a semiconductor column lead-out contact located at the one end of the semiconductor column array in the third direction, wherein the semiconductor column lead-out contact is connected to the semiconductor column.

6. The semiconductor device according to claim 2, wherein: The semiconductor device further comprises: A plurality of gate strips arranged at intervals between rows of semiconductor columns along the second direction; are arranged at intervals between the rows of semiconductor columns along the second direction and are aligned with the plurality of gate strips. A plurality of said shielding strips are arranged in a staggered manner; a plurality of the barrier strips arranged at intervals between the rows of semiconductor pillars along the second direction; and A plurality of the gate conductive structures are arranged at intervals between the rows of semiconductor pillars along the second direction.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises a plurality of gate lead-out contacts, one gate lead-out contact corresponds to one gate conducting structure, and the plurality of gate lead-out contacts are synchronously arranged and spaced along the first direction and the second direction in a stepped distribution.

8. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises a plurality of shielding lead-out contacts, one of the shielding lead-out contacts corresponds to one of the shielding strips, and the plurality of shielding lead-out contacts are synchronously arranged and spaced along the first direction and the second direction in a stepped distribution.

9. The semiconductor device according to claim 6, wherein: The semiconductor device also includes a plurality of gate lead-out contacts and a plurality of shield lead-out contacts, one gate lead-out contact corresponds to one gate conductive structure, one shield lead-out contact corresponds to one shield strip, and the plurality of gate lead-out contacts and the plurality of shield lead-out contacts are synchronously and staggeredly arranged along the first direction and the second direction to form a stepped distribution.

10. The semiconductor device according to claim 6, wherein The semiconductor device also includes a plurality of gate lead-out contacts and a plurality of shield lead-out contacts, one gate lead-out contact corresponds to one gate conductive structure, one shield lead-out contact corresponds to one shielding strip, and the plurality of gate lead-out contacts and the plurality of shield lead-out contacts are arranged in an alternating manner along the second direction.

11. The semiconductor device according to claim 1, wherein The cross-sectional dimension of the semiconductor pillar in the second direction is equal to the spacing dimension between two adjacent semiconductor pillars.

12. The semiconductor device according to claim 1, wherein The difference between the cross-sectional dimension of the semiconductor pillar in the second direction and the spacing dimension between two adjacent semiconductor pillars is smaller than a preset value.

13. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a first oxide layer between the semiconductor column and the gate strip and between the semiconductor column and the shield strip; An isolation structure is located between the gate strips and the shield strips.

14. The semiconductor device according to claim 1, wherein The semiconductor device also includes: a capacitor array located at the other end of the semiconductor column array in the third direction, the capacitor array includes a plurality of capacitor structures arranged in an array along the first direction and the second direction and extending in the third direction, the capacitor structure includes a first electrode layer connected to the other end of the semiconductor column in the third direction, and a capacitor dielectric layer and a second electrode layer located in the first electrode layer.

15. A method for manufacturing a semiconductor device, wherein: include: Forming a plurality of semiconductor pillars, and arranging the plurality of semiconductor pillars in an array in a first direction and a second direction and extending in a third direction, wherein the first direction, the second direction, and the third direction intersect each other; forming a gate bar and a shield bar between adjacent semiconductor columns, and making the gate bar and the shield bar extend along the first direction and be spaced apart in the second direction; and, A blocking bar is formed at one end of the shielding bar along the third direction. The blocking bar extends along the first direction and is located on the same side of the shielding bar and the gate bar in the third direction.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The step of forming a plurality of semiconductor pillars comprises: providing a substrate; forming a plurality of isolation trenches extending along the second direction and arranged at intervals along the first direction in the substrate, and filling the inner walls of the isolation trenches with dielectric material; A plurality of gate trenches extending along the first direction and arranged at intervals along the second direction are formed, and a plurality of semiconductor pillars extending along the first direction, arranged at intervals along the second direction and extending in the third direction are formed.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The step of forming a gate strip and a shield strip comprises: forming a first oxide layer in the sidewalls of the gate trench; forming a conductive layer in the sidewalls of the first oxide layer; The conductive layer located on the sidewall of the first oxide layer and close to the substrate along the third direction and the connecting portions located at both ends of the gate trench in the first direction are removed to form the separated gate bars and shield bars.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The manufacturing method further includes: filling the gate trench with an isolation material, and allowing the isolation material to cover the gate bar and the shielding bar to form an isolation structure.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The production method further comprises: A capacitor array is formed at the other end of the semiconductor column array in the third direction, and the capacitor array includes a plurality of capacitor structures arranged in an array along the first direction and the second direction and extending in the third direction, and the capacitor structure includes a first electrode layer connecting the other end of the semiconductor column in the third direction, and a capacitor dielectric layer and a second electrode layer located in the first electrode.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The production method further comprises: The end of the substrate in the third direction away from the capacitor array and the isolation structure at the bottom of the gate trench are removed to expose one end of the gate bar in the third direction and one end of the shielding bar in the third direction.

21. The method for manufacturing a semiconductor device according to claim 20, wherein: The production method further comprises: A gate conductive structure is formed at the bottom of the gate trench, extending along the first direction and located at one end of the gate bar and the isolation structure in the third direction and spaced apart from the one end of the shielding bar in the third direction.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: The production method further comprises: A gate lead-out contact is formed at one end of the semiconductor column array in the third direction, and the gate lead-out contact is connected to the gate conductive structure.

23. The method for manufacturing a semiconductor device according to claim 17, wherein: The production method further comprises: A shielding lead-out contact is formed at the one end of the semiconductor pillar array in the third direction, and the shielding lead-out contact is connected to the shielding bar.

24. The method for manufacturing a semiconductor device according to claim 15, wherein: The production method further comprises: A semiconductor column lead-out contact is formed at the one end of the semiconductor column array in the third direction, and the semiconductor column lead-out contact is connected to the semiconductor column.

25. The method for manufacturing a semiconductor device according to claim 22, wherein: The step of forming a gate lead contact at one end of the semiconductor column array in the third direction comprises: A plurality of gate lead-out contacts are formed, one gate lead-out contact corresponds to one gate conductive structure, and the plurality of gate lead-out contacts are synchronously arranged and spaced along the first direction and the second direction in a stepped distribution.

26. The method for manufacturing a semiconductor device according to claim 23, wherein: The step of forming a shielding lead contact at the one end of the semiconductor pillar array in the third direction comprises: A plurality of shielding lead-out contacts are formed, one of the shielding lead-out contacts corresponds to one of the shielding strips, and the plurality of shielding lead-out contacts are synchronously arranged and spaced along the first direction and the second direction in a stepped distribution.

27. The method for manufacturing a semiconductor device according to claim 21, wherein: The manufacturing method also includes forming a plurality of gate lead-out contacts and a plurality of shield lead-out contacts, wherein one gate lead-out contact corresponds to one gate conductive structure, and one shield lead-out contact corresponds to one shield strip, and the plurality of gate lead-out contacts and the plurality of shield lead-out contacts are synchronously and staggeredly arranged along the first direction and the second direction to form a stepped distribution.

28. The method for manufacturing a semiconductor device according to claim 15, wherein: The step of forming a plurality of semiconductor pillars includes making the difference between the cross-sectional dimension of the semiconductor pillar in the second direction and the spacing dimension between two adjacent semiconductor pillars smaller than a preset value.

29. A memory, wherein: The memory comprises: An array storage structure, the array storage structure comprising the semiconductor device according to claims 1 to 14; and A peripheral circuit is connected to the array storage structure to control the bias voltage of the array storage structure.

30. A storage system, wherein: include: The memory as claimed in claim 29; as well as A controller is coupled to the memory, and is used to control the memory to perform data writing and reading operations.

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