Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Abstract

A semiconductor device is provided with: a first pillar region (13) of a second conductivity type formed below a plurality of gate trenches (6) in which gate electrodes (8) are embedded; and second pillar regions (14) of the first conductivity type, which are formed between adjacent first pillar regions (13), and which have a higher impurity peak concentration than the drift layer (2). The second column region (14) includes a high-concentration region (14a) and a low-concentration region (14b) that is provided on at least one side of the second column region (14) and that has a lower impurity peak concentration than the high-concentration region (14a).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular to a trench gate semiconductor device. Background Art

[0002] In power electronics, it is necessary to switch on and off the power supply in order to drive loads such as electric motors. To do this, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon are used.

[0003] Among the switching devices that are supposed to be used as power semiconductor devices, MOSFET and IGBT with vertical structures are often used, and they are respectively called "vertical MOSFET" and "vertical IGBT". In addition, in vertical MOSFET and vertical IGBT, there are planar gate type and trench gate type according to the gate structure.

[0004] In a trench-gate MOSFET having a trench (hereinafter referred to as a "gate trench") in which a gate electrode is buried in an active region of a drift layer of a first conductive type (e.g., n-type), due to its structure, a high electric field is applied to a gate insulating film at the bottom of the gate trench when the gate is turned off, and there is a possibility that the gate insulating film is destroyed at the bottom of the gate trench.

[0005] As a technology for solving this problem, for example, Patent Document 1 discloses a technology for relaxing the electric field of the gate insulating film applied to the bottom surface of the gate trench by providing a "trench bottom protection layer" as an electric field relaxation region of the second conductivity type (e.g., p-type) in a manner covering the bottom surface of the gate trench. Furthermore, in Patent Document 1, a "depletion suppression layer" as a current diffusion layer of the first conductivity type is provided on the side of the gate trench to prevent the path of the conduction current between the gate trenches from becoming narrow due to the trench bottom protection layer, thereby reducing the conduction loss during conduction. The depletion suppression layer of Patent Document 1 is formed by injecting the first conductivity type impurities that serve as donors into the side surface of the gate trench using oblique ion implantation.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent No. 6377309 Summary of the invention

[0009] When the trench bottom protection layer and the depletion suppression layer are extended to the depth of the drift layer and used as the p-type column region and the n-type column region of the semi-superjunction structure, the trench gate type MOSFET can be made low in resistance and high in withstand voltage. In addition, the semi-superjunction structure refers to a superjunction structure in which the p-type column region and the n-type column region are formed to a depth midway in the semiconductor layer.

[0010] However, when an n-type column region as a depletion suppression layer is formed at a shallow position of a gate trench by oblique ion implantation, if the width and depth of the gate trench vary, many donors (n-type dopants) are implanted into the p-type column region as a trench bottom protection layer. In this case, it is difficult to achieve charge balance between the p-type column region and the n-type column region, resulting in variations in the withstand voltage characteristics of the semiconductor device, and thus it is not possible to fully obtain the effects of lowering resistance and increasing withstand voltage by the semi-superjunction structure.

[0011] The present disclosure has been made to solve the above problems, and an object of the present disclosure is to suppress the dopant in the second pillar region from being implanted into the first pillar region under the gate trench in a semiconductor device having a half super junction structure.

[0012] The semiconductor device involved in the present disclosure comprises: a semiconductor layer; a drift layer of the first conductivity type, formed in the semiconductor layer; a well region of the second conductivity type, formed in the surface portion of the semiconductor layer; a source region of the first conductivity type, formed in the surface portion of the well region; a source electrode, electrically connected to the well region and the source region; a plurality of gate trenches, penetrating the source region and the well region, and buried with gate electrodes via a gate insulating film; a first column region of the second conductivity type, formed below the plurality of gate trenches; and a second column region of the first conductivity type, formed between adjacent first column regions, the peak concentration of impurities being higher than that of the drift layer, the second column region comprising a high concentration region and a low concentration region, which is arranged on the side of at least one side of the second column region and has a lower peak concentration of impurities than that of the high concentration region.

[0013] According to the semiconductor device disclosed herein, it is possible to suppress the dopant of the second column region from being injected into the first column region under the gate trench, thereby preventing the charge balance between the first column region and the second column region from being destroyed, and contributing to lower resistance and higher withstand voltage through the half-superjunction structure.

[0014] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a cross-sectional view schematically showing the structure of the semiconductor device according to the first embodiment.

[0016] Figure 2 This is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment.

[0017] Figure 3 This is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment.

[0018] Figure 4 This is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment.

[0019] Figure 5 This is a cross-sectional view schematically showing the structure of a semiconductor device according to a modification of the first embodiment.

[0020] Figure 6 This is a cross-sectional view schematically showing the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Figure 7 This is a cross-sectional view schematically showing the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Figure 8 This is a cross-sectional view schematically showing the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig. 9 This is a plan view schematically showing the structure of a semiconductor device according to the second embodiment.

[0024] Fig.10 It is along Fig. 9 A cross-sectional view of the A1-A2 line.

[0025] Fig.11 It is along Fig. 9 Cross-sectional view of line B1-B2.

[0026] Fig.12 It is along Fig. 9 Cross-section of the C1-C2 line.

[0027] Fig.13 This is a cross-sectional view schematically showing the structure of a semiconductor device according to the third embodiment.

[0028] Fig.14 This is a plan view schematically showing the structure of a semiconductor device according to a fourth embodiment.

[0029] Fig.15 It is along Fig.14 A cross-sectional view of the A1-A2 line.

[0030] Fig.16 It is along Fig.14 Cross-sectional view of line B1-B2.

[0031] Fig.17 It is along Fig.14 Cross-section of the C1-C2 line.

[0032] Fig.18 This is a block diagram showing the configuration of a power conversion system according to the fifth embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, with reference to the accompanying drawings, embodiments of the technology disclosed herein will be described. In addition, the accompanying drawings are schematically shown, and the dimensions and positions of the components shown in different drawings may not be correctly recorded and may be appropriately changed. In addition, in different drawings, the same symbols are also attached to the components that are identical or corresponding to each other, and repeated descriptions of them are sometimes omitted. In addition, the terms "upper", "lower", "side", "bottom", "top" or "back" in the description, which mean position or direction, are used for ease of understanding and may not necessarily indicate the position or direction in actual use.

[0034] In the following embodiments, the first conductivity type is set to the n type and the second conductivity type is set to the p type. However, conversely, the first conductivity type may be set to the p type and the second conductivity type may be set to the n type.

[0035] <Implementation Method 1>

[0036] Figure 1 1 is a cross-sectional view schematically showing the structure of a semiconductor device according to Embodiment 1. In Embodiment 1, a vertical trench gate type silicon carbide MOSFET is shown as an example of a semiconductor device. The semiconductor device according to Embodiment 1 has an active region formed by arranging MOSFET cells (active cells) and a terminal region outside the active region, but Figure 1 The structure of the active region is shown.

[0037] The semiconductor device according to the first embodiment is formed using an n-type (first conductivity type) semiconductor substrate 1 composed of silicon carbide having a polytype of 4H. A semiconductor layer 20 composed of silicon carbide is formed on the semiconductor substrate 1. The upper surface of the semiconductor substrate 1 is a (0001) plane having an off-angle θ inclined in the [11-20] axis direction. The off-angle θ may be 10° or less. In the semiconductor layer 20, an n-type drift layer 2 having a lower peak concentration of impurities than the semiconductor substrate 1 is formed.

[0038] In the active region, a p-type (second conductivity type) well region 3 is formed in the surface portion of the semiconductor layer 20. In the surface portion of the well region 3, an n-type source region 4 and a p-type well contact region 5 having a higher peak concentration of impurities than the well region 3 are selectively (i.e., partially) formed. The well contact region 5 is provided in contact with the source region 4 so that a source electrode 10 described later and the well region 3 are electrically connected.

[0039] In addition, in the semiconductor layer 20, a gate trench 6 is formed in a manner penetrating the source region 4 and the well region 3. A gate insulating film 7 is formed on the side and bottom of the gate trench 6. On the gate insulating film 7, a gate electrode 8 is formed in a manner buried in the gate trench 6. The upper surface of the gate electrode 8 is located at a position deeper than the surface of the semiconductor layer 20. That is, the upper surface of the gate electrode 8 is located at a position deeper than the upper end of the gate trench 6. In the upper part of the gate trench 6, an interlayer insulating film 9 is formed in a manner covering the gate electrode 8.

[0040] In the present embodiment, the gate trench 6 penetrates the source region 4, so the edge portion of the gate trench 6 in the semiconductor layer 20 becomes the source region 4. However, the gate electrode 8 is not formed at the upper end portion of the gate trench 6, and the gate insulating film 7 at this portion is covered by the interlayer insulating film 9. Therefore, at the edge portion of the gate trench 6, the source region 4 and the gate electrode 8 are not facing each other.

[0041] A source electrode 10 is formed on the semiconductor layer 20. The source electrode 10 is electrically connected to the source region 4 and the well region 3. In the present embodiment, a silicide layer 15 is formed on the surface of the source region 4 and the well contact region 5, and a barrier metal 16 is provided on the bottom surface of the source electrode 10. Therefore, the source electrode 10 is connected to the source region 4 and the well contact region 5 via the silicide layer 15 and the barrier metal 16. Furthermore, a drain electrode 11 electrically connected to the semiconductor substrate 1 is formed on the lower surface of the semiconductor substrate 1.

[0042] A p-type trench bottom protection layer 12 is formed at the bottom of the gate trench 6 in the semiconductor layer 20. The trench bottom protection layer 12 is electrically connected to the source electrode 10. The trench bottom protection layer 12 functions to relieve the electric field applied to the bottom and side surfaces of the gate trench 6 when the MOSFET is turned off. The trench bottom protection layer 12 is preferably in contact with the gate trench 6.

[0043] The semiconductor layer 20 has a half-superjunction structure in which p-type column regions 13 as p-type first column regions and n-type column regions 14 as n-type second column regions are alternately arranged. The p-type column regions 13 are formed below the trench bottom protection layer 12, and the n-type column regions 14 are formed between adjacent p-type column regions 13.

[0044] In the present embodiment, the n-type column region 14 includes a high-concentration n-type column region 14a as a high-concentration region and a low-concentration n-type column region 14b as a low-concentration region (for ease of illustration, the high-concentration n-type column region 14a in each figure is shaded with a sand hole pattern). The peak concentration of impurities in the high-concentration n-type column region 14a is higher than the peak concentration of impurities in the low-concentration n-type column region 14b. The low-concentration n-type column region 14b is disposed at least a portion of the side portion of the n-type column region 14 (i.e., the portion in contact with the p-type column region 13). Hereinafter, the side portion of the n-type column region 14 is sometimes referred to as the "side portion of the high-concentration n-type column region 14a".

[0045] The n-type column region 14 is sandwiched between the two p-type column regions 13, so there are two side portions in the n-type column region 14. The low-concentration n-type column region 14b is formed on at least one of the two side portions of the n-type column region 14. That is, the high-concentration n-type column region 14a may be provided only on one side portion of the high-concentration n-type column region 14a.

[0046] In addition, Figure 1 In the embodiment, the width of the upper portion and the width of the bottom portion of the low concentration n-type column region 14b are the same, but it may also be possible, for example, as follows Figure 2 As shown, the upper surface or the side surface of the low-concentration n-type column region 14 b is inclined so that the width of the bottom of the low-concentration n-type column region 14 b is wider than the width of the upper portion.

[0047] The details will be described later. The gate trench 6 is formed by performing an oblique ion implantation on the side surfaces of the gate trench 6, that is, by implanting ions in a direction oblique to the depth direction of the semiconductor layer 20. Figure 1 as well as Figure 2 The structures of the high-concentration n-type column region 14a and the low-concentration n-type column region 14b are shown.

[0048] However, the n-type column region 14 composed of the high-concentration n-type column region 14a and the low-concentration n-type column region 14b can also be formed by only performing the oblique ion implantation on one side of the gate trench 6. Figure 3 , Figure 4 or Figure 5 As shown, the bottom of the n-type column region 14 is inclined, and the depth of the n-type column region 14 becomes asymmetric left and right. Figure 3 This is an example in which a high-concentration impurity is implanted from the side surface of the gate trench 6 serving as the implantation surface to a position in the middle between adjacent gate trenches 6 in the oblique ion implantation to form the low-concentration n-type column region 14 b . Figure 4 This is an example of forming a low-concentration n-type column region 14 b by implanting high-concentration impurities at a deep position (near the trench bottom protection layer 12 and the p-type column region 13 under the adjacent gate trench 6 ) from the side surface of the gate trench 6 as the implantation surface for oblique ion implantation. Figure 5 This is an example of forming a low-concentration n-type column region 14 b by implanting high-concentration impurities at a shallow position (near the trench bottom protection layer 12 and the p-type column region 13 under the gate trench 6 ) from the side surface of the gate trench 6 as the implantation surface for oblique ion implantation.

[0049] Regarding the positional relationship between the p-type column region 13 and the n-type column region 14 in the depth direction from the upper surface of the semiconductor layer 20, in order to avoid current narrowing between adjacent p-type column regions 13, the depth of the lower end of the high-concentration n-type column region 14a or the low-concentration n-type column region 14b is preferably the same as the lower end of the p-type column region 13, or at a deeper position than it.

[0050] In addition, the p-type column region 13 and the n-type column region 14 are preferably formed to a position deeper than the distance between adjacent gate trenches 6 or a position deeper than the distance between adjacent p-type column regions 13, based on the position of the bottom of the gate trench 6. That is, the depth from the bottom of the gate trench 6 to the lower end of the p-type column region 13 and the depth from the bottom of the gate trench 6 to the lower end of the n-type column region 14 are preferably longer than the distance between adjacent gate trenches 6 or the distance between adjacent p-type column regions 13.

[0051] The following explains Figure 1 A method for manufacturing a semiconductor device according to Embodiment 1 is shown.

[0052] First, on the surface of the n-type semiconductor substrate 1 having a polytype of 4H, a relatively high resistance n-type (n - The semiconductor layer 20 composed of silicon carbide (type) is epitaxially grown. At this time, the semiconductor layer 20 has a thickness of 1×10 14 [cm -3 ] and above and 1×10 17 [cm -3 ] can be formed in a manner having an n-type impurity concentration below.

[0053] Next, reactive ion etching (RIE) is performed to form an alignment mark in the semiconductor layer 20 . The alignment mark may be formed simultaneously with the gate trench 6 .

[0054] Then, using the alignment mark as a reference, a p-type well region 3 and an n-type region (n) with relatively low resistance are formed in the surface layer of the semiconductor layer 20 by ion implantation. + As an implantation mask for selectively forming the source region 4 by ion implantation, for example, a resist mask or the like can be used.

[0055] The source region 4 is formed to have a 5×10 18 [cm-3 ] and above and 5×10 20 [cm -3 ] or less, the well region 3 is formed to have an n-type impurity concentration of 1×10 16 [cm -3 ] and above and 3×10 19 [cm -3 ] or less. In addition, in order to form the source region 4 in the surface portion of the well region 3, the n-type impurity concentration of the source region 4 is set higher than the p-type impurity concentration of the well region 3. At this time, the n-type region in the semiconductor layer 20 where the well region 3 and the source region 4 are not formed is left as the drift layer 2.

[0056] The impurity concentration of the well region 3 may be constant in the depth direction or may be non-constant. For example, the concentration may be low in the surface portion of the well region 3 or may be peaked in the deep portion.

[0057] Next, a p-type well contact region 5 is formed by ion implantation. At this time, the well contact region 5 is formed to have a 1×10 19 [cm -3 ] and above and 1×10 22 [cm -3 ] or less p-type impurity concentration.

[0058] Next, an etching mask 18 having a pattern in which a formation region of the gate trench 6 is opened is formed on the semiconductor layer 20 (see Figure 6 ), by RIE using the etching mask 18 , a gate trench 6 is formed in the semiconductor layer 20 that penetrates the well region 3 and reaches the drift layer 2 .

[0059] Next, if Figure 6 As shown, by using the etching mask 18 as an ion implantation mask, a p-type trench bottom protection layer 12 and a p-type column region 13 are formed on the bottom surface of the gate trench 6. At this time, the trench bottom protection layer 12 is formed to have a thickness of 1×10 17 [cm -3 ] and above and 1×10 20 [cm -3 ] or less, and the p-type column region 13 is formed to have a p-type impurity concentration of 1×10 16 [cm -3 ] and above and 1×10 18 [cm -3 ] or less p-type impurity concentration.

[0060] After removing the etching mask 18, an n-type column region 14 consisting of a high-concentration n-type column region 14a and a low-concentration n-type column region 14b is formed under the mesa-shaped semiconductor layer 20 between the gate trenches 6 by oblique ion implantation. Figure 7 As shown in FIG. 1 , n-type impurities are implanted into one side of the gate trench 6 by oblique ion implantation, thereby forming a low-concentration n-type column region 14 b under the mesa-shaped semiconductor layer 20. Figure 8 As shown, n-type impurities are also implanted into the other side of the gate trench 6 by the oblique ion implantation, thereby forming a low-concentration n-type column region 14b under the mesa-shaped semiconductor layer 20. A high-concentration n-type column region 14a is formed in the region where the impurities are implanted overlappingly by the two oblique ion implantations.

[0061] In the oblique ion implantation for forming the high concentration n-type column region 14 a and the low concentration n-type column region 14 b , it is important to implant n-type impurities from the side of each gate trench 6 to the trench bottom protection layer 12 and the vicinity of the p-type column region 13 under the adjacent gate trench 6 .

[0062] In addition, in this oblique ion implantation, the lower surface of the gate trench 6 becomes the rear surface of the mesa-shaped semiconductor layer 20, so that the n-type impurities are suppressed from being injected into the lower surface of the gate trench 6. The donors are suppressed from being injected into the trench bottom protection layer 12 and the p-type column region 13 under the gate trench 6, and a stable charge balance can be achieved. As a structural feature, the concentration of the n-type impurities contained in the p-type column region 13 is lower than the concentration of the n-type impurities contained in the low-concentration n-type column region 14b.

[0063] The high concentration n-type column region 14a is formed to have a 1×10 15 [cm -3 ] and above and 5×10 18 [cm -3 ] or less, the low-concentration n-type column region 14b is formed to have a concentration of 5×10 14 [cm -3 ] and above and 1×10 18 [cm -3 ] or less n-type impurity concentration.

[0064] Thereafter, annealing for activating the implanted ions is performed at a temperature range of 1500° C. to 2200° C. for a period of 0.5 minute to 60 minutes.

[0065] Furthermore, an insulating film is formed on the surface of the semiconductor layer 20 by thermal oxidation or chemical vapor deposition (CVD) and patterned by wet etching or dry etching to form a field insulating film (not shown) for protecting the terminal region.

[0066] Next, the gate insulating film 7 is formed on the surface of the semiconductor layer 20 including the inside of the gate trench 6 by thermal oxidation or CVD.

[0067] Next, polysilicon doped with impurities that are the material of the gate electrode 8 is formed by CVD or the like on the entire surface of the semiconductor layer 20 on which the gate insulating film 7 is formed. At this time, the inside of the gate trench 6 is filled with polysilicon. When polysilicon is formed by CVD, polysilicon grows not only upward but also laterally from the bottom surface of the gate trench 6 in the gate trench 6, so that the gate trench 6 can be filled with polysilicon relatively easily.

[0068] Next, the polysilicon on the surface of the semiconductor layer 20 is removed by etching back. At this time, the polysilicon buried in the gate trench 6 is not removed but remains to form the gate electrode 8. In addition, when the polysilicon on the surface of the semiconductor layer 20 is completely removed, a lot of overetching is required, so the upper surface of the gate electrode 8 in the gate trench 6 becomes a position deeper than the upper end of the gate trench 6.

[0069] Next, an interlayer insulating film 9 is formed so as to cover the terminal region and the gate electrode 8, and the source region 4 and the well contact region 5 are exposed from the interlayer insulating film 9 by dry etching or the like. Furthermore, a silicide layer 15 is formed on the well contact region 5 and the n-type source region 4. Furthermore, a gate contact hole (not shown) reaching the gate electrode 8 is formed in the interlayer insulating film 9 by dry etching or wet etching or the like.

[0070] Thereafter, the source electrode 10 is formed on the semiconductor layer 20. In addition, a gate pad connected to the gate insulating film 7 via a gate contact hole or a wiring for connection to the gate pad is formed.

[0071] Finally, a drain electrode 11 is formed on the lower surface of the semiconductor substrate 1, thereby completing Figure 1 A semiconductor device having the structure shown.

[0072] Hereinafter, effects achieved by the semiconductor device according to the first embodiment will be described.

[0073] First, the effect of the trench bottom protective layer 12 will be described. By providing the trench bottom protective layer 12 below the gate trench 6, the electric field applied to the gate insulating film 7 when the MOSFET is in the off state can be significantly relaxed.

[0074] Next, the effects of the p-type column region 13 and the n-type column region 14 (high-concentration n-type column region 14a, low-concentration n-type column region 14b) are described. By setting the p-type column region 13 and the n-type column region 14 deep into the drift layer 2, the charge balance of the p-type column region 13 and the n-type column region 14 is achieved, and their impurity concentration is greater than that of the drift layer 2, thereby obtaining a super junction effect. That is, when the semiconductor device is turned off, the depletion layer extends laterally between the p-type column region 13 and the n-type column region 14, and the p-type column region 13 and the n-type column region 14 can share an electric field larger than that of the drift layer 2, so that it can contribute to the high withstand voltage of the semiconductor device. In addition, when the semiconductor device is turned on, the n-type column region 14, which has a lower resistance than the drift layer 2, becomes a current path, so it can contribute to the low on-resistance of the semiconductor device.

[0075] Here, the effect obtained by the n-type column region 14 including the high-concentration n-type column region 14a and the low-concentration n-type column region 14b is described. In the above-mentioned super junction effect, the high-concentration n-type column region 14a functions as a current path with lower resistance when turned on, and the low-concentration n-type column region 14b functions as a region with high withstand voltage by making the depletion layer easier to extend when turned off.

[0076] In addition, the effects of the method for forming the high-concentration n-type column region 14a and the low-concentration n-type column region 14b are described. When the high-concentration n-type column region 14a and the low-concentration n-type column region 14b are formed by oblique ion implantation, the lower surface of the gate trench 6 becomes the back of the mesa-shaped semiconductor layer 20, so that n-type impurities are suppressed from being injected into the lower surface of the gate trench 6. Therefore, donors are suppressed from being injected into the trench bottom protection layer 12 and the p-type column region 13 under the gate trench 6, and stable charge balance can be achieved.

[0077] In order to obtain a higher super junction effect, the p-type column region 13 and the n-type column region 14 are preferably formed to a position deeper than the distance between adjacent gate trenches 6 or a position deeper than the distance between adjacent p-type column regions 13 based on the position of the bottom of the gate trench 6 .

[0078] The cell structure formed in the active region of the semiconductor device may be any structure, for example, it may be an uninterrupted stripe shape when viewed from above, or it may be partially lattice-shaped or T-shaped in the form of bridging the gate trench 6. In addition, it may be partially polygonal or wavy.

[0079] The crystal orientation of the side surface of the gate trench 6 may be any crystal plane, that is, it may be any one of the (11-20) plane, (-1120) plane, (1-100) plane, (-1100) plane, etc., without limitation.

[0080] In the first embodiment, the surface of the semiconductor substrate 1 is set to be a (0001) plane having an off-angle θ tilted in the [11-20] axis direction, but even if it is set to be a (000-1) plane having an off-angle θ tilted in the [11-20] axis direction, a trench gate type MOSFET having the same structure can be manufactured and the effect of the first embodiment can be obtained. In addition, it is of course possible to use a (1-100) plane or a (03-38) plane.

[0081] In addition, the semiconductor device is not limited to MOSFET. For example, if Figure 1 The structure of the IGBT is obtained by setting the conductivity type of the semiconductor substrate 1 to a p-type, or by removing the semiconductor substrate 1 and forming a p-type impurity region on the lower surface of the drift layer 2. In this case, the source region 4 corresponds to the emitter region of the IGBT, and the drain electrode 11 corresponds to the collector electrode of the IGBT. Even if the semiconductor device is an IGBT, the same effect as that of the MOSFET can be obtained.

[0082] In Embodiment 1, an example of using silicon carbide (SiC) as a semiconductor material constituting a semiconductor device is shown, but other semiconductor materials may also be used. As semiconductor materials, for example, silicon (Si) and wide bandgap materials may be cited. As wide bandgap materials, in addition to SiC, there are Ga2O3, GaN (Gallium Nitride), diamond, etc.

[0083] Semiconductor devices using wide bandgap materials are particularly expected to be used under high temperature and high withstand voltage. The reliability of the insulating film is easily reduced at high temperature, so the effect of applying embodiment 1 is large. In addition, when the semiconductor device is made to have a high withstand voltage, the voltage applied to the insulating film also increases, so the effect of applying embodiment 1 is increased.

[0084] In addition, in silicon carbide semiconductor devices, it is known that more electron traps are generated at the MOS interface between the gate insulating film 7 and the drift layer 2 than in Si, and the reliability of the MOS interface and the gate insulating film 7 is lower than that of silicon (Si) semiconductor devices. Therefore, the effect of applying embodiment 1 that can reduce the electric field applied to the gate insulating film 7 is greater.

[0085] In the first embodiment, nitrogen, phosphorus, and the like are assumed as n-type impurities, and aluminum, boron, and the like are assumed as p-type impurities.

[0086] <Implementation Method 2>

[0087] Fig. 9 2 is a top view schematically showing the structure of a trench gate MOSFET as a semiconductor device according to Embodiment 2. Fig.10 It is along Fig. 9 The cross-sectional view of the A1-A2 line, Fig.11 It is along Fig. 9 The cross-sectional view of line B1-B2, Fig.12 It is along Fig. 9 Cross-sectional view of the C1-C2 line.

[0088] In implementation mode 2, if Fig.10 As shown, a p-type sidewall well region 17 is formed on a portion of the sidewall of the gate trench 6. The sidewall well region 17 plays a role in electrically connecting the trench bottom protection layer 12 or the p-type pillar region 13 and the well region 3 or the well contact region 5.

[0089] In addition, Fig. 9 In order to more easily understand the configuration of the sidewall well region 17, a part of the structure is omitted. Figure 10~Figure 12 , a cross section of the periodic structure of the unit cell at a position where the cross section includes the gate trench 6 in the active region is shown.

[0090] like Fig.11 As shown, along Fig. 9 In the cross section of the line B1-B2 of FIG. 1 , the sidewall well region 17 is not formed, but the well contact region 5 is formed. Fig.12 As shown, along Fig. 9 In the cross section taken along the line C1-C2 of FIG. 1 , neither the sidewall well region 17 nor the well contact region 5 is formed, and the well region 3 reaches the surface of the semiconductor layer 20. In this way, the semiconductor device according to the second embodiment may have a cross section having a well contact region 5 but without the sidewall well region 17, and a cross section having neither the sidewall well region 17 nor the well contact region 5.

[0091] In addition, in one cross section of the active region of the semiconductor device, Figure 10~Figure 12 Two or more cells of the cross-sectional structure shown. That is, Figure 10~Figure 12 The cross-sectional structures shown may also be local structures. Figure 10~Figure 12 The ratios of the respective cross-sectional structures shown are not restricted and can be designed freely.

[0092] The method for manufacturing the p-type sidewall well region 17 is described. After forming the gate trench 6, p-type impurities are implanted into the sidewalls of the gate trench 6 by oblique ion implantation or the like, thereby forming the sidewall well region 17. The sidewall well region 17 can be formed simultaneously with the trench bottom protection layer 12 or separately. The sidewall well region 17 is formed to have a 1×10 17 [cm -3 ] and above and 1×10 22 [cm -3 ] or less p-type impurity concentration.

[0093] The effect of the sidewall well region 17 is described. The sidewall well region 17 electrically connects the trench bottom protection layer 12 and the p-type column region 13 to the well region 3 or the well contact region 5. As a result, during the switching operation of the MOSFET, a current path for charging and discharging the pn junction formed between the trench bottom protection layer 12 and the p-type column region 13 and the n-type column region 14 and the drift layer 2 is ensured, and the switching loss can be reduced. The sidewall well region 17 is formed only on a part of the sidewall of the gate trench 6, so it does not cause a significant decrease in the channel density, and as a result, the on-resistance can be reduced.

[0094] The gate trench 6 may be formed into a stripe shape parallel to the off-angle direction, and a gate trench 6 having a sidewall without forming the sidewall well region 17 may be formed. In this case, since an inversion channel with uniform channel characteristics is formed, current concentration on a specific channel surface and instability of the threshold voltage are not caused, a device with high operation stability can be realized.

[0095] In Embodiment 2, it is shown that Fig. 9 as well as Fig.10 The example shown in the figure is that the sidewall well region 17 is provided only on the sidewall of one side of the gate trench 6, but the sidewall well region 17 may be provided on the sidewalls of both sides of the gate trench 6, and there is no restriction on the formation position of the sidewall well region 17. However, when the interval between the sidewall well regions 17 is too narrow, it may lead to a decrease in channel density, so the interval between adjacent sidewall well regions 17 is preferably the same as or greater than the interval between adjacent gate trenches 6.

[0096] <Implementation Method 3>

[0097] Fig.13 1 is a top view schematically showing the structure of a trench gate MOSFET as a semiconductor device according to Embodiment 3. In the semiconductor device according to Embodiment 3, the trench bottom protection layer 12 is omitted, and the p-type column region 13 is formed to be in contact with the bottom of the gate trench 6. Therefore, in Embodiment 3, the p-type column region 13 plays the role of the trench bottom protection layer 12 that mitigates the electric field applied to the bottom and side surfaces of the gate trench 6.

[0098] According to the third embodiment, the formation of the trench bottom protection layer 12 can be omitted, so the manufacturing process is simplified and the manufacturing cost of the semiconductor device can be suppressed. In addition, the p-type column region 13 can relieve the electric field applied to the bottom and side surfaces of the gate trench 6 instead of the trench bottom protection layer 12, so the same effect as the first embodiment is obtained.

[0099] <Implementation Method 4>

[0100] Fig.141 is a top view schematically showing the structure of a trench gate MOSFET as a semiconductor device according to Embodiment 4. Fig.15 It is along Fig.14 The cross-sectional view of the A1-A2 line, Fig.16 It is along Fig.14 The cross-sectional view of line B1-B2, Fig.17 It is along Fig.14 Cross-sectional view of the C1-C2 line.

[0101] In implementation mode 4, Fig.14 As shown, the well contact region 5 is formed in a linear shape perpendicular to the gate trench 6. That is, the well contact region 5 is in contact with both adjacent gate trenches 6 and extends across the mesa-shaped semiconductor layer 20 therebetween.

[0102] In the fourth embodiment, the technology of the second embodiment is applied to provide a sidewall well region 17 on a part of the sidewall of the gate trench 6. The sidewall well region 17 plays a role in electrically connecting the trench bottom protection layer 12 or the p-type column region 13 and the well region 3 or the well contact region 5.

[0103] like Fig.15 As shown, along Fig.14 In the cross section taken along the line A1-A2 of FIG. 1 , the sidewall well region 17 is formed to be in contact with the well contact region 5. Fig.16 As shown, along Fig.14 In the cross section of the line B1-B2 of FIG. 1 , the sidewall well region 17 is not formed, but the well contact region 5 is formed. Fig.17 As shown, along Fig. 9 In the cross section taken along line C1 - C2 of , neither the sidewall well region 17 nor the well contact region 5 is formed, and the well region 3 reaches the surface of the semiconductor layer 20 .

[0104] For example, as shown in Implementation 2 Fig. 9 In the top view, when the well contact region 5 is island-shaped, if a deviation occurs in the alignment in the photolithography process, the position of the well contact region 5 relative to the gate trench 6 is offset, and the channel characteristics may be deviated.

[0105] In contrast, in the fourth embodiment, the well contact region 5 is a linear shape orthogonal to the gate trench 6. Therefore, even if a positional deviation occurs during the photolithography process, the position of the well contact region 5 relative to the gate trench 6 is not affected, thereby preventing deviations in channel characteristics.

[0106] In addition, the sidewall well region 17 electrically connects the trench bottom protective layer 12 and the p-type column region 13 to the well contact region 5, so that when the MOSFET is switched, a current path for charging and discharging the pn junction formed between the trench bottom protective layer 12 and the p-type column region 13 and the n-type column region 14 and the drift layer 2 is ensured, thereby reducing switching losses.

[0107] <Implementation method 5>

[0108] Fig.18 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the fifth embodiment is applied. Fig.18 The power conversion system shown includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, for example, it can be composed of a DC system, a solar cell, a storage battery, or a rectifier circuit and an AC / DC converter connected to an AC system. In addition, the power supply 100 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0109] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. Fig.18 As shown, it comprises: a main conversion circuit 201, which converts DC power into AC power and outputs it; a drive circuit 202, which outputs a drive signal for driving each switching element of the main conversion circuit 201; and a control circuit 203, which outputs a control signal of the control drive circuit 202 to the drive circuit 202.

[0110] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, and is used as a motor mounted on various electrical devices, such as a hybrid car, an electric car, a railway vehicle, an elevator, or an air conditioning device.

[0111] The power conversion device 200 is described in detail below. The main conversion circuit 201 includes a switching element and a return diode (not shown), and converts the DC power supplied from the power supply 100 into AC power by switching the switching element, and supplies it to the load 300. The specific circuit structure of the main conversion circuit 201 has various structures, but the main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can include 6 switching elements and 6 return diodes connected in reverse parallel with each switching element. In each switching element of the main conversion circuit 201, the semiconductor device involved in any one of the above-mentioned embodiments 1 to 4 and their modified examples is applied. The 6 switching elements connect each 2 switching elements in series to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminal of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, is connected to the load 300.

[0112] The drive circuit 202 generates a drive signal for driving the switch element of the main conversion circuit 201, and supplies it to the control electrode of the switch element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, the drive signal for turning on the switch element and the drive signal for turning off the switch element are output to the control electrode of each switch element. When the switch element is maintained in the on state, the drive signal is a voltage signal (on signal) higher than the threshold voltage of the switch element, and when the switch element is maintained in the off state, the drive signal is a voltage signal (off signal) lower than the threshold voltage of the switch element.

[0113] The control circuit 203 controls the switch elements of the main conversion circuit 201 in such a manner that the desired power is supplied to the load 300. Specifically, the time (on time) when each switch element of the main conversion circuit 201 should be in the on state is calculated according to the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switch element according to the voltage to be output. Moreover, at each time point, a control instruction (control signal) is output to the drive circuit 202 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switch element according to the control signal.

[0114] In the power conversion device according to the present embodiment, the semiconductor devices according to Embodiments 1 to 4 are applied as switching elements of the main conversion circuit 201 , so that a low-loss power conversion device can be realized.

[0115] In this embodiment, an example of applying the semiconductor device involved in embodiments 1 to 4 to a 2-level three-phase inverter is described, but it is not limited to this and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is set, but it can also be a 3-level or multi-level power conversion device, and it can also be applied to a single-phase inverter when supplying power to a single-phase load. In addition, when supplying power to a DC load, etc., it can also be applied to a DC / DC converter and an AC / DC converter.

[0116] In addition, the power conversion device using the semiconductor device involved in embodiments 1 to 4 is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0117] In addition, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

[0118] The above description is merely illustrative in all aspects, and it should be understood that numerous modifications not shown are conceivable.

[0119] (Explanation of symbols)

[0120] 1: semiconductor substrate; 2: drift layer; 3: well region; 4: source region; 5: well contact region; 6: gate trench; 7: gate insulating film; 8: gate electrode; 9: interlayer insulating film; 10: source electrode; 11: drain electrode; 12: trench bottom protective layer; 13: p-type column region; 14: n-type column region; 14a: high-concentration n-type column region; 14b: low-concentration n-type column region; 15: silicide layer; 16: barrier metal; 17: sidewall well region; 18: etching mask; 20: semiconductor layer; 100: power supply; 200: power conversion device; 201: main conversion circuit; 202: drive circuit; 203: control circuit; 300: load.

Claims

1. A semiconductor device comprising: Semiconductor layer; A drift layer of the first conductivity type formed in the semiconductor layer; A well region of the second conductivity type is formed in the surface portion of the semiconductor layer; A source region of the first conductivity type is formed in a surface portion of the well region; a source electrode, electrically connected to the well region and the source region; A plurality of gate trenches, penetrating the source region and the well region, and having gate electrodes buried therein via a gate insulating film; A first column region of a second conductivity type is formed below the plurality of gate trenches; as well as A second column region of the first conductivity type is formed between adjacent first column regions and has a peak concentration of impurities higher than that of the drift layer. The second pillar region includes a high concentration region and a low concentration region provided on at least one side of the second pillar region and having a lower peak concentration of impurities than the high concentration region.

2. The semiconductor device according to claim 1, wherein It also includes a second conductive type trench bottom protective layer, the second conductive type trench bottom protective layer is formed at the bottom of the gate trench, and the peak concentration of impurities in the second conductive type trench bottom protective layer is higher than that in the first column region, The first pillar region is formed below the trench bottom protection layer.

3. The semiconductor device according to claim 1 or 2, wherein: The low concentration region is provided on both sides of the second pillar region.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The concentration of the first conductivity type impurity contained in the first pillar region is lower than the concentration of the first conductivity type impurity contained in the low concentration region.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The lower end of the low-concentration region is located deeper than the lower end of the first pillar region from the surface of the semiconductor layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein: A depth from the bottom of the gate trench to the lower end of the first pillar region is longer than a distance between adjacent gate trenches.

7. The semiconductor device according to any one of claims 1 to 5, wherein: A depth from the bottom of the gate trench to the lower end of the first pillar region is longer than a distance between adjacent first pillar regions.

8. The semiconductor device according to any one of claims 1 to 7, wherein: A well contact region of a second conductivity type is further provided, which is formed on a surface portion of the well region in contact with the source region, and has a peak concentration of impurities higher than that of the well region.

9. The semiconductor device according to claim 8, wherein: The well contact region is formed in a linear shape orthogonal to the gate trench.

10. The semiconductor device according to claim 2, wherein: A second conductivity type sidewall well region is further provided. The second conductivity type sidewall well region is formed at a portion of the sidewall of the gate trench and is used to electrically connect the trench bottom protection layer and the first pillar region to the source electrode.

11. The semiconductor device according to claim 10, wherein The distance between adjacent sidewall well regions is greater than or equal to the distance between adjacent gate trenches.

12. The semiconductor device according to claim 10 or 11, wherein: The invention also includes a well contact region of a second conductivity type, wherein the well contact region of the second conductivity type is formed on a surface portion of the well region in contact with the source region, and the peak concentration of impurities in the well contact region of the second conductivity type is higher than that in the well region. The sidewall well region is in contact with the well contact region.

13. The semiconductor device according to claim 12, wherein: The well contact region is formed in a linear shape orthogonal to the gate trench.

14. A power conversion device comprising: A main conversion circuit, comprising a semiconductor device according to any one of claims 1 to 13, the main conversion circuit converting input power and outputting the power; A driving circuit outputs a driving signal for driving the semiconductor device to the semiconductor device; as well as The control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

15. A method for manufacturing a semiconductor device, comprising: forming a semiconductor layer including a drift layer of a first conductivity type; forming a well region of a second conductivity type in a surface portion of the semiconductor layer; forming a source region of the first conductivity type on a surface portion of the well region; forming a plurality of gate trenches penetrating the source region and the well region; A step of forming a first column region of a second conductivity type below the plurality of gate trenches; A step of forming a second column region of the first conductivity type having a higher peak concentration of impurities than the drift layer between adjacent first column regions; forming a gate electrode in the plurality of gate trenches via a gate insulating film; and forming a source electrode electrically connected to the well region and the source region, The second column region includes a high concentration region and a low concentration region provided on at least one side of the second column region and having a lower peak concentration of impurities than the high concentration region. The high concentration region and the low concentration region are formed by implanting ions with an accuracy inclined with respect to the depth direction of the semiconductor layer and implanting impurities of the first conductivity type into the side surfaces of the plurality of gate trenches.

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