Array substrate and display panel

Abstract

An array substrate (100) comprises a substrate (10), a plurality of pixel driving circuits (Q) and a plurality of first scanning signal lines (G1). The plurality of pixel driving circuits (Q) are located on one side of the substrate (10) and are arranged in multiple rows and multiple columns. Any one of the pixel driving circuits (Q) includes a driving transistor (T3), a compensation transistor (T2) electrically connected to the driving transistor (T3), and a first conductive connection portion (M1). The plurality of first scanning signal lines (G1) are located on one side of the substrate (10), and are arranged in a second direction (Y) extending in a first direction (X). A control pole (c3) of the driving transistor (T3) is electrically connected to the first conductive connection portion (M1), a control pole (c2) of the compensation transistor (T2) is electrically connected to the first scanning signal line (G1), a second pole (b2) of the compensation transistor (T2) is electrically connected to the first conductive connection portion (M1), and a first pole (a2) of the compensation transistor (T2) is electrically connected to a second pole (b3) of the driving transistor (T3). The orthographic projection of the first scanning signal line (G1) on the substrate (10) is not overlapped with the orthographic projection of the first conductive connection part (M1) on the substrate (10).

Description

Array substrate and display panel Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] OLED (Organic Light Emitting Diode) display devices have become one of the most competitive and promising display devices due to their advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display.

[0003] Summary of the Invention

[0004] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel driving circuits, and a plurality of first scanning signal lines. The plurality of pixel driving circuits are located on one side of the substrate and are arranged in multiple rows and columns. Any pixel driving circuit includes a driving transistor, a compensation transistor electrically connected to the driving transistor, and a first conductive connection portion. The plurality of first scanning signal lines are located on one side of the substrate, extend along a first direction, and are arranged along a second direction, wherein the second direction intersects the first direction. The control electrode of the driving transistor is electrically connected to the first conductive connection portion, the control electrode of the compensation transistor is electrically connected to the first scanning signal line, the second electrode of the compensation transistor is electrically connected to the first conductive connection portion, and the first electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor. The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate.

[0005] In some embodiments, any pixel driving circuit further includes a second conductive connection portion, the first electrode of the driving transistor being electrically connected to the second conductive connection portion, wherein an orthographic projection of the first scanning signal line on the substrate does not overlap with an orthographic projection of the second conductive connection portion on the substrate.

[0006] In some embodiments, an orthographic projection of the first conductive connection portion on the substrate is located between an orthographic projection of the driving transistor on the substrate and an orthographic projection of the first scan signal line on the substrate.

[0007] In some embodiments, along the second direction, the second conductive connection portion and the driving transistor are located on the same side of the first scanning signal line, and along the first direction, the orthographic projection of the second conductive connection portion on the substrate is located on a side where the orthographic projection of the first conductive connection portion on the substrate is away from the orthographic projection of the compensation transistor on the substrate.

[0008] In some embodiments, an orthographic projection of the first scan signal line on the substrate does not overlap with an orthographic projection of the control electrode of the driving transistor on the substrate.

[0009] In some embodiments, the orthographic projection of the first scan signal line on the substrate does not overlap with the orthographic projection of the first electrode of the drive transistor on the substrate. And / or the orthographic projection of the first scan signal line on the substrate does not overlap with the orthographic projection of the second electrode of the drive transistor on the substrate.

[0010] In some embodiments, the array substrate further includes a plurality of data write signal lines and a plurality of second scan signal lines. The plurality of data write signal lines are located on one side of the substrate, extend along the second direction, and are arranged in the first direction. The plurality of second scan signal lines are located on one side of the substrate, extend along the first direction, and are arranged in the second direction. The pixel drive circuit further includes a data write transistor, a first electrode of the data write transistor being electrically connected to the data write signal line, a second electrode of the data write transistor being electrically connected to the second conductive connection portion, and a control electrode of the data write transistor being electrically connected to the second scan signal line. Along the first direction, the orthographic projection of the data write transistor on the substrate is located on the side of the orthographic projection of the drive transistor on the substrate, away from the orthographic projection of the compensation transistor on the substrate.

[0011] In some embodiments, along the second direction, the orthographic projection of the first scan signal line on the substrate is located on a side where the orthographic projection of the second scan signal line on the substrate is away from the orthographic projection of the driving transistor on the substrate.

[0012] In some embodiments, an orthographic projection of the first scan signal line on the substrate does not overlap with an orthographic projection of the second electrode of the data writing transistor on the substrate.

[0013] In some embodiments, the array substrate further includes a plurality of first initialization signal lines and a plurality of first reset signal lines. The plurality of first initialization signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of first reset signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The pixel driving circuit further includes a first reset transistor, wherein the control electrode of the first reset transistor is electrically connected to the first reset signal line, the first electrode of the first reset transistor is electrically connected to the first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the second electrode of the driving transistor. Along the second direction, the orthographic projection of the first reset signal line on the substrate is located on a side where the orthographic projection of the first scanning signal line on the substrate is away from the orthographic projection of the driving transistor on the substrate.

[0014] In some embodiments, the array substrate further comprises a plurality of enable signal lines and a plurality of first power signal lines. The plurality of enable signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of first power signal lines are located on one side of the substrate, extend along the second direction, and are arranged along the first direction. The pixel driving circuit further comprises a first light-emitting control transistor. The control electrode of the first light-emitting control transistor is electrically connected to the enable signal line, the first electrode of the first light-emitting control transistor is electrically connected to the first power signal line, and the second electrode of the first light-emitting control transistor is electrically connected to the second conductive connection portion. Along the second direction, the orthographic projection of the enable signal line on the substrate is located on a side of the orthographic projection of the drive transistor on the substrate away from the orthographic projection of the first scanning signal line on the substrate.

[0015] In some embodiments, the array substrate further includes a plurality of second initialization signal lines and a plurality of second reset signal lines. The plurality of second initialization signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of second reset signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The pixel driving circuit further includes a second reset transistor, wherein a control electrode of the second reset transistor is electrically connected to the second reset signal line, a first electrode of the second reset transistor is electrically connected to the second initialization signal line, and a second electrode of the second reset transistor is electrically connected to the light-emitting device. Along the second direction, the orthographic projection of the second reset signal line on the substrate is located on a side of the orthographic projection of the enable signal line on the substrate away from the orthographic projection of the drive transistor on the substrate.

[0016] In some embodiments, the array substrate further includes a plurality of third initialization signal lines and a plurality of third reset signal lines. The plurality of third initialization signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of third reset signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The pixel driving circuit further includes a third reset transistor, wherein a control electrode of the third reset transistor is electrically connected to the third reset signal line, a first electrode of the third reset transistor is electrically connected to the third initialization signal line, and a second electrode of the third reset transistor is electrically connected to the second conductive connection portion. The orthographic projection of the enable signal line on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate.

[0017] In some embodiments, an orthographic projection of the second conductive connection portion on the substrate at least partially overlaps with an orthographic projection of the third initialization signal line on the substrate.

[0018] In some embodiments, the compensation transistor includes a semiconductor structure, the semiconductor structure including a first portion, an orthographic projection of the first portion on the substrate being located between the first scan signal line and an orthographic projection of the drive transistor on the substrate. The first portion is electrically connected to the first conductive connection structure, and the orthographic projection of the first portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate.

[0019] In some embodiments, the compensation transistor includes a semiconductor structure, the semiconductor structure including a first portion, the orthographic projection of the first portion on the substrate being located between the first scan signal line and the orthographic projection of the drive transistor on the substrate. Along the extension direction of the second scan signal line, the first portion includes a first sub-portion and a second sub-portion connected to each other. The orthographic projection of the second sub-portion on the substrate is located between the orthographic projection of the first sub-portion on the substrate and the orthographic projection of the control electrode of the compensation transistor on the substrate, and the first sub-portion is electrically connected to the first conductive connection structure. The orthographic projections of the first sub-portion and the second sub-portion on the substrate both overlap with the orthographic projection of the second scan signal line on the substrate.

[0020] In some embodiments, the compensation transistor includes a semiconductor structure, the semiconductor structure including a first portion, the orthographic projection of the first portion on the substrate being located between the first scan signal line and the orthographic projection of the drive transistor on the substrate. Along the extension direction of the second scan signal line, the first portion includes a third sub-portion, a fourth sub-portion, and a fifth sub-portion, which are connected to each other, and the fourth sub-portion is located between the third sub-portion and the fifth sub-portion. The fourth sub-portion is a first electrode of the compensation transistor and is electrically connected to the first conductive connection structure. The orthographic projections of the third sub-portion, the fourth sub-portion, and the fifth sub-portion on the substrate all overlap with the orthographic projection of the second scan signal line on the substrate.

[0021] In some embodiments, the compensation transistor includes a semiconductor structure comprising a first portion, a second portion, and a third portion. The second portion serves as a channel of the compensation transistor, the third portion serves as a first electrode of the compensation transistor, and the first portion is electrically connected to the first conductive connection. An orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the second scan signal line on the substrate, and the area of ​​the first overlapping area is greater than the area of ​​the orthographic projection of the second portion on the substrate.

[0022] In some embodiments, the semiconductor structure further includes a second portion and a third portion. The second portion is a channel of the compensation transistor, and the third portion is a first electrode of the compensation transistor. The pixel driving circuit further includes a third conductive connection portion, the first electrode of the compensation transistor being electrically connected to the third conductive connection portion, and the second electrode of the driving transistor being electrically connected to the third conductive connection portion. The orthographic projection of the third conductive connection portion on the substrate overlaps with the orthographic projection of the second portion on the substrate.

[0023] In some embodiments, the semiconductor structure further includes a second portion and a third portion, the second portion being the channel of the compensation transistor, and the third portion being the first electrode of the compensation transistor. The pixel driving circuit further includes a third conductive connection portion, the first electrode of the compensation transistor being electrically connected to the third conductive connection portion, and the second electrode of the driving transistor being electrically connected to the third conductive connection portion. The first scanning signal line includes a first portion and a second portion, the orthographic projection of the first portion on the substrate overlapping with the orthographic projection of the second portion on the substrate, and the orthographic projection of the second portion on the substrate overlapping with the orthographic projection of the third conductive connection portion on the substrate, wherein along the second direction, the width of the second portion is smaller than the width of the first portion. The orthographic projection of the third conductive connection portion on the substrate does not overlap with the orthographic projection of the second portion on the substrate.

[0024] In another aspect, a display panel is provided. The display panel includes a light-emitting device layer and an array substrate according to any of the above embodiments. The light-emitting device layer is located on one side of the array substrate and includes a plurality of light-emitting devices, each of which is electrically connected to a pixel driving circuit in the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a structural diagram of a display device according to some embodiments;

[0027] FIG2 is a structural diagram of a display panel according to some embodiments;

[0028] FIG3 is a structural diagram of a display panel according to some embodiments;

[0029] FIG4 is a structural diagram of an array substrate according to some embodiments;

[0030] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0031] FIG6 is a structural diagram of a pixel driving circuit in some possible implementations;

[0032] 7 is a timing diagram of a first node, a first scanning signal line, a second scanning signal line, and an enable signal line in a pixel driving circuit according to some embodiments;

[0033] FIG8 is a partial enlarged view of E in FIG7 ;

[0034] FIG9 is a structural diagram of a pixel driving circuit according to some embodiments;

[0035] FIG10 is a structural diagram of the first semiconductor layer in FIG9 ;

[0036] FIG11 is a structural diagram of the first gate metal layer in FIG9 ;

[0037] FIG12 is a structural diagram of the second gate metal layer in FIG9 ;

[0038] FIG13 is a structural diagram of some film layers in FIG9;

[0039] FIG14 is a structural diagram of the second semiconductor layer in FIG9;

[0040] FIG15 is a structural diagram of the third gate metal layer in FIG9;

[0041] FIG16 is a structural diagram of other film layers in FIG9 ;

[0042] FIG17 is a structural diagram of the first routing metal layer in FIG9 ;

[0043] FIG18 is a structural diagram of some more film layers in FIG9;

[0044] FIG19 is a structural diagram of the second routing metal layer in FIG9 ;

[0045] FIG20 is a structural diagram of a pixel driving circuit according to some other embodiments;

[0046] FIG21 is a structural diagram of a pixel driving circuit according to yet other embodiments;

[0047] FIG22 is a structural diagram of the second gate metal layer in FIG21;

[0048] FIG23 is a structural diagram of the second gate metal layer and the second semiconductor layer in FIG21;

[0049] FIG24 is a structural diagram of the first routing metal layer in FIG21;

[0050] FIG25 is a structural diagram of a pixel driving circuit according to still other embodiments;

[0051] FIG26 is a structural diagram of the second semiconductor layer in FIG25;

[0052] FIG. 27 is a structural diagram of a display panel according to some other embodiments. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0057] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0060] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0061] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0062] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0063] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0064] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0065] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0066] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be structurally symmetrical, the source and drain can be structurally identical. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally identical.

[0067] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0068] FIG1 is a structural diagram of a display device according to some embodiments. Referring to FIG1 , some embodiments of the present disclosure provide a display device 300 , which includes a display panel 200 .

[0069] Exemplarily, the display device 300 further includes a frame and other electronic accessories.

[0070] Exemplarily, the display device 300 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0071] Exemplarily, the display device 300 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0072] FIG. 2 is a structural diagram of a display panel according to some embodiments, and FIG. 3 is a structural diagram of a display panel according to some embodiments.

[0073] Some embodiments of the present disclosure provide a display panel 200. As shown in Figures 2 and 3 , the display panel 200 includes an active area (AA), also known as an effective display area. The active area AA includes multiple sub-pixel regions P, which can be arranged in an array. A sub-pixel region P is the smallest unit used by the display panel 200 for displaying images.

[0074] In some examples, a sub-pixel region P includes a pixel driver circuit Q and a light-emitting device O electrically connected to the pixel driver circuit Q. The pixel driver circuit Q can be adjusted based on a variety of different signal lines to generate a drive signal, and each light-emitting device O can emit light under the drive signal generated by the corresponding pixel driver circuit Q. Based on this, the pixel driver circuits Q in multiple sub-pixel regions can drive the corresponding light-emitting devices O to emit light, so that the display panel 200 can display a predetermined image in the display area AA. Specifically, the multiple sub-pixel regions P can include multiple sub-pixel regions P with different luminescent colors.

[0075] For example, the plurality of sub-pixel regions P may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region, the second sub-pixel region, and the third sub-pixel region each emit three primary colors of light. For example, the first sub-pixel region may emit red light, the second sub-pixel region may emit green light, and the third sub-pixel region may emit blue light. Based on this, by adjusting the brightness (grayscale) of the sub-pixel regions P of different colors, a multi-color display can be achieved through color combination and superposition, thereby achieving full-color display of the display panel 200.

[0076] Continuing with Figures 2 and 3 , the display panel 200 further includes an array substrate 100 and a light-emitting device layer 210. The array substrate 100 may include a plurality of pixel driving circuits Q. The light-emitting device layer 210 is located on one side of the array substrate 100 and includes a plurality of light-emitting devices O, which are electrically connected to the pixel driving circuits Q in the array substrate 100.

[0077] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light by discharge), as long as they can emit light so that the display panel 200 can display a picture.

[0078] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be coupled in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q may be coupled to one light-emitting device O.

[0079] Below, the present disclosure takes the coupling of one pixel driving circuit Q and one light-emitting device O as an example to schematically illustrate the structure of the display panel 200 .

[0080] FIG. 4 is a structural diagram of an array substrate according to some embodiments, and FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0081] 4 and 5 , some embodiments of the present disclosure provide an array substrate 100 . The array substrate 100 includes a substrate 10 and a pixel circuit layer 20 located on one side of the substrate 10 .

[0082] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0083] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0084] The pixel circuit layer 20 includes multiple metal layers stacked on the substrate 10. The multiple metal layers include pixel driving circuits Q and multiple different types of signal lines. The different types of signal lines include, but are not limited to, multiple first scanning signal lines G1. The different types of signal lines may also include other types of signal lines, which will be described in detail below.

[0085] The plurality of pixel driving circuits Q are located on one side of the substrate 10 and are arranged in multiple rows and columns. For ease of description, the plurality of pixel driving circuits Q are described in this disclosure as being arranged in a matrix.

[0086] At this time, the pixel driving circuits Q arranged in a row along the first direction X are called a row of pixel driving circuits Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column of pixel driving circuits Q.

[0087] In some examples, the pixel driving circuit Q includes multiple transistors. In some embodiments, the structure of the pixel driving circuit 211 in the present disclosure includes multiple structures, which can be selected according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is an introduction taking the "8T1C" pixel driving circuit as an example.

[0088] 5 , the pixel driving circuit Q includes: a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a first light emission control transistor T5 , a second light emission control transistor T6 , a second reset transistor T7 , a third reset transistor T8 and a capacitor Cst.

[0089] Because the pixel driving circuit Q needs to be electrically connected to multiple different types of signal lines, FIG5 also illustrates multiple different types of signal lines. These multiple different types of signal lines may include: a first scan signal line G1, a second scan signal line G2, a data write signal line Data, an enable signal line EM, a first power signal line Vdd, a first reset signal line R1, a second reset signal line R2, a third reset signal line R3, a first initialization signal line Vinit1, a second initialization signal line Vinit2, and a third initialization signal line Vinit3. In FIG5 , each signal terminal represents its corresponding signal line.

[0090] The control electrode c1 of the first reset transistor T1 is electrically connected to the first reset signal line R1 , the first electrode a1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1 , and the second electrode b1 of the first reset transistor T1 is electrically connected to the first node N1 .

[0091] In the initialization stage, the first reset transistor T1, under the control of the first reset signal received from the first reset signal line R1, transmits the first initialization signal received at the first initialization signal line Vinit1 to the first node N1, and resets the first node N1, which is beneficial to ensure the stability of the voltage of the first node N1.

[0092] A control electrode c2 of the compensation transistor T2 is electrically connected to the first scan signal line G1 , a first electrode a1 of the compensation transistor T2 is electrically connected to the third node N3 , and a second electrode b1 of the compensation transistor T2 is electrically connected to the first node N1 .

[0093] In the writing phase, the compensation transistor T2 transmits the voltage of the third node N3 to the first node N1 under the control of the first scan signal received from the first scan signal line G1.

[0094] In some examples, the compensation transistor T2 may be an oxide thin film transistor. For example, the compensation transistor T2 may be an indium gallium zinc oxide thin film transistor (English full name: Indium Gallium Zinc Oxide, English abbreviation: IGZO).

[0095] Such a configuration can help reduce the risk of leakage of the compensation transistor T2 and is more conducive to ensuring the stability of the voltage of the first node N1.

[0096] In some examples, the compensation transistor T2 may be an N-type transistor.

[0097] The control electrode c3 of the driving transistor T3 is electrically connected to the first node N1 , the first electrode a3 of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode b3 of the driving transistor T3 is electrically connected to the third node N3 .

[0098] The driving transistor T3 is configured to transfer the voltage from the second node N2 to the third node N3 under the control of the voltage of the first node N1.

[0099] The control electrode c4 of the data writing transistor T4 is electrically connected to the second scanning signal line G2, the first electrode a4 of the data writing transistor T4 is electrically connected to the data writing signal line Data, and the second electrode b4 of the data writing transistor T4 is electrically connected to the second node N2.

[0100] In the writing phase, the data writing transistor T4 transmits the data signal received at the data writing signal line Data to the second node N2 under the control of the first scanning signal received from the first scanning signal line G1 .

[0101] The control electrode c5 of the first light emitting control transistor T5 is electrically connected to the enable signal line EM, the first electrode a5 of the first light emitting control transistor T5 is electrically connected to the first power signal line Vdd, and the second electrode b5 of the first light emitting control transistor T5 is electrically connected to the second node N2.

[0102] A control electrode c6 of the second light-emitting control transistor T6 is electrically connected to the enable signal line EM, a first electrode a6 of the second light-emitting control transistor T6 is electrically connected to the third node N3, and a second electrode b6 of the second light-emitting control transistor T6 is electrically connected to the fourth node N4. The fourth node N4 is electrically connected to the light-emitting device O.

[0103] The control electrode c5 of the first emission control transistor T5 and the control electrode c6 of the second emission control transistor T6 can be electrically connected to the same enable signal line EM. It is understood that in other examples, the control electrode c5 of the first emission control transistor T5 can be electrically connected to one enable signal line EM, while the control electrode c6 of the second emission control transistor T6 can be electrically connected to another enable signal line EM. The embodiments of the present disclosure are not limited to this.

[0104] During the light-emitting phase, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 cooperate with the driving transistor T3 under the control of the enable signal from the enable signal line EM to transmit the driving signal to the fourth node N4. The fourth node N4 is electrically connected to the light-emitting device O. In other words, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 cooperate with the driving transistor T3 under the control of the enable signal from the enable signal line EM to transmit the driving signal to the light-emitting device O.

[0105] A control electrode c7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, a first electrode a7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode b7 of the second reset transistor T7 is electrically connected to a fourth node N4. The fourth node N4 is electrically connected to the light emitting device O.

[0106] During the initialization phase, the second reset transistor T7, under the control of the second reset signal received from the second reset signal line R2, transmits the second initialization signal received from the second initialization signal line Vinit2 to the fourth node N4, thereby resetting the fourth node N4. Since the fourth node N4 is electrically connected to the light-emitting device O, resetting the fourth node N4 is equivalent to using this signal to reset the anode of the light-emitting unit O, which can help improve the stability of the light-emitting unit O.

[0107] In some examples, the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6 and the second reset transistor T7 can be low temperature polysilicon thin film transistors (English full name: Low Temperature Polysilicon Oxide, English abbreviation: LTPO).

[0108] In some examples, the first reset transistor T1 , the driving transistor T3 , the data writing transistor T4 , the first light emission control transistor T5 , the second light emission control transistor T6 , and the second reset transistor T7 may be P-type transistors.

[0109] In addition, a first plate S1 of the storage capacitor Cst is electrically connected to the first node N1, and a second plate S2 of the storage capacitor Cst is electrically connected to the first power signal line Vdd.

[0110] It should be noted that each pixel driving circuit Q includes multiple transistors (TFTs). The use of TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFT has a hysteresis effect. The hysteresis effect of TFT is an uncertainty in the electrical characteristics of TFT under a certain bias voltage. That is, the current flowing through the TFT is not only related to the current bias voltage, but also to the state of the TFT at the previous moment. The hysteresis effect of TFT is related to the gate dielectric, semiconductor material, and the interface state traps between the two of the TFT. During the light-emitting stage, the hysteresis effect of TFT will cause the current to decrease within a frame, which is perceived by the human eye as flickering, thereby affecting the display quality of the display panel.

[0111] Based on this, a third reset transistor T8 may be provided in the pixel driving circuit Q. A control electrode c8 of the third reset transistor T8 is electrically connected to the third reset signal line R3, a first electrode a8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vinit3, and a second electrode b8 of the third reset transistor T8 is electrically connected to the second node N2.

[0112] Under the control of the third reset signal from the third reset signal line R3, the third initialization signal on the third initialization signal line Vinit3 is transmitted to the second node N2 to initialize the second node N2. This fixes the initial state of the driving transistor T3 before the writing phase, thus facilitating the driving transistor T3 to be in a stable state during the writing phase and significantly improving the hysteresis effect of the driving transistor T3.

[0113] In some examples, the third reset transistor T8 may be a low temperature polysilicon thin film transistor (LTPO).

[0114] In some examples, the third reset transistor T8 may be a p-type transistor.

[0115] In some embodiments, the third reset signal line R3 and the second reset signal line R2 can respond to the same signal line. Alternatively, it can be understood that the second reset signal line R2 is multiplexed into the third reset signal line R3. The following description uses the second reset signal line R2 multiplexed into the third reset signal line R3 as an example.

[0116] In some embodiments, the third initialization signal transmitted by the third initialization signal line Vinit3 may be a high voltage signal. Furthermore, the high voltage signal may be used to reset the second node N2, which is equivalent to resetting the first electrode a3 of the driving transistor T3. This fixes the initial state of the driving transistor T3 before the data writing phase t2, thereby facilitating a stable state of the driving transistor T3 during the data writing phase t2 and significantly improving the hysteresis effect of the driving transistor T3.

[0117] In some examples, the first power signal line Vdd can be reused as the third initialization signal line Vinit3, thereby simplifying the arrangement of transistors and their electrically connected signal lines in the pixel driving circuit Q. However, the present disclosure is not limited thereto.

[0118] In some embodiments, the driving process of the pixel driving circuit Q of “8T1C” shown in FIG. 5 is as follows: one frame period includes an initialization phase t1 , a data writing phase t2 , an adjustment phase t3 and a light emitting phase t4 .

[0119] Initialization phase t1: The enable signal transmitted by the enable signal line EM is a high voltage signal. At this time, the first emission control transistor T5 and the second emission control transistor T6 are both in the off state. The second scanning signal transmitted by the second scanning signal line G2 is a high voltage signal. At this time, the data writing transistor T4 is in the off state.

[0120] The first reset signal transmitted by the first reset signal line R1 includes a low voltage signal. At this time, the first reset transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the third node N3, and the third node N3 is reset, so as to improve the stability of the driving transistor T3 included in the pixel driving circuit Q.

[0121] The first scanning signal transmitted by the first scanning signal line G1 includes a high voltage signal, the compensation transistor T2 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 can be transmitted to the first node N1 through the compensation transistor T2, resetting the first node N1, thereby improving the stability of the driving transistor T3 included in the pixel driving circuit Q.

[0122] The second reset signal transmitted by the second reset signal line R2 is a low voltage signal, and the third reset transistor T8 is turned on, and the third initialization signal transmitted by the third initialization signal line Vinit3 is transmitted to the second node N2, which is equivalent to resetting the first electrode a3 of the driving transistor T3, so that the initial state of the driving transistor T3 before the data writing stage t2 is fixed, which facilitates the driving transistor T3 to be in a stable state during the data writing stage t2, thereby greatly improving the hysteresis effect of the driving transistor T3.

[0123] In addition, the second reset signal transmitted by the second reset signal line R2 is a low voltage signal. At this time, the second reset transistor T7 is turned on, and the second initialization signal transmitted by the second initialization signal line Vinit2 is transmitted to the fourth node N4, which is equivalent to resetting the anode of the light-emitting device O, thereby improving the stability of the light-emitting device O.

[0124] Data writing phase t2: The enable signal transmitted by the enable signal line EM is a high voltage signal. At this time, the first emission control transistor T5 and the second emission control transistor T6 are both in the off state. The first reset signal transmitted by the first reset signal line R1 is a low voltage signal. At this time, the first reset transistor T1 is in the off state. The second reset signal transmitted by the second reset signal line R2 is a high voltage signal. At this time, the second reset transistor T7 and the third reset transistor T8 are both in the off state.

[0125] The first scanning signal transmitted by the first scanning signal line G1 includes a high voltage signal, and the compensation transistor T2 is turned on. Furthermore, the second scanning signal transmitted by the second scanning signal line G2 is a low voltage signal. At this time, the data write transistor T4 is turned on, and the data write signal transmitted by the data write signal line Data can be transmitted to the first node N1 through the data write transistor T4, the drive transistor T3, and the compensation transistor T2 in sequence, compensating the first node N1. The potential of the first node N1 gradually rises to Vdata+Vth. Vdata is the voltage value of the data write signal provided by the data write signal line Data, and Vth is the threshold voltage of the drive transistor T3 in the pixel drive circuit Q. When the potential of the first node N1 is Vdata+Vth, the charging process is completed. Subsequently, the storage capacitor Cst is used to discharge to keep the drive transistor T3 included in the pixel drive circuit Q continuously turned on, ensuring that the light-emitting device O emits light.

[0126] Adjustment phase t3: The enable signal transmitted by the enable signal line EM is a high voltage signal. At this time, the first emission control transistor T5 and the second emission control transistor T6 are both in the off state. The second scanning signal transmitted by the second scanning signal line G2 is a high voltage signal. At this time, the data write transistor T4 is in the off state. The first scanning signal provided by the first scanning signal line G1 is a low voltage signal. At this time, the compensation transistor T2 is in the off state. The first reset signal transmitted by the first reset signal line R1 is a low voltage signal. At this time, the first reset transistor T1 is in the off state.

[0127] The second reset signal transmitted by the second reset signal line R2 includes a low voltage signal. The third reset transistor T8 is turned on, and the third initialization signal transmitted by the third initialization signal line Vinit3 is transmitted to the second node N2, which is equivalent to resetting the first electrode a3 of the driving transistor T3, so that the initial state of the driving transistor T3 before the data writing stage t2 is fixed, which facilitates the driving transistor T3 to be in a stable state during the data writing stage t2, thereby greatly improving the hysteresis effect of the driving transistor T3.

[0128] In addition, the second reset signal transmitted by the second reset signal line R2 is a low voltage signal. At this time, the second reset transistor T7 is turned on, and the second initialization signal transmitted by the second initialization signal line Vinit2 is transmitted to the fourth node N4, which is equivalent to resetting the anode of the light-emitting unit O, thereby improving the stability of the light-emitting unit O.

[0129] Light-emitting phase t4: The first scanning signal provided by the first scanning signal line G1 is a low voltage signal, at which point the compensation transistor T2 is off. The first reset signal transmitted by the first reset signal line R1 is a high voltage signal, at which point the first reset transistor T1 is off. The second scanning signal transmitted by the second scanning signal line G2 is a high voltage signal, at which point the data writing transistor T4 is off. The second reset signal transmitted by the second reset signal line R2 is a high voltage signal, at which point the second reset transistor T7 and the third reset transistor T8 are both off.

[0130] Furthermore, the enable signal transmitted by the enable signal line EM is a low voltage signal. At this time, both the first emission control transistor T5 and the second emission control transistor T6 are turned on. At this time, the discharge of the storage capacitor Cst can keep the drive transistor T3 included in the pixel drive circuit Q continuously turned on. Based on this, the constant voltage power signal provided by the first power signal line Vdd can flow sequentially through the first emission control transistor T5, the drive transistor T3, and the second emission control transistor T6 to the anode of the light-emitting device O, while the cathode of the light-emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light-emitting device O to emit light. The first power signal line Vdd can be a high power signal line, and the second power signal line Vss can be a low power signal line.

[0131] The effective signal of the first scanning signal transmitted by the first scanning signal line G1 is in phase opposite to the effective signal of the second scanning signal transmitted by the second scanning signal line G2.

[0132] Here, a "valid signal" refers to a signal that can turn on the transistor to which it is electrically connected. For example, if the first scanning signal line G1 is electrically connected to a P-type transistor, the valid signal is a low voltage signal. Alternatively, if the first scanning signal line G1 is electrically connected to an N-type transistor, the valid signal is a high voltage signal. The same applies to the second scanning signal line G2.

[0133] It should be noted that an N-type transistor turns on when the gate receives a high voltage signal, while a P-type transistor turns on when the gate receives a low voltage signal. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turning-on condition for an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, and the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turning-on condition for a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. The gate voltage signal that turns on the P-type transistor is called a low voltage signal, where the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0134] FIG6 is a structural diagram of a pixel driving circuit in some possible implementations.

[0135] In some embodiments, referring to FIG. 5 and FIG. 6 , any pixel driving circuit Q in the array substrate 100 further includes a first conductive connection portion M1. The first conductive connection portion M1 is electrically connected to the control electrode c3 of the driving transistor T3 and the second electrode b1 of the compensation transistor T2. Furthermore, the first conductive connection portion M1 is also electrically connected to the storage capacitor Cst.

[0136] In some examples, any pixel driving circuit Q in the array substrate 100 further includes a second conductive connection portion M2 and a third conductive connection portion M3. The second conductive connection portion M2 is electrically connected to the first electrode a3 of the driving transistor T3. Furthermore, the second conductive connection portion M2 is electrically connected to the second electrode b4 of the data write transistor T4, the second electrode b5 of the first emission control transistor T5, and the second electrode b8 of the third reset transistor T8. The third conductive connection portion M3 is electrically connected to the second electrode b3 of the driving transistor T3 and the first electrode a1 of the compensation transistor T2. Furthermore, the third conductive connection portion M3 is electrically connected to the second electrode b1 of the first reset transistor T1 and the first electrode a6 of the second emission control transistor T6.

[0137] It should be noted that, in combination with Figures 4 and 5, the first conductive connection part M1 can be the first node N1 in the equivalent circuit diagram of the pixel driving circuit Q, the second conductive connection part M2 can be the second node N2 in the equivalent circuit diagram of the pixel driving circuit Q, and the third conductive connection part M3 can be the third node N3 in the equivalent circuit diagram of the pixel driving circuit Q.

[0138] Research has found that since the pixel driving circuit Q includes structures such as 8 transistors, the layout of the pixel driving circuit Q is relatively compact, which will cause the positive projections of various different types of signal lines electrically connected to it on the substrate 10 to easily overlap with the positive projections of each transistor in the pixel driving circuit Q on the substrate 10.

[0139] 6 , the various types of signal lines include a plurality of first scanning signal lines G1 extending along a first direction X and arranged along a second direction Y. The second direction Y intersects the first direction X.

[0140] In some examples, the first direction X is perpendicular to the second direction Y. It is understood that in other embodiments, the first direction X and the second direction Y intersect to form a first angle, which may be an acute angle or an obtuse angle.

[0141] The orthographic projection of the first scanning signal line G1 on the substrate 10 overlaps with the orthographic projections of the first conductive connection portion M1 , the second conductive connection portion M2 and the third conductive connection portion M3 in the pixel driving circuit Q on the substrate 10 .

[0142] As shown in the above structure, parasitic capacitance will be generated between the first scanning signal line G1 and the first conductive connection part M1, the second conductive connection part M2 and the third conductive connection part M3. Furthermore, when the first scanning signal line G1 is used to transmit the first scanning signal, the jump of the first scanning signal potential will cause the first conductive connection part M1, the second conductive connection part M2 and the third conductive connection part M3 to follow the jump. Moreover, during the data writing phase, the potentials of the first conductive connection part M1, the second conductive connection part M2 and the third conductive connection part M3 will all jump as the data write signal from the data write signal line Data is written. At this time, the jump of the potentials of the first conductive connection part M1, the second conductive connection part M2 and the third conductive connection part M3 will also cause the jump of the potential of the first scanning signal.

[0143] Specifically, with reference to FIG7 , FIG7 is a timing diagram of a first node, a first scan signal line, a second scan signal line, and an enable signal line in a pixel driving circuit according to some embodiments, and FIG8 is a partial enlarged view of E in FIG7 . N1-1 and N1-2 are respectively the potentials of the first node N1 (first conductive connection portion M1), N1-1-2 represents a waveform formed by the difference between N1-1 and N1-2, G1(Gate3) represents the first scan signal line G1 formed on the third gate metal layer Gate3, and G1(Gate2) represents the first scan signal line G1 formed on the second gate metal layer Gate2.

[0144] When the first scan signal provided by the first scan signal line G1 rises to a high voltage, the first scan signal can control the compensation transistor T2 to turn on. At this time, the first scan signal transmitted by the first scan signal line will increase the voltage of the first conductive connection part M1, the second conductive connection part M2, and the third conductive connection part M3.

[0145] When the second scan signal provided by the second scan signal line G2 drops to a low voltage, the second scan signal can control the data write transistor T4 to turn on. The data write signal line Data transmits the data write signal and sequentially writes it to the second conductive connection portion M2, the third conductive connection portion M3, and the first conductive connection portion M1 (the control electrode c3 of the driving transistor T3). At this time, the potentials of the second conductive connection portion M2, the third conductive connection portion M3, and the first conductive connection portion M1 are pulled high by the data write signal. Furthermore, the increase in the potential of the second conductive connection portion M2, the third conductive connection portion M3, and the first conductive connection portion M1 will also increase the potential of the first scan signal transmitted by the first scan signal line G1.

[0146] Furthermore, in the related art, since a first scan signal line G1 is electrically connected to a row of pixel drive circuits Q, parasitic capacitance may be formed between the first scan signal line G1 and the first conductive connection structure M1 of the row of pixel drive circuits Q. Furthermore, the first scan signal line G1 may also affect the voltage of a first node N1 within a pixel drive circuit Q adjacent to the pixel drive circuit Q in the first direction X (row direction). The voltage of the first node N1 may affect the degree of activation of the drive transistor T3, thereby affecting the brightness of the light-emitting device O. This phenomenon may be referred to as lateral crosstalk deterioration.

[0147] That is, since a first scanning signal line G1 is electrically connected to a row of pixel driving circuits Q, at least one pixel driving circuit Q adjacent to a certain target pixel driving circuit Q drives the corresponding light-emitting device O to have different brightness when displaying pictures in two adjacent frames; this will cause the first scanning signal line G1 and the first conductive connection part M1, the second conductive connection part M2 and the third conductive connection part M3 of the row of pixel driving circuits Q to have different degrees of mutual pulling potential jump when displaying pictures in two adjacent frames, thereby affecting the opening degree of the driving transistor T3 of the target pixel driving circuit Q, and failing to drive the light-emitting device O to emit light at the target brightness.

[0148] Specifically, three pixel driving circuits Q arranged in sequence along the first direction X are taken as an example for description:

[0149] Continuing with Figures 7 and 8, the dotted lines in Figures 7 and 8 represent the timing diagram corresponding to the previous frame, and the dashed lines in Figures 7 and 8 represent the timing diagram corresponding to the next frame. In the previous frame, all pixel drive circuits display the same brightness (white screen), while in the next frame, one pixel drive circuit displays the previous brightness (white screen), while its two adjacent pixel drive circuits display a different brightness (black screen).

[0150] The three pixel driving circuits Q are respectively a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit. Along the first direction X, the second pixel driving circuit is located between the first pixel driving circuit and the third pixel driving circuit.

[0151] During the preceding frame of two adjacent frames, the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are driven so that the light-emitting devices O electrically connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit all emit the same first brightness. For example, the first brightness may be the brightness corresponding to a white image displayed on the display panel.

[0152] In the second frame of the two adjacent frames, the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are driven so that the light-emitting devices O electrically connected to the first pixel driving circuit and the third pixel driving circuit all emit the same second brightness. For example, the second brightness can be the brightness corresponding to when the display panel displays a black image.

[0153] At this time, the same electrical signal (the signal output to the second pixel driving circuit in the previous frame) is still provided. Ideally, the second pixel driving circuit can drive the corresponding light-emitting device O to emit the first brightness.

[0154] However, because the first brightness is greater than the second brightness, the voltage value of the data write signal corresponding to the first brightness is greater than the voltage value of the data write signal corresponding to the second brightness. Therefore, during the data write phase corresponding to the first brightness, the first conductive connection portion M1, the second conductive connection portion M2, and the third conductive connection portion M3 pull up the potential of the first scanning signal line G1 to a greater extent than during the data write phase corresponding to the first brightness. Consequently, the potential of the first scanning signal line G1 must drop further to turn off the compensation transistor T2.

[0155] However, corresponding to the first brightness, during the process of turning off the compensation transistor T2, that is, during the process of decreasing the potential of the first scanning signal line G1, the potential of the first conductive connection portion M1, the second conductive connection portion M2, and the third conductive connection portion M3 decreases more significantly than the potential decrease of the first conductive connection portion M1, the second conductive connection portion M2, and the third conductive connection portion M3 during the second brightness. Consequently, the potential of the control electrode c1 of the driving transistor T3 decreases to different degrees in two adjacent frames, that is, the degree to which the driving transistor T3 is turned on differs, which in turn affects the brightness of the light-emitting device O. In other words, even if the data write signal required for the first brightness is provided to the second pixel driving circuit during the subsequent frame display, the different degrees of turn-on of the driving transistor T3 will prevent the light-emitting device O electrically connected to the second pixel driving circuit from emitting the first brightness (for example, due to the relatively lower potential of the control electrode c3 of the driving transistor T3, the driving transistor T3 is turned on to a greater extent, causing the brightness of the light-emitting device O to be greater than the first brightness).

[0156] FIG. 9 is a structural diagram of a pixel driving circuit according to some embodiments.

[0157] To address the above technical issues, some embodiments of the present disclosure provide another array substrate 100. Referring to FIG. 9 , and in conjunction with FIG. 4 , the pixel driving circuit Q in the array substrate 100 includes a compensation transistor T2 , a driving transistor T3 , a first conductive connection portion M1 , a second conductive connection portion M2 , and a third conductive connection portion M3 .

[0158] It should be noted that the equivalent circuit diagram corresponding to the pixel driving circuit Q shown in FIG9 is consistent with the equivalent circuit diagram corresponding to the pixel driving circuit Q shown in FIG6 , but the layout of the pixel driving circuit Q is different. Specifically, the positions of the first scanning signal line G1 and other transistors can be adjusted so that the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the first conductive connection portion M1 on the substrate 10.

[0159] Based on this, parasitic capacitance can be prevented from forming between the first scanning signal line G1 and the first conductive connection portion M1 in the corresponding pixel driving circuit Q, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the first conductive connection portion M1. Therefore, the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3) can be improved, thereby improving the problem of worsening lateral crosstalk.

[0160] As described above, by adjusting the pixel drive circuit Q and setting the orthographic projection of the first scan signal line G1 on the substrate 10 to not overlap with the orthographic projection of the first conductive connection portion M1 on the substrate 10, it is possible to prevent the potential of the first conductive connection portion M1 from jumping during the data writing phase, thereby pulling up the potential of the first scan signal transmitted on the first scan signal line G1. Furthermore, it is also possible to prevent the first scan signal transmitted on the first scan signal line G1 from pulling down the potential of the first conductive connection portion M1 during the light-emitting phase, i.e., when the potential of the first scan signal transmitted on the first scan signal line G1 needs to be reduced to a level that causes the compensation transistor T2 to be turned off. This can thereby improve the stability of the potentials of the first conductive connection portion M1 and the first scan signal line G1, and further, improve the stability of the drive transistor T3, thereby improving the problem of worsening lateral crosstalk.

[0161] In summary, some embodiments of the present disclosure provide an array substrate 100 that minimizes overlap between the orthographic projection of the first scan signal line G1 on the substrate 10 and the orthographic projection of the first conductive connection portion M1 on the substrate 10 by adjusting the layout within the pixel driving circuit Q in the array substrate 10. Furthermore, due to the connection relationships between the various transistors, as well as the connection relationship between the first scan signal line G1 and the compensation transistor T2, the orthographic projection of the first scan signal line G1 on the substrate 10 and the orthographic projection of the first conductive connection portion M1 on the substrate 10 do not overlap, thereby reducing the overlap between the driving transistor T3 and the first scan signal line G1, improving the stability of the driving transistor T3, and thereby alleviating the problem of deteriorating lateral crosstalk.

[0162] In some embodiments, referring to FIG. 9 and FIG. 4 , the orthographic projection of the first scan signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second conductive connection portion M2 on the substrate 10 .

[0163] Based on this, parasitic capacitance can be prevented from forming between the first scanning signal line G1 and the second conductive connection portion M2 in the corresponding pixel driving circuit Q, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the second conductive connection portion M2. Therefore, the stability of the driving transistor T3 (the first electrode a3 of the driving transistor T3) can be improved, and the problem of unstable potential of the control electrode c3 of the driving transistor T3 due to gate-source capacitance coupling can be prevented, thereby improving the problem of worsening lateral crosstalk.

[0164] As described above, by adjusting the pixel drive circuit Q, the orthographic projection of the first scan signal line G1 on the substrate 10 is set to not overlap with the orthographic projection of the second conductive connection portion M2 on the substrate 10. This can prevent the potential of the second conductive connection portion M2 from jumping during the data writing phase and pulling up the potential of the first scan signal transmitted on the first scan signal line G1. Furthermore, it can also prevent the first scan signal transmitted on the first scan signal line G1 from pulling down the potential of the second conductive connection portion M2 during the light-emitting phase, i.e., when the potential of the first scan signal transmitted on the first scan signal line G1 needs to be reduced to a level where the compensation transistor T2 is turned off. This can help improve the stability of the potential of the second conductive connection portion M2 and the first scan signal line G1, thereby improving the stability of the driving transistor T3 (the first electrode a3 of the driving transistor T3), preventing the potential instability of the control electrode c3 of the driving transistor T3 due to gate-source capacitance coupling, and further improving the problem of worsening lateral crosstalk.

[0165] In some embodiments, referring to FIG. 9 and in conjunction with FIG. 4 , the orthographic projection of the first scan signal line G1 on the substrate 10 does not overlap with the orthographic projection of the first conductive connection portion M1 on the substrate 10, and the orthographic projection of the first scan signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second conductive connection portion M2 on the substrate 10. This prevents the first scan signal line G1 from forming parasitic capacitance with the first conductive connection portion M1 and the second conductive connection portion M2 in the corresponding pixel drive circuit Q, thereby improving the potential jump caused by the first scan signal line G1 and the first conductive connection portion M1 and the second conductive connection portion M2. Consequently, this can improve the stability of the driving transistor T3 and alleviate the problem of deteriorating lateral crosstalk.

[0166] As described above, by adjusting the pixel drive circuit Q and setting the orthographic projection of the first scan signal line G1 on the substrate 10 to not overlap with the orthographic projection of the second conductive connection portion M2 on the substrate 10, it is possible to prevent the potential of the second conductive connection portion M2 from jumping during the data writing phase and pulling up the potential of the first scan signal transmitted on the first scan signal line G1. Furthermore, it is also possible to prevent the first scan signal transmitted on the first scan signal line G1 from pulling down the potential of the second conductive connection portion M2 during the light-emitting phase, i.e., when the potential of the first scan signal transmitted on the first scan signal line G1 needs to be reduced to the point where the compensation transistor T2 is turned off. This can help improve the stability of the potentials of the second conductive connection portion M2 and the first scan signal line G1, thereby improving the stability of the drive transistor T3 and, in turn, improving the problem of worsening lateral crosstalk.

[0167] In summary, some embodiments of the present disclosure provide an array substrate 100 that adjusts the layout within the pixel driving circuit Q in the array substrate 100 to minimize the degree of overlap between the orthographic projection of the first scan signal line G1 on the substrate 10 and the orthographic projections of the first conductive connection portion M1, the second conductive connection portion M2, and the third conductive connection portion M3 on the substrate 10. Due to the connection relationships between the various transistors, as well as the connection relationship between the first scan signal line G1 and the compensation transistor T2, the orthographic projection of the first scan signal line G1 on the substrate 10 can be made to not overlap with the orthographic projection of the first conductive connection portion M1 on the substrate 10, and / or the orthographic projection of the first scan signal line G1 on the substrate 10 can be made to not overlap with the orthographic projection of the second conductive connection portion M2 on the substrate 10, thereby reducing the degree of overlap between the driving transistor T3 and the first scan signal line G1, improving the stability of the driving transistor T3, and thereby facilitating improvements in the problem of deteriorating lateral crosstalk.

[0168] The above describes the overlapping relationship between the driving transistor T3 and the first scanning signal line G1 of the array substrate 100 in conjunction with the accompanying drawings. Based on this, the following describes in detail the film layer distribution of multiple transistors and each signal line in the array substrate 100 in conjunction with the relevant drawings.

[0169] Figure 10 is a structural diagram of the first semiconductor layer in Figure 9, Figure 11 is a structural diagram of the first gate metal layer in Figure 9, Figure 12 is a structural diagram of the second gate metal layer in Figure 9, Figure 13 is a structural diagram of some film layers in Figure 9, Figure 14 is a structural diagram of the second semiconductor layer in Figure 9, Figure 15 is a structural diagram of the third gate metal layer in Figure 9, Figure 16 is a structural diagram of other film layers in Figure 9, Figure 17 is a structural diagram of the first routing metal layer in Figure 9, Figure 18 is a structural diagram of some other film layers in Figure 9, and Figure 19 is a structural diagram of the second routing metal layer in Figure 9.

[0170] In some embodiments, as shown in conjunction with Figures 4 and 9 to 19, the array substrate 100 includes a substrate and a pixel circuit layer 20 stacked on the substrate 10. The pixel driving circuit Q and various types of signals are disposed in a multilayer film layer in the pixel circuit layer 20. The multilayer film layer in the pixel circuit layer 20 includes: a first semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a second semiconductor layer IGZO, a third gate metal layer Gate3, a first routing metal layer SD1, and a second routing metal layer SD2.

[0171] 9 and 10 , the first semiconductor layer POLY is located on the substrate 10 . The first semiconductor layer POLY includes a first electrode a3 of the driving transistor T3 and a second electrode b3 of the driving transistor T3 .

[0172] In addition, the first semiconductor layer POLY further includes corresponding first electrodes and second electrodes of six transistors, namely, a first reset transistor T1 , a data writing transistor T4 , a first light emission control transistor T5 , a second light emission control transistor T6 , a second reset transistor T7 and a third reset transistor T8 .

[0173] In some examples, the material of the first semiconductor layer POLY may include amorphous silicon, single crystal silicon, or polycrystalline silicon semiconductor material.

[0174] 9 and 11 , the first gate metal layer Gate1 is located on a side of the first semiconductor layer POLY away from the substrate 10 (as shown in FIG4 ). The first gate metal layer Gate1 includes a control electrode c3 of the driving transistor T3.

[0175] In addition, the first gate metal layer Gate1 also includes: the first semiconductor layer POLY also includes corresponding control electrodes of six transistors: a first reset transistor T1, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7 and a third reset transistor T8.

[0176] Exemplarily, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0177] Illustratively, a first gate insulating layer is provided between the first semiconductor layer POLY and the first gate metal layer Gate1 , and the first gate insulating layer electrically insulates the first semiconductor layer POLY from the first gate metal layer Gate1 .

[0178] For example, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0179] In addition, the first gate metal layer Gate1 can also be used to form part of the signal lines, including the first reset signal line R1, the enable signal line EM, the second scan signal line G2 and the second reset signal line R2.

[0180] In some examples, the first gate metal layer Gate1 may include a plurality of second scan signal lines G2 extending in a first direction X and arranged along a second direction Y. One second scan signal line G2 is electrically connected to a row of pixel driving circuits Q. The second scan signal line G2 may include a first portion, and the first portion of the second scan signal line G2 may be multiplexed as a control electrode c4 of the data writing transistor T4.

[0181] In some examples, the first gate metal layer Gate1 may include a plurality of first reset signal lines R1 extending in a first direction X and arranged along a second direction Y. The first reset signal line R1 may include a first portion, and the first portion of the first reset signal line R1 may be multiplexed as a control electrode c1 of the first reset transistor T1.

[0182] In some examples, the second reset signal line R2 located on the first gate metal layer Gate1 may include a first portion, and the first portion of the second reset signal line R2 may be multiplexed as the control electrode c7 of the second reset transistor T7. It will be understood that in other embodiments, when the second reset signal line R2 can be multiplexed as the third reset signal line R3, the second reset signal line R2 also includes a second portion spaced apart from the first portion, and the second portion of the second reset signal line R2 is multiplexed as the control electrode c8 of the third reset transistor T8.

[0183] In some examples, the first gate metal layer Gate1 may include a plurality of enable signal lines EM extending in a first direction X and arranged along a second direction Y. The enable signal lines EM may include a first portion and a second portion spaced apart from each other. The first portion of the enable signal line EM may be multiplexed as a control electrode c5 of the first emission control transistor T5, and the second portion of the enable signal line EM may be multiplexed as a control electrode c6 of the second emission control transistor T6.

[0184] It should be noted that, as shown in FIG13 , the orthographic projection of the first semiconductor layer POLY on the substrate 10 (referring to FIG4 ) overlaps with the orthographic projection of the first gate metal layer Gate1 on the substrate 10. The portion of the first semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the first semiconductor layer POLY not covered by the first gate metal layer G1 is a conductive portion, constituting a portion of the first electrode or the second electrode of each transistor.

[0185] In addition, in some examples, the first gate metal layer Gate1 further includes a first electrode S1 of the storage capacitor Cst, wherein the first electrode S1 of the storage capacitor Cst can be reused as the control electrode c3 of the driving transistor T3.

[0186] Based on this, there is no need to separately provide the control electrode c3 of the driving transistor T3, which can help simplify the manufacturing process of the pixel driving circuit Q. In addition, the first plate S1 of the storage capacitor Cst can be reused as the control electrode c3 of the driving transistor T3, and the first plate S1 of the storage capacitor Cst can be directly electrically connected to the control electrode c3 of the driving transistor T3 without the need for a separate connection portion, which can also facilitate the layout of the pixel driving circuit Q.

[0187] 9 and 12 , the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the first semiconductor layer POLY.

[0188] For example, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0189] For example, a second gate insulating layer may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1 , so as to electrically insulate the second gate metal layer Gate2 from the first gate metal layer Gate1 .

[0190] For example, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0191] In some embodiments, the second gate metal layer Gate2 includes a second plate S2 of a storage capacitor Cst, wherein an orthographic projection of the first plate S1 of the storage capacitor Cst on the substrate 10 (referring to FIG. 4 ) at least partially overlaps with an orthographic projection of the second plate S2 of the storage capacitor Cst on the substrate 10 to form the storage capacitor Cst. The second plate S2 of the storage capacitor Cst is electrically connected to the first power signal line Vdd.

[0192] In addition, the second gate metal layer Gate2 can also be used to form part of the signal lines, including the first scan signal line G1.

[0193] In some examples, the first scan signal line G1 located in the second gate metal layer Gate2 may include a first portion, and the first portion of the first scan signal line G1 may be reused as the control electrode c2 of the compensation transistor T2.

[0194] 9 and 14 , the second semiconductor layer IGZO is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. The second semiconductor layer IGZO includes a first electrode a2 of the compensation transistor T2 and a second electrode b2 of the compensation transistor T2.

[0195] 9 and 15 , the third gate metal layer Gate3 is located on a side of the second semiconductor layer IGZO away from the second gate metal layer Gate2. The third gate metal layer Gate3 may also include a plurality of first scan signal lines G1 extending along the first direction X and arranged along the second direction Y.

[0196] It should be noted that the compensation transistor T2 may be an oxide thin film transistor with a dual-gate structure. Specifically, the control electrode c2 of the compensation transistor T2 includes a top gate c21 of the compensation transistor T2 and a bottom gate c22 of the compensation transistor T2.

[0197] Based on this, the first portion of the first scan signal line G1 located on the second gate metal layer Gate2 can be reused as the bottom gate c22 of the compensation transistor T2. The first scan signal line G1 located on the third gate metal layer Gate3 can include a second portion, which can be reused as the top gate c21 of the compensation transistor T2.

[0198] In addition, the third gate metal layer Gate3 may further include a first initialization signal line Vinit1 , a second initialization signal line Vinit2 , and a third initialization signal line Vinit3 extending along the first direction X and arranged along the second direction Y.

[0199] 9 and 17 , the first routing metal layer SD1 is located on a side of the third gate metal layer Gate3 away from the second gate metal layer Gate2. The first routing metal layer SD1 can also be used to form the first conductive connection portion M1, the second conductive connection portion M2, and the third conductive connection portion M3.

[0200] In addition, the first routing metal layer SD1 also includes multiple other conductive transition structures. The multiple conductive transition structures include a first conductive transition structure PAD1, a second conductive transition structure PAD2, a third conductive transition structure PAD3, a fourth conductive transition structure PAD4, a fifth conductive transition structure PAD5, a sixth conductive transition structure PAD6, and a seventh conductive transition structure PAD7.

[0201] The first conductive transfer structure PAD1 can be used to electrically connect the first initialization signal line Vinit1 and the first electrode a1 of the first reset transistor T1 .

[0202] The second conductive transfer structure PAD2 can be used to electrically connect the second initialization signal line Vinit2 and the first electrode a7 of the second reset transistor T7.

[0203] The third conductive transfer structure PAD3 can be used to electrically connect the third initialization signal line Vinit3 and the first electrode a8 of the third reset transistor T8.

[0204] The fourth conductive transfer structure PAD4 can be used to electrically connect the data writing signal Data and the first electrode a4 of the data writing transistor T4.

[0205] The fifth conductive transfer structure PAD5 can be used to electrically connect the storage capacitor Cst (the second electrode of the storage capacitor Cst) and the first power signal line Vdd.

[0206] The sixth conductive transfer structure PAD6 can be used to electrically connect to the first electrode a5 of the first light emitting control transistor T5 and the first power signal line Vdd.

[0207] In addition, the multiple conductive transfer structures can also include a seventh conductive conversion structure PAD7, which can be equivalent to the fourth node N4 (return to Figure 5), and the seventh conductive conversion structure PAD7 can be used to electrically connect the second electrode b6 of the second light-emitting control transistor T6 and the light-emitting device O (anode layer).

[0208] Exemplarily, the material package of the first wiring metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0209] For example, a first planarization layer (PLN) is provided between the first wiring metal layer SD1 and the second gate metal layer Gate2 to electrically insulate the first wiring metal layer SD1 from the second gate metal layer Gate2.

[0210] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0211] As shown in Figures 9 and 19 , the second routing metal layer SD2 is located on a side of the first routing metal layer SD1 away from the first gate metal layer Gate1. The second routing metal layer SD2 includes a plurality of first power signal lines VDD extending in the second direction Y and arranged in the first direction X, and a plurality of data write signal lines Data extending in the second direction Y and arranged in the first direction X. Each data write signal line Data is electrically connected to a column of pixel driver circuits Q.

[0212] In some examples, the material of the second routing metal layer SD2 can be the same as that of the first routing metal layer SD1. It is understood that the material of the second routing metal layer SD2 can be different from that of the first routing metal layer SD1. The embodiments of the present disclosure are not limited to this.

[0213] Exemplarily, a second planarization layer is provided between the second routing metal layer SD2 and the first routing metal layer SD1 , and the second planarization layer electrically insulates the second routing metal layer SD2 from the first routing metal layer SD1 .

[0214] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0215] FIG20 is a structural diagram of a pixel driving circuit according to some other embodiments.

[0216] In some embodiments, as shown in conjunction with FIG. 9 and FIG. 20 , the difference between the pixel driving circuit Q shown in FIG. 9 and the pixel driving circuit Q shown in FIG. 20 is that the multilayer film layer in the pixel circuit layer 20 (referring to FIG. 4 ) further includes a shielding layer 30 (Bottom Shield Metal, BSM). The other film layer structures corresponding to the pixel driving circuit shown in FIG. 20 are the same as those corresponding to the pixel driving circuit Q shown in FIG. For reference, the film layer structure diagram corresponding to the pixel driving circuit Q shown in FIG. 9 is provided and will not be further described here.

[0217] The shielding layer 30 is located on a side of the first semiconductor layer POLY away from the first gate metal layer Gate1. The orthographic projection of the shielding layer 30 on the substrate 10 (as shown in FIG. 4 ) covers the orthographic projection of the driving transistor T3 on the substrate 10. At this time, the orthographic projection of the driving transistor T3 on the substrate 10 can be located within the area covered by the orthographic projection of the shielding layer 30 on the substrate 10. The shielding layer 30 is configured to receive a first voltage signal. By allowing the shielding layer 30 to receive the first voltage signal, static electricity accumulation in the shielding layer 30 can be reduced.

[0218] The above description, combined with the accompanying drawings, details the film layer distribution of the eight transistors and each signal line in the array substrate 100. Based on this, the following description will specifically describe the planar position relationship of each transistor in the pixel driving circuit Q in combination with the accompanying drawings.

[0219] In some embodiments, in combination with FIG5 and FIG9 to FIG19 , the pixel driving circuit Q includes a compensation transistor T2 , a data writing transistor T4 and a driving transistor T3 :

[0220] The second electrode b2 of the compensation transistor T2 is electrically connected to the control electrode c3 of the driving transistor T3, the first electrode a2 of the compensation transistor T2 is electrically connected to the second electrode b3 of the driving transistor T3, and the control electrode c2 of the compensation transistor T2 is electrically connected to the first scanning signal line G1. Furthermore, the first electrode a4 of the data writing transistor T4 is electrically connected to the data writing signal line Data, the second electrode b4 of the data writing transistor T4 is electrically connected to the second conductive connecting portion M2, and the control electrode c4 of the data writing transistor T4 is electrically connected to the second scanning signal line G2.

[0221] Based on the electrical connection between the compensation transistor T2, the data writing transistor T4 and the driving transistor T3, the data writing transistor T4 and the compensation transistor T2 are respectively electrically connected to different poles (the first pole and the second pole) of the driving transistor T3. Therefore, the data writing transistor T4 and the compensation transistor T2 can be respectively arranged on both sides of the driving transistor T3, so that the data writing transistor T4 and the compensation transistor T2 are respectively electrically connected to different poles of the driving transistor T3, thereby improving problems such as cross-wires and windings, and helping to simplify the layout of the array substrate 100.

[0222] In some embodiments, as shown in conjunction with Figures 4, 5, and 9 to 19, the pixel driving circuit Q further includes a first reset transistor T1. A control electrode c1 of the first reset transistor T1 is electrically connected to a first reset signal line R1, a first electrode a1 of the first reset transistor T1 is electrically connected to a first initialization signal line Vinit1, and a second electrode b1 of the first reset transistor T1 is electrically connected to a third conductive connection portion M3. Along the second direction Y, an orthogonal projection of the first reset signal line R1 on the substrate 10 is located on a side of the orthogonal projection of the first scanning signal line G1 on the substrate 10 that is away from an orthogonal projection of the driving transistor T3 on the substrate 10.

[0223] Because the first reset signal line R1 can include a first portion, the first portion of the first reset signal line R1 is multiplexed as the control electrode c1 of the first reset transistor T1. Positioning the first reset signal line R1 on a side of the first scan signal line G1 away from the drive transistor T3 is equivalent to positioning the first reset transistor T1 on a side of the first scan signal line G1 closer to the edge of the pixel drive circuit Q. Furthermore, the first reset signal line R1 and the first reset transistor T1 can be staggered relative to the first scan signal line G1, preventing parasitic capacitance from forming between the first reset signal line R1 and the first reset transistor T1 and the first scan signal line G1, thereby preventing the potential of the first scan signal transmitted by the first scan signal line G1 from being affected.

[0224] In some embodiments, as shown in conjunction with Figures 4, 5, and 9 to 19, along the second direction Y, the orthographic projection of the first initialization signal line Vinit1 on the substrate 10 is located on a side of the orthographic projection of the first reset signal line R1 on the substrate 10 that is away from the orthographic projection of the first scan signal line G1 on the substrate 10. This is equivalent to arranging the first initialization signal line Vinit1 at the edge of the corresponding sub-pixel driving circuit Q. Figure 6 illustrates an example of arranging the first initialization signal line Vinit1 at the upper edge of the corresponding pixel driving circuit Q.

[0225] This arrangement prevents the orthographic projection of the first initialization signal line Vinit1 on the substrate 10 from overlapping with the orthographic projections of other transistors and other structures in the corresponding pixel driving circuit Q on the substrate 10. This not only facilitates the layout of the pixel driving circuit Q, but also prevents the generation of coupling capacitance that would cause mutual influence on potential, thereby improving the stability of the pixel driving circuit Q.

[0226] In some embodiments, as shown in conjunction with FIG5 , FIG9 to FIG19 , two adjacent pixel driving circuits Q are included along the second direction Y. In the two adjacent pixel driving circuits Q, the first initialization signal line Vinit1 electrically connected to the previous pixel driving circuit Q is arranged at an edge position of a side of the previous pixel driving circuit Q away from the next pixel driving circuit Q. Furthermore, in the two adjacent pixel driving circuits Q, the first initialization signal line Vinit1 electrically connected to the next pixel driving circuit Q is arranged at an edge position of a side of the previous pixel driving circuit Q close to the next pixel driving circuit Q.

[0227] Such an arrangement fully utilizes the space in the array substrate 100 along the direction perpendicular to the substrate 10 to layout the pixel driving circuit and various signal lines electrically connected thereto, thereby simplifying the layout of the array substrate 100 .

[0228] In some examples, in two adjacent pixel driving circuits Q, the positive projection of the first initialization signal line Vinit1 electrically connected to the next pixel driving circuit Q on the substrate 10 overlaps with the positive projection of the second reset signal line R2 electrically connected to the previous pixel driving circuit Q on the substrate 10.

[0229] Since the first initialization signal line Vinit1 is located on the third gate metal layer Gate3, and the second reset signal line R2 is located on the first gate metal layer Gate1, that is, the first initialization signal line Vinit1 and the second reset signal line R2 are arranged on different layers. Based on this, in two adjacent pixel driving circuits Q, the orthographic projection of the first initialization signal line Vinit1 electrically connected to the next pixel driving circuit Q on the substrate 10 overlaps with the orthographic projection of the second reset signal line R2 electrically connected to the previous pixel driving circuit Q on the substrate 10. This can fully utilize the space in the array substrate 100 along the direction perpendicular to the substrate 10, thereby simplifying the layout of the array substrate 100.

[0230] In some embodiments, as shown in conjunction with FIG. 5 , FIG. 9 to FIG. 19 , the pixel driving circuit Q further includes a first emission control transistor T5 and a second emission control transistor T6. A control electrode c5 of the first emission control transistor T5 is electrically connected to the enable signal line EM, a first electrode a5 of the first emission control transistor T5 is electrically connected to the first power signal line Vdd, and a second electrode b5 of the first emission control transistor T5 is electrically connected to the second conductive connection portion M2. A control electrode c6 of the second emission control transistor T6 is electrically connected to the enable signal line EM, a first electrode a6 of the second emission control transistor T6 is electrically connected to the third conductive connection portion M3, and a second electrode b6 of the second emission control transistor T6 is electrically connected to the light-emitting device O. Along the second direction Y, the orthographic projection of the enable signal line EM on the substrate 10 is located on a side of the orthographic projection of the driving transistor T3 on the substrate 10 that is away from the orthographic projection of the first scan signal line G1 on the substrate 10.

[0231] Based on this, the driving transistor T3 and the enable signal line EM are collectively arranged on one side of the first scanning signal line G1, that is, the driving transistor T3 and the enable signal line EM are staggered with the first scanning signal line G1. This can help prevent the problem of parasitic capacitance between them causing the pull potential change.

[0232] Furthermore, since the enable signal line EM may include a first portion and a second portion spaced apart, the first portion of the enable signal line EM may be multiplexed as the control electrode c5 of the first emission control transistor T5, and the second portion of the enable signal line EM may be multiplexed as the control electrode c6 of the second emission control transistor T6.

[0233] Based on this, it is equivalent to arranging the first light-emitting control transistor T5 and the second light-emitting control transistor T6 on a side of the driving transistor T3 away from the first scanning signal line G1. This can also prevent the first electrode a3 of the driving transistor T3, the second electrode b3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, and the first electrode a6 of the second light-emitting control transistor T6 from overlapping with the first scanning signal line G1 when the driving transistor T3 is electrically connected to the first light-emitting control transistor T5 and the second light-emitting control transistor T6. Therefore, it can also prevent the first electrode a3 of the driving transistor T3, the second electrode b3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, and the first electrode a6 of the second light-emitting control transistor T6 from influencing each other with the potential of the first scanning signal transmitted by the first scanning signal line G1, so as to prevent the stability of the driving transistor T3 from being affected in the end.

[0234] In some embodiments, as shown in conjunction with Figures 4, 5, and 9 to 19, the array substrate 100 further includes: a plurality of second initialization signal lines Vinit2 and a plurality of second reset signal lines R2. The plurality of second initialization signal lines Vinit2 extend along the first direction X and are arranged along the second direction Y. Furthermore, the plurality of second reset signal lines R2 extend along the first direction X and are arranged along the second direction Y. The pixel driving circuit Q further includes a second reset transistor T7, wherein a control electrode c7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, a first electrode a7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode b7 of the second reset transistor T7 is electrically connected to the light-emitting device O.

[0235] Along the second direction Y, the orthographic projection of the second reset signal line R2 on the substrate 10 is located on a side of the orthographic projection of the enable signal line EM on the substrate 10 that is away from the orthographic projection of the drive transistor T3 on the substrate 10. Furthermore, this is equivalent to arranging the second reset signal line R2 at an edge region of the enable signal line EM close to the pixel drive circuit Q. This prevents the second reset signal line R2 from overlapping with structures such as the first conductive connection structure M1 and the second conductive connection structure M2 in the pixel drive circuit Q, thereby preventing the generation of coupling capacitance that could affect potentials, and improving the stability of the pixel drive circuit Q.

[0236] Furthermore, in some examples, since the second reset signal line R2 may include a first portion and a second portion spaced apart, the first portion of the second reset signal line R2 may be multiplexed as the control electrode c7 of the second reset transistor T7, and the second portion of the second reset signal line R2 may be multiplexed as the control electrode c8 of the third reset transistor T8. This is equivalent to disposing the second reset transistor T7 and the third reset transistor T8 on a side of the enable signal line EM away from the driving transistor T3. In other words, the second reset transistor T7 and the third reset transistor T8 are disposed on a side of the first emission control transistor T5 and the second emission control transistor T6 away from the driving transistor T3.

[0237] Based on this, it is advantageous to centrally arrange the first emission control transistor T5 and the third reset transistor T8 on one side of the driving transistor T3, so that the second electrode b3 of the first emission control transistor T5 and the second electrode b8 of the third reset transistor T8 are electrically connected. Furthermore, it is advantageous to centrally arrange the second emission control transistor T6 and the second reset transistor T7 on one side of the driving transistor T3, so that the first electrode a6 of the second emission control transistor T6 and the second electrode b7 of the second reset transistor T7 are electrically connected.

[0238] In some embodiments, as shown in conjunction with FIG4 , FIG5 , and FIG9 to FIG19 , two adjacent pixel driving circuits Q are included along the second direction Y. In the two adjacent pixel driving circuits Q, the second initialization signal line Vinit2 electrically connected to the previous pixel driving circuit Q is disposed at an edge position of a side of the previous pixel driving circuit Q away from the next pixel driving circuit Q. Furthermore, in the two adjacent pixel driving circuits Q, the second initialization signal line Vinit2 electrically connected to the next pixel driving circuit Q is disposed at an edge position of a side of the previous pixel driving circuit Q close to the next pixel driving circuit Q.

[0239] Such an arrangement fully utilizes the space in the array substrate 100 along the direction perpendicular to the substrate 10 to layout the pixel driving circuit and various signal lines electrically connected thereto, thereby simplifying the layout of the array substrate 100 .

[0240] In some examples, in two adjacent pixel driving circuits Q, the positive projection of the second initialization signal line Vinit2 electrically connected to the next pixel driving circuit Q on the substrate 10 overlaps with the positive projection of the first reset signal line R1 electrically connected to the previous pixel driving circuit Q on the substrate 10.

[0241] Since the second initialization signal line Vinit2 is located on the third gate metal layer Gate3, and the first reset signal line R1 is located on the first gate metal layer Gate1, that is, the second initialization signal line Vinit2 and the first reset signal line R1 are arranged on different layers. Based on this, in two adjacent pixel driving circuits Q, the orthographic projection of the second initialization signal line Vinit2 electrically connected to the next pixel driving circuit Q on the substrate 10 overlaps with the orthographic projection of the first reset signal line R1 electrically connected to the previous pixel driving circuit Q on the substrate 10. This can fully utilize the space in the array substrate 100 along the direction perpendicular to the substrate 10, thereby simplifying the layout of the array substrate 100.

[0242] In some embodiments, as shown in conjunction with Figures 5, 9 to 19, the array substrate 100 further includes: a plurality of third initialization signal lines Vinit3 and a plurality of third reset signal lines R3. The plurality of third initialization signal lines Vinit3 extend along the first direction X and are arranged along the second direction Y. The plurality of third reset signal lines R3 extend along the first direction X and are arranged along the second direction Y. The pixel driving circuit Q further includes a third reset transistor T8, a control electrode c8 of the third reset transistor T8 electrically connected to the third reset signal line R3, a first electrode a8 of the third reset transistor T8 electrically connected to the third initialization signal line Vinit3, and a second electrode b8 of the third reset transistor T8 electrically connected to the second conductive connection portion M2. The orthographic projection of the third initialization signal line Vinit3 on the substrate 10 is located on a side of the orthographic projection of the driving transistor T3 on the substrate 10 that is away from the orthographic projection of the first scan signal line G1 on the substrate 10.

[0243] This can prevent the third initialization signal line Vinit1 from overlapping with the drive transistor T3 and the first scanning signal line G1, thereby preventing coupling capacitance from being generated and affecting the potential of the drive transistor T3, thereby improving the stability of the pixel drive circuit Q.

[0244] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , the orthographic projection of the enable signal line EM on the substrate 10 at least partially overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate 10 .

[0245] Because the third initialization signal line Vinit3 is located on the third gate metal layer Gate3, and the enable signal line EM is located on the first gate metal layer Gate1, that is, the third initialization signal line Vinit3 and the enable signal line EM are arranged on different layers. Based on this, the orthographic projection of the third initialization signal line Vinit3 on the substrate 10 is set to overlap with the orthographic projection of the enable signal line EM on the substrate 10. This can fully utilize the space in the array substrate 100 in a direction perpendicular to the substrate 10, thereby simplifying the layout of the array substrate 100.

[0246] In some embodiments, in combination with Figures 4, 5, and 9 to 19, the orthographic projection of the second conductive connection portion M2 on the substrate 10 at least partially overlaps with the orthographic projection of the enable signal line EM on the substrate 10, and the orthographic projection of the second conductive connection portion M2 on the substrate 10 at least partially overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate 10.

[0247] Since the third initialization signal provided by the third initialization signal line Vinit3 is a constant voltage signal, the positive projection of the second conductive connection part M2 on the substrate 10 is set to at least partially overlap with the positive projection of the third initialization signal line Vinit3 on the substrate 10. The third initialization signal line Vinit3 can be used to maintain the voltage of the second conductive connection part M2, thereby preventing the enable signal provided by the enable signal line EM from affecting the potential of the driving transistor T3 when it jumps, which can help improve the stability of the pixel driving circuit Q.

[0248] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , the orthographic projection of the second conductive connection portion M2 on the substrate 10 overlaps with the orthographic projection of the first power signal line Vdd on the substrate 10 .

[0249] Since the first power signal provided by the first power signal line Vdd is a constant voltage signal, the orthographic projection of the second conductive connection portion M2 on the substrate 10 is set to at least partially overlap with the orthographic projection of the first power signal line Vdd on the substrate 10. The first power signal line Vdd can be used to maintain the voltage of the second conductive connection portion M2, further preventing the problem of the enable signal provided by the enable signal line EM affecting the potential of the driving transistor T3 when jumping, which can be beneficial to improving the stability of the pixel driving circuit Q.

[0250] The above description, combined with the accompanying drawings, details the distribution of the transistors in the array substrate 100. Based on this, the following description, combined with the accompanying drawings, details how to layout the first conductive connection portion M1 and the second conductive connection portion M2 in the pixel driving circuit Q so that the first conductive connection portion M1 and the second conductive connection portion M2 do not overlap with the first scan signal line.

[0251] In some embodiments, as shown in FIG. 5 and FIG. 9 to FIG. 19 , the position of the first conductive connection portion M1 is adjusted so that along the second direction Y, the first conductive connection portion M2 is located on one side of the first scan signal line G1 .

[0252] In this way, the first conductive connection portion M1 and the first scanning signal line G1 can be staggered, that is, the orthographic projection of the first conductive connection portion M1 on the substrate 10 does not overlap with the orthographic projection of the first scanning signal line G1 on the substrate 10 .

[0253] Based on this, parasitic capacitance can be prevented from forming between the first scanning signal line G1 and the first conductive connection portion M1 in the corresponding pixel driving circuit Q, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the first conductive connection portion M1. Therefore, the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3) can be improved, thereby improving the problem of worsening lateral crosstalk.

[0254] In other embodiments, since the first conductive connection portion M1 needs to be electrically connected to the control electrode c3 of the driving transistor T3, when the first conductive connection portion M2 is located in a region on one side of the first scanning signal line G1 along the second direction Y, the orthographic projection of the first conductive connection portion M1 on the substrate 10 is arranged to be between the orthographic projection of the driving transistor T3 on the substrate 10 and the orthographic projection of the first scanning signal line G1 on the substrate 10.

[0255] This is equivalent to arranging the first conductive connection portion M1 on the side of the first scanning signal line G1 close to the driving transistor T3, which can also help to reduce the distance between the first conductive connection portion M1 and the control electrode c3 of the driving transistor T3, facilitate electrical connection between the two, and facilitate the layout of the pixel driving circuit Q.

[0256] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , along the second direction Y, the second conductive connection portion M2 is located on one side of the first scan signal line G1 .

[0257] In this way, the second conductive connection portion M2 and the first scanning signal line G1 can be staggered, that is, the orthographic projection of the second conductive connection portion M2 on the substrate 10 does not overlap with the orthographic projection of the first scanning signal line G1 on the substrate 10 .

[0258] Based on this, parasitic capacitance can be prevented from forming between the first scanning signal line G1 and the second conductive connection portion M2 in the corresponding pixel driving circuit Q, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the second conductive connection portion M2. Therefore, the stability of the driving transistor T3 (the first electrode a3 of the driving transistor T3) can be improved, thereby improving the problem of worsening lateral crosstalk.

[0259] In other embodiments, as shown in combination with FIG. 5 and FIG. 9 to FIG. 19 , along the second direction Y, the second conductive connection portion M2 and the driving transistor T3 are located on the same side of the first scan signal line G1 .

[0260] Since the second conductive connection portion M2 can be the second node N2 in the equivalent circuit diagram of the pixel driving circuit Q (returning to FIG. 4 ), and the second conductive connection portion M2 needs to be electrically connected to the first electrode a3 of the driving transistor T3, arranging the second conductive connection portion M2 and the driving transistor T3 on the same side of the first scanning signal line G1 along the second direction Y allows the second conductive connection portion M2 and the driving transistor T3 to be centrally arranged, preventing the connection component between the second conductive connection portion M2 and the driving transistor T3 from crossing the first scanning signal line G1, thereby preventing the second conductive connection portion M2 and the driving transistor T3 from mutually inducing a potential jump with the first scanning signal line G1. Therefore, it can be beneficial to improve the stability of the driving transistor T3 (the first electrode a3 of the driving transistor T3), further, it can be beneficial to improve the stability of the control electrode c2 of the driving transistor, and it can be beneficial to improve the problem of worsening lateral crosstalk.

[0261] Here, “across” means that the orthographic projection of the connecting component on the substrate 10 overlaps with the orthographic projection of the first scanning signal line G1 on the substrate 10 .

[0262] It should be noted that, in combination with Figures 4, 5, and 9 to 19, since the second conductive connection part M2 can be the second node N2 in the equivalent circuit diagram of the pixel driving circuit Q, the first electrode a3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, the second electrode b4 of the data writing transistor T4, and the second electrode b8 of the third reset transistor T8 are all electrically connected to the second node N2.

[0263] Based on the above connection relationship, the first electrode a3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, and the second electrode b4 of the data writing transistor T4 can be formed on the first semiconductor layer POLY through the same patterning process, so that the first electrode a3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, and the second electrode b4 of the data writing transistor T4 are directly electrically connected.

[0264] As for the third reset transistor T8, the second electrode b8 of the third reset transistor T8 can be electrically connected to the second electrode b4 of the data writing transistor T4 by setting a second conductive connection part M2, so that the first electrode a3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, the second electrode b4 of the data writing transistor T4, and the second electrode b8 of the third reset transistor T8 are all electrically connected to the second node N2.

[0265] In summary, the second conductive connection portion M2 is used to electrically connect the second electrode b8 of the third reset transistor T8 to the second electrode b4 of the data write transistor T4. The second conductive connection portion M2 needs to utilize the second electrode b4 of the data write transistor T4 to electrically connect to the first electrode a3 of the drive transistor T3. In other words, the "connecting member between the second conductive connection portion M2 and the drive transistor T3" can be the second electrode b4 of the data write transistor T4.

[0266] In some other embodiments, in combination with Figures 4, 5, and 9 to 19, when the second conductive connection portion M2 and the driving transistor T3 are located on the same side of the first scanning signal line G1 along the second direction Y: it can also be arranged that along the first direction X, the orthographic projection of the second conductive connection portion M2 on the substrate 10 is located on a side where the orthographic projection of the first conductive connection portion M1 on the substrate 10 is away from the orthographic projection of the compensation transistor T2 on the substrate 10, and the orthographic projection of the second conductive connection portion M2 on the substrate 10 is located on a side where the orthographic projection of the driving transistor T3 on the substrate 10 is away from the orthographic projection of the compensation transistor T2 on the substrate 10.

[0267] Because the data write transistor T4 and the compensation transistor T2 are electrically connected to different poles (the first pole and the second pole) of the drive transistor T3, respectively, the data write transistor T4 and the compensation transistor T2 can be respectively arranged on either side of the drive transistor T3 to facilitate wiring layout. Based on this, the second conductive connection portion M2 is arranged on the side of the drive transistor T3 away from the compensation transistor T2, that is, the second conductive connection portion M2 is arranged on the side of the drive transistor T3 close to the data write transistor T4. This can facilitate the electrical connection between the second conductive connection portion M2 and the second pole b4 of the data write transistor T4, thereby facilitating the layout of the pixel drive circuit Q.

[0268] The above describes in detail how to layout the first conductive connection part M1 and the second conductive connection part M2 in the pixel driving circuit Q in combination with the drawings. The following describes in detail how to layout the first scanning signal line in the space corresponding to the pixel driving circuit Q in combination with the drawings.

[0269] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the control electrode c3 of the driving transistor T3 on the substrate 10 .

[0270] Based on this, parasitic capacitance can be prevented from forming between the first scanning signal line G1 and the control electrode c3 of the driving transistor T3, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the control electrode c3 of the driving transistor T3. Therefore, the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3) can be improved, thereby improving the problem of worsening lateral crosstalk.

[0271] In some embodiments, as shown in conjunction with Figures 4, 5, and 9 to 19, because the first conductive connection portion M1 is electrically connected to the control electrode c3 of the driving transistor T3 and the second electrode b2 of the compensation transistor T2, the potentials of the second electrode b2 of the compensation transistor T2, the first conductive connection portion M1, and the control electrode c3 of the driving transistor T3 affect each other.

[0272] Based on this, the orthographic projection of the first scanning signal line G1 on the substrate 10 is set to not overlap with the orthographic projection of the second electrode b2 of the compensation transistor T2 on the substrate 10. This prevents the formation of parasitic capacitance between the first scanning signal line G1 and the second electrode b2 of the compensation transistor T2, thereby improving the problem of potential jumps caused by the first scanning signal line G1 and the second electrode b2 of the compensation transistor T2. In other words, it prevents the second electrode b2 of the compensation transistor T2 from pulling the potential of the control electrode c3 of the driving transistor T3. Therefore, it can help improve the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3) and further improve the problem of worsening lateral crosstalk.

[0273] In some embodiments, referring to Figures 4, 5, 15 and 16, the orthographic projection of the first scanning signal line G1 on the substrate 10 can be set to not overlap with the orthographic projection of the control electrode c3 of the driving transistor T3 on the substrate 10, and the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second electrode b2 of the compensation transistor T2 on the substrate 10.

[0274] Based on this, the first scanning signal line G1 can be prevented from forming a coupling capacitance with the control electrode c3 of the driving transistor T3 and the second electrode b2 of the compensation transistor T2, thereby being beneficial to improving the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3), and further being beneficial to improving the problem of deterioration of lateral crosstalk.

[0275] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the first electrode a3 of the driving transistor T3 on the substrate 10 .

[0276] Based on this, the formation of a coupling capacitor between the first scanning signal line G1 and the first electrode a3 of the driving transistor T3 can be prevented, thereby preventing the problem of potential jumps caused by the first scanning signal line G1 and the first electrode a3 of the driving transistor T3. Furthermore, the first electrode a3 of the driving transistor T3 can be prevented from pulling the potential of the control electrode c3 of the driving transistor T3 due to the gate-source capacitance, thereby improving the stability of the driving transistor T3 and further alleviating the problem of deteriorating lateral crosstalk.

[0277] In some embodiments, as shown in conjunction with FIG4 , FIG5 , and FIG9 to FIG19 , since the first electrode a3 of the driving transistor T3 and the second electrode b4 of the data writing transistor T4 are electrically connected, the potentials of the first electrode a3 of the driving transistor T3 and the second electrode b4 of the data writing transistor T4 may affect each other.

[0278] Based on this, the orthographic projection of the first scanning signal line G1 on the substrate 10 can be set to not overlap with the orthographic projection of the first electrode a3 of the driving transistor T3 on the substrate 10, and the orthographic projection of the first scanning signal line G1 on the substrate 10 can also be set to not overlap with the orthographic projection of the second electrode b4 of the data writing transistor T4 on the substrate 10.

[0279] Furthermore, this prevents the formation of a coupling capacitor between the first scanning signal line G1 and the second electrode b4 of the data writing transistor T4, thereby preventing the potential jump caused by the first scanning signal line G1 and the second electrode b4 of the data writing transistor T4. This also prevents the potential between the second electrode b4 of the data writing transistor T4 and the first electrode a3 of the driving transistor T3 from influencing each other, thereby preventing the potential change of the control electrode c3 of the driving transistor T3. This improves the stability of the driving transistor T3 and further improves the problem of worsening lateral crosstalk.

[0280] In addition, in other embodiments, in combination with Figures 4, 5, and 9 to 19, the first electrode a3 of the driving transistor T3, the second electrode b5 of the first light-emitting control transistor T5, the second electrode b4 of the data writing transistor T4, and the second electrode b8 of the third reset transistor T8 are electrically connected to each other.

[0281] In addition to setting the orthographic projection of the first scanning signal line G1 on the substrate 10 to not overlap with the orthographic projection of the first electrode a3 of the driving transistor T3 on the substrate 10, and setting the orthographic projection of the first scanning signal line G1 on the substrate 10 to not overlap with the orthographic projection of the second electrode b4 of the data writing transistor T4 on the substrate 10, the orthographic projection of at least one of the second electrode b5 of the first light-emitting control transistor T5 and the second electrode b8 of the third reset transistor T8 on the substrate 10 can also be set to not overlap with the orthographic projection of the first scanning signal line G1 on the substrate 10.

[0282] Based on this, the problem of potential jump of the driving transistor T3 (first electrode a3 and control electrode c3) caused by the potential jump of any transistor following the first scanning signal transmitted by the first scanning signal line G1 can be prevented.

[0283] To sum up, the positive projection of the first scanning signal line G1 on the substrate 10 needs to avoid the positive projection of any one of the first electrode a3 of the driving transistor T3 electrically connected to the second node N2 (return to Figure 5) in the equivalent circuit, the second electrode b5 of the first light-emitting control transistor T5, the second electrode b4 of the data writing transistor T4, and the second electrode b8 of the third reset transistor T8 on the substrate 10, so as to prevent them from ultimately affecting the driving transistor T3 (the control electrode c3 of the driving transistor T3), which can help to improve the problem of worsening lateral crosstalk.

[0284] In some embodiments, as shown in combination with FIG. 4 , FIG. 5 , and FIG. 9 to FIG. 19 , the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second electrode b3 of the driving transistor T3 on the substrate 10 .

[0285] Based on this, the formation of a coupling capacitor between the first scanning signal line G1 and the second electrode b3 of the driving transistor T3 can be prevented, thereby preventing the problem of potential jumps caused by the first scanning signal line G1 and the second electrode b3 of the driving transistor T3. Furthermore, the second electrode b3 of the driving transistor T3 can be prevented from pulling the potential of the control electrode c3 of the driving transistor T3 due to the formed capacitance, thereby improving the stability of the driving transistor T3 and further alleviating the problem of deteriorating lateral crosstalk.

[0286] In some embodiments, in combination with Figures 4, 5, and 9 to 19, the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the first electrode a3 of the driving transistor T3 on the substrate 10, and the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second electrode b3 of the driving transistor T3 on the substrate 10.

[0287] Based on this, the formation of a coupling capacitance between the first scanning signal line G1 and the first electrode a3 and the second electrode b3 of the driving transistor T3 can be prevented, thereby preventing the problem of potential jumps caused by the first scanning signal line G1 and the first electrode a3 and the second electrode b3 of the driving transistor T3. Furthermore, the first electrode a3 and the second electrode b3 of the driving transistor T3 can be prevented from pulling the potential of the control electrode c3 of the driving transistor T3 due to the formed capacitance, thereby improving the stability of the driving transistor T3 and further alleviating the problem of deteriorating lateral crosstalk.

[0288] In some embodiments, in combination with Figures 4, 5, and 9 to 19, the difference from the pixel driving circuit shown in Figure 6 is that the relative positions of the first scanning signal line G1 and the second scanning signal line G2 are adjusted so that along the second direction Y, the positive projection of the first scanning signal line G1 on the substrate 10 is located on the side where the positive projection of the second scanning signal line G2 on the substrate 10 is away from the positive projection of the driving transistor T3 on the substrate 10.

[0289] Since the second scanning signal line G2 needs to be electrically connected to the control electrode c4 of the data writing transistor T4, the second scanning signal line G2 is set at a position closer to the driving transistor T3 relative to the first scanning signal line G1, so that the data writing transistor T4 can be set at a position closer to the driving transistor T3 than the first scanning signal line G1.

[0290] Such a configuration can help avoid the problem that the second conductive connection portion M2 electrically connected to the second electrode b4 of the data writing transistor T4 needs to cross the first scanning signal line G1, thereby achieving the orthographic projection of the first scanning signal line G1 on the substrate 10 and the orthographic projection of the second conductive connection portion M2 on the substrate 10 without overlapping, thereby reducing the mutual influence of voltage jumps between the first scanning signal line G1 and the second conductive connection portion M2.

[0291] In addition, since the first scanning signal line G1 needs to be electrically connected to the control electrode c2 of the compensation transistor T2, the second scanning signal line G2 is set at a position closer to the driving transistor T3 relative to the first scanning signal line G1, so that the control electrode c2 of the compensation transistor T2 can be set on the side of the second scanning signal line G2 away from the driving transistor T3, and the second electrode b2 of the compensation transistor T2 can also be set at a position closer to the driving transistor T3 on the first scanning signal line G1.

[0292] Such a configuration can help avoid the problem that the first conductive connection portion M1 electrically connected to the second electrode b2 of the compensation transistor T2 needs to cross the first scanning signal line G1, thereby realizing the orthographic projection of the first scanning signal line G1 on the substrate 10, and the orthographic projection of the first conductive connection portion M1 on the substrate 10 has no overlap, so as to reduce the mutual influence of voltage jumps between the first scanning signal line G1 and the first conductive connection portion M1.

[0293] Based on the above embodiments, the present disclosure introduces how to implement the first scanning signal line G1 so that it does not overlap with the first conductive connection structure M1 and the second conductive connection structure M2.

[0294] However, the inventors have discovered, based on the pixel driving circuit Q shown in FIG6 and FIG9 , that the first conductive connection structure M1 overlaps with both the first scan signal line G1 and the second scan signal line G2. In this case, the potential of the first conductive connection structure M1 is affected by the scan signals transmitted by the first scan signal line G1 and the second scan signal line G2.

[0295] Specifically, after the data writing phase, the second scanning signal transmitted by the second scanning signal line G2 is boosted from a low voltage signal to a high voltage signal, thereby turning off the data writing transistor T4. Furthermore, the first scanning signal transmitted by the first scanning signal line G1 is stepped down from a high voltage signal to a low voltage signal, thereby turning off the compensation transistor T2.

[0296] That is, the voltage jumps of the two scan signal lines mentioned above will affect the potential of the first conductive connection structure M1. Specifically, the second scan signal transmitted by the second scan signal line G2 is boosted from a low voltage signal to a high voltage signal, which will increase the potential of the first conductive connection structure M1. Furthermore, the first scan signal transmitted by the first scan signal line G1 is stepped down from a high voltage signal to a low voltage signal, which will lower the potential of the first conductive connection structure M1.

[0297] At this time, the potential of the first conductive connection portion M1 can be set to a voltage value within a preset range. Furthermore, the data write signal provided by the data write signal line Data, which is within a preset range, can be used to perform potential compensation based on the potential of the control electrode c3 (first conductive connection portion M1) of the driving transistor T3, so that the subsequent pixel driving circuit Q can drive the light-emitting device O to emit light.

[0298] However, when the pixel driving circuit Q shown in Figure 6 is adjusted to the pixel driving circuit Q shown in Figure 9, the first conductive connection structure M1 is adjusted from overlapping with both the first scanning signal line G1 and the second scanning signal line G2 to a situation where the first conductive connection structure M1 does not overlap with the first scanning signal line G, and the first conductive connection structure M1 overlaps with the second scanning signal line G2.

[0299] That is, the potential of the first conductive connection structure M1 is basically not affected by the first scan signal transmitted by the first scan signal line G1, and the potential of the first conductive connection structure M1 is still affected by the second scan signal transmitted by the second scan signal line G2.

[0300] At this time, since the potential of the first conductive connection structure M1 is still affected by the second scanning signal transmitted by the second scanning signal line G2, the second scanning signal will increase the potential of the first conductive connection part M1, which is equivalent to increasing the potential of the first conductive connection part M1 to a voltage value higher than the preset range.

[0301] Furthermore, the data write signal from the data write signal line Data required for the control electrode c3 of the subsequent driving transistor T3 can be lower than the originally preset value. For example, the threshold value range of the data write signal from the data write signal line Data required for the potential of the control electrode c3 of the driving transistor T3 in the pixel driving circuit Q shown in FIG6 is approximately 3V to 7.5V, while the threshold value range of the data write signal from the data write signal line Data required for the potential of the control electrode c3 of the driving transistor T3 in the pixel driving circuit Q shown in FIG9 is approximately 2.8V to 7.3V.

[0302] In summary, the pixel driving circuit Q shown in FIG9 may cause the threshold range of the data write signal from the data write signal line Data to change, which may cause the driver chip (full name: Integrated Circuit, English abbreviation: IC) in the display panel 200 to be unable to provide the stepped-down data write signal, thereby affecting the display effect of the display panel 200.

[0303] In some embodiments, referring to FIG. 9 and FIG. 14 , the compensation transistor T2 includes a semiconductor structure H, which includes a first portion H1, a second portion H2, and a third portion H3 connected in sequence. The third portion H3 extends along a first direction X, the second portion H2 extends along a second direction Y, and the first portion H1 extends along the first direction X.

[0304] In some examples, the semiconductor structure H is approximately L-shaped, wherein the first sub-portion H11 protrudes relative to the second portion H2 toward a side of the data writing transistor T4 . Along the first direction X, the width of the third portion H3 is approximately equal to the width of the second portion H2 .

[0305] The orthographic projection of the second portion H2 of the conductor structure H on the substrate 10 (referring to FIG. 4 ) overlaps with the orthographic projection of the first scan signal line G1 (the control electrode c3 of the driving transistor T3) on the substrate 10. The orthographic projection of the third portion H3 of the semiconductor structure H on the substrate 10 is located on a side of the orthographic projection of the first scan signal line G1 on the substrate 10 that is away from the orthographic projection of the driving transistor T3 on the substrate 10. The third portion H3 of the semiconductor structure H serves as the first electrode a2 of the compensation transistor T2. Furthermore, the orthographic projection of the first portion H1 of the semiconductor structure H on the substrate 10 is located between the first scan signal line G1 and the orthographic projection of the driving transistor T3 on the substrate 10.

[0306] Along the extension direction of the second scan signal line, the first portion H1 includes a first sub-portion H11 and a second sub-portion H12, which are connected. The orthographic projection of the second sub-portion H12 on the substrate 10 is located between the orthographic projection of the first sub-portion H11 on the substrate 10 and the orthographic projection of the control electrode c2 of the compensation transistor T2 on the substrate 10. The first sub-portion H11 is electrically connected to the first conductive connection structure M2. The orthographic projection of the first portion H1 on the substrate 10 overlaps with the orthographic projection of the second scan signal line G2 on the substrate 10. In other words, the orthographic projections of the first sub-portion H11 and the second sub-portion H12 on the substrate 10 both overlap with the orthographic projection of the second scan signal line G2 on the substrate 10. Along the first direction X, the width of the first sub-portion H11 is approximately equal to the width of the second portion H2.

[0307] In some examples, the first sub-portion H11 is the second electrode b2 of the compensation transistor T2 .

[0308] In the above structure, because the orthographic projections of the first sub-portion H11 and the second sub-portion H12 in the first portion H1 on the substrate 10 overlap with the orthographic projections of the second scan signal line G2 on the substrate 10, coupling capacitance is generated between the first sub-portion H11 and the second sub-portion H12 in the first portion H1 and the second scan signal line G2. This, in turn, causes the potentials of the first sub-portion H11 and the second sub-portion H12 to interact with the potential of the second scan signal transmitted by the second scan signal line G2. This, in turn, affects the potential of the control electrode c3 of the driving transistor T3.

[0309] Based on this, the embodiment of the present disclosure provides an array substrate 100. Since one end of the first conductive connection portion M1 is electrically connected to the control electrode c3 of the driving transistor T3, and the other end of the first conductive connection portion M1 is electrically connected to the second electrode b2 of the compensation transistor T2, the potential of the control electrode c3 of the driving transistor T3 can be compensated by adjusting the overlapping area between the second scan signal line G2 and the second electrode b2 of the compensation transistor T2.

[0310] Specifically, the size of the first portion H11 of the semiconductor structure H in the compensation transistor T2 can be adjusted to adjust the overlapping area between the second scan signal line G2 and the second electrode b2 of the compensation transistor T2 to compensate for the potential of the control electrode c3 of the driving transistor T3.

[0311] In some embodiments, referring to FIG. 9 and FIG. 14 , the semiconductor structure H includes a first portion H1, a second portion H2, and a third portion H3 connected in sequence. The structure formed by the second portion H2 and the third portion H3 extends along the second direction Y, and the orthographic projection of the third conductive connection portion M3 on the substrate overlaps with the orthographic projection of the second portion H2 on the substrate.

[0312] Since the second portion H2 and the third portion H3 are connected to form a structure extending along the second direction Y, when forming the second portion H2 and the third portion H3, a structure extending along the second direction Y can be first formed, and then operations such as doping can be performed on this structure to form the corresponding second portion H2 and third portion H3. Based on this, the process of forming the semiconductor structure H can be simplified.

[0313] Figure 21 is a structural diagram of a pixel driving circuit according to some further embodiments, Figure 22 is a structural diagram of the second gate metal layer in Figure 21, Figure 23 is a structural diagram of the second gate metal layer and the second semiconductor layer in Figure 21, and Figure 24 is a structural diagram of the first routing metal layer in Figure 21.

[0314] Referring to Figures 21 to 24 , in some embodiments, the pixel driving circuit Q shown in Figure 21 differs from the pixel driving circuit shown in Figure 9 in the following: the first scanning signal line G1 located on the second gate metal layer Gate2, the semiconductor structure of the compensation transistor T2 located on the second semiconductor layer IGZO, and the first conductive connection structure M1 located on the first routing metal layer SD1. Based on this, Figures 22 to 24 illustrate the structural diagrams of the corresponding film layers. The other first semiconductor layer POLY, first gate metal layer Gate1, third gate metal layer Gate3, and second routing metal layer SD2 can be combined with the corresponding film layer structures of the pixel driving circuit Q in Figure 9 , and will not be further described here.

[0315] The compensation transistor T2 includes a semiconductor structure H including a first portion H1, a second portion H2, and a third portion H3 connected in sequence, wherein the third portion H3 extends along a first direction X, the second portion H2 extends along a second direction Y, and the first portion H1 extends along the first direction X.

[0316] In some examples, the semiconductor structure H has an approximately ┐-shaped shape. In the first direction X, the length of the third portion H3 is greater than the width of the second portion H2, and the third portion H3 faces a side away from the data writing transistor T4 relative to the second portion H2. Furthermore, in the first direction X, the width of the first portion H1 can be approximately equal to the width of the second portion H2.

[0317] The orthographic projection of the second portion H2 of the semiconductor structure H on the substrate 10 (referring to FIG. 4 ) overlaps with the orthographic projection of the first scan signal line G1 (the control electrode c3 of the driving transistor T3) on the substrate 10. The orthographic projection of the third portion H3 of the semiconductor structure H on the substrate 10 is located on a side of the orthographic projection of the first scan signal line G1 on the substrate 10 that is away from the orthographic projection of the driving transistor T3 on the substrate 10. The third portion H3 of the semiconductor structure H serves as the first electrode a2 of the compensation transistor T2. Furthermore, the orthographic projection of the first portion H1 of the semiconductor structure H on the substrate 10 is located between the first scan signal line G1 and the orthographic projection of the driving transistor T3 on the substrate 10. The first portion H1 is electrically connected to the first conductive connection structure M1, and the orthographic projection of the first portion H1 on the substrate 10 overlaps with the orthographic projection of the second scan signal line G2 on the substrate 10.

[0318] In some examples, the first portion H1 is the second electrode b2 of the compensation transistor T2 .

[0319] The difference from the pixel driving circuit Q shown in FIG9 is that the structure of the semiconductor structure H in the compensation transistor T2 is adjusted so that the first portion H1 forms the second electrode b2 of the compensation transistor T2. Furthermore, the first portion H1 of the semiconductor structure H shown in FIG21 can be equivalent to the first subportion H11 of the first portion H1 in the pixel driving circuit Q shown in FIG9. That is, the adjusted first portion H1 of the semiconductor structure H in the compensation transistor T2 only includes the first subportion H11 that forms the second electrode b2 of the compensation transistor T2, and removes the corresponding second subportion H12 (referring to FIG9).

[0320] Based on this, the orthographic projection of the second scan signal line G2 on the substrate 10 only overlaps with the orthographic projection of the first portion H1 of the second electrode b2 of the compensation transistor T2 on the substrate 10. This can help reduce the coupling capacitance formed between the second scan signal line G2 and the second electrode b2 of the compensation transistor T2 (the first portion H1 of the semiconductor structure H), thereby reducing the length of the potential change caused by the second scan signal transmitted on the second scan signal line G2 to pull the control electrode c3 of the driving transistor T3. Correspondingly, it can also reduce the impact on the range of the data write signal of the data write signal line Data, thereby preventing the driver chip from being unable to provide the stepped-down data write signal, thereby improving the display quality of the display panel 200.

[0321] The above embodiment, in conjunction with the accompanying drawings, describes the interaction between the data signal line Data and the control electrode c3 of the driving transistor T3. However, the inventors have discovered that the factors that affect the potential of the control electrode c3 of the driving transistor T3 and thus the range of the data write signal transmitted by the data signal line Data are not limited to the first scanning signal line G1 and the second scanning signal line G2, but are also related to the magnitude of the first power signal transmitted by the first power signal line Vdd.

[0322] Specifically, the current I output by the pixel driving circuit Q to the light emitting device O is I=β(Vdata-V dd ) 2 , where β is a known value, Vdata is the voltage value of the data write signal, V dd is the voltage value of the first power signal.

[0323] As can be seen, the magnitude of the current is related to both the data write signal transmitted by the data signal line Data and the first power signal transmitted by the first power signal line Vdd. Furthermore, when the first power signal transmitted by the first power signal line Vdd is reduced, the data write signal transmitted by the data signal line Data is increased. This can also cause the driver chip (Integrated Circuit, or IC) within the display panel 200 to be unable to provide the reduced voltage data write signal, affecting the display quality of the display panel 200.

[0324] FIG25 is a structural diagram of a pixel driving circuit according to still other embodiments, and FIG26 is a structural diagram of the second semiconductor layer in FIG25 .

[0325] As shown in conjunction with Figures 25 and 26 , in other embodiments, the pixel driving circuit Q shown in Figure 25 differs from the pixel driving circuit shown in Figure 21 in the semiconductor structure of the compensation transistor T2 located in the second semiconductor layer IGZO. Based on this, Figure 26 schematically illustrates the structure of the second semiconductor layer IGZO. Other film layers, such as the second gate metal layer Gate2 and the first routing metal layer SD1, can be combined with the structure diagram of each film layer corresponding to the pixel driving circuit Q in Figure 21 . Furthermore, the first semiconductor layer POLY, the first gate metal layer Gate1, the third gate metal layer Gate3, and the second routing metal layer SD2 are substantially the same as those shown in Figure 21 , and can also be combined with the structure diagram of each film layer corresponding to the pixel driving circuit Q in Figure 9 , and will not be further described here.

[0326] The compensation transistor T2 includes a semiconductor structure H, which includes a first portion H1, a second portion H2, and a third portion H3 connected in sequence. The third portion H3 extends along a first direction X, the second portion H2 extends along a second direction Y, and the first portion H1 extends along the first direction X.

[0327] The orthographic projection of the second portion H2 of the semiconductor structure H on the substrate 10 (referring to FIG. 4 ) overlaps with the orthographic projection of the first scan signal line G1 (the control electrode c3 of the drive transistor T3) on the substrate 10. The orthographic projection of the third portion H3 of the semiconductor structure H on the substrate 10 is located on a side of the orthographic projection of the first scan signal line G1 on the substrate 10 that is away from the orthographic projection of the drive transistor T3 on the substrate 10. The third portion H3 of the semiconductor structure H serves as the first electrode a2 of the compensation transistor T2. Furthermore, the orthographic projection of the first portion H1 of the semiconductor structure H on the substrate 10 is located between the first scan signal line G1 and the orthographic projection of the drive transistor T3 on the substrate 10.

[0328] Along the extension direction of the second scan signal line G2, the first portion H1 includes a third sub-portion H13, a fourth sub-portion H14, and a fifth sub-portion H15, which are connected to each other. The fourth sub-portion H14 is located between the third sub-portion H13 and the fifth sub-portion H15. The fourth sub-portion H14 is electrically connected to the first conductive connection structure M1. The orthographic projections of the third sub-portion H13, the fourth sub-portion H14, and the fifth sub-portion H15 on the substrate 10 all overlap with the orthographic projection of the second scan signal line G2 on the substrate 10.

[0329] In some examples, the fourth subsection H14 is the second electrode b2 of the compensation transistor T2.

[0330] In some examples, along the first direction X, the width of the fourth sub-portion H14 may be approximately equal to the width of the second portion H2 .

[0331] The difference from the pixel driving circuit Q shown in Figure 9 is that: the structure of the semiconductor structure H in the compensation transistor T2 is adjusted, and the first part H1 is set to include a fourth sub-part H14 located at the second electrode b2 forming the compensation transistor T2, and also include a third sub-part H13 and a fifth sub-part H15 respectively arranged on both sides of the fourth sub-part H14.

[0332] Based on this, the third sub-portion H13 and the fifth sub-portion H15 can be used to increase the size of the first portion H1, thereby increasing the overlapping area between the orthographic projection of the first portion H1 on the substrate 10 and the orthographic projection of the second scan signal line G2 on the substrate 10, thereby increasing the coupling capacitance between the first portion H1 and the second scan signal line G2. This increases the effect of the second scan signal line G2 on the potential of the control electrode c3 of the driving transistor T3, thereby compensating for the effect of a decrease in the first power signal transmitted by the first power signal line Vdd on the potential of the control electrode c3 of the driving transistor T3. This also compensates for the effect of a decrease in the first power signal on the range of the data write signal of the data write signal line Data, thereby preventing the driver chip from being unable to provide a reduced-voltage data write signal, thereby facilitating improved display quality of the display panel 200.

[0333] In some examples, along the first direction X, the length of the third sub-portion H13 and the length of the fifth sub-portion H15 can be adjusted according to specific circumstances to better compensate for the impact of the first power signal on the range of the data write signal of the data write signal line Data when the first power signal is reduced, so as to prevent the driving chip from being unable to provide the data write signal after the voltage is reduced, thereby helping to improve the display effect of the display panel 200.

[0334] In some embodiments, the compensation transistor T2 includes a semiconductor structure H, which includes a first portion H1, a second portion H2, and a third portion H3 connected in sequence. The second portion H2 forms the channel of the compensation transistor T2, and the third portion H3 forms the first electrode a2 of the compensation transistor T2. The first portion H1 is electrically connected to the first conductive connection portion M1 and may include the second electrode b2 of the compensation transistor T2. The orthographic projection of the first portion H1 on the substrate 10 has a first overlapping region with the orthographic projection of the second scan signal line G2 on the substrate 10. The area of ​​the first overlapping region is larger than the orthographic projection of the second portion H2 on the substrate 10.

[0335] The coupling capacitance between the first portion H1 and the second scan signal line G2 can be adjusted by adjusting the area of ​​the first overlapping region. To this end, the orthographic projection of the first portion H1 on the substrate 10 is configured to have a first overlapping region with the orthographic projection of the second scan signal line G2 on the substrate 10. The area of ​​the first overlapping region is larger than the orthographic projection of the second portion H2 on the substrate 10. The area of ​​the first overlapping region is utilized to increase the effect of the second scan signal line G2 on the potential of the control electrode c3 of the driving transistor T3. This can compensate for the effect of a decrease in the first power signal transmitted by the first power signal line Vdd on the potential of the control electrode c3 of the driving transistor T3. This can also compensate for the effect of a decrease in the first power signal on the range of the data write signal of the data write signal line Data. This prevents the driver chip from being unable to provide a reduced-voltage data write signal, thereby facilitating improved display quality of the display panel 200.

[0336] In some examples, a ratio of an area of ​​the first overlapping region to an orthographic projection area of ​​the second portion H2 on the substrate 10 ranges from approximately 2:1 to 10:1.

[0337] When the ratio of the area of ​​an overlapping region to the orthographic projection area of ​​the second portion H2 on the substrate 10 is equal to or close to 2:1, the area of ​​the first overlapping region is relatively small. This can reduce the coupling capacitance formed between the second scan signal line G2 and the second electrode b2 of the compensation transistor T2 (the first portion H1 of the semiconductor structure H), thereby reducing the length of the potential change caused by the second scan signal transmitted on the second scan signal line G2 to pull the control electrode c3 of the driving transistor T3. This can also reduce the impact on the range of the data write signal on the data write signal line Data, thereby preventing the driver chip from being unable to provide the stepped-down data write signal, thereby improving the display quality of the display panel 200.

[0338] When the ratio of the area of ​​an overlapping region to the orthographic projection area of ​​the second portion H2 on the substrate 10 is equal to or close to 10:1, the area of ​​the first overlapping region is larger. This can increase the coupling capacitance between the first portion H1 and the second scan signal line G2. This increases the effect of the second scan signal line G2 on the potential of the control electrode c3 of the driving transistor T3, thereby compensating for the effect of a decrease in the first power signal transmitted by the first power signal line Vdd on the potential of the control electrode c3 of the driving transistor T3. This can also compensate for the effect of a decrease in the first power signal on the range of the data write signal of the data write signal line Data, thereby preventing the driver chip from being unable to provide a reduced-voltage data write signal. This, in turn, improves the display quality of the display panel 200.

[0339] For example, the area of ​​the first overlapping region is approximately one of 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times the orthographic projection area of ​​the second portion H2 on the substrate 10. However, the embodiments of the present disclosure are not limited thereto. If there is sufficient space within the pixel driving circuit Q, the area of ​​the first overlapping region can be adjusted to be greater than 10 times the orthographic projection area of ​​the second portion H2 on the substrate 10 as needed.

[0340] In some embodiments, as shown in conjunction with Figures 21 to 26 , the compensation transistor T2 includes a semiconductor structure H, which includes a first portion H1, a second portion H2, and a third portion H3 connected in sequence. The second portion H2 forms the channel of the compensation transistor T2, and the third portion H3 forms the first electrode a2 of the compensation transistor T2. The first portion H1 is electrically connected to the first conductive connection portion M1 and may include the second electrode b2 of the compensation transistor T2.

[0341] The first scan signal line G1 includes a first portion GA and a second portion GB. The orthographic projection of the first portion GA on the substrate 10 overlaps with the orthographic projection of the second portion H2 on the substrate 10. The orthographic projection of the second portion GB on the substrate 10 overlaps with the orthographic projection of the third conductive connection portion M3 on the substrate 10. In the second direction Y, the width of the second portion GA is smaller than the width of the first portion GB.

[0342] Based on this, the structure of the semiconductor structure H in the compensation transistor T2 is adjusted so that the orthographic projection of the third conductive connection portion M3 on the substrate 10 does not overlap with the orthographic projection of the second portion H2 on the substrate 10, and the orthographic projection of the third conductive connection portion M3 on the substrate 10 does not overlap with the orthographic projection of the wider first portion GA in the first scanning signal line G1 on the substrate 10, and the orthographic projection of the third conductive connection portion M3 on the substrate 10 overlaps with the orthographic projection of the smaller second portion GB in the first scanning signal line G1 on the substrate 10.

[0343] Furthermore, it can be beneficial to reduce the overlapping area of ​​the orthographic projection of the third conductive connection part M3 on the substrate 10 and the orthographic projection of the first scanning signal line G1 on the substrate 10, thereby reducing the coupling capacitance formed by the first scanning signal line G1 and the third conductive connection part M3, thereby reducing the influence of the first scanning signal transmitted by the first scanning signal line G1 on the potential of the third conductive connection part M3 when it jumps, which is beneficial to improve the stability of the driving transistor T3.

[0344] In other embodiments, as shown in FIG. 27 , FIG. 27 is a structural diagram of a display panel according to other embodiments. The display panel 200 includes a display area AA and a non-display area FA surrounding the display area AA. The display area AA includes a via area K. The display area AA includes a plurality of sub-pixel regions P, which may be arranged in an array. The display area AA further includes a first display area AA1, a second display area AA2, and a third display area AA3 along the second direction Y, wherein the second display area AA2 includes the via area K.

[0345] Exemplarily, the via area K may be a camera area or a fingerprint recognition area, etc. The following only takes the via area K as an example of a camera area, and the same is applicable to fingerprint recognition.

[0346] Along the first direction X, the non-display area FA includes a first non-display area FA1 and a second non-display area FA2 located on both sides of the display area AA.

[0347] For the "8T1C" pixel driving circuit Q in any of the above embodiments, each row of the pixel driving circuit Q requires multiple scan signal lines. The multiple scan signal lines include a first scan signal line G1 and a second scan signal line G2. For example, the multiple scan signal lines may also include a first reset signal line R1 and a second reset signal line R2.

[0348] A corresponding shift register needs to be set for each scanning signal line, and multiple shift registers need to be set in the first non-display area FA1 or the second non-display area FA2, resulting in an increase in the proportion of the first non-display area FA1 and the second non-display area FA2 occupied by the display panel 200, making it impossible to achieve a narrow-border design of the display panel 200.

[0349] Based on this, the first scan signal line G1 can adopt a "one drives two" approach and a unilateral drive approach (taking the shift registers both being arranged in the first non-display area FA1 as an example for introduction). Specifically, one first scan signal line G1 may include a first branch G11 of the first scan signal line and a second branch G12 of the first scan signal line. The first branch G11 of the first scan signal line can drive the upper row of pixel drive circuits Q in two adjacent rows of pixel drive circuits Q in the second direction Y, and the second branch G12 of the first scan signal line can drive the lower row of pixel drive circuits Q in two adjacent rows of pixel drive circuits Q in the second direction Y. That is, one first scan signal line G1 can drive two adjacent rows of pixel drive circuits Q along the second direction Y. Furthermore, this can help reduce the number of shift registers corresponding to the first scan signal line G1, thereby facilitating the realization of a narrow-frame design for the display panel 200.

[0350] Furthermore, within the second display area AA2, multiple pixel driver circuits Q within a row of pixel driver circuits Q need to be electrically connected using a branch of the first scan signal line G1 (either the first branch G11 or the second branch G12). To prevent the first scan signal line G1 from affecting the transmittance of the via area K, a routing design can be employed within the via area K. Specifically, a branch of the first scan signal line G1 electrically connecting a row of pixel driver circuits Q must bypass the via area K. Similarly, the second scan signal line G2 also requires a routing arrangement.

[0351] As described above, the first scan signal line G1 (the first branch G11 and the second branch G12 ) and the second scan signal line G2 occupy too much of the frame of the via area K, affecting the appearance of the display panel 200 .

[0352] Based on this, the first scan signal line G1 can be routed in the via area K within the second display area AA2, using a "one-drives-two" approach. The first branch G11 and the second branch G12 belonging to the same first scan signal line G1 are then merged at the via area K. That is, a single connecting line electrically connects the left and right first branches G11 and G12 at the via area K. This reduces the number of branches of the first scan signal line G1, which helps reduce the amount of space occupied by the first scan signal line G1 and the routing wires on the frame of the via area K, thereby improving the display quality of the display panel 200.

[0353] However, the inventors discovered through research that, because the first branch G11 and the second branch G12 corresponding to a first scan signal line G1 in the second display area AA2 are electrically connected by a connecting line at a position corresponding to the via area K, they are then divided into the first branch G11 and the second branch G12. In other words, the first branch G11 and the second branch G12 corresponding to a first scan signal line G1 in the second display area AA2 are not only electrically connected at the starting end of the first scan signal line G1 (at the shift register position), but are also electrically connected at a position corresponding to the via area K.

[0354] The first branch G11 and the second branch G12 of the first scan signal line G1 in the first display area AA1 and the third display area AA3 are electrically connected only at the starting end (the shift register position) of the first scan signal line G1.

[0355] Since the first scanning signal line G1 can adopt "one drives two", while the second scanning signal line G2 still adopts "one drives one", under ideal conditions, the potentials of the first conductive connection part, the second conductive connection part and the third conductive connection part in multiple pixel driving circuits Q in each row of pixel driving circuits will be pulled twice by the same first scanning signal line G1 (the first branch G11 is pulled once, and the second branch G12 is pulled once).

[0356] However, due to the voltage drop loading on the first scanning signal line G1, the voltage drop loading refers to the difference between the voltage on both sides of the screen and the voltage in the middle position due to the resistance of the wire. This will cause the potential of the first conductive connection part, the second conductive connection part and the third conductive connection part in the pixel driving circuit Q at a position near the electrical connection position of the first branch G11 and the second branch G12 to be greatly affected by a branch (the first branch G11) of the first scanning signal line G1 to which it is electrically connected, while the other branch (the second branch G12) of the same first scanning signal line G1 has a small pulling effect on it and can be ignored.

[0357] Based on the above statements, it can be seen that in the first display area AA1 and the third display area AA3, the potentials of the first conductive connection part, the second conductive connection part and the third conductive connection part in the multiple pixel driving circuits Q close to the first non-display area FA1 side will be pulled twice by the same first scanning signal line G1, while the potentials of the first conductive connection part, the second conductive connection part and the third conductive connection part in the multiple pixel driving circuits Q away from the first non-display area FA1 and close to the second non-display area FA2 side will be pulled once by the same first scanning signal line G1.

[0358] The first branch G11 and the second branch G12 of the first scanning signal line G1 in the second display area AA2 are electrically connected again by the same connecting line at the position of the via area K. As a result, the potentials of the first conductive connection part, the second conductive connection part and the third conductive connection part in the multiple pixel driving circuits Q on the left and right sides of the via area K in the second display area AA2 will be pulled twice by the same first scanning signal line G1.

[0359] In summary, the display area AA is away from the first non-display area FA1, and the multiple pixel driving circuits Q on the side close to the second non-display area FA2 are pulled by the first scanning signal line G1 at different times, which will cause the brightness of the sub-pixel area P in the second display area AA2 at the corresponding position to be different from the brightness of the sub-pixel area P in the first display area AA1 and the third display area AA3, affecting the brightness uniformity of the display panel 200.

[0360] Any of the above embodiments can ensure that the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the first conductive connection part M1 (return to Figure 9) on the substrate 10 (return to Figure 4), and the orthographic projection of the first scanning signal line G1 on the substrate 10 does not overlap with the orthographic projection of the second conductive connection part M2 on the substrate 10.

[0361] Furthermore, the influence of the first scanning signal line G1 on the potential of the first conductive connection part M1 and the second conductive connection part M2 can be improved, which can be beneficial to improving the stability of the driving transistor T3 (the control electrode c3 of the driving transistor T3), and further can be beneficial to improving the problem of worsening lateral crosstalk.

[0362] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: substrate; A plurality of pixel driving circuits are located on one side of the substrate and arranged in multiple rows and columns; Any one of the pixel driving circuits comprises a driving transistor, a compensation transistor electrically connected to the driving transistor, and a first conductive connection portion; A plurality of first scanning signal lines are located on one side of the substrate, extending along a first direction and arranged along a second direction, wherein the second direction intersects the first direction; The control electrode of the driving transistor is electrically connected to the first conductive connection portion, the control electrode of the compensation transistor is electrically connected to the first scanning signal line, the second electrode of the compensation transistor is electrically connected to the first conductive connection portion, and the first electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor; The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the first conductive connecting portion on the substrate.

2. The array substrate according to claim 1, wherein: Any pixel driving circuit further includes a second conductive connection portion, and the first electrode of the driving transistor is electrically connected to the second conductive connection portion; The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the second conductive connecting portion on the substrate.

3. The array substrate according to claim 1 or 2, wherein: The orthographic projection of the first conductive connection portion on the substrate is located between the orthographic projection of the driving transistor on the substrate and the orthographic projection of the first scanning signal line on the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: Along the second direction, the second conductive connection portion and the driving transistor are located on the same side of the first scanning signal line, and along the first direction, the orthographic projection of the second conductive connection portion on the substrate is located on a side where the orthographic projection of the first conductive connection portion on the substrate is away from the orthographic projection of the compensation transistor on the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the control electrode of the driving transistor on the substrate.

6. The array substrate according to any one of claims 1 to 5, wherein: The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the first electrode of the driving transistor on the substrate; and / or, The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the second electrode of the driving transistor on the substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising: a plurality of data writing signal lines, located on one side of the substrate and extending along the second direction and arranged in the first direction; and, a plurality of second scanning signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; The pixel driving circuit further comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected to the data writing signal line, a second electrode of the data writing transistor is electrically connected to the second conductive connecting portion, and a control electrode of the data writing transistor is electrically connected to the second scanning signal line; Along the first direction, the orthographic projection of the data writing transistor on the substrate is located on a side of the orthographic projection of the driving transistor on the substrate away from the orthographic projection of the compensation transistor on the substrate.

8. The array substrate according to claim 7, wherein: Along the second direction, the orthographic projection of the first scanning signal line on the substrate is located on a side where the orthographic projection of the second scanning signal line on the substrate is away from the orthographic projection of the driving transistor on the substrate.

9. The array substrate according to claim 7 or 8, wherein: The orthographic projection of the first scanning signal line on the substrate does not overlap with the orthographic projection of the second electrode of the data writing transistor on the substrate.

10. The array substrate according to any one of claims 1 to 9, further comprising: A plurality of first initialization signal lines are located on one side of the substrate, extending along the first direction and arranged along the second direction; and, a plurality of first reset signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; The pixel driving circuit further comprises a first reset transistor, a control electrode of the first reset transistor is electrically connected to the first reset signal line, a first electrode of the first reset transistor is electrically connected to the first initialization signal line, and a second electrode of the first reset transistor is electrically connected to the second electrode of the driving transistor; Along the second direction, the orthographic projection of the first reset signal line on the substrate is located on a side where the orthographic projection of the first scan signal line on the substrate is away from the orthographic projection of the drive transistor on the substrate.

11. The array substrate according to any one of claims 1 to 10, further comprising: a plurality of enable signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; a plurality of first power signal lines, located on one side of the substrate, extending along the second direction and arranged along the first direction; The pixel driving circuit further includes a first light emitting control transistor; The control electrode of the first light emission control transistor is electrically connected to the enable signal line, the first electrode of the first light emission control transistor is electrically connected to the first power signal line, and the second electrode of the first light emission control transistor is electrically connected to the second conductive connection portion; Along the second direction, the orthographic projection of the enable signal line on the substrate is located on a side where the orthographic projection of the drive transistor on the substrate is away from the orthographic projection of the first scan signal line on the substrate.

12. The array substrate according to claim 11, further comprising: A plurality of second initialization signal lines are located on one side of the substrate and extend along the first direction and along the second direction. Direction arrangement; and, a plurality of second reset signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; The pixel driving circuit further includes a second reset transistor, a control electrode of the second reset transistor is electrically connected to the second reset signal line, a first electrode of the second reset transistor is electrically connected to the second initialization signal line, and a second electrode of the second reset transistor is electrically connected to the light emitting device; Along the second direction, the orthographic projection of the second reset signal line on the substrate is located on a side where the orthographic projection of the enable signal line on the substrate is away from the orthographic projection of the drive transistor on the substrate.

13. The array substrate according to claim 12, further comprising: a plurality of third initialization signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; and, a plurality of third reset signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; The pixel driving circuit further includes a third reset transistor, a control electrode of the third reset transistor is electrically connected to the third reset signal line, a first electrode of the third reset transistor is electrically connected to the third initialization signal line, and a second electrode of the third reset transistor is electrically connected to the second conductive connection portion; An orthographic projection of the enable signal line on the substrate at least partially overlaps with an orthographic projection of the third initialization signal line on the substrate.

14. The array substrate according to claim 13, wherein: An orthographic projection of the second conductive connection portion on the substrate at least partially overlaps with an orthographic projection of the third initialization signal line on the substrate.

15. The array substrate according to any one of claims 1 to 14, wherein: The compensation transistor comprises a semiconductor structure, the semiconductor structure comprises a first portion, an orthographic projection of the first portion on the substrate is located between the first scanning signal line and an orthographic projection of the driving transistor on the substrate; The first portion is electrically connected to the first conductive connection structure, and an orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the second scanning signal line on the substrate.

16. The array substrate according to any one of claims 1 to 14, wherein: The compensation transistor comprises a semiconductor structure, the semiconductor structure comprises a first portion, an orthographic projection of the first portion on the substrate is located between the first scanning signal line and an orthographic projection of the driving transistor on the substrate; Along the extension direction of the second scanning signal line, the first portion includes a first sub-portion and a second sub-portion connected to each other; wherein the orthographic projection of the second sub-portion on the substrate is located between the orthographic projection of the first sub-portion on the substrate and the orthographic projection of the control electrode of the compensation transistor on the substrate, and the first sub-portion is electrically connected to the first conductive connection structure; The orthographic projections of the first sub-section and the second sub-section on the substrate are both aligned with the second scanning signal The orthographic projections of the lines on the substrate overlap.

17. The array substrate according to any one of claims 1 to 14, wherein: The compensation transistor comprises a semiconductor structure, wherein the semiconductor structure comprises a first portion, a second portion and a third portion; the second portion is a channel of the compensation transistor, the third portion is a first electrode of the compensation transistor, and the first portion is electrically connected to the first conductive connection portion; The orthographic projection of the first part on the substrate has a first overlapping region with the orthographic projection of the second scanning signal line on the substrate, and the area of ​​the first overlapping region is larger than the orthographic projection area of ​​the second part on the substrate.

18. The array substrate according to any one of claims 15 to 17, wherein: The semiconductor structure further includes a second portion and a third portion, the second portion being a channel of the compensation transistor, and the third portion being a first electrode of the compensation transistor; The pixel driving circuit further includes a third conductive connection portion, the first electrode of the compensation transistor is electrically connected to the third conductive connection portion, and the second electrode of the driving transistor is electrically connected to the third conductive connection portion; An orthographic projection of the third conductive connection portion on the substrate overlaps with an orthographic projection of the second portion on the substrate.

19. The array substrate according to any one of claims 15 to 17, wherein: The semiconductor structure further includes a second portion and a third portion, the second portion being a channel of the compensation transistor, and the third portion being a first electrode of the compensation transistor; The pixel driving circuit further includes a third conductive connection portion, the first electrode of the compensation transistor is electrically connected to the third conductive connection portion, and the second electrode of the driving transistor is electrically connected to the third conductive connection portion; The first scanning signal line comprises a first portion and a second portion, wherein an orthographic projection of the first portion on the substrate overlaps with an orthographic projection of the second portion on the substrate, and an orthographic projection of the second portion on the substrate overlaps with an orthographic projection of the third conductive connecting portion on the substrate, wherein along the second direction, a width of the second portion is smaller than a width of the first portion; The orthographic projection of the third conductive connection portion on the substrate does not overlap with the orthographic projection of the second portion on the substrate.

20. A display panel, comprising: The array substrate according to any one of claims 1 to 19; and, The light emitting device layer is located on one side of the array substrate. The light emitting device layer includes a plurality of light emitting devices. The light emitting devices are electrically connected to the pixel driving circuit in the array substrate.

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