Abnormal frequency detection circuit applied to wheel speed sensor and detection method thereof
By designing an abnormal frequency detection circuit including low frequency detection circuit, high frequency detection circuit, inverter and OR gate, the problem of unstable signals generated by bandpass filters in traditional circuits is solved, and more accurate frequency detection is achieved, ensuring the normal operation of the wheel speed sensor chip.
Patent Information
- Application Number
- CN202411930317.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-03-11
AI Technical Summary
The traditional abnormal frequency detection circuit will generate unstable signals due to the bandpass filtering of the input abnormal frequency, resulting in output errors and affecting the normal operation of the wheel speed sensor chip.
Design an abnormal frequency detection circuit including low-frequency detection circuit, high-frequency detection circuit, inverter and OR gate. Through a monostable trigger circuit and a shaping circuit, the discharge current and capacitor size are adjusted, and the normal frequency range is flexibly set.
This avoids unstable signals caused by bandpass filters, improves the accuracy of abnormal frequency detection, and ensures the normal operation of the wheel speed sensor chip.
Smart Images
Figure CN119595941A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an abnormal frequency detection circuit and a detection method thereof, in particular to an abnormal frequency detection circuit and a detection method thereof applied to a wheel speed sensor, and belongs to the technical field of semiconductor integrated circuits. Background Art
[0002] The anti-lock braking system (ABS) is used to assist driving and prevent the wheels from being locked during braking, which may cause safety accidents. The wheel speed sensor is a sensor that measures the speed of the car wheels, and its output signal is an important basis for the anti-lock braking system (ABS) controller to control. Therefore, whether the wheel speed sensor chip can work properly is crucial to driving safety. The oscillator in the chip provides a reference clock for the digital circuit and the analog circuit, and its output frequency has a huge impact on the functional safety of the chip. Therefore, in order to ensure functional safety, it is necessary to design an abnormal frequency detection circuit to detect the output frequency of the oscillator to prevent the chip from working at a frequency that is too large or too small.
[0003] The abnormal frequency detection circuit traditionally used in wheel speed sensor chips is mainly composed of a bandpass filter, a comparator, a D flip-flop and a logic gate. The low-pass filter and the high-pass filter together form a bandpass filter. The upper cutoff frequency and the lower cutoff frequency of the bandpass filter correspond to the upper limit FIN_H and the lower limit FIN_L of the normal clock frequency. The abnormal input clock frequency greater than the upper limit FIN_H of the normal clock frequency and less than the lower limit FIN_L of the normal clock frequency are filtered out, and the corresponding flag signal FOUT is output, indicating that the clock frequency of the chip is abnormal. The normal clock signal passing through the bandpass filter is detected by the comparator, the D flip-flop and the logic gate, and the corresponding flag signal FOUT is output, indicating that the clock frequency of the chip is within the normal range. However, the bandpass filter filters the abnormal input frequency, which will produce an unstable signal and affect the normal frequency detection.
[0004] From the above analysis, we can see that the traditional abnormal frequency detection circuit will produce unstable signals due to the bandpass filter filtering the input abnormal frequency, which will lead to the output error of the abnormal frequency detection circuit, thus affecting the normal operation of the wheel speed sensor chip. Therefore, a stable abnormal frequency detection circuit is very important for the normal operation of the wheel speed sensor chip. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide an abnormal frequency detection circuit and a detection method thereof applied to a wheel speed sensor, so as to solve the technical problem of unstable signals generated in the prior art.
[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: An abnormal frequency detection circuit applied to a wheel speed sensor comprises a low frequency detection circuit, a high frequency detection circuit, an inverter INV0 and an OR gate OR, wherein the input ends of the low frequency detection circuit and the high frequency detection circuit are connected to a clock signal FIN of the wheel speed sensor, the output end of the low frequency detection circuit is connected to a first input end of the OR gate OR, the output end of the high frequency detection circuit is connected to an input end of the inverter INV0, the output end of the inverter INV0 is connected to a second input end of the OR gate OR, and the output end of the OR gate OR generates an output signal OUT.
[0007] Furthermore, the low frequency detection circuit and the high frequency detection circuit respectively include a monostable trigger circuit and a shaping circuit, the output end of the monostable trigger circuit is connected to the input end of the shaping circuit, and the output end of the shaping circuit generates an output signal FOUT.
[0008] Furthermore, the monostable trigger circuit includes a charge and discharge circuit, a D flip-flop DFF1 with reset, a delay module Delay1 and a NAND gate NAND1, the CLK end of the D flip-flop DFF1 with reset is connected to the clock signal FIN of the wheel speed sensor, the RST end of the D flip-flop DFF1 with reset is connected to the output end of the NAND gate NAND1, the D end of the D flip-flop DFF1 with reset is connected to the power supply VDD, the QN end of the D flip-flop DFF1 with reset is connected to the input end of the charge and discharge circuit, the Q end of the D flip-flop DFF1 with reset is connected to the output end of the delay module Delay1 and the A end of the NAND gate NAND1, and the output end of the charge and discharge circuit is connected to the B end of the NAND gate NAND1.
[0009] Further, the charge and discharge circuit comprises an NMOS tube NM1, an NMOS tube NM2, an NMOS tube NM3, an NMOS tube NM4, an NMOS tube NM5, an NMOS tube NM6, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a capacitor C1 and an inverter INV1, the drain of the NMOS tube NM1 is connected to the gate of the NMOS tube NM1, the gate of the NMOS tube NM2, the gate of the NMOS tube NM3 and the gate of the NMOS tube NM4 and connected to a bias current Ibias, the drain of the NMOS tube NM2 is connected to the source of the NMOS tube NM5, the gate of the NMOS tube NM5 is connected to the gate of the PMOS tube PM1 and serves as an input end of the charge and discharge circuit, the drain of the NMOS tube NM5 is connected to the drain of the PMOS tube PM1, one end of the capacitor C1, and the PMOS The gate of the transistor PM4 is connected to the gate of the NMOS transistor NM6, the source of the PMOS transistor PM1 is connected to the other end of the capacitor C1, the source of the PMOS transistor PM2 and the source of the PMOS transistor PM3 and connected to the power supply VDD, the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM3, the drain of the PMOS transistor PM2 and the drain of the NMOS transistor NM3, the drain of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM4, the drain of the PMOS transistor PM4 is connected to the input end of the inverter INV1 and the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to the drain of the NMOS transistor NM4, the output end of the inverter INV1 serves as the output end of the charge and discharge circuit, the source of the NMOS transistor NM1, the source of the NMOS transistor NM2, the source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.
[0010] Further, the shaping circuit comprises an NMOS tube NM7, an NMOS tube NM8, an NMOS tube NM9, an NMOS tube NM10, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, a capacitor C2 and an inverter INV2, a source of the PMOS tube PM5 is connected to one end of the capacitor C2 and the source of the PMOS tube PM6 and is connected to a power supply VDD, a gate of the PMOS tube PM5 is connected to the gate of the NMOS tube NM8 and serves as an input end of the shaping circuit, a drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM8, the other end of the capacitor C2, the gate of the PMOS tube PM7 and the gate of the NMOS tube NM10, and the NMOS tube NM8 is connected to the gate of the PMOS tube PM7. The source of M8 is connected to the drain of NMOS tube NM7, the gate of NMOS tube NM7 is connected to the gate of NMOS tube NM9 and connected to bias current Ibias, the source of NMOS tube NM7 and the source of NMOS tube NM9 are grounded, the gate of PMOS tube PM6 is connected to the gate of PMOS tube PM2, the drain of PMOS tube PM6 is connected to the source of PMOS tube PM7, the drain of PMOS tube PM7 is connected to the input end of inverter INV2 and the drain of NMOS tube NM10, the source of NMOS tube NM10 is connected to the drain of NMOS tube NM9, and the output end of inverter INV2 serves as the output end of the shaping circuit and generates an output signal FOUT.
[0011] Further, the NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM7 and NMOS tube NM9 constitute an NMOS current mirror, and the PMOS tube PM2, PMOS tube PM3 and PMOS tube PM6 constitute a PMOS current mirror.
[0012] A detection method for an abnormal frequency detection circuit applied to a wheel speed sensor comprises the following steps: By setting the discharge current and the size of the capacitor C1, the critical detection frequency of the monostable trigger circuit is determined. The larger the discharge current, the higher the critical detection frequency; the smaller the capacitor C1, the higher the critical detection frequency; When the input of the shaping circuit is a bistable state of high and low levels, the high level pulls up the gate of the PMOS tube PM5 of the shaping circuit, and the PMOS tube PM5 is turned off; the gate of the NMOS tube NM8 is pulled up, the NMOS tube NM8 is turned on, and the NMOS tube NM7 discharges the capacitor C2; by setting the discharge current and the size of the capacitor C2, the high level pulse of a certain pulse width time cannot pull down the lower plate voltage of the capacitor C2 to less than the flip threshold of the inverting circuit composed of the PMOS tube PM7 and the NMOS tube NM10, and the PMOS tube PM7 and NM The output of the inverter circuit formed by the OS tube NM10 remains at a low level, and outputs a high level through the inverter INV2, that is, the output signal FOUT always remains at a high level; when the input of the shaping circuit is a high-level monostable, the high level pulls the lower plate voltage of the capacitor C2 down to a level lower than the flip threshold of the inverter circuit formed by the PMOS tube PM7 and the NMOS tube NM10, and the output of the inverter circuit formed by the PMOS tube PM7 and the NMOS tube NM10 remains at a high level, and outputs a low level through the inverter INV2, that is, the output signal FOUT always remains at a low level; When the rising edge of the clock signal FIN of the wheel speed sensor comes, the D-end power supply VDD of the D-type flip-flop DFF1 with reset is output, and the Q-end of the D-type flip-flop DFF1 with reset is high level, and the high level is input to the A-end of the NAND gate NAND1 after being delayed by the delay module Delay1; the QN-end of the D-type flip-flop DFF1 with reset is low level, and the low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, and the NMOS tube NM5 is turned off, and the lower plate voltage of the capacitor C1 increases. After it is greater than the flip threshold of the inverting circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the PMOS tube PM1 is turned on. The inverting circuit composed of the MOS tube PM4 and the NMOS tube NM6 outputs a low level, which is outputted at a high level through the inverter INV1 and inputted to the B terminal of the NAND gate NAND1; the inputs of the NAND gate NAND1 are all high levels, and the output of the NAND gate NAND1 is a low level; it is inputted to the RST terminal of the D flip-flop DFF1 with reset to reset it, so that the Q terminal of the D flip-flop DFF1 with reset is a low level and the QN terminal is a high level, and the high level pulls up the gate of the PMOS tube PM1 of the charge and discharge circuit, the PMOS tube PM1 is turned off, the gate of the NMOS tube NM5 is pulled up, the NMOS tube NM5 is turned on, and the NMOS tube NM2 discharges the capacitor C1; When the frequency of the clock signal FIN of the wheel speed sensor is lower than the critical detection frequency of the frequency detection circuit, there is enough time to pull down the lower plate voltage of the capacitor C1 before turning on the PMOS tube PM1 in the next clock cycle; after the lower plate voltage of the capacitor C1 is less than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a high level, and outputs a low level through the inverter INV1; when the next clock cycle comes, the QN terminal of the D flip-flop DFF1 with reset becomes a low level again, and the low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, the NMOS tube NM5 is turned off, and the lower plate voltage of the capacitor C1 increases, which is greater than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6. After reaching the threshold, the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a low level, and outputs a high level through the inverter INV1; therefore, the output signal of the monostable trigger circuit is bistable, and the output signal FOUT of the bistable signal outputted by the shaping circuit always maintains a high level; when the frequency of the clock signal FIN of the wheel speed sensor is higher than the critical detection frequency of the frequency detection circuit, before the PMOS tube PM1 is turned on in the next clock cycle, the lower plate voltage of the capacitor C1 cannot be pulled down to a level lower than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, and the output of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 remains low, and outputs a high level through the inverter INV1; therefore, the output of the monostable trigger circuit is always high, and the output signal FOUT of the monostable signal outputted by the shaping circuit always maintains a low level; The clock signal of the wheel speed sensor chip is simultaneously input into the abnormal frequency detection circuit composed of the low frequency detection circuit and the high frequency detection circuit. When the clock signal FIN of the wheel speed sensor chip is at the normal clock frequency, the output signal FOUT_L of the low frequency detection circuit is low level, and the output signal FOUT_H of the high frequency detection circuit is high level. The output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is low level, indicating that the chip clock frequency is normal; when the clock signal FIN of the wheel speed sensor chip is lower than the normal clock frequency, the output signal FOUT_L of the low frequency detection circuit is low level. _L is high, the output signal FOUT_H of the high-frequency detection circuit is high, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal; when the clock signal FIN of the wheel speed sensor chip is higher than the normal clock frequency, the output signal FOUT_L of the low-frequency detection circuit is low, the output signal FOUT_H of the high-frequency detection circuit is low, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal.
[0013] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an abnormal frequency detection circuit and a detection method thereof applied to a wheel speed sensor, which can avoid generating an unstable signal due to filtering of the input abnormal frequency by a bandpass filter, thereby avoiding output errors of the abnormal frequency detection circuit; the present invention can flexibly set the normal frequency range by adjusting the discharge current and the capacitance size. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 The present invention is a schematic diagram of an abnormal frequency detection circuit applied to a wheel speed sensor.
[0015] Figure 2 It is a circuit diagram of a low frequency detection circuit and a high frequency detection circuit of the present invention.
[0016] Figure 3 It is a timing diagram of the frequency detection circuit of the present invention when the input frequency is lower than the critical frequency.
[0017] Figure 4 It is a timing diagram of the frequency detection circuit of the present invention when the input frequency is higher than the critical frequency. DETAILED DESCRIPTION
[0018] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0019] like Figure 1 As shown, an abnormal frequency detection circuit applied to a wheel speed sensor of the present invention comprises a low frequency detection circuit, a high frequency detection circuit, an inverter INV0 and an OR gate OR, the input ends of the low frequency detection circuit and the high frequency detection circuit are connected to a clock signal FIN of the wheel speed sensor, the output end of the low frequency detection circuit is connected to a first input end of the OR gate OR, the output end of the high frequency detection circuit is connected to an input end of the inverter INV0, the output end of the inverter INV0 is connected to a second input end of the OR gate OR, and the output end of the OR gate OR generates an output signal OUT.
[0020] like Figure 2 As shown, the low frequency detection circuit and the high frequency detection circuit respectively include a monostable trigger circuit and a shaping circuit, the output end of the monostable trigger circuit is connected to the input end of the shaping circuit, and the output end of the shaping circuit generates an output signal FOUT.
[0021] The monostable trigger circuit includes a charge and discharge circuit, a D flip-flop DFF1 with reset, a delay module Delay1 and a NAND gate NAND1, wherein the CLK end of the D flip-flop DFF1 with reset is connected to the clock signal FIN of the wheel speed sensor, the RST end of the D flip-flop DFF1 with reset is connected to the output end of the NAND gate NAND1, the D end of the D flip-flop DFF1 with reset is connected to the power supply VDD, the QN end of the D flip-flop DFF1 with reset is connected to the input end of the charge and discharge circuit, the Q end of the D flip-flop DFF1 with reset is connected to the output end of the delay module Delay1 and the A end of the NAND gate NAND1, and the output end of the charge and discharge circuit is connected to the B end of the NAND gate NAND1.
[0022] The charge and discharge circuit comprises NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, capacitor C1 and inverter INV1, the drain of NMOS tube NM1 is connected to the gate of NMOS tube NM1, the gate of NMOS tube NM2, the gate of NMOS tube NM3 and the gate of NMOS tube NM4 and connected to bias current Ibias, the drain of NMOS tube NM2 is connected to the source of NMOS tube NM5, the gate of NMOS tube NM5 is connected to the gate of PMOS tube PM1 and serves as the input end of the charge and discharge circuit, the drain of NMOS tube NM5 is connected to the drain of PMOS tube PM1, one end of capacitor C1 and PMOS tube PM4 The gate of the PMOS tube PM1 is connected to the gate of the NMOS tube NM6, the source of the PMOS tube PM1 is connected to the other end of the capacitor C1, the source of the PMOS tube PM2 and the source of the PMOS tube PM3 and connected to the power supply VDD, the gate of the PMOS tube PM2 is connected to the gate of the PMOS tube PM3, the drain of the PMOS tube PM2 and the drain of the NMOS tube NM3, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4 is connected to the input end of the inverter INV1 and the drain of the NMOS tube NM6, the source of the NMOS tube NM6 is connected to the drain of the NMOS tube NM4, the output end of the inverter INV1 serves as the output end of the charge and discharge circuit, the source of the NMOS tube NM1, the source of the NMOS tube NM2, the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded. The critical detection frequency of the monostable trigger circuit is determined by setting the discharge current and the size of the capacitor C1. The larger the discharge current, the higher the critical detection frequency; the smaller the capacitor C1, the higher the critical detection frequency.
[0023] The shaping circuit comprises an NMOS tube NM7, an NMOS tube NM8, an NMOS tube NM9, an NMOS tube NM10, a PMOS tube PM5, a PMOS tube PM6, a PMOS tube PM7, a capacitor C2 and an inverter INV2. The source of the PMOS tube PM5 is connected to one end of the capacitor C2 and the source of the PMOS tube PM6 and is connected to the power supply VDD. The gate of the PMOS tube PM5 is connected to the gate of the NMOS tube NM8 and serves as the input end of the shaping circuit. The drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM8, the other end of the capacitor C2, the gate of the PMOS tube PM7 and the gate of the NMOS tube NM10. The source is connected to the drain of the NMOS tube NM7, the gate of the NMOS tube NM7 is connected to the gate of the NMOS tube NM9 and is connected to the bias current Ibias, the source of the NMOS tube NM7 and the source of the NMOS tube NM9 are grounded, the gate of the PMOS tube PM6 is connected to the gate of the PMOS tube PM2, the drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM7, the drain of the PMOS tube PM7 is connected to the input end of the inverter INV2 and the drain of the NMOS tube NM10, the source of the NMOS tube NM10 is connected to the drain of the NMOS tube NM9, and the output end of the inverter INV2 serves as the output end of the shaping circuit and generates an output signal FOUT.
[0024] The NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3, NMOS tubes NM4, NMOS tubes NM7 and NMOS tubes NM9 constitute an NMOS current mirror, and the PMOS tubes PM2, PMOS tubes PM3 and PMOS tubes PM6 constitute a PMOS current mirror.
[0025] Among them, the PMOS tube PM5 is a reset switch, the NMOS tube NM8 is a constant current source discharge switch, the NMOS tube NM7 is a constant current source, the PMOS tube PM1 is a reset switch, the NMOS tube NM5 is a discharge switch, and the NMOS tube NM2 is a constant current source.
[0026] A detection method for an abnormal frequency detection circuit applied to a wheel speed sensor comprises the following steps: The critical detection frequency of the monostable trigger circuit is determined by setting the discharge current and the size of the capacitor C1. The larger the discharge current, the higher the critical detection frequency; the smaller the capacitor C1, the higher the critical detection frequency.
[0027] When the input of the shaping circuit is a bistable state of high and low levels, the high level pulls up the gate of the PMOS tube PM5 of the shaping circuit, and the PMOS tube PM5 is turned off; the gate of the NMOS tube NM8 is pulled up, the NMOS tube NM8 is turned on, and the NMOS tube NM7 discharges the capacitor C2; by setting the discharge current and the size of the capacitor C2, the high level pulse of a certain pulse width time cannot pull down the lower plate voltage of the capacitor C2 to less than the flip threshold of the inverting circuit composed of the PMOS tube PM7 and the NMOS tube NM10, and the PMOS tube PM7 and NM The output of the inverter circuit composed of the OS tube NM10 maintains a low level, and outputs a high level through the inverter INV2, that is, the output signal FOUT always maintains a high level; when the input of the shaping circuit is a high-level monostable, the high level pulls down the lower plate voltage of the capacitor C2 to a level lower than the flip threshold of the inverter circuit composed of the PMOS tube PM7 and the NMOS tube NM10, and the output of the inverter circuit composed of the PMOS tube PM7 and the NMOS tube NM10 maintains a high level, and outputs a low level through the inverter INV2, that is, the output signal FOUT always maintains a low level.
[0028] When the rising edge of the clock signal FIN of the wheel speed sensor comes, the D-end power supply VDD of the D-type flip-flop DFF1 with reset is output, and the Q-end of the D-type flip-flop DFF1 with reset is high level, and the high level is input to the A-end of the NAND gate NAND1 after being delayed by the delay module Delay1; the QN-end of the D-type flip-flop DFF1 with reset is low level, and the low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, and the NMOS tube NM5 is turned off, and the lower plate voltage of the capacitor C1 increases. After it is greater than the flip threshold of the inverting circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the PMOS tube PM1 is turned on. The inverting circuit composed of the MOS tube PM4 and the NMOS tube NM6 outputs a low level, which is outputted at a high level through the inverter INV1 and inputted to the B terminal of the NAND gate NAND1; the inputs of the NAND gate NAND1 are all high levels, and the output of the NAND gate NAND1 is a low level; it is inputted to the RST terminal of the D flip-flop DFF1 with reset to reset it, so that the Q terminal of the D flip-flop DFF1 with reset is a low level and the QN terminal is a high level, and the high level pulls up the gate of the PMOS tube PM1 of the charge and discharge circuit, the PMOS tube PM1 is turned off, the gate of the NMOS tube NM5 is pulled up, the NMOS tube NM5 is turned on, and the NMOS tube NM2 discharges the capacitor C1.
[0029] When the frequency of the clock signal FIN of the wheel speed sensor is lower than the critical detection frequency of the frequency detection circuit, that is, the clock cycle is relatively long, there is enough time to pull down the voltage of the lower plate of the capacitor C1 before turning on the PMOS tube PM1 in the next clock cycle; after the voltage of the lower plate of the capacitor C1 is less than the flip threshold of the inverting circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the inverting circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a high level, and outputs a low level through the inverter INV1; when the next clock cycle comes, the QN terminal of the D flip-flop DFF1 with reset becomes a low level again, The low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, and the NMOS tube NM5 is turned off, and the voltage of the lower plate of the capacitor C1 increases. After it is greater than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a low level, and outputs a high level through the inverter INV1; therefore, the output signal of the monostable trigger circuit is bistable, and the output signal FOUT of the bistable signal output through the shaping circuit always maintains a high level, and its timing diagram is as follows Figure 3 As shown; when the frequency of the clock signal FIN of the wheel speed sensor is higher than the critical detection frequency of the frequency detection circuit, before the PMOS tube PM1 is turned on in the next clock cycle, the lower plate voltage of the capacitor C1 cannot be pulled down to a level lower than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, and the output of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 remains at a low level, and outputs a high level through the inverter INV1; therefore, the output of the monostable trigger circuit is always at a high level, and the output signal FOUT of the monostable signal outputted by the shaping circuit remains at a low level, and its timing diagram is as shown Figure 4 shown.
[0030] By designing different discharge currents and capacitor sizes, a low-frequency detection circuit with a low critical detection frequency and a high-frequency detection circuit with a high critical detection frequency are realized. The clock signal of the wheel speed sensor chip is simultaneously input into the abnormal frequency detection circuit composed of the low-frequency detection circuit and the high-frequency detection circuit. When the clock signal FIN of the wheel speed sensor chip is at the normal clock frequency, the output signal FOUT_L of the low-frequency detection circuit is low level, and the output signal FOUT_H of the high-frequency detection circuit is high level. The output signal FOUT_H is or-ed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is low level, indicating that the chip clock frequency is normal; when the clock signal FIN of the wheel speed sensor chip is lower than the normal clock frequency, the output signal FOUT_L of the low-frequency detection circuit is low level. _L is high, the output signal FOUT_H of the high-frequency detection circuit is high, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal; when the clock signal FIN of the wheel speed sensor chip is higher than the normal clock frequency, the output signal FOUT_L of the low-frequency detection circuit is low, the output signal FOUT_H of the high-frequency detection circuit is low, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal.
[0031] The present invention provides an abnormal frequency detection circuit and a detection method for a wheel speed sensor, which can avoid generating an unstable signal due to filtering of an input abnormal frequency by a bandpass filter, thereby avoiding output errors of the abnormal frequency detection circuit; the present invention can flexibly set a normal frequency range by adjusting a discharge current and a capacitor size.
[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims
1. An abnormal frequency detection circuit applied to a wheel speed sensor, characterized in that: It includes a low frequency detection circuit, a high frequency detection circuit, an inverter INV0 and an OR gate OR, the input ends of the low frequency detection circuit and the high frequency detection circuit are connected to the clock signal FIN of the wheel speed sensor, the output end of the low frequency detection circuit is connected to the first input end of the OR gate OR, the output end of the high frequency detection circuit is connected to the input end of the inverter INV0, the output end of the inverter INV0 is connected to the second input end of the OR gate OR, and the output end of the OR gate OR generates an output signal OUT.
2. The abnormal frequency detection circuit for a wheel speed sensor according to claim 1, characterized in that: The low frequency detection circuit and the high frequency detection circuit respectively include a monostable trigger circuit and a shaping circuit, the output end of the monostable trigger circuit is connected to the input end of the shaping circuit, and the output end of the shaping circuit generates an output signal FOUT.
3. The abnormal frequency detection circuit for a wheel speed sensor according to claim 2, characterized in that: The monostable trigger circuit includes a charge and discharge circuit, a D flip-flop DFF1 with reset, a delay module Delay1 and a NAND gate NAND1, wherein the CLK end of the D flip-flop DFF1 with reset is connected to the clock signal FIN of the wheel speed sensor, the RST end of the D flip-flop DFF1 with reset is connected to the output end of the NAND gate NAND1, the D end of the D flip-flop DFF1 with reset is connected to the power supply VDD, the QN end of the D flip-flop DFF1 with reset is connected to the input end of the charge and discharge circuit, the Q end of the D flip-flop DFF1 with reset is connected to the output end of the delay module Delay1 and the A end of the NAND gate NAND1, and the output end of the charge and discharge circuit is connected to the B end of the NAND gate NAND1.
4. The abnormal frequency detection circuit for a wheel speed sensor according to claim 3, characterized in that: The charge and discharge circuit comprises NMOS tube NM1, NMOS tube NM2, NMOS tube NM3, NMOS tube NM4, NMOS tube NM5, NMOS tube NM6, PMOS tube PM1, PMOS tube PM2, PMOS tube PM3, PMOS tube PM4, capacitor C1 and inverter INV1, the drain of NMOS tube NM1 is connected to the gate of NMOS tube NM1, the gate of NMOS tube NM2, the gate of NMOS tube NM3 and the gate of NMOS tube NM4 and connected to bias current Ibias, the drain of NMOS tube NM2 is connected to the source of NMOS tube NM5, the gate of NMOS tube NM5 is connected to the gate of PMOS tube PM1 and serves as the input end of the charge and discharge circuit, the drain of NMOS tube NM5 is connected to the drain of PMOS tube PM1, one end of capacitor C1, PMOS tube PM The gate of the PMOS tube PM4 is connected to the gate of the NMOS tube NM6, the source of the PMOS tube PM1 is connected to the other end of the capacitor C1, the source of the PMOS tube PM2 and the source of the PMOS tube PM3 and are connected to the power supply VDD, the gate of the PMOS tube PM2 is connected to the gate of the PMOS tube PM3, the drain of the PMOS tube PM2 and the drain of the NMOS tube NM3, the drain of the PMOS tube PM3 is connected to the source of the PMOS tube PM4, the drain of the PMOS tube PM4 is connected to the input end of the inverter INV1 and the drain of the NMOS tube NM6, the source of the NMOS tube NM6 is connected to the drain of the NMOS tube NM4, the output end of the inverter INV1 serves as the output end of the charge and discharge circuit, the source of the NMOS tube NM1, the source of the NMOS tube NM2, the source of the NMOS tube NM3 and the source of the NMOS tube NM4 are grounded.
5. The abnormal frequency detection circuit for a wheel speed sensor according to claim 4, characterized in that: The shaping circuit comprises NMOS tube NM7, NMOS tube NM8, NMOS tube NM9, NMOS tube NM10, PMOS tube PM5, PMOS tube PM6, PMOS tube PM7, capacitor C2 and inverter INV2, the source of PMOS tube PM5 is connected to one end of capacitor C2 and the source of PMOS tube PM6 and connected to power supply VDD, the gate of PMOS tube PM5 is connected to the gate of NMOS tube NM8 and serves as the input end of the shaping circuit, the drain of PMOS tube PM5 is connected to the drain of NMOS tube NM8, the other end of capacitor C2, the gate of PMOS tube PM7 and the gate of NMOS tube NM10, and the NMOS tube NM8 is connected to the gate of PMOS tube PM7. The source of the NMOS tube NM7 is connected to the drain of the NMOS tube NM7, the gate of the NMOS tube NM7 is connected to the gate of the NMOS tube NM9 and is connected to the bias current Ibias, the source of the NMOS tube NM7 and the source of the NMOS tube NM9 are grounded, the gate of the PMOS tube PM6 is connected to the gate of the PMOS tube PM2, the drain of the PMOS tube PM6 is connected to the source of the PMOS tube PM7, the drain of the PMOS tube PM7 is connected to the input end of the inverter INV2 and the drain of the NMOS tube NM10, the source of the NMOS tube NM10 is connected to the drain of the NMOS tube NM9, and the output end of the inverter INV2 serves as the output end of the shaping circuit and generates an output signal FOUT.
6. The abnormal frequency detection circuit for a wheel speed sensor according to claim 5, characterized in that: The NMOS tubes NM1, NMOS tubes NM2, NMOS tubes NM3, NMOS tubes NM4, NMOS tubes NM7 and NMOS tubes NM9 constitute an NMOS current mirror, and the PMOS tubes PM2, PMOS tubes PM3 and PMOS tubes PM6 constitute a PMOS current mirror.
7. A detection method for an abnormal frequency detection circuit applied to a wheel speed sensor according to any one of claims 1 to 6, characterized in that The following steps are involved: By setting the discharge current and the size of the capacitor C1, the critical detection frequency of the monostable trigger circuit is determined. The larger the discharge current, the higher the critical detection frequency; the smaller the capacitor C1, the higher the critical detection frequency; When the input of the shaping circuit is a bistable state of high and low levels, the high level pulls up the gate of the PMOS tube PM5 of the shaping circuit, and the PMOS tube PM5 is turned off; the gate of the NMOS tube NM8 is pulled up, the NMOS tube NM8 is turned on, and the NMOS tube NM7 discharges the capacitor C2; by setting the discharge current and the size of the capacitor C2, the high level pulse of a certain pulse width time cannot pull down the lower plate voltage of the capacitor C2 to less than the flip threshold of the inverting circuit composed of the PMOS tube PM7 and the NMOS tube NM10, and the PMOS tube PM7 and NM The output of the inverter circuit formed by the OS tube NM10 remains at a low level, and outputs a high level through the inverter INV2, that is, the output signal FOUT always remains at a high level; when the input of the shaping circuit is a high-level monostable, the high level pulls the lower plate voltage of the capacitor C2 down to a level lower than the flip threshold of the inverter circuit formed by the PMOS tube PM7 and the NMOS tube NM10, and the output of the inverter circuit formed by the PMOS tube PM7 and the NMOS tube NM10 remains at a high level, and outputs a low level through the inverter INV2, that is, the output signal FOUT always remains at a low level; When the rising edge of the clock signal FIN of the wheel speed sensor comes, the D-end power supply VDD of the D-type flip-flop DFF1 with reset is output, and the Q-end of the D-type flip-flop DFF1 with reset is high level, and the high level is input to the A-end of the NAND gate NAND1 after being delayed by the delay module Delay1; the QN-end of the D-type flip-flop DFF1 with reset is low level, and the low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, and the NMOS tube NM5 is turned off, and the lower plate voltage of the capacitor C1 increases. After it is greater than the flip threshold of the inverting circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the PMOS tube PM1 is turned on. The inverting circuit composed of the MOS tube PM4 and the NMOS tube NM6 outputs a low level, which is outputted at a high level through the inverter INV1 and inputted to the B terminal of the NAND gate NAND1; the inputs of the NAND gate NAND1 are all high levels, and the output of the NAND gate NAND1 is a low level; it is inputted to the RST terminal of the D flip-flop DFF1 with reset to reset it, so that the Q terminal of the D flip-flop DFF1 with reset is a low level and the QN terminal is a high level, and the high level pulls up the gate of the PMOS tube PM1 of the charge and discharge circuit, the PMOS tube PM1 is turned off, the gate of the NMOS tube NM5 is pulled up, the NMOS tube NM5 is turned on, and the NMOS tube NM2 discharges the capacitor C1; When the frequency of the clock signal FIN of the wheel speed sensor is lower than the critical detection frequency of the frequency detection circuit, there is enough time to pull down the lower plate voltage of the capacitor C1 before turning on the PMOS tube PM1 in the next clock cycle; after the lower plate voltage of the capacitor C1 is less than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a high level, and outputs a low level through the inverter INV1; when the next clock cycle comes, the QN terminal of the D flip-flop DFF1 with reset becomes a low level again, and the low level pulls down the gate of the PMOS tube PM1 of the charge and discharge circuit, and the PMOS tube PM1 is turned on; the gate of the NMOS tube NM5 is pulled down, the NMOS tube NM5 is turned off, and the lower plate voltage of the capacitor C1 increases, which is greater than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6. After reaching the threshold, the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 outputs a low level, and outputs a high level through the inverter INV1; therefore, the output signal of the monostable trigger circuit is bistable, and the output signal FOUT of the bistable signal outputted by the shaping circuit always maintains a high level; when the frequency of the clock signal FIN of the wheel speed sensor is higher than the critical detection frequency of the frequency detection circuit, before the PMOS tube PM1 is turned on in the next clock cycle, the lower plate voltage of the capacitor C1 cannot be pulled down to a level lower than the flip threshold of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6, and the output of the inverter circuit composed of the PMOS tube PM4 and the NMOS tube NM6 remains low, and outputs a high level through the inverter INV1; therefore, the output of the monostable trigger circuit is always high, and the output signal FOUT of the monostable signal outputted by the shaping circuit always maintains a low level; The clock signal of the wheel speed sensor chip is simultaneously input into the abnormal frequency detection circuit composed of the low frequency detection circuit and the high frequency detection circuit. When the clock signal FIN of the wheel speed sensor chip is at the normal clock frequency, the output signal FOUT_L of the low frequency detection circuit is low level, and the output signal FOUT_H of the high frequency detection circuit is high level. The output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is low level, indicating that the chip clock frequency is normal; when the clock signal FIN of the wheel speed sensor chip is lower than the normal clock frequency, the output signal FOUT_L of the low frequency detection circuit is low level. _L is high, the output signal FOUT_H of the high-frequency detection circuit is high, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal; when the clock signal FIN of the wheel speed sensor chip is higher than the normal clock frequency, the output signal FOUT_L of the low-frequency detection circuit is low, the output signal FOUT_H of the high-frequency detection circuit is low, the output signal FOUT_H is ORed with the output signal FOUT_L through the inverter INV0, and the final output signal OUT is high, indicating that the chip clock frequency is abnormal.