Integrated circuit chip testing system, method, equipment and medium

Abstract

This application discloses an integrated circuit chip testing system, method, device, and medium, primarily relating to the field of integrated circuit chip technology. The system addresses the problem that existing integrated circuit chip fault detection solutions focus solely on testing a single link, such as current, and determine passability through preliminary testing, potentially failing to identify potential risks in chip operation. The system comprises: a set acquisition module, configured to cluster a data set to obtain a number of cluster sets; a probability determination module, configured to determine the actual fault probability corresponding to the current cluster set; a data addition module, configured to determine the corresponding data set based on the chip model and specific measurement link of the integrated circuit chip under test; and to add the measured data of the integrated circuit chip under test to the data set; and an anomaly detection module, configured to cluster the current data set to obtain the corresponding actual fault probability.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit chips, and in particular to an integrated circuit chip testing system, method, device and medium. Background Art

[0002] An integrated circuit chip is a miniature electronic device that contains a variety of electronic components. It is a miniature electronic device that integrates a large number of microelectronic components (such as transistors, resistors, capacitors, etc.) through a specific process and encapsulates them on a small piece or several small pieces of semiconductor wafers or dielectric substrates. Integrated circuit chips have a wide range of applications, from simple signal amplification or timing functions to complex computing task processing. In particular, integrated circuit chips play an indispensable role in electronic devices that require advanced computing, such as computers and smartphones.

[0003] Existing integrated circuit chip fault detection schemes involve: actual testing, which mainly divides the test into several links, collects the test results corresponding to each link (for example, in the current test link, the test current value), and determines whether the measured data meets the preset qualified range. When it is within the preset qualified range, the preliminary test is completed and the integrated circuit chip is determined to be qualified.

[0004] However, existing solutions for fault detection in integrated circuit chips focus solely on testing a single link, such as current, and may overlook other key parameters, such as voltage, timing, and functionality, making it impossible to fully evaluate chip performance. Furthermore, determining compliance only through preliminary testing may fail to uncover potential problems with the chip during operation. Summary of the Invention

[0005] In response to the above-mentioned deficiencies in the prior art, the present application provides an integrated circuit chip testing system, method, equipment and medium to solve the existing solutions for fault detection of integrated circuit chips: only focusing on the test of a single link such as current, while ignoring other key parameters; in addition, only preliminary testing is used to determine whether the chip is qualified, and there is a problem of not being able to discover potential risks of the chip during operation.

[0006] In a first aspect, the present application provides an integrated circuit chip testing system, the system comprising:

[0007] The sample acquisition module is used to obtain the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; the set acquisition module is used to treat the sample data belonging to the same chip model and the same actual measurement link as a data set, and then cluster the data set to obtain a plurality of cluster sets; the feedback acquisition module is used to obtain the actual fault feedback results corresponding to the sample data, wherein the actual fault feedback results are divided into: fault presence and no fault; the probability determination module is used to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults; the data addition module is used to obtain the chip model of the integrated circuit chip to be tested, the specific actual measurement link, and the actual measurement data corresponding to each actual measurement link; based on the chip model and specific measurement link of the integrated circuit chip to be tested, determine the corresponding data set; add the actual measurement data of the integrated circuit chip to be tested to the data set; the anomaly detection module is used to cluster the current data set to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip, and then obtain the corresponding actual fault probability; when the actual fault probability is greater than a preset probability threshold, generate an anomaly alarm to the preset maintenance terminal.

[0008] The integrated circuit chip testing system provided in the embodiments of the present application uses a collection acquisition module to organize sample data from the same chip model and measurement phase into data sets for clustering. A probability determination module calculates and determines the actual failure probability corresponding to each cluster set (failure probability determination is performed because chip data from the same type and measurement phase is more comparable, improving the accuracy of fault detection). This helps determine which cluster a new data point (such as the data of the chip under test) belongs to. Furthermore, the actual failure probability of the current chip data can be predicted based on the actual failure probability of the specific cluster. Furthermore, the system can process data from different chip models and measurement phases. For a new chip under test, simply obtain its model and measured data through the data addition module and incorporate it into the corresponding data set for analysis. This implementation process involves measured data corresponding to each measurement phase, reducing the risk of focusing solely on a single phase, such as current, which may overlook other key parameters, such as voltage, timing, and functionality, and fail to fully evaluate chip performance. Furthermore, the present application uses an aggregation algorithm to perform correlation analysis on the measured data corresponding to each measurement phase, reducing the risk of failing to identify potential problems in the chip during operation by only determining pass status through preliminary testing.

[0009] In one implementation of the present application, the system further includes a data set correction module, which is used to obtain actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the preset maintenance terminal after generating an abnormal alarm to the preset maintenance terminal.

[0010] The integrated circuit chip testing system provided in this embodiment utilizes a dataset correction module to obtain actual fault feedback results for newly added integrated circuit chip data. This module effectively expands the dataset, continuously increasing the number of datasets and providing more reliable data support for integrated circuit chip fault prediction and diagnosis.

[0011] In one implementation of the present application, the sample acquisition module includes a first acquisition unit and a second acquisition unit; the first acquisition unit is used to obtain the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through a preset data upload interface; the second acquisition unit is used to obtain the actual measurement data corresponding to each actual measurement link according to the actual measurement terminal corresponding to each actual measurement link.

[0012] In one implementation of the present application, the set acquisition module includes a clustering unit for obtaining the type K of actual faults; randomly selecting M sample data from the data set as initial cluster centers; wherein M K; use the K-Means clustering algorithm to obtain M cluster sets.

[0013] In one implementation of the present application, the probability determination module includes a calculation unit for calculating the probability of the following equation:

[0014] , calculate and obtain the actual failure probability corresponding to the current cluster set.

[0015] In a second aspect, the present application provides an integrated circuit chip testing method, the method comprising:

[0016] Obtain the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; take the sample data belonging to the same chip model and the same actual measurement link as a data set, and then cluster the data set to obtain several cluster sets; obtain the actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault presence and no fault; based on the total amount of sample data in the cluster set and the component of sample data with faults, determine the actual fault probability corresponding to the current cluster set; obtain the chip model of the integrated circuit chip to be tested, the specific actual measurement link and the actual measurement data corresponding to each actual measurement link; based on the chip model of the integrated circuit chip to be tested and the specific actual measurement link, determine the corresponding data set; add the actual measurement data of the integrated circuit chip to be tested to the data set; cluster the current data set to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, generate an abnormal alarm to the preset maintenance terminal.

[0017] In one implementation of the present application, obtaining the chip model of the integrated circuit chip, the measurement steps of the integrated circuit chip, and the measured data corresponding to each measurement step as sample data specifically includes:

[0018] Through the preset data upload interface, the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip are obtained; according to the actual measurement terminal corresponding to each actual measurement link, the actual measurement data corresponding to each actual measurement link are obtained.

[0019] In one implementation of the present application, clustering is performed on the data set to obtain several cluster sets, specifically including:

[0020] Get the actual fault type K; randomly select M sample data from the data set as the initial cluster center; where M K; use the K-Means clustering algorithm to obtain M cluster sets.

[0021] In a third aspect, the present application provides an integrated circuit chip testing device, the device comprising:

[0022] processor;

[0023] and a memory storing executable codes, which, when executed, enable the processor to execute any one of the above-mentioned integrated circuit chip testing methods.

[0024] In a fourth aspect, the present application provides a non-volatile computer storage medium having computer instructions stored thereon, which, when executed, implement an integrated circuit chip testing method as described above.

[0025] Those skilled in the art will appreciate that this application has at least the following beneficial effects:

[0026] This application discloses an integrated circuit chip testing system, method, device, and medium. Using a collection acquisition module, sample data from the same chip model and measurement phase are organized into data sets. These data sets are then clustered to obtain several cluster sets. A probability determination module calculates and determines the actual failure probability corresponding to each cluster set (this determination of failure probability improves fault detection accuracy because chip data from the same type and measurement phase are more comparable). This helps determine which cluster a new data point (such as the data from the chip under test) belongs to. Furthermore, the actual failure probability of the current chip data can be predicted based on the actual failure probability of the specific cluster. Furthermore, the system can process data from different chip models and measurement phases. For a new chip under test, simply obtain its model and measurement data through the data addition module and incorporate it into the corresponding data set for analysis. This implementation process involves measured data corresponding to each measurement phase, focusing not only on testing a single phase, such as current, but also addressing the risk of overlooking other key parameters, such as voltage, timing, and functionality, leading to an inability to fully assess chip performance. In addition, this application uses an aggregation algorithm to perform correlation analysis on the measured data corresponding to each measured link, reducing the risk of failing to discover potential problems in the chip during operation by only determining its qualification through preliminary testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Some embodiments of the present disclosure are described below with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a schematic diagram of the internal structure of an integrated circuit chip testing system provided in an embodiment of the present application.

[0029] Figure 2 This is a flow chart of an integrated circuit chip testing method provided in an embodiment of the present application.

[0030] Figure 3 This is a schematic diagram of the internal structure of an integrated circuit chip testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] It should be understood by those skilled in the art that the embodiments described below are merely preferred embodiments of the present disclosure and do not imply that the present disclosure can only be implemented through these preferred embodiments. These preferred embodiments are merely intended to explain the technical principles of the present disclosure and are not intended to limit the scope of protection of the present disclosure. Based on the preferred embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of the present disclosure.

[0032] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0033] The technical solutions proposed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0034] This application Figure 1 An integrated circuit chip testing system is provided in an embodiment of the present application. Figure 1 As shown, the system provided in the embodiment of the present application mainly includes:

[0035] The sample acquisition module 110 is used to acquire the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data.

[0036] It should be noted that the actual measurement link may be a voltage actual measurement link, a timing actual measurement link, a function actual measurement link, etc. The sample acquisition module 110 is software or hardware capable of acquiring data.

[0037] Those skilled in the art will appreciate that, in this application, by collecting data from different chip models and different measurement links, a data set containing test data from multiple links can be constructed.

[0038] As an example, the sample acquisition module 110 includes a first acquisition unit and a second acquisition unit; the first acquisition unit is used to obtain the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through a preset data upload interface; the second acquisition unit is used to obtain the actual measurement data corresponding to each actual measurement link according to the actual measurement terminal corresponding to each actual measurement link.

[0039] The set acquisition module 120 is used to treat the sample data belonging to the same chip model and the same measurement link as a data set, and then perform clustering processing on the data set to obtain a plurality of cluster sets.

[0040] It should be noted that the set acquisition module 120 is connected to the sample acquisition module 110 and can perform clustering processing on the data obtained by the sample acquisition module 110 .

[0041] Among them, the clustering processing process can be: implemented through an existing algorithm that can automatically cluster data, for example, through the clustering unit embedded in the set acquisition module 120, to obtain the actual fault type K; randomly select M sample data from the data set as the initial cluster center; where M>K; use the K-Means clustering algorithm to obtain M cluster sets.

[0042] It should be noted that, in this application, due to differences in the way data are presented between different specific actual faults, in order to make the clustering accurate, M is at least K+1; K means that specific actual faults are classified into the same category (so there are K categories), and 1 means that data without faults are classified into one category (1 category).

[0043] The feedback obtaining module 130 is used to obtain actual fault feedback results corresponding to the sample data.

[0044] It should be noted that the feedback acquisition module 130 is a device that can obtain the actual fault feedback results of the above data from the outside. The feedback acquisition module 130 can be a server, including an upload interface, through which the actual fault feedback results returned by the technician are obtained. The actual fault feedback results are divided into: fault presence and no fault.

[0045] The probability determination module 140 is configured to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults.

[0046] As an example, the probability determination module 140 includes a calculation unit for determining the probability of the product by the formula:

[0047] , calculate and obtain the actual failure probability corresponding to the current cluster set.

[0048] Those skilled in the art will appreciate that the probability determination module 140 can obtain a more reliable fault probability estimate by considering the total number of samples in the cluster set and the proportion of samples with faults.

[0049] The data adding module 150 is used to obtain the chip model of the integrated circuit chip to be tested, the specific measurement steps and the measured data corresponding to each measurement step; determine the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement steps; and add the measured data of the integrated circuit chip to be tested to the data set.

[0050] It should be noted that the present application matches the model of the chip to be tested with the actual measurement link through the data adding module 150 to find the corresponding data set. Comparing and analyzing the data of the chip to be tested with the existing sample data helps to improve the accuracy of fault prediction.

[0051] The anomaly detection module 160 is used to perform clustering processing on the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; and then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, an anomaly alarm is generated to the preset maintenance terminal.

[0052] It should be noted that the present application performs clustering processing through the anomaly detection module 160 to find the cluster set to which the actual measured data of the chip under test belongs. The data of the chip under test is matched with the existing cluster set, so that its failure risk (actual failure probability) can be more accurately assessed.

[0053] In addition, this application can increase the data capacity by adding actual fault feedback results later, thereby updating and optimizing the data set, enabling the clustering algorithm to continuously learn and adapt to new data, thereby improving clustering accuracy.

[0054] The specific implementation process can be:

[0055] Through the data set correction module included in the system; after generating an abnormal alarm to the preset maintenance terminal, the actual fault feedback result of the newly added integrated circuit chip data to be tested in the data set is obtained through the preset maintenance terminal.

[0056] In addition, the embodiment provides an integrated circuit chip testing method, such as Figure 2 As shown, the method provided in the embodiment of the present application mainly includes the following steps:

[0057] Step 210: Obtain the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data.

[0058] This step specifically includes:

[0059] Obtain the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data, specifically including:

[0060] Obtain the chip model and actual measurement link of the integrated circuit chip through the preset data upload interface;

[0061] According to the measuring terminals corresponding to each measuring link, the measured data corresponding to each measuring link is obtained.

[0062] Step 220: The sample data belonging to the same chip model and the same measurement link are taken as a data set, and then clustering processing is performed on the data set to obtain a plurality of cluster sets.

[0063] The data set is clustered to obtain several cluster sets, which can be:

[0064] Get the actual fault type K; randomly select M sample data from the data set as the initial cluster center; where M K; use the K-Means clustering algorithm to obtain M cluster sets.

[0065] Step 230: Obtain actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault exists and no fault.

[0066] Step 240: Determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults.

[0067] Step 250: Obtain the chip model of the integrated circuit chip to be tested, the specific measurement steps, and the measured data corresponding to each measurement step; determine the corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement steps; and add the measured data of the integrated circuit chip to be tested to the data set.

[0068] Step 260: cluster the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; then obtain the corresponding actual fault probability; when the actual fault probability is greater than a preset probability threshold, generate an abnormal alarm to the preset maintenance terminal.

[0069] The above is a method embodiment of the present application. Based on the same inventive concept, the present application embodiment also provides an integrated circuit chip testing device. Figure 3 As shown, the device includes: a processor; and a memory on which executable codes are stored. When the executable codes are executed, the processor executes an integrated circuit chip testing method as described in the above embodiment.

[0070] Specifically, the server side obtains the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; the sample data belonging to the same chip model and the same actual measurement link are taken as a data set, and then the data set is clustered to obtain several cluster sets; the actual fault feedback results corresponding to the sample data are obtained; wherein the actual fault feedback results are divided into: fault presence and no fault; based on the total amount of sample data in the cluster set and the component of sample data with faults, the actual fault probability corresponding to the current cluster set is determined; the chip model of the integrated circuit chip to be tested, the specific actual measurement link and the actual measurement data corresponding to each actual measurement link are obtained; based on the chip model of the integrated circuit chip to be tested and the specific actual measurement link, the corresponding data set is determined; the actual measurement data of the integrated circuit chip to be tested is added to the data set; the current data set is clustered to determine the cluster set corresponding to the actual measurement data of the current integrated circuit chip; and then the corresponding actual fault probability is obtained; when the actual fault probability is greater than the preset probability threshold, an abnormal alarm is generated to the preset maintenance terminal.

[0071] In addition, an embodiment of the present application further provides a non-volatile computer storage medium having executable instructions stored thereon, which, when executed, implements the above-mentioned integrated circuit chip testing method.

[0072] Thus far, the technical solutions of the present disclosure have been described in conjunction with the foregoing multiple embodiments. However, it is easy for those skilled in the art to understand that the scope of protection of the present disclosure is not limited to these specific embodiments. Without departing from the technical principles of the present disclosure, those skilled in the art may split and combine the technical solutions in the above-mentioned various embodiments, and may also make equivalent changes or replacements to the relevant technical features. Any changes, equivalent replacements, improvements, etc. made within the technical concepts and / or technical principles of the present disclosure will fall within the scope of protection of the present disclosure.

Claims

1. An integrated circuit chip testing system, characterized in that: The system comprises: A sample acquisition module is used to obtain the chip model of the integrated circuit chip, the actual measurement link of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; The set acquisition module is used to treat the sample data of the same chip model and the same measurement link as a data set, and then cluster the data set to obtain several cluster sets; The feedback acquisition module is used to obtain the actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault existence and no fault; A probability determination module is used to determine the actual fault probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with faults; The data adding module is used to obtain the chip model of the integrated circuit chip to be tested, the specific measurement steps and the measured data corresponding to each measurement step; based on the chip model of the integrated circuit chip to be tested and the specific measurement steps, determine the corresponding data set; and add the measured data of the integrated circuit chip to be tested to the data set; The anomaly detection module is used to perform clustering processing on the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; thereby obtaining the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, an anomaly alarm is generated and sent to the preset maintenance terminal; The data set correction module is used to obtain the actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the preset maintenance terminal after generating an abnormal alarm to the preset maintenance terminal.

2. The integrated circuit chip testing system according to claim 1, wherein: The sample acquisition module includes a first acquisition unit and a second acquisition unit; A first acquisition unit is used to acquire the chip model of the integrated circuit chip and the actual measurement link of the integrated circuit chip through a preset data upload interface; The second acquisition unit is used to obtain the measured data corresponding to each measurement link according to the measurement terminal corresponding to each measurement link.

3. The integrated circuit chip testing system according to claim 1, wherein: The collection acquisition module includes a clustering unit, Used to obtain the actual fault type K; Randomly select M sample data from the data set as the initial cluster center; where M>K; Using the K-Means clustering algorithm, we can obtain M cluster sets.

4. The integrated circuit chip testing system according to claim 1, wherein: The probability determination module includes a calculation unit, Used by the formula: Actual failure probability = (component / total amount)*100%, calculate and obtain the actual failure probability corresponding to the current cluster set.

5. A method for testing an integrated circuit chip, characterized in that: The method comprises: Obtaining the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data; The sample data of the same chip model and the same measurement link are taken as a data set, and then the data set is clustered to obtain several cluster sets; Obtaining actual fault feedback results corresponding to the sample data; wherein the actual fault feedback results are divided into: fault presence and no fault; Determine the actual failure probability corresponding to the current cluster set based on the total amount of sample data in the cluster set and the proportion of sample data with failures; Obtaining the chip model of the integrated circuit chip to be tested, specific measurement steps, and measured data corresponding to each measurement step; determining a corresponding data set based on the chip model of the integrated circuit chip to be tested and the specific measurement steps; and adding the measured data of the integrated circuit chip to be tested to the data set; Perform clustering on the current data set to determine the cluster set corresponding to the measured data of the current integrated circuit chip; then obtain the corresponding actual fault probability; when the actual fault probability is greater than the preset probability threshold, generate an abnormal alarm to the preset maintenance terminal, and obtain the actual fault feedback results of the newly added integrated circuit chip data to be tested in the data set through the preset maintenance terminal.

6. The integrated circuit chip testing method according to claim 5, wherein: Obtain the chip model of the integrated circuit chip, the actual measurement links of the integrated circuit chip, and the actual measurement data corresponding to each actual measurement link as sample data, specifically including: Obtain the chip model and actual measurement link of the integrated circuit chip through the preset data upload interface; According to the measuring terminals corresponding to each measuring link, the measured data corresponding to each measuring link is obtained.

7. The integrated circuit chip testing method according to claim 5, wherein: Perform clustering on the data set to obtain several cluster sets, including: Get the actual fault type K; Randomly select M sample data from the data set as the initial cluster center; where M>K; Using the K-Means clustering algorithm, we can obtain M cluster sets.

8. An integrated circuit chip testing device, characterized in that: The device comprises: processor; and a memory storing executable code, which, when executed, causes the processor to execute an integrated circuit chip testing method according to any one of claims 5 to 7.

9. A non-volatile computer storage medium, characterized in that Computer instructions are stored thereon, and when the computer instructions are executed, an integrated circuit chip testing method according to any one of claims 5 to 7 is implemented.

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