Storage system

Abstract

An object of the invention is to reduce power consumption. Each of a plurality of controllers of the storage system includes: a plurality of first power supply regions capable of independently performing power supply control; a processor provided in each of the first power supply regions and configured to process an input / output request; and a memory provided in each of the first power supply regions and connected to the processor. Each of the plurality of controllers is configured so as to be capable of switching: a first operation mode in which all of the first power supply regions provided in the controller are set to an operating state; and a second operation mode in which a part of the first power supply regions provided in the controller are set to a stopped state and the other first power supply regions are set to an operating state.

Description

Technical Field

[0001] The invention relates to power control of a storage system. Background Art

[0002] In a storage system that receives a request for data input / output from a host computer and stores / outputs data, a processor and a memory are mounted in the controller for internal control. The processor and the memory operate at high speed to achieve high processing performance, and consume a lot of power. On the other hand, in the storage system, there are also cases where there is no constant request for data input / output from the host computer. Even when there is no request for data input / output from the host computer, that is, when the storage system is in standby mode, the processor of the controller continues to work in order to detect the request when the input / output request arrives.

[0003] In addition, in the storage system, when a controller stops processing due to a failure, data input / output with the host computer may become impossible or data received from the host computer may be lost, so two or more controllers are provided to achieve controller redundancy. That is, when one of the two or more controllers stops processing due to a failure, the remaining controllers continue processing or the two or more controllers repeatedly hold the data received from the host computer, thereby continuing data input / output with the host computer and preventing the loss of data received from the host computer.

[0004] In such a storage system, power consumption reduction is also required. In particular, in a storage system, when there is no data input / output request from a host computer, the processor of the controller continues to operate and consumes power, so it is required to reduce the power consumption during the standby period as much as possible according to the presence or absence of data input / output request from the host computer.

[0005] In such a case, if the number of controllers in the storage system is three or more, redundancy can be maintained by operating only two of the controllers, so it is conceivable to stop processing in controllers exceeding two and turn off the power. Patent Document 1 is an example of such a case.

[0006] In Patent Document 1, since the power is turned off for each controller, redundancy is lost if one of the controllers is turned off in a storage system having a maximum of two controllers, and therefore the system cannot be applied. That is, if only one controller is to continue to operate, when the processing of the controller stops due to a failure, data input and output with the host computer cannot be continued, and data received from the host computer is lost.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2007-102409 Summary of the invention

[0010] Problems to be solved by the invention

[0011] The problem to be solved by the present invention is to control the power supply of a processor and a memory in a storage system without damaging redundancy, thereby reducing power consumption.

[0012] Means used to solve problems

[0013] A technical solution of the present invention is a storage system for saving or outputting data through input and output requests of data from a host device, comprising multiple controllers; each of the multiple controllers includes: multiple first power supply areas capable of independently performing power supply control; a processor, provided in each of the above-mentioned first power supply areas, processing the above-mentioned input and output requests; and a memory, provided in each of the above-mentioned first power supply areas, connected to the above-mentioned processor; each of the multiple controllers is configured to be able to switch: a first action mode, setting all of the above-mentioned first power supply areas provided in the controller to a working state; and a second action mode, setting a part of the above-mentioned first power supply areas provided on the controller to a stopped state, and setting the other above-mentioned first power supply areas to a working state.

[0014] A technical solution of the present invention is a storage system for storing or outputting data through an input / output request of data from a host device, comprising a plurality of controllers; a first controller among the plurality of controllers comprises a plurality of power supply areas capable of performing power supply control respectively; a first power supply area among the plurality of power supply areas comprises a first processor and a first memory connected to the first processor; a second power supply area among the plurality of power supply areas comprises a second processor and a second memory connected to the second processor; the first processor consumes more power than the second processor; a second controller among the plurality of controllers comprises a plurality of power supply areas capable of performing power supply control respectively; a third power supply area among the plurality of power supply areas of the second controller comprises a third processor and a second memory connected to the third processor a third memory connected to the controller; a fourth power area among the plurality of power areas of the second controller includes a fourth processor and a fourth memory connected to the fourth processor; the third processor consumes more power than the fourth processor; the storage system has a first action mode and a second action mode; the first action mode sets the power supply of the first power area to a working state and sets the power supply of the second power area to a stopped state, sets the power supply of the third power area to a working state and sets the power supply of the fourth power area to a stopped state; the second action mode sets the power supply of the first power area to a stopped state and sets the power supply of the second power area to a working state, sets the power supply of the third power area to a stopped state and sets the power supply of the fourth power area to a working state.

[0015] Effects of the Invention

[0016] A technical solution of the present invention can reduce the power consumption of a storage system. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is an example of the configuration of a storage system.

[0018] Figure 2 This is the first example of a flowchart of power supply control.

[0019] Figure 3 This is an example of the first processing procedure of the write request process.

[0020] Figure 4 This is an example of the first processing procedure of the read request process.

[0021] Figure 5 This is the second example of the power supply control flowchart.

[0022] Figure 6 This is an example of the second processing procedure of the write request process.

[0023] Figure 7This is an example of the second processing procedure of the read request process.

[0024] Description of symbols

[0025] 1: Storage system

[0026] 101a~101d: protocol chip

[0027] 102a, 102b: front-end switches

[0028] 103: Inter-controller path

[0029] 104a~104d: Processor

[0030] 105a~105a:Memory

[0031] 106a, 106b: Backend switches

[0032] 107a~107h: Storage devices

[0033] 110a, 110b: Controller

[0034] 120a, 120b, 121a~d, 122a, 122b: power supply area

[0035] 130a, 130b, 131a to 131d, 132a, 132b: power supply control unit DETAILED DESCRIPTION

[0036] The embodiments are merely examples for implementing the present invention and do not limit the technical scope of the present invention. Moreover, not all combinations of features described in the embodiments are necessarily essential for solving the problems of the present invention.

[0037] In the following description, various information is sometimes described by the expression of "xxx table", but various information can also be expressed in data structures other than tables. In order to indicate that it does not depend on the data structure, "xxx table" can be called "xxx information". In addition, in the following description, numbers are used as identification information of elements, but other types of identification information (such as names, identifiers) can be used.

[0038] In the following description, when describing the same kind of elements without distinguishing them from each other, common reference numerals (or reference numerals) may be used, and when describing the same kind of elements while distinguishing them from each other, reference numerals (or element IDs) may be used.

[0039] Since the program is executed by a processor (e.g., CPU (Central Processing Unit)) included in the storage controller, and the set processing is performed while appropriately using storage resources (e.g., main storage) and / or communication interface devices, the subject of the processing can also be the storage controller or the processor. In addition, the storage controller can also include a part or all of the hardware circuits that perform the processing. The computer program can also be installed from a program source. The program source can also be, for example, a program distribution server or a computer-readable storage medium.

[0040] [Example 1]

[0041] use Figure 1 , Figure 2 , Figure 3 and Figure 4 Example 1 is described. Figure 1 This is an example of the configuration of the storage system of Example 1. Figure 1 In the embodiment 1, the storage system 1 includes two controllers 110a and 110b and eight storage devices 107a to 107h. The controllers 110a and 110b are detachable from the storage system 1. Thus, the storage controllers can be easily replaced.

[0042] The controller 110a includes two protocol chips 101a and 101b, one front-end switch 102a, two processors 104a and 104b, two memories 105a and 105b, and one back-end switch 106a. The back-end switch 106a is a storage device connection unit.

[0043] Similarly, the controller 110b includes two protocol chips 101c and 101d, one front-end switch 102b, two processors 104c and 104d, two memories 105c and 105d, and one back-end switch 106b. The back-end switch 106b is a storage device connection unit.

[0044] In addition, the two controllers 110a and 110b are connected via an inter-controller path 103. Figure 1 In the example, the inter-controller path 103 connects the front-end switch 102a of the controller 110a and the front-end switch 102b of the controller 110b.

[0045] The protocol chips 101a to 101d are respectively connected to a host device (not shown), perform protocol control for communication with the host device, and retrieve data input / output requests from the host device or return responses to data input / output requests to the host device.

[0046] In the storage system 1, an example of a protocol for communication with a host device is Fibre Channel. Another example is iSCSI (internet Small Computer System Interface). Another example is NVMe over Fabrice (Non-Volatile Memory express over Fabric, NVMe-oF).

[0047] exist Figure 1 In the figure, an example of a configuration in which two controllers 110a and 110b respectively have two protocol chips 101a and 101b and 101c and 101d is shown, but the number of protocol chips 101a to 101d is not limited to two per controller, and can be any number greater than one.

[0048] The front-end switch 102a connects the protocol chips 101a and 101b to the processors 104a and 104b. The front-end switch 102a sends the data input / output request received from the host device (not shown) by the protocol chips 101a and 101b to one of the processors 104a and 104b, and sends the response of the data input / output request to the host device returned by one of the processors 104a and 104b to the protocol chip 101a and 101b.

[0049] Similarly, the front-end switch 102b connects the protocol chips 101c and 101d to the processors 104c and 104d. The front-end switch 102b sends the data input / output request received from the host device (not shown) by the protocol chips 101c and 101d to one of the processors 104c and 104d, and sends the response of the data input / output request to the host device returned by one of the processors 104c and 104d to the protocol chip 101c or 101d.

[0050] Furthermore, the front-end switches 102a and 102b are connected by an inter-controller path 103. The front-end switches 102a and 102b transfer data sent from the processor 104a or 104b of the controller 110a to the processor 104c or 104d of the controller 110b, and transfer data sent from the processor 104c or 104d of the controller 110b to the processor 104a or 104b of the controller 110a.

[0051] exist Figure 1 In the figure, one front-end switch 102a and one front-end switch 102b are respectively shown in the controllers 110a and 110b, but the number of front-end switches is not limited to one per controller, and can be any number of one or more.

[0052] The processors 104a to 104d are responsible for processing data input / output requests from the host device in the storage system 1. Figure 1 In the figure, two processors 104a and 104b and 104c and 104d are respectively shown in two controllers 110a and 110b, but the number of processors is not limited to two in each controller, and can be any number of more than two.

[0053] Likewise, the memories 105a to 105d store program codes executed by the processors 104a to 104d and data processed, and in particular temporarily store data written from the host device until it is written to any of the storage devices 107a to 107h.

[0054] At this time, if the processors 104a and 104b, memories 105a and 105b of the controller 110a, or the processors 104c and 104d, memories 105c and 105d of the controller 110b, or the processors or memories belonging to a certain controller fail, the data written from the host device may disappear from the controller.

[0055] Therefore, once data is written from the host device to the memory 105a or 105b of the controller 110a or the memory 105c or 105d of the controller 110b, a copy of the data is sent to a memory of the other controller and saved. Thus, even if the processor or memory of one of the controllers 110a or 110b fails, the data written from the host device will not be lost as a whole.

[0056] Furthermore, in the memory 105a-105d, the data read from any of the storage devices 107a-107h is temporarily stored until it is returned to the host device. Such memory 105a-105d is typically a volatile memory such as DRAM (Dynamic Random Access Memory). Figure 1 Although one memory 105a to 105d is shown in each of the processors 104a to 104d in the figure, the number of memories per processor is not limited to one, and may be any number of one or more.

[0057] The backend switches 106a and 106b connect the processors 104a to 104d and the storage devices 107a to 107h. At this time, the backend switches 106a and 106b connect the processors 104a to 104d and the storage devices 107a to 107h in accordance with the storage protocol used by the storage devices 107a to 107h for data input and output.

[0058] A typical example of a storage protocol used by the storage devices 107a to 107h is NVMe (Non-Volatile Memory express). Another example of a storage protocol used by the storage devices 107a to 107h is SAS (Serial Attached Small Computer System Interface).

[0059] The storage protocol used by the storage devices 107a to 107h and the conversion of the communication with the processors 104a to 104d may be implemented by the backend switches 106a and 106b, or by an additional storage protocol processing unit (not shown). Alternatively, the processors 104a to 104d may perform storage protocol processing by software.

[0060] In addition, Figure 1 Although two backend switches 106a and 106b are shown in the figure, the number of backend switches 106a and 106b is not limited to 2 and is arbitrary. As long as the processors 104a to 104d process the storage protocol by software, the processors 104a to 104d and the storage devices 107a to 107h may be directly connected without providing the backend switches 106a and 106b.

[0061] The storage devices 107a to 107h read or write data according to a data input / output request sent from the processors 104a to 104d via the backend switch 106a or 106b. A typical example of the storage devices 107a to 107h is an SSD (Solid State Drive) using a flash memory as a storage element. Another example of the storage devices 107a to 107h is an HDD (Hard Disk Drive) using a magnetic disk as a storage element.

[0062] The storage devices 107a to 107h may be a single storage device or a mixture of multiple storage devices. Figure 1 Although eight storage devices 107a to 107h are shown in the figure, the number of the storage devices 107a to 107h is not limited to 8 and is arbitrary. Therefore, the storage devices 107a to 107h do not need to be mounted in the storage system 1.

[0063] In this case, other storage systems can be connected to the protocol chips 101a~101d in addition to the host device, and the request for reading or writing data can be sent from the processors 104a~104d to the other connected storage systems via the front-end switch 102a or 102b from the protocol chips 101a~101d to read or write data.

[0064] In addition, Figure 1 In the embodiment, the controller 110a includes a power area 120a, power areas 121a and 121b, and a power area 122a. The power area 120a includes protocol chips 101a and 101b and a front-end switch 102a, and is controlled by a power control unit 130a to operate or stop the power supply. The protocol chips 101a and 101b are connected to a host device for communication, so the operation or stop of the power supply by the power control unit 130a is controlled according to whether the communication with the host device is in progress, so that the power supply is not stopped when the communication is in progress. In addition, the power area of ​​the present embodiment is an area that can independently control the on and off of the power supply, and at least two or more are provided in the controller.

[0065] Various electronic devices constituting the controller, such as processors and memories, are set in a certain power area, and the supply and stop of their operating power are controlled in power area units. In addition, the power area is not limited to the definition of a physically set division, but can also be defined as a grouping of electronic devices that control the on and off of the supply of operating power. In either definition, the electronic devices in the controller exclusively belong to one of the power areas, and are powered on or off based on the power area unit. In addition, the number of electronic devices set in the power area is arbitrary, and can be one or more.

[0066] In addition, when multiple power supply areas are constructed, the specific form thereof can be, for example, a so-called electronic circuit substrate on which multiple independent power wirings are provided, each electronic component is connected to a certain power wiring, and the independent power wirings have power terminals that can be independently connected / disconnected. In such a form, for example, these power terminals can also be regarded as a power supply control unit. In addition, when the power supply areas are constructed in the form of the specific form, each power supply area is defined as a structure that cannot be removed from the controller.

[0067] The power area 121a includes a processor 104a and a memory 105a, and is controlled by a power control unit 131a to operate or stop the power supply. Similarly, the power area 121b includes a processor 104b and a memory 105b, and is controlled by a power control unit 131b to operate or stop the power supply. In addition, the power area 122a includes a back-end switch 106a, and is controlled by a power control unit 132a to operate or stop the power supply.

[0068] Similarly, the controller 110b includes a power supply area 120b, power supply areas 121c and 121d, and a power supply area 122b. In each power supply area, the controller 110b is configured to be non-detachable from the controller 110a. The power supply area 120b includes the protocol chips 101c and 101d and the front-end switch 102b, and is controlled by the power supply control unit 130b to operate or stop the power supply.

[0069] The power area 121c includes a processor 104c and a memory 105c, and is controlled by a power control unit 131c to operate or stop the power supply. Similarly, the power area 121d includes a processor 104d and a memory 105d, and is controlled by a power control unit 131d to operate or stop the power supply. In addition, the power area 122b includes a back-end switch 106b, and is controlled by a power control unit 132b to operate or stop the power supply.

[0070] The storage system 1 of the first embodiment has a plurality of operation modes including a first operation mode and a second operation mode. The first operation mode sets the power supplies of all power supply areas to an operating state, and the second operation mode sets the power supplies of a part of the power supply areas to an operating state and sets the power supplies of the other part of the power supply areas to a stopped state.

[0071] In the first embodiment, at the start-up of the system, the power supplies of all power supply areas 120a, 120b, 121a to 121d, 122a, and 122b are set to the operating state, and all processors 104a to 104d are made to perform processing. This is the first operation mode.

[0072] Then, according to the frequency of the input / output request from the host device, the processing of one of the processors 104a or 104b is stopped in the controller 110a, and the power supply of the power supply area 121a or 121b to which the stopped processor belongs is set to a stopped state. In addition, the processing of one of the processors 104c or 104d is also stopped in the controller 110b, and the power supply of one of the power supply areas 121c or 121d to which the stopped processor belongs is set to a stopped state. This is the second operation mode. Therefore, when the storage system 1 operates in the second operation mode, a part of the multiple processors included in the controller is stopped, and the power supply of the power supply area to which the stopped processors belong is in a stopped state. In addition, in order to process the input / output request, at least one processor in the controller continues to operate, and the power supply of the power supply area to which the processor that continues to operate belongs is in a working state.

[0073] Then, according to the input / output frequency from the host device, the stopped power area 121a or 121b, power area 121c or 121d is set to the working state again, so that the processing of the processor 104a or 104b, processor 104c or 104d that stopped the processing is restarted. This is the first operation mode. That is, the storage system 1 changes from the first operation mode to the second operation mode, and then changes to the first operation mode. Figure 2 The situation is described in . Figure 2 This is a flowchart of an example of power supply control.

[0074] 201: When the storage system 1 is started, the power supplies of all the power supply areas 120a, 120b, 121a to 121d, 122a, and 122b are operating.

[0075] 202: Then, the storage system 1 observes the frequency of input / output requests from the host device.

[0076] 203: If the condition that the frequency is less than the predetermined value (threshold) within the predetermined period is not satisfied (203: No), the flow returns to step 202. Therefore, the observation of the frequency related to the input / output request and the determination related to the observation result shown in steps 202 and 203 are periodically performed.

[0077] 204: When the frequency is less than the predetermined value during the predetermined period (203: Yes), the storage system 1 determines to stop the power supply of the power supply areas 121a and 121c (stop the processing of the processors 104a and 104c). That is, when the storage system 1 of this embodiment is started, it starts to operate in the first operation mode. Then, when the storage system 1 detects that the frequency of input / output requests is lower than an arbitrarily set reference while operating in the first operation mode, it determines to shift to the second operation mode.

[0078] 205: Then, processor 104a hands over its processing to processor 104b, and processor 104c hands over its processing to processor 104d.

[0079] 206: Then, processors 104a and 104c stop their processing.

[0080] 207: Furthermore, the power control unit 131a stops the power supply to the power supply area 121a, and the power control unit 131c stops the power supply to the power supply area 121c. Thus, in step 203, the power supply to the processor 104a and the memory 105a provided in the power supply area 121a is stopped, and the power supply to the processor 104c and the memory 105c provided in the power supply area 121c is stopped.

[0081] 208: When the storage system 1 shifts to the second operation mode, it continues to observe the frequency of input / output requests from the host device.

[0082] 209: If the frequency is less than the preset value (threshold) within the preset period (209: No), the process returns to 208. Therefore, the observation of the frequency related to the input / output request and the determination related to the observation result shown in steps 208 and 209 are periodically performed. In addition, the prescribed period of this step may be the same as or different from the prescribed period of step 203.

[0083] There is no particular regulation on the size of the specified value of this step compared to the specified value of step 203. However, if the specified value of step 203 is larger than the specified value of this step, the condition of step 203 is satisfied (203: Yes), and steps 204 to 207 are executed. Even if the power supply of power supply areas 121a and 121c is stopped, in this step 209, the frequency of input / output requests from the host device becomes larger than the specified value of this step, and the process does not return to step 208 but directly transfers to the next step 210.

[0084] Therefore, the prescribed value of step 203 is preferably smaller than the prescribed value of this step 209. That is, by appropriately setting the prescribed value (203) related to the switch from the first mode to the second mode and the prescribed value (208) related to the switch from the second mode to the first mode, it is possible to prevent unnecessary switching operations from being performed.

[0085] 210: When the frequency is equal to or higher than the predetermined value during the predetermined period (209: Yes), the power control unit 131a operates the power supply of the power supply area 121a, and the power control unit 131c operates the power supply of the power supply area 121c. Therefore, in step 210, power supply to the processor 104a and the memory 105a provided in the power supply area 121a is started, and power supply to the processor 104c and the memory 105c provided in the power supply area 121c is started.

[0086] 211: Then, processors 104a and 104c restart their respective processing.

[0087] 212: Then, the processor 104b reallocates the processing related to the input / output request to the processor 104a, and the processor 104d reallocates the processing to the processor 104c.

[0088] The observation of the frequency of the input / output request from the host device in 202 and 208 may be performed by the processors 104a to 104d that are in operation, or by a separate dedicated processor for observation. As a method of observation, for example, a function such as a timer for measuring time is given to the processors 104a to 104d or the dedicated processor for observation, and the frequency of the input / output request from the host device is counted within a certain period of time using the time measuring function.

[0089] In addition to observing the frequency of input / output requests from the host device, the object of observation may be replaced by other values ​​related to the frequency of input / output requests from the host device. For example, in the processors 104a to 104d that are working, a processor operating rate defined by the ratio of the time for processing input / output requests from the host device or garbage collection (GC) associated with the input / output requests to the time for waiting for input / output requests from other host devices, or the time for self-checking / repairing processing / rebuilding processing in the case of a RAID (Redundant Array of Independent Disks) structure in the storage system 1 or the storage devices 107a to 107d, etc. may be set instead of the frequency of input / output requests from the host device.

[0090] In the following description, when the frequency of input / output requests from the host device is replaced by a separately defined processor operating rate or the like, the frequency of input / output requests from the host device is referred to as the separately defined processor operating rate or the like.

[0091] The decision to stop the power supply to the power supply areas 121a and 121c of 204 can also be made by one or more processors of the processors 104a~104d communicating, exchanging or counting the observation results of the frequency of input and output requests from each host device, or a dedicated processor can be set up for decision processing and the decision can be made by counting the observation results of the frequency of input and output requests from the host device.

[0092] When the processors 104a to 104d communicate the observation results of the frequency of the input / output request from the host device with each other, or when a dedicated processor for the decision processing is separately provided, the communication can be performed via the communication mechanism of the front-end switch 102a or 102b or the back-end switch 106a or 106b, or a dedicated communication signal line can be separately provided. Alternatively, when a dedicated processor for observing the frequency of the input / output request from the host device is separately provided, the decision processing can also be performed together by the processor.

[0093] Next, an example of processing of a write request from the host device will be described. Figure 3 A sequence diagram showing an example of write request processing. In addition, the following takes the operation when a write request from a host device is sent to the controller 110a as an example. However, the operation shown below can also be applied when the controller 110b receives a write request from a host device by changing the relationship between the protocol switch, processor, memory, front-end switch, and back-end switch.

[0094] 301: The protocol chip 101a sends a write request received from the host device to the memory 105a of the processor 104a.

[0095] 302: The processor 104a retrieves the write request and write data from the host device from the memory 105a.

[0096] 303: The processor 104a sends the write data to the memory 105c of the processor 104c for duplication.

[0097] 304: The processor 104a sends a notification instruction of completion of the write request to the host device to the protocol chip 101a. Upon receiving the notification instruction of completion of the write request to the host device, the protocol chip 101a notifies the host device of the completion of the write request.

[0098] 305: The processor 104a sends a write command to the storage device 107a.

[0099] 306: The storage device 107a sends a request to write data to the processor 104a.

[0100] 307: The processor 104a fetches the write data from the memory 105a. This fetching may be performed by providing a function in a part of the hardware circuit of the processor 104a to automatically fetch the write data from the memory 105a in accordance with the write data request from the storage device 107a, or by software executed by the processor 104a.

[0101] 308: The processor 104a returns the write data to the storage device 107a. This return can also be performed by providing a function in a part of the hardware circuit of the processor 104a to automatically return the write data retrieved from the memory 105a in accordance with the write data request from the storage device 107a, or by software executed by the processor 104a.

[0102] 309: The storage device 107a receives the write data and notifies the processor 104a that the storage is complete.

[0103] 310 to 318: Steps 310 to 318 are described by replacing the processor 104a in steps 301 to 309 with the processor 104b, the processor 104c with the processor 104d, the memory 105a with the memory 105b, and the memory 105c with the memory 105d.

[0104] Next, in 319 to 336, when a write request from the host device is sent to the controller 110a, the processing performed on the two controllers 110a and 110b when the controllers 110a and 110b are determined to transfer from the first operation mode to the second operation mode is described. In addition, the processor and memory to be stopped are not limited to the examples shown below, and may also be the processor and memory of the other party in each controller.

[0105] 319-322: These steps are the same as steps 301-304.

[0106] 323: A processor decides to stop the processor 104a and the memory 105a. That is, it decides to stop the power supply of the power supply area 121a. That is, 323 indicates that the controller 110a is determined to shift from the first operation mode to the second mode, and at this time, the processor 104a and the memory 105a are stopped.

[0107] 324: A processor determines to stop the processor 104c and the memory 105c. That is, the power supply area 121c is determined to be power-off. That is, 324 indicates that the controller 110b is determined to shift from the first operation mode to the second mode, and at this time, the processor 104c and the memory 105c are stopped.

[0108] 325: In order to hand over the write data, the processor 104a retrieves the write data from the memory 105a.

[0109] 326: In order to hand over the write data, the processor 104a sends the write data to the memory 105b of the processor 104b.

[0110] 327: In order to hand over the write data, the processor 104c retrieves the write data from the memory 105c.

[0111] 328: In order to hand over the write data, the processor 104c sends the write data to the memory 105d of the processor 104d.

[0112] 329: The processor 104a and the memory 105a are stopped. That is, the power control unit 131a stops the power supply of the power supply area 121a.

[0113] 330: The processor 104c and the memory 105c are stopped. That is, the power control unit 131c stops the power supply of the power supply area 121c.

[0114] 331: The processor 104b confirms the write data on the memory 105b handed over from the processor 104a, that is, confirms the write request from the host.

[0115] 332-336: Steps 332 to 336 are the same as steps 314-318.

[0116] As described above, when all power domains are operating, a write request (data save request) from the host device can be received and processed by either the processor 104 a or 104 b of the controller 110 a .

[0117] When the power supply areas 121a and 121c are stopped, that is, when the processors 104a and 104c are stopped, the processor 104a can hand over the write request received from the host to the processor 104b. Furthermore, a copy of the write data from the host device, which is sent from the memory 105a of the processor 104a of the controller 110a to the memory 105c of the processor 104c of the controller 110b and stored, can also be handed over from the memory 105c of the processor 104c to the memory 105d of the processor 104d. Thus, even if some kind of failure occurs in the processor 104b or the memory 105b to which the write data from the host device is handed over by the controller 110a, the write data from the host device can be prevented from being lost.

[0118] In addition, in the processing sequence of the write request described above, it is shown that the controller 110a performs switching from the first operation mode to the second operation mode when receiving the write request. Therefore, when a new write request is sent from the host device after the handover shown in the above is completed, the processor and memory included in the power supply area that continues to operate perform the operations shown in 301 to 309.

[0119] Next, an example of processing of a read request from the host device will be described. Figure 4 A sequence diagram showing an example of read request processing. In addition, the following uses the operation when a read request from a host device is sent to the controller 110a as an example. However, the operation shown below can also be applied when the controller 110b receives a read request from a host device by changing the relationship between the protocol chip, processor, memory, front-end switch, and back-end switch.

[0120] 401: The protocol chip 101a sends a read request received from the host device to the memory 105a of the processor 104a.

[0121] 402: The processor 104a fetches the read request from the host device from the memory 105a.

[0122] 403: The processor 104a sends a read command to the storage device 107a.

[0123] 404: The storage device 107a returns the read data to the processor 104a.

[0124] 405: The processor 104a saves the read data from the storage device 107a to the memory 105a. The storage of the read data may be performed by providing a function in a part of the hardware circuit of the processor 104a to automatically save the read data in the memory 105a in accordance with the read data returned from the storage device 107a, or may be performed by software executed by the processor 104a.

[0125] 406: The processor 104a retrieves the read data from the memory 105a.

[0126] 407: The processor 104a sends a read response transmission instruction including read data to the host device and the read data to the protocol chip 101a. Upon receiving the read response transmission instruction including read data to the host device and the read data, the protocol chip 101a sends a read response including the read data to the host device.

[0127] 408 to 414: Steps 408 to 414 are described below with the processor 104a replaced by the processor 104b and the memory 105a replaced by the memory 105b in steps 401 to 407.

[0128] 415 : The protocol chip 101 a sends the read request received from the host to the memory 105 a of the processor 104 a . This step is the same as step 401 .

[0129] 416: A processor decides to stop the processor 104a and the memory 105a. That is, it decides to stop the power supply of the power supply area 121a. This step is the same as step 323.

[0130] 417: A processor decides to stop the processor 104c and the memory 105c. That is, it decides to stop the power supply of the power supply area 121c. This step is the same as step 324.

[0131] 418: The processor 104a fetches the read request from the host device from the memory 105a for read request handover.

[0132] 419: The processor 104a sends the read request from the host device to the memory 105b of the processor 104b in order to hand over the read request.

[0133] 420: The processor 104a and the memory 105a are stopped. That is, the power control unit 131a stops the power supply of the power supply area 121a. This step is the same as step 329.

[0134] 421: The processor 104c and the memory 105c are stopped. That is, the power control unit 131c stops the power supply of the power supply area 121c. This step is the same as step 330.

[0135] 422: The processor 104b retrieves the read request from the host device from the memory 105b handed over from the processor 104a.

[0136] 423-427: Steps 423-427 are the same as steps 410-414.

[0137] As described above, regarding a read request from the host device, when all power areas are operating, either the processor 104a or 104b of the controller 110a can receive the read request and process it. When the power area 121a is stopped, that is, when the processor 104a is stopped, the processor 104a can hand over the read request received from the host to the processor 104b. In addition, in the processing sequence of the read request described above, a situation in which the controller 110a receives a read request and switches from the first operation mode to the second operation mode is shown. Therefore, when a write request is newly sent from the host device after the handover shown in the above is completed, the processor and memory included in the operating power area perform the actions shown in 401 to 407.

[0138] [Example 2]

[0139] use Figure 1 , Figure 5 , Figure 6 and Figure 7 The second embodiment is described. The configuration of the storage system of the second embodiment is also the same as that of the storage system of the first embodiment. Figure 1 Indicated in. Figure 1 The description of is the same as that of the first embodiment, so it is omitted. However, in the second embodiment, it is assumed that the processors 104a and 104c consume more power than the processors 104b and 104d, and the processors 104b and 104d consume sufficiently less power than the processors 104a and 104c (for example, less than 1 / 10). For example, the processors 104a and 104c with greater power consumption can show higher processing capabilities than the processors 104b and 104d with less power consumption.

[0140] The storage system of the second embodiment has a plurality of operation modes including a first operation mode and a second operation mode. In the first operation mode and the second operation mode, a part of the power supply area is in an operating state, and a part of the power supply area is in a stopped state. In the first operation mode and the second operation mode, the power supply area in the operating state is different.

[0141] In the first embodiment, all power supply areas 120a, 120b, 121a to 121d, 122a, and 122b are first set to the power supply operating state. On the other hand, in the second embodiment, only the power supply areas 120a and 120b, the power supply area 121a including the processor 104a and the memory 105a, the power supply area 121c including the processor 104c and the memory 105c, and the power supply areas 122a and 122b are first set to the power supply operating state. The power supply area 121b including the processor 104b and the memory 105b, and the power supply area 121d including the processor 104d and the memory 105d are set to the power supply stopping state. This is the first operation mode.

[0142] Then, according to the frequency of input / output requests from the host, power area 121a and power area 121c are in power-off state, and power area 121b and power area 121d are in power-on state. This is the second operation mode. Thus, power consumption can be reduced. The power control of this embodiment is described. Figure 5 A flowchart showing an example of power supply control.

[0143] 501: When the storage system 1 is started, the power supply areas 120a, 120b, 121a, 121c, 122a, and 122b are in operation, and the power supply areas 121b and 121d are in operation.

[0144] 502: Then, the storage system 1 observes the frequency of input / output requests from the host device.

[0145] 503 : When the condition that the frequency is equal to or less than a predetermined value (threshold) in a predetermined period is not satisfied ( 503 : No), the flow returns to step 502 .

[0146] 504: When the frequency is below a predetermined value during a predetermined period, the storage system 1 decides to switch the operating power domain from power domain 121a and 121c to power domain 121b and 121d. In other words, it decides to switch the processing from processors 104a and 104c to processors 104b and 104d.

[0147] 505: The power control units 131b and 131d activate the power supply of the power supply areas 121b and 121d. This activates the processing of the processors 104b and 104d.

[0148] 506: Processor 104a hands over its processing to processor 104b, and processor 104c hands over its processing to processor 104d.

[0149] 507: The power control units 131a and 131c stop the power supply to the power supply areas 121a and 121c, thereby stopping the processing of the processors 104a and 104c.

[0150] 508: The storage system 1 observes the frequency of input / output requests from the host device.

[0151] 509: When the frequency does not satisfy the condition of being above the predetermined value (threshold) within the predetermined period (509: No), the process returns to step 508. The predetermined period of this step may be the same as or different from the predetermined period of step 503. There is no particular predetermined size between the predetermined value of this step and the predetermined value of step 503. However, if the predetermined value of step 503 is larger than the predetermined value of this step, even if the condition of step 503 is satisfied (503: Yes), steps 504 to 507 are executed, and power supply areas 121b and 121d operate. Even if the power supply of power supply areas 121a and 121c is stopped, in this step 509, the frequency of input / output requests from the host device is larger than the predetermined value of this step, and the process may not return to step 508 but immediately move to the next step 510. Therefore, the predetermined value of step 503 is preferably smaller than the predetermined value of this step 509.

[0152] 510: When the frequency is equal to or higher than the predetermined value during the predetermined period (509: Yes), the power control units 131a and 131c operate the power supply of the power supply areas 121a and 121c. As a result, the processing of the processors 104a and 104c is resumed.

[0153] 511: Processor 104b hands over its processing to processor 104a, and processor 104d hands over its processing to processor 104c.

[0154] 512: The power control units 131b and 131d stop the power supply to the power supply areas 121b and 121d, thereby stopping the processing of the processors 104b and 104d.

[0155] The observation of the frequency of the input / output request from the host device in steps 502 and 508 may be performed by the processors 104a to 104d that are currently operating, or by a separate dedicated processor for observation. As a method of observation, similar to the first embodiment, for example, a function such as a timer for measuring time may be given to the processors 104a to 104d or the dedicated processor for observation, and the frequency of the input / output request from the host device may be counted within a certain period of time using the time measuring function.

[0156] In addition, as in the first embodiment, in addition to observing the frequency of the input / output request from the host device, the object to be observed may be replaced by another value related to the frequency of the input / output request from the host device. For example, as in the first embodiment, as for the processors 104a to 104d that are working, a processor operating rate or the like may be defined separately to replace it. In the following description, when the frequency of the input / output request from the host device is replaced by the processor operating rate or the like that is defined separately, the frequency of the input / output request from the host device is referred to as the processor operating rate or the like that is defined separately.

[0157] The decision of step 504 to switch from power areas 121a and 121c to power areas 121b and 121d can be made by having one or both of the working processors 104a or 104c communicate and exchange or count the observed results of the frequency of input and output requests from each host device, or by setting up a dedicated processor for decision processing and counting the observed results of the frequency of input and output requests from the host device.

[0158] When the processors 104a to 104d communicate the observation results of the frequency of the input / output request from the host device with each other, or when a dedicated processor for the decision processing is separately provided, the communication can be performed via the communication mechanism of the front-end switch 102a or 102b or the back-end switch 106a or 106b, or a dedicated communication signal line can be separately provided. Alternatively, when a dedicated processor for observing the frequency of the input / output request from the host device is separately provided, the decision processing can also be performed together by the processor.

[0159] Next, an example of processing of a write request from the host device will be described. Figure 6 A sequence diagram showing an example of write request processing.

[0160] 601: The protocol chip 101a sends a write request received from the host device to the memory 105a of the processor 104a.

[0161] 602: The processor 104a retrieves the write request and write data from the host device from the memory 105a.

[0162] 603: The processor 104a sends the write data to the memory 105c of the processor 104c for duplication.

[0163] 604: The processor 104a sends a notification instruction of completion of the write request to the host device to the protocol chip 101a. Upon receiving the notification instruction of completion of the write request to the host device, the protocol chip 101a notifies the host device of the completion of the write request.

[0164] 605: The processor 104a sends a write command to the storage device 107a.

[0165] 606: The storage device 107a sends a request to write data to the processor 104a.

[0166] 607: The processor 104a fetches the write data from the memory 105a. This fetching may be performed by providing a function in a part of the hardware circuit of the processor 104a to automatically fetch the write data from the memory 105a in accordance with the write data request from the storage device 107a, or by software executed by the processor 104a.

[0167] 608: The processor 104a returns the write data to the storage device 107a. This return can also be performed by providing a function in a part of the hardware circuit of the processor 104a to automatically return the write data retrieved from the memory 105a in accordance with the write data request from the storage device 107a, or by software executed by the processor 104a.

[0168] 609: The storage device 107a receives the write data and notifies the processor 104a that the saving is completed.

[0169] 610-613: Steps 610-613 are the same as steps 601-604.

[0170] 614: A certain processor that is operating decides to switch the processing from the processor 104a and the memory 105a to the processor 104b and the memory 105b. In other words, it decides to switch the operating power supply area from the power supply area 121a to the power supply area 121b.

[0171] 615: A certain processor that is operating decides to switch the processing from the processor 104c and the memory 105c to the processor 104d and the memory 105d. In other words, it decides to switch the operating power supply area from the power supply area 121c to the power supply area 121d.

[0172] 616: The processor 104b and the memory 105b are activated. That is, the power supply control unit 131b activates the power supply of the power supply area 121b.

[0173] 617: The processor 104d and the memory 105d are activated. That is, the power supply control unit 131d activates the power supply of the power supply area 121d.

[0174] 618: In order to hand over the write data, the processor 104a retrieves the write data from the memory 105a.

[0175] 619: In order to hand over the write data, the processor 104a sends the write data to the memory 105b of the processor 104b.

[0176] 620: In order to hand over the write data, the processor 104c retrieves the write data from the memory 105c.

[0177] 621: In order to hand over the write data, the processor 104c sends the write data to the memory 105d of the processor 104d.

[0178] 622: The processor 104a and the memory 105a are stopped. That is, the power supply control unit 131a stops the power supply of the power supply area 121a.

[0179] 623: The processor 104c and the memory 105c are stopped. That is, the power control unit 131c stops the power supply of the power supply area 121c.

[0180] 624: The processor 104b confirms the write data on the memory 105b handed over from the processor 104a, that is, confirms the write request from the host.

[0181] 625 to 629: Steps 625 to 629 are described below with the processor 104a in steps 605 to 609 replaced by the processor 104b and the memory 105a replaced by the memory 105b.

[0182] 630 to 638: Steps 630 to 638 are described by replacing the processor 104a in steps 601 to 609 with the processor 104b, the processor 104c with the processor 104d, the memory 105a with the memory 105b, and the memory 105c with the memory 105d.

[0183] As described above, regarding a write request (data save request) from the host device, when the power supply of the power area 121a and the power area 121c is working, the processor 104a of the controller 110a can receive the write request and process it. When switching from the power area 121a and 121c to the power area 121b and 121d, that is, when the processing is switched from the processors 104a and 104c to the processors 104b and 104d, the processor 104a can hand over the write request received from the host to the processor 104b.

[0184] Furthermore, a copy of the write data from the host device, which is sent from the memory 105a of the processor 104a to the memory 105c of the processor 104c of the controller 110b and stored therein, can also be transferred from the memory 105c of the processor 104c to the memory 105d of the processor 104d. Thus, even if some kind of failure occurs in the processor 104b or the memory 105b to which the write data from the host device is transferred by the controller 110a, the write data from the host device can be prevented from being lost.

[0185] Next, an example of processing of a read request from the host device will be described. Figure 7 A sequence diagram showing an example of read request processing.

[0186] 701: The protocol chip 101a sends a read request received from the host device to the memory 105a of the processor 104a.

[0187] 702: The processor 104a fetches the read request from the host device from the memory 105a.

[0188] 703: The processor 104a sends a read command to the storage device 107a.

[0189] 704: The storage device 107a returns the read data to the processor 104a.

[0190] 705: The processor 104a saves the read data from the storage device 107a to the memory 105a. The read data can be saved by providing a function in a part of the hardware circuit of the processor 104a to automatically save the read data in the memory 105a in accordance with the read data returned from the storage device 107a, or by software executed by the processor 104a.

[0191] 706: The processor 104a retrieves the read data from the memory 105a.

[0192] 707: Processor 104a sends a read response transmission instruction including read data to the host device and the read data to protocol chip 101a. Upon receiving the read response transmission instruction including read data to the host device and the read data, protocol chip 101a sends a read response including the read data to the host device.

[0193] 708 : The protocol chip 101 a sends the read request received from the host to the memory 105 a of the processor 104 a . This step is the same as step 701 .

[0194] 709: A certain processor that is operating decides to switch the processing from processor 104a and memory 105a to processor 104b and memory 105b. In other words, it decides to switch the operating power supply area from power supply area 121a to power supply area 121b. This step is the same as step 614.

[0195] 710: A certain processor in operation switches the processing from the processor 104c and the memory 105c to the processor 104d and the memory 105d. That is, it is decided to switch the operating power supply area from the power supply area 121c to the power supply area 121d. This step is the same as step 615.

[0196] 711: The processor 104b and the memory 105b are activated. That is, the power control unit 131b activates the power supply of the power supply area 121b. This step is the same as step 616.

[0197] 712: The processor 104d and the memory 105d are activated. That is, the power control unit 131d activates the power supply of the power supply area 121d. This step is the same as step 617.

[0198] 713: The processor 104a fetches the read request from the host device from the memory 105a in order to hand over the read request.

[0199] 714: The processor 104a sends the read request from the host device to the memory 105b of the processor 104b for read request handover.

[0200] 715: The processor 104a and the memory 105a are stopped. That is, the power control unit 131a stops the power supply of the power supply area 121a. This step is the same as step 622.

[0201] 716: The processor 104c and the memory 105c are stopped. That is, the power control unit 131c stops the power supply of the power supply area 121c. This step is the same as step 623.

[0202] 717: The processor 104b retrieves the read request from the host device on the memory 105b handed over from the processor 104a.

[0203] 718 to 722: Steps 718 to 722 are described below with the processor 104a in steps 703 to 707 replaced by the processor 104b and the memory 105a replaced by the memory 105b.

[0204] 723 to 729: Steps 723 to 729 are described below with the processor 104a in steps 701 to 707 replaced by the processor 104b and the memory 105a replaced by the memory 105b.

[0205] As described above, regarding a read request from the host device, when the power supply of the power area 121a and the power area 121c is working, the processor 104a of the controller 110a can receive and process the read request. When the power area 121a and 121c is switched to the power area 121b and 121d, that is, when the processing is switched from the processors 104a and 104c to the processors 104b and 104d, the processor 104a can hand over the read request received from the host to the processor 104b.

[0206] In addition, the present invention is not limited to the above-mentioned embodiments, but includes various modified examples. For example, the above-mentioned embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and are not limited to necessarily having all the described structures. In addition, a part of the structure of a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the structure of a certain embodiment. In addition, with respect to a part of the structure of each embodiment, other structures can be added / deleted / replaced.

[0207] In addition, the above-mentioned components / functions / processing units, etc. can also be implemented by hardware by designing a part or all of them, for example, using integrated circuits. In addition, the above-mentioned components, functions, etc. can also be implemented by software by interpreting and executing programs that implement each function through a processor. Information such as programs, tables, files, etc. that implement each function can be placed in a recording device such as a memory, a hard disk, an SSD (Solid State Drive), or a recording medium such as an IC card or an SD card.

[0208] Furthermore, the control lines and information lines are shown as necessary for explanation, and do not necessarily show all the control lines and information lines on the product. In fact, it can be considered that almost all components are connected to each other.

Claims

1. A storage system for storing or outputting data in response to a data input / output request from a host device, characterized in that: Includes multiple controllers; Each of the above-mentioned multiple controllers includes: Multiple first power supply areas can independently control power supply; a processor, disposed in each of the first power supply areas, for processing the input / output request; and A memory, provided in each of the first power supply areas and connected to the processor; Each of the above-mentioned multiple controllers is configured to be able to switch: A first operation mode is to set all the first power supply areas provided in the controller to an operating state; and In the second operation mode, a part of the first power supply area provided in the controller is set to a stopped state, and the other first power supply areas are set to an operating state.

2. The storage system according to claim 1, characterized in that: The plurality of controllers are configured to be detachable from the storage system; The plurality of first power supply areas included in each of the plurality of controllers are configured so as not to be detachable from the respective controllers.

3. The storage system according to claim 1, characterized in that: One of the plurality of first power supply areas of each of the plurality of controllers includes a protocol chip connected to the host device and controlling a protocol for communication with the host device; All of the processors of each of the plurality of controllers are configured to process a data input / output request received by the protocol chip from the host device.

4. The storage system according to claim 1, wherein: Also includes more than 1 storage device; One of the plurality of first power supply areas of each of the plurality of controllers includes a storage device connection portion that connects the processor of the plurality of first power supply areas to the storage device; The processor of each of the plurality of first power supply areas of each controller writes the data on the memory into the storage device via the storage device connecting portion, and reads the data from the storage device and stores the data in the memory.

5. The storage system according to claim 1, wherein: Each of the plurality of controllers performs: adopting the first operation mode when the frequency of the data input / output request from the host device is equal to or higher than a first threshold value; The second operation mode is adopted when the frequency of data input / output requests from the host device is equal to or lower than a second threshold value.

6. The storage system according to claim 1, wherein: The plurality of controllers include a first controller and a second controller; When the first controller and the second controller adopt the first operation mode, The first controller receives write data from the host device; The first memory of the first controller stores the write data; The first controller sends a copy of the write data to the second controller; The second memory of the second controller stores a copy of the write data; When the first controller and the second controller change from the first operation mode to the second operation mode, When the first memory is included in the first power region in which the power is set to a stopped state in the second operation mode, the first controller transfers the write data stored in the first memory to a third memory included in the first power region in which the power is set to an operating state in the second operation mode of the first controller; When the second memory is included in the power area in which the power is set to a stopped state in the second action mode, the second controller transfers a copy of the write data stored in the second memory to the fourth memory included in the first power area in which the power is set to a working state in the second action mode of the second controller.

7. The storage system according to claim 1, characterized in that: At least one of the plurality of controllers comprises: at least one second power supply area capable of performing power supply control independently of the first power supply area; and a protocol chip, disposed in the second power supply area, connected to the host device to control communication with the host device; The second power supply area is configured to be switchable between an operating state and a stop state; The second power supply area is configured such that when the protocol chip communicates with the host device, the operation state is entered, and when the protocol chip does not communicate with the host device, the stop state is entered.

8. A storage system for storing or outputting data in response to a data input / output request from a host device, characterized in that: Includes multiple controllers; A first controller among the plurality of controllers includes a plurality of power supply areas capable of performing power supply control respectively; A first power supply area among the plurality of power supply areas includes a first processor and a first memory connected to the first processor; A second power supply area among the plurality of power supply areas includes a second processor and a second memory connected to the second processor; The first processor consumes more power than the second processor; The second controller among the plurality of controllers includes a plurality of power supply areas capable of performing power supply control respectively; A third power supply area among the plurality of power supply areas of the second controller includes a third processor and a third memory connected to the third processor; A fourth power supply area among the plurality of power supply areas of the second controller includes a fourth processor and a fourth memory connected to the fourth processor; The third processor consumes more power than the fourth processor; The storage system has a first operation mode and a second operation mode; The first operation mode sets the power supply of the first power supply area to an operating state and sets the power supply of the second power supply area to a stopped state, and sets the power supply of the third power supply area to an operating state and sets the power supply of the fourth power supply area to a stopped state; The second operation mode sets the power supply of the first power supply area to a stopped state and sets the power supply of the second power supply area to an operating state, and sets the power supply of the third power supply area to a stopped state and sets the power supply of the fourth power supply area to an operating state.

9. The storage system according to claim 8, characterized in that: The first controller and the second controller are removable from the storage system; The first power supply area and the second power supply area of ​​the first controller are configured so as not to be detachable from the first controller; The third power supply area and the fourth power supply area of ​​the second controller are configured so as not to be detachable from the second controller.

10. The storage system according to claim 8, characterized in that: One of the plurality of power supply areas of each of the first controller and the second controller includes a protocol chip for controlling a protocol for communication with the host device; The first processor and the second processor are each configured to process a data input / output request from the host device received by the protocol chip of the first controller; The third processor and the fourth processor are each configured to process a data input / output request from the host device received by the protocol chip of the second controller.

11. The storage system according to claim 8, characterized in that: Also includes more than 1 storage device; One of the plurality of power supply areas of the first controller includes a first storage device connection portion connected to the storage device; One of the plurality of power supply areas of the second controller includes a second storage device connection portion connected to the storage device; The first processor writes the data on the first memory into the storage device via the first storage device connection unit, and reads the data from the storage device and stores it in the first memory; The second processor is configured to write the data on the second memory into the storage device via the first storage device connection unit, and read the data from the storage device and store it in the second memory; The third processor writes the data on the third memory into the storage device via the second storage device connection unit, and reads the data from the storage device and stores it in the third memory; The fourth processor writes the data on the fourth memory into the storage device via the second storage device connecting unit, and reads the data from the storage device and stores the data in the fourth memory.

12. The storage system according to claim 8, characterized in that: When the frequency of the data input / output request from the host device is equal to or higher than a first threshold, the first controller and the second controller adopt the first operation mode; When the frequency of the data input / output request from the host device is equal to or lower than a second threshold, the first controller and the second controller adopt the second operation mode.

13. The storage system according to claim 8, characterized in that: When the first controller and the second controller adopt the first operation mode, If the first controller receives write data from the host device, it stores the write data in the first memory; The first controller sends a copy of the write data to the second controller; The second controller stores a copy of the write data in the third memory; When the first controller and the second controller adopt the second operation mode, If the first controller receives write data from the host device, it stores the write data in the second memory; The first controller sends a copy of the write data to the second controller; The second controller stores a copy of the write data in the fourth memory; When the first controller and the second controller change from the first operation mode to the second operation mode, The first controller transfers the write data stored in the first memory to the second memory; The second controller transfers a copy of the write data stored in the third memory to the fourth memory.

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