Security system multi-algorithm core scheduling method, device and equipment and storage medium

Abstract

The invention discloses a security system multi-algorithm core scheduling method, device and equipment and a storage medium, and relates to the technical field of algorithm scheduling, the method comprises the following steps: packaging user data information and to-be-scheduled algorithm information to obtain a to-be-scheduled algorithm packet, and storing the to-be-scheduled algorithm packet into a waiting queue; establishing a stack polling counter, and polling full stack signal identifiers of all algorithm core preprocessing stacks according to a count value of the stack polling counter; and if the full stack signal identifier is invalid, distributing the to-be-scheduled algorithm packet to a corresponding algorithm core preprocessing stack for scheduling. According to the method, the to-be-scheduled algorithm packets are stored in the waiting queue according to a certain sequence, and scheduling is performed according to the indication of the stack polling counter, so that the system can dynamically allocate tasks according to the real-time load condition of the algorithm cores; and system resources can be utilized to the maximum extent through a dynamic resource allocation mechanism, and the utilization rate of the algorithm core is improved.

Description

Technical Field

[0001] The present application relates to the technical field of algorithm scheduling, and more specifically, to a method, device, equipment and storage medium for scheduling multiple algorithm cores in a security system. Background Art

[0002] In the field of information security, in addition to ensuring basic information security, the algorithm performance of the security system is also used to measure the core value of the entire security system. The algorithm performance of the security system is directly related to the user experience. Therefore, how to improve the algorithm performance of the security system is a very important issue in the field of information security.

[0003] In the early days, algorithms of security systems were implemented on processors using C language (commonly known as soft implementation). With the promotion of FPGA, algorithms implemented on FPGA using hardware description languages ​​VHDL / Verilog HDL (commonly known as hard implementation) have become very common and even indispensable. The performance of algorithms can be greatly improved by optimizing logic resources and increasing clock frequency. The performance of algorithms implemented with hard implementation is dozens or even hundreds of times higher than that of algorithms implemented with soft implementation, and the performance improvement is obvious.

[0004] However, with the explosive growth of data volume, the performance of single-core FPGA hard-implemented algorithms still cannot meet user needs. After all, the clock frequency cannot increase indefinitely, and as the clock frequency increases, the stability of the FPGA will inevitably decrease. When the signal change speed exceeds the response time of the circuit, logical errors may occur. Summary of the invention

[0005] In response to at least one defect or improvement need in the prior art, the present invention provides a multi-algorithm core scheduling method, device, equipment and storage medium for a security system, which are used to solve the problem in the prior art that as the clock frequency increases, the stability of the FPGA gradually decreases, and when the signal change speed exceeds the response time of the circuit, the security system may have logical errors.

[0006] To achieve the above object, according to a first aspect of the present invention, a multi-algorithm core scheduling method for a security system is provided, comprising:

[0007] Packing the user data information and the algorithm to be scheduled information to obtain an algorithm to be scheduled package, and storing the algorithm to be scheduled package in a waiting queue;

[0008] Establishing a stack polling counter, and polling full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter;

[0009] If the full stack signal flag is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling.

[0010] In a possible implementation, a stack polling counter is established, and full stack signal identifiers of all algorithm core preprocessing stacks are polled according to the count value of the stack polling counter, including:

[0011] Initialize the count value of the stack polling counter and label all algorithm core preprocessing stacks in sequence;

[0012] Polling in the order of the labels of the algorithm core preprocessing stack according to the initialized stack polling counter;

[0013] After all algorithm core preprocessing stacks are polled, if there are still algorithm packets to be scheduled in the waiting queue, the count value of the stack polling counter is initialized and polling is repeated.

[0014] In one possible implementation, if the full stack signal identifier is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling, and also includes: if the full stack signal identifier is valid, the count value of the stack polling counter is increased by one, and the next algorithm core preprocessing stack is polled according to the count value of the stack polling counter.

[0015] In a possible implementation, polling the full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter also includes: if there is no algorithm packet to be scheduled in the waiting queue, terminating the polling of the algorithm core preprocessing stack.

[0016] In a possible implementation, the algorithm core preprocessing stack includes a write end flag and a read end flag;

[0017] When a to-be-scheduled algorithm packet is distributed to the algorithm core preprocessing stack, the write end flag is incremented by one;

[0018] When the algorithm core preprocessing stack schedules an algorithm packet to be scheduled, the read end flag is reduced by one.

[0019] In a possible implementation, the algorithm core preprocessing stack can store at least two algorithm packages to be scheduled.

[0020] In a possible implementation, the maximum count value of the stack polling counter is not less than the number of algorithm core preprocessing stacks.

[0021] According to a second aspect of the present invention, there is also provided a multi-algorithm core scheduling device for a security system, comprising:

[0022] A packaging module, which is configured to package the user data information and the algorithm to be scheduled information to obtain an algorithm package to be scheduled, and store the algorithm package to be scheduled in a waiting queue;

[0023] A polling module is configured to establish a stack polling counter, and poll the full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter;

[0024] The distribution module is configured to distribute the algorithm package to be scheduled to the corresponding algorithm core preprocessing stack for scheduling if the full stack signal identifier is invalid.

[0025] According to the third aspect of the present invention, a security system multi-algorithm core scheduling device is also provided, which includes at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes any step of the above-mentioned security system multi-algorithm core scheduling method.

[0026] According to a fourth aspect of the present invention, there is also provided a storage medium storing a computer program executable by an access authentication device, wherein when the computer program runs on the access authentication device, the access authentication device executes any of the steps of the multi-algorithm core scheduling method for a security system described above.

[0027] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0028] The present invention provides a multi-algorithm core scheduling method for a security system. By packaging user data information and information of algorithms to be scheduled into an algorithm package to be scheduled and storing it in a waiting queue, the tasks to be scheduled can be managed in an orderly manner, thereby avoiding confusion and conflict between tasks. By polling the full stack signal identifiers of all algorithm core preprocessing stacks, dynamic monitoring and allocation of algorithm core resources can be realized, ensuring that the system can understand the load of each algorithm core in real time, thereby reasonably scheduling tasks and avoiding idle or overloaded resources. By checking the full stack signal identifier, the system can ensure that tasks are distributed only when the algorithm core preprocessing stack is not full, thereby avoiding task loss or system crash caused by stack overflow. The combined use of the stack polling counter and the full stack signal identifier enables the system to dynamically allocate tasks according to the real-time load of the algorithm core, and the dynamic resource allocation mechanism can maximize the use of system resources, improve the utilization rate of the algorithm core, and thus optimize the overall performance. With the expansion of the system scale or the increase in the number of algorithm cores, the system can easily expand and manage more algorithm core resources without major modifications to the original architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of a flow chart of an embodiment of a multi-algorithm core scheduling method for a security system provided by the present invention;

[0031] Figure 2 The present invention provides Figure 1 A schematic diagram of a flow chart of an embodiment of step S102;

[0032] Figure 3 A schematic diagram of the structure of an embodiment of a multi-algorithm core scheduling device for a security system provided by the present invention;

[0033] Figure 4 A schematic diagram of the structure of a multi-algorithm core scheduling device for a security system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0036] The present invention provides a method, device, equipment and storage medium for scheduling multiple algorithm cores in a security system, which are described below respectively.

[0037] See also Figure 1 , Figure 1 The present invention provides a flowchart of an embodiment of a method for scheduling multiple algorithm cores in a security system. In a specific embodiment of the present invention, a method for scheduling multiple algorithm cores in a security system is disclosed, including:

[0038] S101, packing user data information and information of the algorithm to be scheduled to obtain an algorithm package to be scheduled, and storing the algorithm package to be scheduled in a waiting queue;

[0039] S102, establishing a stack polling counter, and polling full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter;

[0040] S103: If the full stack signal flag is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling.

[0041] In the above embodiment, the original data information and the algorithm information to be scheduled are received from the user, and the algorithm information to be scheduled includes but is not limited to the information such as the key, algorithm mode and parameter category obtained locally. In order to ensure the integrity and accuracy of the information, the information can be preprocessed, including data verification, format conversion, etc. Then, the preprocessed user data information and the algorithm information to be scheduled are packaged according to specific rules to form a complete algorithm package to be scheduled. The algorithm package to be scheduled contains all the necessary information required to execute the algorithm, such as input data, algorithm parameters, etc. The algorithm package to be scheduled will be stored in a specially designed waiting queue. The waiting queue adopts the first-in-first-out principle to ensure that each algorithm package to be scheduled can be processed in the order received. At the same time, the waiting queue also has a capacity limit and overflow processing mechanism to prevent performance degradation due to excessive queue length.

[0042] First, a stack polling counter is established to record the index of the currently polled algorithm core preprocessing stack. According to the count value of the stack polling counter, the full stack signal flags of all algorithm core preprocessing stacks are polled in a certain order. The full stack signal flag is an important status flag used to indicate whether the stack is currently full and whether it can receive new algorithm packages to be scheduled. By checking this flag, the load of each algorithm core preprocessing stack can be understood in real time, so as to make reasonable scheduling decisions. It should be noted that the stack polling counter also has loop counting and reset functions to ensure that a new round of polling can be restarted after all algorithm core preprocessing stacks are polled.

[0043] According to the status of the full stack signal flag checked in step S102, it is decided whether to distribute the algorithm package to be scheduled to the corresponding algorithm core preprocessing stack for scheduling. If the full stack signal flag of a certain algorithm core preprocessing stack is invalid (i.e., the stack is not full), the algorithm package to be scheduled in the waiting queue will be distributed to the stack for scheduling. During the distribution process, it is ensured that each algorithm package to be scheduled is correctly allocated to the algorithm core preprocessing stack with sufficient processing power to maximize the overall processing efficiency. At the same time, it is also necessary to record relevant information of the distribution process, such as distribution time, target stack, etc., for subsequent performance analysis and optimization.

[0044] Compared with the prior art, the present embodiment provides a multi-algorithm core scheduling method for a security system. By packaging user data information and information of the algorithm to be scheduled into an algorithm package to be scheduled and storing it in a waiting queue, the tasks to be scheduled can be managed in an orderly manner, avoiding confusion and conflict between tasks. By polling the full stack signal identifier of all algorithm core preprocessing stacks, dynamic monitoring and allocation of algorithm core resources can be realized, ensuring that the system can understand the load of each algorithm core in real time, so as to reasonably schedule tasks and avoid idle or overloaded resources. By checking the full stack signal identifier, the system can ensure that tasks are distributed only when the algorithm core preprocessing stack is not full, avoiding task loss or system crash caused by stack overflow. The combined use of the stack polling counter and the full stack signal identifier enables the system to dynamically allocate tasks according to the real-time load of the algorithm core, and the dynamic resource allocation mechanism can maximize the use of system resources, improve the utilization of the algorithm core, and thus optimize the overall performance. With the expansion of the system scale or the increase in the number of algorithm cores, the system can easily expand and manage more algorithm core resources without major modifications to the original architecture.

[0045] See also Figure 2 , Figure 2 The present invention provides Figure 1 In some embodiments of the present invention, a stack polling counter is established, and the full stack signal identifiers of all algorithm core preprocessing stacks are polled according to the count value of the stack polling counter, including:

[0046] S201, initializing the count value of the stack polling counter, and sequentially labeling all algorithm core preprocessing stacks;

[0047] S202, polling the algorithm core preprocessing stack in the order of the labels according to the initialized stack polling counter;

[0048] S203: After all algorithm core preprocessing stacks are polled, if there are still algorithm packets to be scheduled in the waiting queue, the count value of the stack polling counter is initialized and polling is repeated.

[0049] In the above embodiment, in order to ensure the continuity and accuracy of the polling process, the initial value of the counter is usually set to 0 or a specific starting value (initialized to 0 in the specific embodiment of the present invention). At the same time, all algorithm core preprocessing stacks are numbered in sequence, and the number of the algorithm core preprocessing stack is used as a unique identifier of each stack during the polling process. It can be understood that the order of the numbers can be specifically designed according to the needs of the actual situation, for example, the algorithm core can be sorted according to performance, priority or other relevant factors.

[0050] According to the count value of the initialized stack polling counter, polling is performed in the order of the number of the algorithm core preprocessing stack. During the polling process, the full stack signal flag of each stack is checked to determine whether the stack is full. The full stack signal flag indicates whether the stack can currently receive a new algorithm package to be scheduled. If the full stack signal flag of a stack is invalid (i.e., the stack is not full, which is recorded as 0 in the present invention), the algorithm package to be scheduled is distributed to the stack for scheduling; if all stacks are full, the next algorithm core preprocessing stack is queried, and the polling is repeated to complete.

[0051] If the waiting queue is empty, it means that all algorithm packages to be scheduled have been successfully distributed and are being processed, and the polling process can end at this time. However, if there are still algorithm packages to be scheduled in the waiting queue, it means that there are still tasks to be scheduled. At this time, the count value of the stack polling counter is reinitialized and the polling process is repeated. When repeating the polling, check again according to the label order of the algorithm core preprocessing stack, and try to distribute the algorithm packages to be scheduled to the unfull stack. This process will continue until the waiting queue is empty, or until a certain condition set in advance according to actual needs (such as the number of polling limits, time limits, etc.) is reached.

[0052] In addition, in order to ensure the stability and reliability of the polling process, a boundary check can be performed each time the count value of the stack polling counter is updated to ensure that the count value does not exceed its valid range. If the count value is out of range, reset it to the starting value or take other appropriate measures. The status of the algorithm core preprocessing stack can also be monitored in real time, including the stack's full stack signal identification, the remaining capacity of the stack, etc. This information helps to make more accurate scheduling decisions and avoid task loss or crashes due to stack overflow. During the polling process, if any errors or abnormal conditions (such as stack corruption, communication failure, etc.) are encountered, take appropriate error handling measures immediately and try to restore the normal operation of the polling process. At the same time, record the error information for subsequent problem analysis and resolution.

[0053] In some embodiments of the present invention, if the full stack signal identifier is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling, and also includes: if the full stack signal identifier is valid, the count value of the stack polling counter is increased by one, and the next algorithm core preprocessing stack is polled according to the count value of the stack polling counter.

[0054] In the above embodiment, when the full stack signal flag of a certain algorithm core preprocessing stack is detected, different processing decisions will be made according to its status. If the full stack signal flag is invalid (i.e., the stack is not full), the algorithm package to be scheduled in the waiting queue will be immediately distributed to the stack for scheduling. If the full stack signal flag is valid (i.e., the stack is full), no new tasks will be distributed to the stack, but the count value of the stack polling counter will be increased by one, and then the next algorithm core preprocessing stack will be polled according to the new count value. This mechanism ensures that the algorithm core resources can be efficiently utilized, avoiding the distribution of tasks to a full stack, thereby reducing resource waste and possible conflicts.

[0055] In some embodiments of the present invention, polling the full stack signal identifier of all algorithm core preprocessing stacks according to the count value of the stack polling counter also includes: if there is no algorithm packet to be scheduled in the waiting queue, terminating the polling of the algorithm core preprocessing stack.

[0056] In the above embodiment, during the process of polling the algorithm core preprocessing stack, the status of the waiting queue is checked in real time. If there is no algorithm package to be scheduled in the waiting queue, it means that there is no new task that needs to be scheduled. At this time, the polling of the algorithm core preprocessing stack is terminated to save resources and reduce unnecessary operations. By dynamically adjusting the polling process, flexible scheduling can be performed according to the actual needs of the task, thereby improving the overall operating efficiency.

[0057] In some embodiments of the present invention, the algorithm core preprocessing stack includes a write end flag and a read end flag;

[0058] When a to-be-scheduled algorithm packet is distributed to the algorithm core preprocessing stack, the write end flag is incremented by one;

[0059] When the algorithm core preprocessing stack schedules an algorithm packet to be scheduled, the read end flag is reduced by one.

[0060] In the above embodiment, in order to more accurately manage the state of the algorithm core preprocessing stack, a write end flag and a read end flag are introduced, so that the number of tasks in the stack can be tracked in real time, thereby making more accurate scheduling decisions. The number of data packets cached in the current stack = the write end counter value - the read end counter value. It should be noted that if the write end and the read end occur at the same time in a cycle, this means that one data packet is written while another data packet is read, so the number of data packets cached in the current stack remains unchanged. In this case, the write end counter is increased by 1, the read end counter is decreased by 1, and the total of the counters remains unchanged.

[0061] In some embodiments of the present invention, the algorithm core preprocessing stack can store at least two algorithm packages to be scheduled.

[0062] In the above embodiment, in order to ensure stability and efficiency, the algorithm core preprocessing stack in the present invention is designed to store at least two algorithm packages to be scheduled. This design takes into account the actual situation of task scheduling. Even if a stack is occupied at a certain moment, there is still enough space to store new tasks, thereby avoiding task loss or performance degradation due to insufficient stack capacity.

[0063] In some embodiments of the present invention, the maximum count value of the stack polling counter is not less than the number of algorithm core preprocessing stacks.

[0064] In the above embodiment, in order to ensure that all algorithm core preprocessing stacks can be polled, the maximum count value of the stack polling counter is designed to be no less than the number of algorithm core preprocessing stacks. Even if multiple pollings are required to find available stacks, the counter can ensure that no stack will overflow or be missed, thereby ensuring the integrity and accuracy of the scheduling.

[0065] In order to better implement the multi-algorithm core scheduling method for a security system in an embodiment of the present invention, based on the multi-algorithm core scheduling method for a security system, correspondingly, please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of an embodiment of a multi-algorithm core scheduling device for a security system provided by the present invention. The embodiment of the present invention provides a multi-algorithm core scheduling device 300 for a security system, including:

[0066] A packaging module 310 is configured to package the user data information and the algorithm to be scheduled information to obtain an algorithm to be scheduled package, and store the algorithm to be scheduled package in a waiting queue;

[0067] A polling module 320 is configured to establish a stack polling counter, and poll the full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter;

[0068] The distribution module 330 is configured to distribute the algorithm package to be scheduled to the corresponding algorithm core preprocessing stack for scheduling if the full stack signal flag is invalid.

[0069] It should be noted here that: the device 300 provided in the above embodiment can implement the technical solutions described in the above method embodiments. The specific implementation principles of the above modules or units can refer to the corresponding contents in the above method embodiments, which will not be repeated here.

[0070] See also Figure 4 , Figure 4 The schematic diagram of the structure of the multi-algorithm core scheduling device for a security system provided by an embodiment of the present invention. Based on the above-mentioned multi-algorithm core scheduling method for a security system, the present invention also provides a multi-algorithm core scheduling device for a security system, which can be a computing device such as a mobile terminal, a desktop computer, a notebook, a PDA, and a server. The multi-algorithm core scheduling device 400 for a security system includes a processor 410, a memory 420, and a display 430. Figure 4 Only some components of the multi-algorithm core scheduling device for a safety system are shown, but it should be understood that it is not required to implement all of the shown components, and more or fewer components may be implemented instead.

[0071] In some embodiments, the memory 420 may be an internal storage unit of the security system multi-algorithm core scheduling device 400, such as a hard disk or memory of the security system multi-algorithm core scheduling device 400. In other embodiments, the memory 420 may also be an external storage device of the security system multi-algorithm core scheduling device 400, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the security system multi-algorithm core scheduling device 400. Further, the memory 420 may also include both an internal storage unit and an external storage device of the security system multi-algorithm core scheduling device 400. The memory 420 is used to store application software and various types of data installed in the security system multi-algorithm core scheduling device 400, such as the program code for installing the security system multi-algorithm core scheduling device 400. The memory 420 may also be used to temporarily store data that has been output or is to be output. In one embodiment, a security system multi-algorithm core scheduling program 440 is stored in the memory 420, and the security system multi-algorithm core scheduling program 440 can be executed by the processor 410, so as to implement the security system multi-algorithm core scheduling method of each embodiment of the present application.

[0072] In some embodiments, the processor 410 may be a central processing unit (CPU), a microprocessor or other data processing chip, used to run program codes or process data stored in the memory 420, such as executing a multi-algorithm core scheduling method for a security system.

[0073] In some embodiments, the display 430 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch device, etc. The display 430 is used to display information on the security system multi-algorithm core scheduling device 400 and to display a visual user interface. The components 410-430 of the security system multi-algorithm core scheduling device 400 communicate with each other via a system bus.

[0074] In one embodiment, when the processor 410 executes the safety system multi-algorithm core scheduling program 440 in the memory 420 , the steps in the above safety system multi-algorithm core scheduling method are implemented.

[0075] This embodiment further provides a computer-readable storage medium on which a safety system multi-algorithm core scheduling program is stored. When the safety system multi-algorithm core scheduling program is executed by a processor, the following steps are implemented:

[0076] Packing the user data information and the algorithm to be scheduled information to obtain an algorithm to be scheduled package, and storing the algorithm to be scheduled package in a waiting queue;

[0077] Establishing a stack polling counter, and polling full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter;

[0078] If the full stack signal flag is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling.

[0079] In summary, the present invention provides a multi-algorithm core scheduling method for a security system. By packaging user data information and information of the algorithm to be scheduled into an algorithm package to be scheduled and storing it in a waiting queue, the tasks to be scheduled can be managed in an orderly manner, avoiding confusion and conflict between tasks. By polling the full stack signal identifier of all algorithm core preprocessing stacks, dynamic monitoring and allocation of algorithm core resources can be achieved, ensuring that the system can understand the load of each algorithm core in real time, thereby reasonably scheduling tasks and avoiding idle or overloaded resources. By checking the full stack signal identifier, the system can ensure that tasks are distributed only when the algorithm core preprocessing stack is not full, avoiding task loss or system crash caused by stack overflow. The combined use of the stack polling counter and the full stack signal identifier enables the system to dynamically allocate tasks according to the real-time load of the algorithm core, and the dynamic resource allocation mechanism can maximize the use of system resources, improve the utilization of the algorithm core, and thus optimize the overall performance. With the expansion of the system scale or the increase in the number of algorithm cores, the system can easily expand and manage more algorithm core resources without major modifications to the original architecture.

[0080] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0081] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0082] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.

[0087] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0088] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

[0089] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-algorithm core scheduling method for a security system, characterized in that: include: Packing the user data information and the algorithm to be scheduled information to obtain an algorithm package to be scheduled, and storing the algorithm package to be scheduled in a waiting queue; Establishing a stack polling counter, and polling full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter; If the full stack signal identifier is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling.

2. The multi-algorithm core scheduling method for a security system according to claim 1, characterized in that: The step of establishing a stack polling counter and polling full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter comprises: Initialize the count value of the stack polling counter, and label all algorithm core preprocessing stacks in sequence; Polling in the order of the labels of the algorithm core preprocessing stack according to the initialized stack polling counter; After all algorithm core preprocessing stacks are polled, if there are still algorithm packets to be scheduled in the waiting queue, the count value of the stack polling counter is initialized and polling is repeated.

3. The multi-algorithm core scheduling method for a security system according to claim 1, characterized in that: If the full stack signal identifier is invalid, the algorithm package to be scheduled is distributed to the corresponding algorithm core preprocessing stack for scheduling, and also includes: if the full stack signal identifier is valid, the count value of the stack polling counter is increased by one, and the next algorithm core preprocessing stack is polled according to the count value of the stack polling counter.

4. The multi-algorithm core scheduling method for a security system according to claim 1, characterized in that: The method of polling the full stack signal identifier of all algorithm core preprocessing stacks according to the count value of the stack polling counter also includes: if there is no algorithm packet to be scheduled in the waiting queue, terminating the polling of the algorithm core preprocessing stack.

5. The multi-algorithm core scheduling method for a security system according to claim 1, characterized in that: The algorithm core preprocessing stack includes a write end flag and a read end flag; When a to-be-scheduled algorithm packet is distributed to the algorithm core preprocessing stack, the write end flag is incremented by one; When the algorithm core preprocessing stack schedules an algorithm packet to be scheduled, the read end flag is reduced by one.

6. The multi-algorithm core scheduling method for a security system according to any one of claims 1 to 5, characterized in that: The algorithm core preprocessing stack can store at least two of the algorithm packages to be scheduled.

7. The multi-algorithm core scheduling method for a security system according to any one of claims 1 to 5, characterized in that: The maximum count value of the stack polling counter is not less than the number of the algorithm core preprocessing stacks.

8. A multi-algorithm core scheduling device for a security system, characterized in that: include: A packaging module, configured to package the user data information and the algorithm to be scheduled information to obtain an algorithm package to be scheduled, and store the algorithm package to be scheduled in a waiting queue; A polling module is configured to establish a stack polling counter, and poll the full stack signal identifiers of all algorithm core preprocessing stacks according to the count value of the stack polling counter; The distribution module is configured to distribute the algorithm package to be scheduled to the corresponding algorithm core preprocessing stack for scheduling if the full stack signal identifier is invalid.

9. A multi-algorithm core scheduling device for a security system, characterized in that: It includes at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of the multi-algorithm core scheduling method for a security system as described in any one of claims 1 to 7.

10. A storage medium, characterized in that: It stores a computer program executable by an access authentication device. When the computer program runs on the access authentication device, the access authentication device executes the steps of the multi-algorithm core scheduling method for a security system according to any one of claims 1 to 7.

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