Memory expansion system, method and device

Abstract

The invention relates to a memory expansion system, method and device. The memory expansion system comprises a plurality of memory modules; the host module is used for accessing the memory module according to system operation requirements; the signal switching modules and the memory modules are arranged in a one-to-one correspondence manner, and the signal switching modules are used for establishing access links between the host module and the memory modules, so that the host module accesses the memory modules; the interconnection control module is connected with the host module and the signal switching module, and the interconnection control module is used for determining a current interconnection topology network between the host module and the signal switching module and a current bandwidth of the host module; and the memory module is used for monitoring the real-time required bandwidth of the host module in real time and gating the signal switching module connected with the host module based on the current bandwidth and the real-time required bandwidth so as to redistribute access to the host module. Compared with the prior art, the running memory distributed on each host module can be dynamically adjusted in real time.

Description

Technical Field

[0001] The present application relates to the technical field of server interconnection, and in particular to a memory expansion system, method and device. Background Art

[0002] With the rapid development of information technology, the demand for memory capacity and performance of computer systems continues to grow. In modern computing environments, the amount of data processing is increasing exponentially, and various complex applications, such as big data analysis, artificial intelligence, and high-performance computing, have increasingly higher requirements for memory. In particular, the number of cores of processors has continued to increase in recent years. For example, processors with ARM (Advanced RISC Machine) architecture have up to 256 cores. The memory capacity and bandwidth of each core are limited by the traditional local DDR (Double Data Rate) bus memory, which has severely limited the performance of the processor. The number of CPU (Central Processing Unit) cores has grown faster than the memory bandwidth and capacity. The memory bandwidth and capacity of each core have become bottlenecks, prompting applications to demand memory expansion (elasticity).

[0003] At present, due to the low memory utilization in data centers, memory resources are idle. It is usually necessary to decouple memory resources through memory pooling technology to improve the utilization rate of memory resources in data centers. However, the traditional method of adding memory sticks or using memory expansion cards to expand memory is limited by the specific structure of the motherboard and interface, with poor flexibility and low expansion efficiency, which cannot meet the growing demand. Summary of the invention

[0004] Based on this, it is necessary to provide a memory expansion system, method, device, equipment and storage medium with high flexibility and high expansion efficiency to address the above technical problems.

[0005] In a first aspect, the present invention provides a memory expansion system, the system comprising:

[0006] Multiple memory modules;

[0007] A host module, used to access the memory module according to system operation requirements;

[0008] A signal exchange module, wherein the signal exchange module is arranged in a one-to-one correspondence with the memory module, and the signal exchange module is used to establish an access link between the host module and the memory module so that the host module accesses the memory module;

[0009] An interconnection control module is connected to both the host module and the signal exchange module, and is used to determine the current interconnection topology network between the host module and the signal exchange module and the current bandwidth of the host module; and is used to monitor the real-time required bandwidth of the host module in real time, and select the signal exchange module connected to the host module based on the current bandwidth and the real-time required bandwidth to reallocate the memory module accessed by the host module.

[0010] In one embodiment, the host module includes:

[0011] Multiple processors, used to access different memory modules according to system operation requirements during system operation; the multiple processors communicate with each other via a high-speed interconnect bus;

[0012] A plurality of connection ports, used to connect the processor and the signal exchange module; the processor is connected to at least one connection port;

[0013] The first interconnection control terminal is connected to the interconnection control module and is used to realize data transmission between the processor and the interconnection control module.

[0014] In one of the embodiments, the signal exchange module has a plurality of selectively selected signal upstream ports, a signal downstream port connected to the memory module, and a second interconnection control end connected to the interconnection control module. Each signal upstream port of the signal exchange module is connected to any connection port of a different host module through an interface module. When the signal upstream port of the signal exchange module is selected, the access link is established between the host module connected to the signal upstream port and the corresponding memory module, so that the host module accesses the corresponding memory module.

[0015] The processor is also used to respond to the access request of the interconnection control module and encapsulate the Ethernet data packet based on the current network topology information; the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module and the current bandwidth of the host module;

[0016] In one embodiment, the interconnection control module includes:

[0017] A data parsing unit, configured to parse the received Ethernet data packet to obtain the current network topology information, and determine the current connection state between the connection port and the signal uplink port and the current bandwidth when the processor of the host module accesses the memory module according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module;

[0018] A data monitoring unit, used to monitor the operating status of the processor of the host module in real time and obtain the real-time required bandwidth of the host module;

[0019] A memory allocation unit, configured to determine a bandwidth difference of the processor according to the real-time required bandwidth and the current bandwidth, increase or decrease the allocated memory module for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory module as a mobile memory module;

[0020] A strobe control unit is used to select a signal upstream port of a signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

[0021] In one embodiment, it also includes:

[0022] A protocol switching module is used to enable the host module to access the memory module; the protocol switching module has a switching upstream port and a switching downstream port, the switching upstream port is connected to the signal downstream port in a one-to-one correspondence, the switching downstream port is connected to the memory module in a one-to-one correspondence, and the convergence ratio of the switching upstream port to the switching downstream port is 1:1.

[0023] In a second aspect, the present invention provides a memory expansion method, which is applied to an interconnection control module, wherein the interconnection control module is respectively connected to at least one host module and a plurality of signal exchange modules, and the plurality of signal exchange modules are connected to a plurality of memory modules in a one-to-one correspondence; the method comprises:

[0024] Obtaining an Ethernet data packet of the host module;

[0025] Determine the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine the current signal exchange module that exchanges signals with the host module at the current moment based on the current network topology information;

[0026] Monitor the real-time bandwidth requirement of the host module in real time;

[0027] A signal exchange module connected to the host module is selected based on the current bandwidth of the host module and the real-time required bandwidth to reallocate the memory module to be accessed by the host module.

[0028] In one of the embodiments, the Ethernet data packet is encapsulated based on the current network topology information of the host module, and the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module;

[0029] The obtaining of the Ethernet data packet of the host module comprises:

[0030] Access each host module of the memory expansion system through an IP address, and send a data acquisition request to the host module;

[0031] Receive and parse the Ethernet data packet sent by the host module, and obtain the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module.

[0032] In one embodiment, the host module has a plurality of connection ports, each of the signal exchange modules has a signal downstream port and a plurality of signal upstream ports, the signal downstream ports are connected to the memory modules one by one, and the plurality of signal upstream ports are respectively connected to any connection port of different host modules;

[0033] The method of determining the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determining the current signal exchange module that exchanges signals with the host module at the current moment based on the current network topology information, comprises:

[0034] Determine the current connection state between the connection port and the signal uplink port and the current bandwidth when the processor of the host module accesses the memory module according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module;

[0035] A current signal exchange module that currently exchanges signals with the host module is determined according to the current connection state and the current bandwidth.

[0036] In one embodiment, the selecting of the signal exchange module connected to the host module based on the current bandwidth of the host module and the real-time required bandwidth to reallocate the memory module accessed by the host module comprises:

[0037] Determine a bandwidth difference of a processor of the host module according to the real-time required bandwidth and the current bandwidth, increase or decrease an allocated memory module for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory module as a mobile memory module;

[0038] A signal upstream port of a signal exchange module connected to the mobile memory module is selectively enabled to increase or decrease the number of memory modules accessed by the host module.

[0039] In a third aspect, the present invention provides a memory expansion device, applied to an interconnection control module, wherein the interconnection control module is respectively connected to at least one host module and a plurality of signal exchange modules, and the plurality of signal exchange modules are connected to a plurality of memory modules in a one-to-one correspondence; the device comprises:

[0040] A data acquisition module, used to acquire the Ethernet data packet of the host module;

[0041] an information construction module, configured to determine current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine a current signal exchange module that is currently exchanging signals with the host module based on the current network topology information;

[0042] A monitoring module, used for monitoring the real-time bandwidth requirement of the host module in real time;

[0043] The memory expansion module is used to select the signal exchange module connected to the host module based on the current bandwidth of the host module and the real-time required bandwidth, so as to reallocate the memory module accessed by the host module.

[0044] In a fourth aspect, the present invention provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the method described above when executing the computer program.

[0045] In a fifth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the method described above when executed by a processor.

[0046] The above-mentioned memory expansion system, method and device obtain the Ethernet data packet of the host module through the interconnection control module, determine the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine the current signal exchange module that is exchanging signals with the host module at the current moment based on the current network topology information, so as to determine the operating status of the host module at the current moment; then, by real-time monitoring the real-time required bandwidth of the host module, the signal exchange module connected to the host module is selected based on the current bandwidth and the real-time required bandwidth to reallocate the memory module accessed by the host module; in this way, the operating memory allocated to each host module can be adjusted in real time and dynamically during the operation of the host module, which is conducive to realizing the expansion of memory bandwidth and capacity and meeting the needs of memory elastic expansion. At the same time, it can also solve the problem of low memory utilization in some cases, realize memory pooling to decouple memory resources, improve the utilization rate of memory resources in the data center, and reduce the cost of the entire data center. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 is a structural block diagram of a memory expansion system in one embodiment;

[0049] Figure 2 is a structural block diagram of a host module in one embodiment;

[0050] Figure 3 is a structural block diagram of interconnected control modules in one embodiment;

[0051] Figure 4 A schematic diagram of a flow chart of a memory expansion method in one embodiment;

[0052] Figure 5 It is a structural block diagram of a memory expansion system based on CXL bus technology in an application example;

[0053] Figure 6 It is a structural block diagram of a memory expansion system based on CXL bus technology in Example 1 of an application example;

[0054] Figure 7 It is a structural block diagram of a memory expansion system based on CXL bus technology in Example 2 of an application example;

[0055] Figure 8 is a structural block diagram of a memory expansion device in one embodiment;

[0056] Fig. 9 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment.

[0057] Description of reference numerals:

[0058] 101 - memory module, 102 - host module, 103 - signal exchange module, 104 - interconnection control module, interface module 105, protocol exchange module 105;

[0059] 201-processor, 202-connection port;

[0060] 301 - data parsing unit, 302 - data monitoring unit, 303 - memory allocation unit, 304 - selection control unit. DETAILED DESCRIPTION

[0061] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0063] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

[0064] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0065] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0066] As described in the background technology, in the prior art, memory expansion is achieved by adding memory sticks, which requires designing more memory slots on the motherboard to install more memory sticks. In addition, memory expansion is achieved by using a memory expansion card, which requires connecting to the motherboard through a specific interface and installing memory sticks on the memory expansion card, thereby increasing the memory capacity by using the internal space of the server. Both of the above methods are limited by the specific structure of the server and the motherboard and the support of the memory controller, and the capacity and bandwidth expansion are limited. At the same time, the bandwidth between the host node and the memory expansion node is fixed. If the bandwidth needs to be changed, the power supply between the host node and the memory expansion node needs to be cut off, which makes it impossible to achieve uninterrupted business and flexibility. In addition, when the application software (such as databases, supercomputers, etc.) needs to allocate an increased number of memory units to the host node, there is a bandwidth bottleneck, and the performance advantage of the extended memory cannot be brought into play.

[0067] Based on the above reasons, the present invention provides a memory expansion solution that can adjust the bandwidth of each host in real time according to the actual system performance requirements without interrupting the system, so as to achieve flexible access and use of the memory on the downstream memory module by the processor on the upstream host module.

[0068] In one embodiment, Figure 1 As shown, a memory expansion system is provided, including a plurality of memory modules 101 , a host module 102 , a signal exchange module 103 and an interconnection control module 104 .

[0069] The memory module 101 is used to provide bandwidth (or running memory) for the operation of the host module 102 to ensure that the host module 102 can operate stably. The host module 102 is used to access the memory on the memory module 101 according to the system operation requirements to run the application. The signal exchange module 103 is used to form an access link between the host module 102 and the memory module 101, so that the host module 102 can access and use the memory on the memory module 101 when running the application software. The interconnection control module 104 is used to determine the current interconnection topology network between the host module 102 and the signal exchange module 103 and the current bandwidth of the host module 102; and to monitor the real-time required bandwidth of the host module 102 in real time, and select the signal exchange module 103 connected to the host module 102 based on the current bandwidth and the real-time required bandwidth to reallocate the memory module 101 accessed by the host module 102; that is, by analyzing the current interconnection topology network, the current bandwidth and the real-time bandwidth requirement, when the host module 102 needs more bandwidth (or memory) or less bandwidth, the selection of the signal exchange module 103 is controlled, so that the host module 102 can access and use more or less memory modules 101 according to the operating requirements of the system to optimize resource allocation.

[0070] Among them, the signal exchange module 103 is arranged corresponding to the memory module 101, that is, a plurality of signal exchange modules 103 are arranged, and usually, the signal exchange module 103 is arranged one by one with the memory module 101, and the host module 102 can be arranged with one or more, so that a host module 102 can access and use the memory on one or more memory modules 101 through the access link formed by one or more signal exchange modules 103, so as to flexibly adjust the bandwidth of the host module 102 according to the demand, so as to achieve the purpose of changing the bandwidth of the host module 102, solve the problem of fixed bandwidth bottleneck, give full play to the performance advantage of extended memory, realize link redundancy between different host modules 102 to the memory module 101, and improve the high availability of the system.

[0071] The interconnection control module 104 is connected to the host module 102 to obtain the current bandwidth of the host module 102 and the connection and operation status between the host module 102 and the signal exchange module 103, so as to build the current interconnection topology network. The interconnection control module 104 is also connected to the signal exchange module 103 to send a control instruction or signal to the signal exchange module 103 when the bandwidth of the host module 102 needs to be adjusted, so as to turn on or off the signal exchange module 103, so as to enable the host module 102 to access the memory module 101 as needed.

[0072] The access link refers to a signal transmission channel formed when the host module 102 accesses the memory module 101 .

[0073] The current interconnection topology network refers to the connection relationship for communication between the host module 102 and the signal exchange module 103 at the current moment. The current bandwidth refers to the bandwidth or memory occupied by the host module 102 when running the application at the current moment.

[0074] Exemplarily, a plurality of host modules 102 , four signal exchange modules 103 , and four memory modules 101 are arranged.

[0075] If at a certain moment, a certain host module 102 is connected to the first and third memory modules 101 respectively through the first and third signal exchange modules 103, so as to access and use the two downstream memory modules 101 through the two signal exchange modules 103, the interconnection control module 104 determines which two signal exchange modules 103 and their corresponding memory modules 101 the host module 102 is currently connected to by obtaining the number of accesses and access status of the host module 102 to the memory module 101, so as to construct the current interconnection topology network and determine the current bandwidth of the host module 102 according to the two memory modules 101. That is, the first and third memory modules 101 provide memory for the operation of the host module 102, and the interconnection control module 104 determines that the first and third signal exchange modules 103 and the first and third memory modules 101 are connected to the host module 102 through the relevant information sent to the host module 102, so as to construct the current interconnection topology network, and determine that the current bandwidth is the sum of the bandwidths provided by the first and third memory modules 101.

[0076] If at the next moment, the interconnection control module 104 monitors that the application running on the host module 102 needs more bandwidth or running memory (i.e., determines the real-time required bandwidth), then based on the current interconnection topology network, it determines the memory module 101 (such as the fourth memory module 101) that can be allocated to the host module 102 for use, and sends the instruction to the fourth signal exchange module 103 to control the fourth signal exchange module 103 to be connected so that the fourth memory module 101 can provide memory for the host module 102; conversely, when the interconnection control module 104 monitors that the application running on the host module 102 needs less memory or bandwidth, it can also control the corresponding signal exchange module 103 to be disconnected based on the current interconnection topology network to free up more memory modules 101 for use by other host modules 102, thereby achieving the purpose of dynamically adjusting the bandwidth of the host module 102.

[0077] It is understandable that the data of the host module 102, signal exchange module 103 and memory module 101 recorded above is merely an example and is not intended to be a limitation of this embodiment; in specific implementation, the number of each module can be set according to actual needs to achieve the purpose of memory expansion.

[0078] In the above-mentioned memory expansion system, the interconnection control module 104 monitors the operation status of the host module 102, so as to determine the bandwidth demand of the host module 102 in real time. Combined with the constructed current interconnection topology network control, the corresponding signal exchange module 103 is enabled. The bandwidth between each host module 102 can be flexibly configured according to actual needs, which is conducive to meeting the needs of elastic memory expansion. In addition, the entire process does not require power outages to interrupt business, thereby ensuring the continuity of the business process.

[0079] In one embodiment, Figure 2 As shown, the host module 102 includes multiple processors 201, multiple connection ports 204 and a first interconnection control terminal. The processor 201 is used to access different memory modules 101 according to the system operation requirements during the system operation process to ensure that the application program running on the corresponding processor 201 runs normally and stably. The connection port 202 is used to connect the processor 201 with the signal exchange module 103 to ensure that the processor 201 can access and use the memory on the memory module 101. The first interconnection control terminal is used to realize data transmission between the processor 201 and the interconnection control module 104.

[0080] The connection port 202 is connected to the signal exchange module 103 through the interface module 105 to establish a connection between the processor 201 and the signal exchange module 103 , and further establish an access link between the processor 201 and the memory module 101 .

[0081] The uplink signal of the interface module 105 is connected to the connection port 202 of the host module 102 , and the downlink signal is connected to the signal exchange module 103 , so as to establish a connection between the host module 102 and the signal exchange module 103 .

[0082] Among them, multiple processors 201 communicate and expand through a high-speed interconnect bus, and the processor 201 is connected to at least one connection port 202. In specific implementation, the processor 201 can be connected to one or more connection ports 202 according to actual operation requirements to lead the signal of the processor 201 to the signal exchange module 103, so that the processor 201 accesses one or multiple memory modules 101 in parallel. The processor 201 is also used to respond to the access request of the interconnection control module 104 and encapsulate the Ethernet data packet based on the current network topology information.

[0083] Among them, Ethernet data packet refers to the transmission unit that divides the transmitted data into several small blocks for transmission in order to ensure that all computers sharing network resources can use the network fairly and quickly when transmitting data in a computer network.

[0084] The current network topology information refers to the identification information of each module corresponding to the network lock that constructs the current interconnection topology to determine the connection and correspondence between the modules. The current network topology information includes the host ID of the host module 102, the processor ID of the host module 102, the port ID of the host module 102, the interface ID of the interface module 105, and the current bandwidth of the host module 102.

[0085] Among them, the host ID is used to distinguish different host modules 102 in the entire system; the processor ID is used to identify the processor 201 inside the host module 102; the port ID is used to identify the connection port 202 to which the processor 201 is connected; the interface ID is used to identify the interconnection correspondence between the connection port 202 of the host module 102 and the physical cable between the signal exchange module 103; the current bandwidth is used to identify the interconnection information of the signal pair between the host module 102 and the interface module 105, and the signal pair can be 4 pairs, 8 pairs, 16 pairs, etc.

[0086] Among them, the first interconnection control terminal is connected to the interconnection control module 104 to realize data transmission between the interconnection control module 104 and the host module 102 (or the processor 201); usually, the data transmission between the interconnection control module 104 and the host module 102 is bidirectional transmission, including the interconnection control module 104 sending the access request to the host module 102 through the first interconnection control terminal and the host module 102 sending the operation data to the interconnection control module 104 through the first interconnection control terminal.

[0087] For example, Figure 1Taking the structure shown as an example, the host IDs of the host module 102 are recorded as Z1 to ZN in sequence, where Z1 represents the first host module 102 and ZN represents the Nth host module 102; the processor IDs of the processor 201 are recorded as C1.1 to CN.n in sequence, where C1.1 represents the first processor 201 of the first host module 102 and CN.n represents the nth processor 201 of the Nth host module 102; the port IDs are recorded as CXL1.1 to CXLN.n in sequence (when the processor 201 corresponds to the connection port 202 one by one), where CXL1.1 represents the first connection port 202 of the first host module 102 and CXLN.n represents the nth connection port 202 of the Nth host module 102; the interface IDs of the interface module 105 are recorded as J1 to JM in sequence, where J1 represents the first interface module 105 and JM represents the Mth interface module 105.

[0088] When the application is running on the first processor 201 (C1.1) of the first host module 102 (Z1), C1.1 is connected to the corresponding interface module 105 (J1) through the first connection port 202 (CXL1.1) connected thereto, and then accesses the corresponding memory module 101 after connecting through the signal exchange module 103 connected to J1, thereby realizing the access and use of the memory on the memory module 101; in this process, C1.1 can respond to the access request of the interconnection control module 104, and send the host ID (i.e., Z1) of the host module 102 to which C1.1 belongs to , the processor ID of C1.1 (i.e., C1.1), the port ID of the connection port 202 connected to C1.1 (i.e., CXL1.1), the interface ID of the interface module 105 connected to CXL1.1 (i.e., J1), and the current bandwidth of C1.1 are encapsulated into an Ethernet data packet and sent to the interconnection control module 104 via the first interconnection control terminal; at the same time, when the bandwidth demand of C1.1 changes, C1.1 can respond to the monitoring request of the interconnection control module 104 and send the real-time bandwidth demand to the interconnection control module 104 so that the interconnection control module 104 can perform data processing.

[0089] In this embodiment, by providing multiple processors 201 and multiple connection ports 202, multiple external connection ports can be provided for the host module 102, so as to dynamically adjust the connection between the connection port 202 and the interface module 105 during operation, thereby realizing dynamic adjustment of bandwidth.

[0090] In one embodiment, Figure 1As shown, the signal exchange module 103 has a plurality of selectively selected signal uplink ports, a signal downlink port, and a second interconnection control terminal. The signal uplink port is used to connect to the connection port 202 of the host module 102 via the interface module 105; the signal downlink port is used to connect to the corresponding storage module to form an access link between the host module 102 and the storage module. The second interconnection control terminal is used to transmit data with the interconnection control module 104.

[0091] Each signal uplink port is connected to any connection port 202 of different host modules 102 through the interface module 105. When the signal uplink port of the signal exchange module 103 is enabled, an access link is established between the host module 102 connected to the signal uplink port and the corresponding memory module 101, so that the host module 102 can access the corresponding memory module 101.

[0092] Among them, the second interconnection control end is connected to the interconnection control module 104 to realize data transmission between the interconnection control module 104 and the signal transmission module; usually, the data transmission between the interconnection control module 104 and the signal exchange module 103 is unidirectional, that is, the interconnection control module 104 sends the control instruction to the signal transmission module through the second interconnection control end to control the selection of the signal upstream port.

[0093] Exemplarily, taking the signal exchange module 103 having two signal upstream ports as an example, each signal upstream port is connected to a different connection port 202 of a different host module 102 through an interface module 105, and the interconnection control module 104 controls one of the two signal upstream ports to be enabled, so as to allow the processor 201 connected to the enabled signal upstream port to access the memory module 101, while the processor 201 connected to the unenabled signal upstream port cannot access the memory module 101, so as to achieve the purpose of memory allocation.

[0094] In this embodiment, multiple signal uplink ports are set on the signal exchange module 103, and each of the multiple signal uplink ports of the signal exchange module 103 can be selected one by one. By selecting the signal uplink port, the host module 102 connected to the signal exchange module 103 can be dynamically adjusted to achieve the purpose of dynamically adjusting the bandwidth of the host module 102 and optimizing the bandwidth configuration.

[0095] In one embodiment, Figure 3 As shown, the interconnection control module 104 includes a data parsing unit 301 , a data monitoring unit 302 , a memory allocation unit 303 and a gating control unit 305 .

[0096] The data parsing unit 301 is used to parse the received Ethernet data packet to obtain the current network topology information, and determine the current connection status between the connection port 202 and the signal uplink port and the current bandwidth when the processor 201 of the host module 102 accesses the memory module 101 according to the host ID of the host module 102, the processor ID of the host module 102, the port ID of the host module 102, and the interface ID of the interface module 105. The data monitoring unit 302 is used to monitor the running status of the processor 201 of the host module 102 in real time to obtain the real-time required bandwidth of the host module 102. The memory allocation unit 303 is used to determine the bandwidth difference of the processor 201 according to the real-time required bandwidth and the current bandwidth, increase or decrease the allocated memory module 101 for the host module 102 based on the bandwidth difference, and determine the increased or decreased allocated memory module 101 as the mobile memory module 101. The selection control unit 305 is used to select one of the signal uplink ports of the signal exchange module 103 connected to the mobile memory module 101 to increase or decrease the number of memory modules 101 accessed by the host module 102.

[0097] The current connection state refers to the connection relationship between the processor 201 of the host module 102 and the connection port 202, between the connection port 202 and the interface module 105, and the selection state between the interface module 105 and each signal upstream port at the current moment.

[0098] The real-time required bandwidth refers to the bandwidth required to ensure that the processor 201 executes the application after the application running on the processor 201 of the host module 102 changes. The bandwidth difference is the difference between the current bandwidth and the implementation required bandwidth, that is, the difference obtained by subtracting the current bandwidth from the implementation required bandwidth. The bandwidth difference can be positive or negative. When the bandwidth difference is positive, it means that the host module 102 needs more bandwidth at this time, so more memory modules 101 need to be allocated for use and access by the host module 102. On the contrary, when the bandwidth difference is negative, it means that there is a margin of running memory on the host module 102 at this time, which can be released for access by other host modules 102, so less memory needs to be allocated. In this way, the purpose of dynamic adjustment can be achieved.

[0099] The mobile memory module 101 refers to the memory module 101 that needs to be increased or decreased when the bandwidth requirement of the host module 102 changes.

[0100] Exemplarily, in the case where a host module 102 corresponds to multiple signal exchange modules 103 and multiple memory modules 101; taking a host module 102, four signal exchange modules 103, four memory modules 101, and each signal exchange module 103 having two signal uplink ports as an example, the two signal uplink ports of the first signal exchange module 103 are respectively recorded as the first uplink port (UP1.1) and the second uplink port (UP1.2), and the signal uplink ports of the second signal exchange module 103 are UP2.1 and UP2.2, and so on. The first to fourth connection ports CXL1.1~CXL1.4 of the processor 201 (C1.1) of the host module 102 (Z1) are connected to UP1.1, UP2.1, UP3.1 and UP4.1 through J1, J3, J5 and J7 respectively. At time T1, the first memory module 101 is allocated to the host module 102 for access, that is, UP1.1 is selected. At this time, the data parsing unit 301 can obtain the host ID, processor ID, port ID, and interface ID by parsing the Ethernet data packet to determine the topological relationship at time T1, and can determine the current bandwidth based on the accessed memory module 101 data. Subsequently, the data monitoring unit 302 continuously monitors the running status of the host module 102 (Z1). If at time T2, the application running on the host module 102 (Z1) needs to allocate more bandwidth, such as the bandwidth provided by two memory modules 101, that is, the real-time required bandwidth is the bandwidth that can be provided by the two memory modules 101; at this time, the memory allocation unit 303 will determine the bandwidth difference (that is, the bandwidth provided by one memory module 101), and determine the need to increase the bandwidth of a port based on the bandwidth difference, then find out the idle memory module 101, signal exchange module 103 and corresponding interface module 105 in the remaining three interface modules 105 (such as at this time to allocate the second memory module 101 to the host module 102), and the selection control unit 305 controls the UP2.1 on the second signal exchange module 103 connected to the host module 102 to be turned on, so that the first memory module 101 and the second memory module 101 provide running memory to the host module 102 in parallel.

[0101] In this embodiment, by setting the data parsing unit 301 to construct the interconnection topology network at the current moment, the connection relationship between the connection port 202 of the host module 102 and the interface module 105 can be determined, and based on this, it can be determined whether the host module 102 needs to allocate more connection ports 202 to access the memory in the current state or whether the connection port 202 needs to be reduced, thereby achieving link redundancy between different host nodes to the memory module 101 and improving the high availability of the system.

[0102] In one embodiment, Figure 1 As shown, the memory expansion system further includes a protocol switching module 106 .

[0103] Among them, the protocol switching module 106 is used to implement the host module 102 to access the memory module 101. The protocol switching module 106 has a switching uplink port and a switching downlink port. The switching uplink port is connected to the signal downlink port in a one-to-one correspondence, and the switching downlink port is connected to the memory module 101 in a one-to-one correspondence, ensuring that the processor 201 on the uplink host module 102 accesses and uses the memory on the downlink memory module 101. In this embodiment, the convergence ratio of the switching uplink port and the switching downlink port is 1:1, that is, the data is transmitted in a one-to-one manner during the data transmission process.

[0104] In this embodiment, by setting a protocol exchange unit between the signal exchange module 103 and the memory module 101, high-bandwidth, low-latency data transmission can be provided for both, achieving high-speed data transmission and resource sharing to improve access efficiency.

[0105] In one embodiment, Figure 4 As shown, a memory expansion method is provided, which is described by taking the method applied to the interconnection control module of the above embodiment as an example; in specific implementation, the interconnection control module can be implemented based on a controller, a server or other devices or equipment that can perform data processing and calculation.

[0106] The above memory expansion method includes the following steps S401 to S404. Among them:

[0107] Step S401, obtaining an Ethernet data packet of a host module.

[0108] The Ethernet data packet refers to a transmission unit in which the transmitted data is divided into several small pieces for transmission in order to ensure that all computers sharing network resources can use the network fairly and quickly when transmitting data in a computer network. Specifically, the Ethernet data packet of this embodiment specifically refers to a data packet encapsulated by the host module based on the current network topology information.

[0109] Exemplarily, when the host module responds to the acquisition request of the interconnection control module, it encapsulates the current network topology information into an Ethernet data packet and sends it to the interconnection control module, so that the interconnection control module can obtain the Ethernet data packet from the first interconnection control terminal of the host module.

[0110] Step S402: determining the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determining the current signal exchange module that is currently exchanging signals with the host module based on the current network topology information.

[0111] The current network topology information refers to the identification information of each module corresponding to the network lock that constructs the current interconnection topology to determine the connection and correspondence between the modules. The current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module.

[0112] The current signal exchange module refers to the signal exchange module that is connected to the host module and forms an access link between the host module and the memory module at the moment when the interconnection control module obtains the Ethernet data packet. For example, at time T1, the interconnection control module obtains the Ethernet data packet from the host module Z1. At this time, the connection port 202 (CXL1.1) of the host module Z1 is connected to the signal uplink port UP1.1 of a signal exchange module through the interface J1, then this signal exchange module is the current signal exchange module.

[0113] Exemplarily, after acquiring the Ethernet data packet, the interconnection control module can parse the Ethernet data packet and determine the current network topology information of the host module and the signal exchange module based on the parsed Ethernet data packet, that is, determine the connection relationship between the host module and the signal exchange module; then, the interconnection control module determines the current signal exchange module that is exchanging signals with the host module at the current moment based on the current network topology information, so as to further determine which memory modules provide running memory for which host modules at the current moment.

[0114] Step S403: monitor the real-time bandwidth requirement of the host module in real time.

[0115] The real-time required bandwidth refers to the bandwidth required to ensure that the processor executes the application program when the application program running on the processor of the host module changes.

[0116] Exemplarily, during the operation of the host module, the interconnection control module monitors the operation of the host module in real time to obtain the real-time bandwidth requirement of the host module. Specifically, during the operation of the host module, it can determine how much bandwidth it needs at a certain moment to ensure the normal and stable operation of these applications based on the applications running on it, and encapsulate the required bandwidth into an Ethernet data packet in the same way as the current network topology information and send it to the interconnection control module, so that the interconnection control module can monitor the real-time bandwidth requirement of the host module.

[0117] Step S404: Select the signal exchange module connected to the host module based on the current bandwidth and the real-time required bandwidth to reallocate the memory module to be accessed by the host module.

[0118] Among them, selecting the signal exchange module connected to the host module refers to selecting the signal exchange module connected to the host module according to the real-time demand of the host module to change the number of memory modules accessed by the host module to achieve the purpose of adjusting the bandwidth.

[0119] Exemplarily, the interconnection control module determines the number of memory modules required after the bandwidth changes based on the current bandwidth and the real-time required bandwidth, and determines which memory modules need to be added or reduced according to the required number of memory modules and the memory modules currently communicating with the host module. Based on this, the signal exchange module connected to the host module is enabled to reallocate the memory modules accessed by the host module.

[0120] The above-mentioned memory expansion method can determine the running status of the host module at the current moment by obtaining the Ethernet data packet of the host module, determining the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determining the current signal exchange module that is exchanging signals with the host module at the current moment based on the current network topology information; then, by real-time monitoring the real-time required bandwidth of the host module, the signal exchange module connected to the host module is selected based on the current bandwidth and the real-time required bandwidth to reallocate the memory module accessed by the host module; in this way, the running memory allocated to each host module can be adjusted in real time and dynamically during the operation of the host module, which is conducive to realizing the expansion of memory bandwidth and capacity and meeting the needs of memory elastic expansion. At the same time, it can also solve the problem of low memory utilization in some cases, realize memory pooling to decouple memory resources, improve the utilization rate of memory resources in the data center, and reduce the cost of the entire data center.

[0121] In one embodiment, in step S401, an Ethernet data packet of the host module is obtained, and the Ethernet data packet is encapsulated based on the current network topology information of the host module, and the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module. Step S401 includes:

[0122] Access each host module of the memory expansion system through the IP address and send a data acquisition request to the host module; receive and parse the Ethernet data packet sent by the host module to obtain the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module and the current bandwidth of the host module.

[0123] The IP address (Internet Protocol Address) refers to the logical address assigned to each host module on the Internet, which is used to mask the difference in physical addresses so that the interconnection control module can query and access each host module.

[0124] The data acquisition request refers to a request or instruction for instructing the host module to send an Ethernet data packet to the interconnection control module.

[0125] Parsing the Ethernet data packet refers to extracting the current network topology information in the Ethernet data packet to obtain the host ID, processor ID, port ID, interface ID and current bandwidth.

[0126] Exemplarily, the interconnection control module accesses each host module through the IP address corresponding to each host module in the memory expansion system, and sends a data acquisition request to each host module after establishing access; then, after the host module responds to the data acquisition request and sends an Ethernet data packet to the interconnection control module, the Ethernet data packet is received and the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module and the current bandwidth of the host module in the Ethernet data packet are extracted.

[0127] In this embodiment, by accessing the host module and acquiring data, the operation data of the host module at the current moment can be obtained, so as to subsequently construct an interconnection topology network between the host module and the signal exchange module.

[0128] In one embodiment, the host module has multiple connection ports, each signal exchange module has a signal downstream port and multiple signal upstream ports, the signal downstream ports are connected to the memory modules one by one, and the multiple signal upstream ports are respectively connected to any connection port of different host modules. In step S402, the current network topology information of the host module and the signal exchange module is determined according to the Ethernet data packet, and the current signal exchange module that is currently exchanging signals with the host module is determined based on the current network topology information, including:

[0129] The current connection state between the connection port and the signal upstream port and the current bandwidth when the processor of the host module accesses the memory module are determined according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module; the current signal exchange module that exchanges signals with the host module at the current moment is determined according to the current connection state and the current bandwidth.

[0130] Exemplarily, the interconnection control module determines the corresponding connection relationship between the connection port and the signal upstream port at the current moment according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module, so as to determine the current connection state between the connection port and the signal upstream port, and determine the current bandwidth when the processor of the host module accesses the memory module; then, the interconnection control module determines the current signal exchange module that exchanges signals with the host module at the current moment according to the current connection state and the current bandwidth, so as to determine the corresponding memory module.

[0131] In this embodiment, by determining the current connection status between the host module and the signal exchange module and the current bandwidth of the host module, the memory module that provides running memory for the host module can be further determined, so as to achieve the purpose of dynamic bandwidth adjustment with the minimum adjustment cost in the subsequent adjustment process.

[0132] In one embodiment, in step S404, the signal exchange module connected to the host module is selected based on the current bandwidth and the real-time required bandwidth to reallocate the memory module to be accessed by the host module, including:

[0133] Determine the bandwidth difference of the processor of the host module according to the real-time required bandwidth and the current bandwidth, increase or decrease the allocated memory modules for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory modules as mobile memory modules; select and enable a signal upstream port of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

[0134] Among them, selecting and selecting a signal upstream port of a signal exchange module connected to a mobile memory module means that among the various signal upstream ports of the same signal exchange module, only one signal upstream port can communicate with the connection port of a host module through the corresponding interface module at a time, that is, a memory module is only allowed to be accessed by one host module, but this does not mean that a signal exchange module can only be connected to one host module. It can be connected to multiple different host modules through different signal upstream ports. It is just that during the operation of the host module, only one signal upstream port is allowed to be connected, so that the corresponding memory module can only be accessed or used by one host module to avoid conflicts.

[0135] Exemplarily, the interconnection control module determines the bandwidth difference of the processor of the host module according to the real-time required bandwidth and the current bandwidth, determines whether it is necessary to increase or decrease the bandwidth for the host module based on the bandwidth difference, increases or decreases the allocated memory modules for the host module, and determines the increased or decreased allocated memory modules as mobile memory modules; then, the interconnection control module selects a signal uplink port of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module. The specific process of the interconnection control module performing memory module reallocation in this embodiment can be found in the record of the interconnection control module in the above embodiment, which will not be repeated here.

[0136] In this embodiment, by selecting a selection signal upstream port, the memory module can be accessed and used by only one host module at the same time, so as to avoid access conflicts and occupation and ensure stable operation of the application program; at the same time, by controlling the selection of the signal upstream port, the bandwidth of each host module can be adjusted without interrupting the system, thereby effectively ensuring business continuity.

[0137] In a specific application example, Figure 5 As shown, this embodiment provides a memory expansion system and method based on CXL bus technology, the system comprising:

[0138] 1. The host unit mainly includes a CPU processor and a CXL port. The CPU processors communicate and expand through a high-speed interconnect bus. The CXL port connects the CXL signal from the CPU processor to the connector.

[0139] 2. CXL interface unit, the main uplink can be connected to the CXL port of the host unit, and the downlink can be connected to the input of the CXL signal exchange unit.

[0140] 3. The CXL signal exchange unit includes two CXL signal input terminals, one CXL signal output terminal and a control terminal, and only performs physical signal switching. The CXL signal input terminal is connected to the CXL signal of the CPU processor on the host, and the CXL signal output terminal is connected to the input of the CXL protocol exchange unit. The CXL signal exchange unit switches the signal control of the two CXL signal input terminals to one output terminal according to the control command of the interconnection network control unit.

[0141] Fourth, the interconnection network control unit is mainly responsible for obtaining the bandwidth of the CXL bus currently required by the host unit from the host unit, and converting the information of the required bandwidth into control logic code, including host ID, port ID, interface ID, and controlling the CXL signal exchange unit after processing to realize the control of the signal interconnection of each exchange unit. The communication bus between the interconnection network control unit and the host unit is mainly responsible for the interactive transmission of the CXL interconnection topology information of the entire memory pool. The interconnection bus between them can be selected such as PCIE bus, UART bus, Ethernet bus, etc. Considering the universality and transmission distance factors, the Ethernet transmission protocol can be adopted. The interconnection network control unit and the host unit have their own IP addresses as access unique identifiers. The host unit and the required CXL bus bandwidth and other information are encapsulated in Ethernet data packets and sent to the interconnection network control unit, including the host ID, which is used to distinguish different hosts in the CXL memory expansion system; the processor ID, which is used to identify a specific processor in a host unit; the port ID, which is used to identify the specific CXL port of the processor; the interface ID of the CXL interface unit, which is used to identify the corresponding relationship of the physical cable interconnection; and the bandwidth information, which is used to identify the situation information of the interconnection signal pair.

[0142] The interconnection network control unit performs a specific control process. First, the interconnection network control unit accesses all host units of the memory expansion system through an IP address and sends data acquisition information. Each host unit sends the data segment information defined in the present invention to the interconnection network control unit through an Ethernet data packet. The interconnection control unit parses the data packet to obtain the required host ID, processor ID, port ID and other information. Through this information, the CXL network topology information between each host unit and the CXL interface unit in the current memory expansion system can be established. When the host unit has a demand for a change in the CXL interconnection bandwidth, the interconnection network control unit controls the CXL signal exchange unit according to the new CXL network topology information to achieve switching control of the CXL network topology.

[0143] 5. CXL protocol exchange unit provides high-bandwidth, low-latency data transmission, realizing high-speed data transmission and resource sharing. Uplink is connected to the CXL signal exchange unit, and downlink is connected to the memory module. The uplink and downlink ports adopt a 1:1 convergence ratio, mainly realizing the CPU processor on the uplink host unit to access and use the memory on the downlink memory module.

[0144] 6. The memory module unit includes a CXL controller and memory media, which can be allocated to the CPU processors of different host units through the CXL protocol exchange unit.

[0145] Example 1

[0146] like Figure 6As shown, a specific implementation process of the method is provided. The details are as follows:

[0147] In this embodiment, four host units are taken as an example. The four CXL ports of the host unit 1 are connected to four CXL interface units. The signals of each CXL interface unit can be 16 pairs of signals, 8 pairs of signals, or 4 pairs of signals, which can be set according to the actual host bandwidth requirements. In this embodiment, according to each CXL port being 16 pairs of signals, under the default configuration, the interconnection network control unit controls the CXL signal exchange unit to allocate 1 CXL port to each host unit, and each host unit can access the downstream memory module through the CXL protocol exchange unit. If the application running on the host unit 1 needs to allocate more CXL bandwidth, such as the bandwidth of 2 CXL ports, the interconnection network control unit can control the CXL signal exchange unit 2 to enable the connection of the signal of the CXL interface unit 3, so that the host unit can access the downstream memory module through the two links of the CXL interface unit 1 and the CXL interface unit 3, so as to increase the bandwidth. Therefore, the bandwidth of the host unit 1 in this embodiment can support up to 4 ports × 16 signal pairs, which can reach 64 signal pairs.

[0148] Example 2

[0149] like Figure 7 As shown, another specific embodiment of the implementation process of the method is provided. The details are as follows:

[0150] In this embodiment, four host units are taken as an example. Host unit 1 and host unit 3 are connected to CXL signal exchange unit 1 and CXL signal exchange unit 2 respectively through one CXL port, and host unit 2 and host unit 4 are connected to CXL signal exchange unit 3 and CXL signal exchange unit 4 respectively through one CXL port. Under the default configuration, the interconnection network control unit controls the CXL signal exchange unit to assign CXL signal exchange unit 1 and CXL signal exchange unit 2 to host unit 1, and assigns CXL signal exchange unit 3 and CXL signal exchange unit 4 to host unit 2. Host unit 3 serves as the backup host of host unit 1, and host unit 4 serves as the backup host of host unit 2. The interconnection network control unit monitors whether the status of host unit 1 and host unit 2 is normal. If an abnormality occurs, the signal link is switched to backup host unit 3 and backup host unit 4 by controlling the CXL signal exchange unit. High availability of the system is achieved.

[0151] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0152] Based on the same inventive concept, the embodiment of the present application also provides a memory expansion device for implementing the memory expansion method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more memory expansion device embodiments provided below can refer to the limitations on the memory expansion method above, and will not be repeated here.

[0153] In one embodiment, Figure 8 As shown, a memory expansion device is provided, including: a data acquisition module 801, an information construction module 802, a monitoring module 803 and a memory expansion module 804, wherein:

[0154] The data acquisition module 801 is used to acquire the Ethernet data packet of the host module.

[0155] The information construction module 802 is used to determine the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine the current signal exchange module that exchanges signals with the host module at the current moment based on the current network topology information.

[0156] The monitoring module 803 is used to monitor the real-time bandwidth requirement of the host module in real time.

[0157] The memory expansion module 804 is used to select the signal exchange module connected to the host module based on the current bandwidth and the real-time required bandwidth to reallocate the memory module accessed by the host module.

[0158] In an optional embodiment, the data acquisition module 801 is also used to access each host module of the memory expansion system through an IP address and send a data acquisition request to the host module; and receive and parse the Ethernet data packet sent by the host module to obtain the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module and the current bandwidth of the host module.

[0159] In an optional embodiment, the information construction module 802 is also used to determine the current connection status between the connection port and the signal upstream port and the current bandwidth when the processor of the host module accesses the memory module based on the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module; and determine the current signal exchange module that is currently exchanging signals with the host module based on the current connection status and the current bandwidth.

[0160] In an optional embodiment, the memory expansion module 804 is also used to determine the bandwidth difference of the processor of the host module based on the real-time required bandwidth and the current bandwidth, increase or decrease the allocated memory modules for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory modules as mobile memory modules; and select a signal upstream port of the signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

[0161] Each module in the above-mentioned memory expansion device can be implemented in whole or in part by software, hardware or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module above.

[0162] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Fig. 9 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, the current bandwidth of the host module and the IP address. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a memory expansion method is implemented.

[0163] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0164] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the memory expansion method of the above embodiment when executing the computer program.

[0165] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the memory expansion method of the above embodiment is implemented.

[0166] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0167] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0168] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0169] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A memory expansion system, characterized in that: The system comprises: Multiple memory modules; A host module, used to access the memory module according to system operation requirements; A signal exchange module, wherein the signal exchange module is arranged in a one-to-one correspondence with the memory module, and the signal exchange module is used to establish an access link between the host module and the memory module so that the host module accesses the memory module; An interconnection control module is connected to both the host module and the signal exchange module, and is used to determine the current interconnection topology network between the host module and the signal exchange module and the current bandwidth of the host module; and is used to monitor the real-time required bandwidth of the host module in real time, and select the signal exchange module connected to the host module based on the current bandwidth and the real-time required bandwidth to reallocate the memory module accessed by the host module.

2. The system according to claim 1, characterized in that The host module comprises: Multiple processors, used to access different memory modules according to system operation requirements during system operation; the multiple processors communicate with each other via a high-speed interconnect bus; A plurality of connection ports, used to connect the processor and the signal exchange module; the processor is connected to at least one connection port; The first interconnection control terminal is connected to the interconnection control module and is used to realize data transmission between the processor and the interconnection control module.

3. The system according to claim 2, characterized in that The signal exchange module has a plurality of selectively selected signal upstream ports, a signal downstream port connected to the memory module, and a second interconnection control terminal connected to the interconnection control module. Each signal upstream port of the signal exchange module is connected to any connection port of a different host module through an interface module. When the signal upstream port of the signal exchange module is selected, the access link is established between the host module connected to the signal upstream port and the corresponding memory module, so that the host module accesses the corresponding memory module.

4. The system according to claim 3, characterized in that The processor is also used to respond to the access request of the interconnection control module and encapsulate the Ethernet data packet based on the current network topology information; the current network topology information includes the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module and the current bandwidth of the host module; The interconnection control module comprises: A data parsing unit, configured to parse the received Ethernet data packet to obtain the current network topology information, and determine the current connection state between the connection port and the signal uplink port and the current bandwidth when the processor of the host module accesses the memory module according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module; A data monitoring unit, used to monitor the operating status of the processor of the host module in real time and obtain the real-time required bandwidth of the host module; A memory allocation unit, configured to determine a bandwidth difference of the processor according to the real-time required bandwidth and the current bandwidth, increase or decrease the allocated memory module for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory module as a mobile memory module; A strobe control unit is used to select a signal upstream port of a signal exchange module connected to the mobile memory module to increase or decrease the number of memory modules accessed by the host module.

5. The system according to any one of claims 3 to 4, characterized in that: Also includes: A protocol exchange module, used for enabling the host module to access the memory module; The protocol switching module has a switching upstream port and a switching downstream port, the switching upstream port is connected to the signal downstream port in a one-to-one correspondence, the switching downstream port is connected to the memory module in a one-to-one correspondence, and the convergence ratio of the switching upstream port to the switching downstream port is 1:

1.

6. A memory expansion method, characterized in that: Applied to an interconnection control module, the interconnection control module is respectively connected to at least one host module and a plurality of signal exchange modules, and the plurality of signal exchange modules are connected to a plurality of memory modules in a one-to-one correspondence; the method comprises: Obtaining an Ethernet data packet of the host module; Determine the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine the current signal exchange module that exchanges signals with the host module at the current moment based on the current network topology information; Monitor the real-time bandwidth requirement of the host module in real time; A signal exchange module connected to the host module is selected based on the current bandwidth of the host module and the real-time required bandwidth to reallocate the memory module to be accessed by the host module.

7. The method according to claim 6, characterized in that The Ethernet data packet is encapsulated based on the current network topology information of the host module, wherein the current network topology information includes a host ID of the host module, a processor ID of the host module, a port ID of the host module, an interface ID of the interface module, and a current bandwidth of the host module; The obtaining of the Ethernet data packet of the host module comprises: Access each host module of the memory expansion system through an IP address, and send a data acquisition request to the host module; Receive and parse the Ethernet data packet sent by the host module, and obtain the host ID of the host module, the processor ID of the host module, the port ID of the host module, the interface ID of the interface module, and the current bandwidth of the host module.

8. The method according to claim 7, characterized in that The host module has a plurality of connection ports, each of the signal exchange modules has a signal downstream port and a plurality of signal upstream ports, the signal downstream ports are connected to the memory modules one by one, and the plurality of signal upstream ports are respectively connected to any connection port of different host modules; The method of determining the current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determining the current signal exchange module that exchanges signals with the host module at the current moment based on the current network topology information, comprises: Determine the current connection state between the connection port and the signal uplink port and the current bandwidth when the processor of the host module accesses the memory module according to the host ID of the host module, the processor ID of the host module, the port ID of the host module, and the interface ID of the interface module; A current signal exchange module that currently exchanges signals with the host module is determined according to the current connection state and the current bandwidth.

9. The method according to claim 8, characterized in that The signal exchange module connected to the host module is selected based on the current bandwidth of the host module and the real-time required bandwidth to reallocate the memory module to be accessed by the host module, including: Determine a bandwidth difference of a processor of the host module according to the real-time required bandwidth and the current bandwidth, increase or decrease an allocated memory module for the host module based on the bandwidth difference, and determine the increased or decreased allocated memory module as a mobile memory module; A signal upstream port of a signal exchange module connected to the mobile memory module is selectively enabled to increase or decrease the number of memory modules accessed by the host module.

10. A memory expansion device, characterized in that: Applied to an interconnection control module, the interconnection control module is respectively connected to at least one host module and a plurality of signal exchange modules, and the plurality of signal exchange modules are connected to a plurality of memory modules in a one-to-one correspondence; the device comprises: A data acquisition module, used to acquire the Ethernet data packet of the host module; an information construction module, configured to determine current network topology information of the host module and the signal exchange module according to the Ethernet data packet, and determine a current signal exchange module that is currently exchanging signals with the host module based on the current network topology information; A monitoring module, used for monitoring the real-time bandwidth requirement of the host module in real time; The memory expansion module is used to select the signal exchange module connected to the host module based on the current bandwidth of the host module and the real-time required bandwidth, so as to reallocate the memory module accessed by the host module.

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