Memory management methods and memory controllers

Abstract

This invention discloses a memory management method and a memory controller. The memory management method is used in a rewritable non-volatile memory module. The method includes: identifying multiple first memory groups, each first memory group containing multiple first physical units, and the multiple first memory groups belonging to a second memory group; counting the number of first reads for each first memory group; obtaining a target first memory group based on the multiple first read counts; counting the target first read count for the target first memory group and the second read count for the second memory group; obtaining an expected block read count based on at least one of the target first read count and the second read count; and if the expected block read count exceeds a preset read count threshold, performing a read verification operation on the second memory group. This invention, through a multi-level statistical and predictive mechanism, improves the evaluation accuracy of triggering read verification operations while reducing storage space usage, effectively balancing storage efficiency and data reliability.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory management method for triggering a memory device to perform a read verification operation and a memory controller using the method. Background Technology

[0002] Non-volatile memory refers to computer memory that retains its data even when the current is cut off. It has advantages such as non-volatile data, low power consumption, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is memory configured with flash memory (such as solid-state drives), which has the characteristics of high read and write speeds and no need for mechanical structures to access data.

[0004] In NAND flash memory storage devices, frequent read operations on the NAND can cause crosstalk to other word lines (WL). Therefore, when the number of reads on a memory block reaches a certain threshold, i.e., the read interference threshold, a read verification operation is required for that memory block. Read verification involves rescanning the data on the memory block; if uncorrectable errors are found, error handling is necessary to recover the data.

[0005] Currently, the primary method for determining whether a read verification operation is necessary is based on evaluation using storage blocks as the basic unit. This method requires counting the number of reads for each storage block, thus consuming significant storage space. As storage device capacity continues to increase, the storage overhead of this method also increases, impacting the overall performance and cost-effectiveness of the storage device. Summary of the Invention

[0006] The purpose of this invention is to provide a method for triggering read verification on a storage device, aiming to overcome the problems existing in the prior art. This invention employs a higher-level organizational structure than physical units as the basic statistical unit, and achieves a more efficient and accurate read verification triggering mechanism through prediction and dynamic adjustment.

[0007] One or more embodiments of the present invention provide a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, the method comprising: identifying a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; counting a first read count for each first storage group, wherein the first read count reflects the sum of read counts for each first physical unit belonging to the corresponding first storage group; obtaining a target first storage group among the plurality of first storage groups based on the plurality of first read counts of the plurality of first storage groups; after obtaining the target first storage group, counting a target first read count for the target first storage group and a second read count for the second storage group, wherein the second read count reflects the sum of read counts for all first physical units belonging to the second storage group; obtaining an expected block read count based on at least one of the target first read count and the second read count; and if the expected block read count exceeds a preset read count threshold, performing a read verification operation on the second storage group.

[0008] In one or more embodiments of the present invention, the method further includes: during the period of counting the first read count of each first storage group, dividing the predetermined storage space into a plurality of first counting spaces, wherein a plurality of storage bits in the plurality of first counting spaces are used to record the first read count of each first storage group respectively, wherein a first number of the plurality of storage bits in the plurality of first counting spaces reflects the maximum number of reads that can be recorded; when the target first read count recorded in a target first counting space among the plurality of first counting spaces reaches the maximum number of reads, determining the target first storage group corresponding to the target first counting space.

[0009] In one or more embodiments of the present invention, the step of counting the target first read count of the target first storage group and the second read count of the second storage group includes: after obtaining the target first storage group, re-dividing the predetermined storage space into a second counting space and a third counting space, wherein the second counting space is used to record the second read count, and the third counting space is used to record the target first read count, wherein the second number of multiple storage bits in the second counting space and the third number of multiple storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

[0010] In one or more embodiments of the present invention, the method further includes: during the counting of the first read count for each first storage group, incrementing the first read count recorded in the corresponding first counting space whenever a read operation is performed on any first entity unit belonging to a first storage group; during the counting of the target first read count for the target first storage group and the second read count for the second storage group: incrementing the target first read count recorded in the third counting space whenever a read operation is performed on any first entity unit belonging to the target first storage group; and incrementing the second read count recorded in the second counting space whenever a read operation is performed on any first entity unit belonging to the second storage group.

[0011] In one or more embodiments of the present invention, the step of obtaining the expected block read count based on at least one of the target first read count and the second read count includes: obtaining a first expected block read count based on the target first read count; obtaining a second expected block read count based on the second read count; obtaining the expected block read count based on the first expected block read count and the second expected block read count, wherein the expected block read count is the largest of the first expected block read count and the second expected block read count; or obtaining the expected block read count based on the target first read count and the second read count.

[0012] In one or more embodiments of the present invention, the step of obtaining the first expected block read count based on the target first read count includes: obtaining a first average block read count based on the target first read count and the number of first entity units corresponding to the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; and using the first average block read count as the first expected block read count.

[0013] In one or more embodiments of the present invention, the step of obtaining the second expected block read count based on the second read count includes: obtaining a second average block read count based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and using the second average block read count as the second expected block read count.

[0014] In one or more embodiments of the present invention, the step of obtaining the expected block read count based on the target first read count and the second read count includes: obtaining a first average block read count based on the target first read count and the number of first entity units corresponding to the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; obtaining a second average block read count based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and obtaining the expected block read count based on the first average block read count and the second average block read count.

[0015] In one or more embodiments of the present invention, the step of obtaining the expected number of block reads based on the first average number of block reads and the second average number of block reads includes: obtaining the larger value between the first average number of block reads and the second average number of block reads; obtaining the absolute difference between the first average number of block reads and the second average number of block reads; and taking the sum of the larger value and the absolute difference as the expected number of block reads.

[0016] In one or more embodiments of the present invention, the step of obtaining the expected block read count based on the target first read count and the second read count includes:

[0017] Obtain an imbalance coefficient, which reflects the degree of imbalance in the number of reads of each first entity unit within the second storage group;

[0018] The expected number of block reads is obtained by multiplying the imbalance coefficient by the average number of reads of the first entity cell in the second storage group.

[0019] In one or more embodiments of the present invention, the step of obtaining the imbalance coefficient includes:

[0020] The first average block read count is obtained based on the target first read count and the number of first entity units corresponding to the target first storage group;

[0021] The second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group;

[0022] Calculate the maximum expected number of reads, wherein the maximum expected number of reads is the sum of the absolute value of the larger of the first average block read count and the second average block read count and the difference between the two;

[0023] Divide the maximum expected number of reads by the second average number of block reads to obtain the current imbalance coefficient;

[0024] The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

[0025] One or more embodiments of the present invention provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units; and a processor electrically connected to the memory interface control circuit. The processor is configured to: identify a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, and wherein the plurality of first storage groups belong to a second storage group; count a first read count for each first storage group, wherein the first read count reflects the sum of the read counts of each first physical unit belonging to the corresponding first storage group; obtain a target first storage group among the plurality of first storage groups based on the plurality of first read counts; after obtaining the target first storage group, count a target first read count for the target first storage group and a second read count for the second storage group, wherein the second read count reflects the sum of the read counts of all first physical units belonging to the second storage group; obtain an expected block read count based on at least one of the target first read count and the second read count; and if the expected block read count exceeds a preset read count threshold, perform a read verification operation on the second storage group.

[0026] Based on the above, the memory management method and memory controller provided in this embodiment of the invention can significantly save storage space and computing resources used to record the number of reads of each block through multi-level memory group statistics and dynamic prediction mechanisms, while also maintaining the execution of necessary read verification operations, realizing accurate triggering of read verification operations, and enhancing system adaptability and reliability. Attached Figure Description

[0027] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0028] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention;

[0029] Figure 2A flowchart illustrating a memory management method according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the architecture of a rewritable non-volatile memory module according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram illustrating the division of a predetermined storage space into multiple first counting spaces according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram illustrating the re-division of a predetermined storage space into a second counting space and a third counting space, according to an embodiment of the present invention.

[0033] Explanation of icon numbers

[0034] 10: Host System

[0035] 20: Storage device

[0036] 211: First Processor

[0037] 110: Second Processor

[0038] 120: Host memory

[0039] 130: Data transmission interface circuit

[0040] 210: Memory controller

[0041] 212: Data Management Circuit

[0042] 213: Memory Interface Control Circuit

[0043] 214: Buffer memory

[0044] 220: Rewritable Non-volatile Memory Module

[0045] 230: Connection interface circuit

[0046] S210~S260: Flowchart of memory management method

[0047] BM: Reserved storage space

[0048] BM1: Initially allocated pre-defined storage space

[0049] BM2: Re-allocated pre-defined storage space

[0050] CS1(1)~CS1(4): First counting space

[0051] CS2: Second counting space

[0052] CS3: Third counting space

[0053] 221(1)~221(4): First memory group

[0054] 222(1)~222(M): Second memory group

[0055] 220(1)~220(4): Physical architecture (channel, CE, chip or plane)

[0056] BK1, BK2, BKN: Solid unit

[0057] A41~A42, A51~A53: Arrows Detailed Implementation

[0058] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0059] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0060] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0061] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0062] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0063] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0064] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0065] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0066] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0067] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to implement the memory management method provided by this invention. The control instructions / program codes corresponding to the memory management method can also be implemented as hardware circuit units to implement the memory management method provided by this invention.

[0068] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0069] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0070] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write instruction from the host system 10). Another example is reading data from one or more physical units of the rewritable non-volatile memory module 220 (data can be read from one or more memory cells in one or more physical units) via the memory interface control circuit 213 and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0071] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming) operations, read operations, or erase operations on the rewritable non-volatile memory module 220.

[0072] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0073] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages, or logical columns) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages, physical columns) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0074] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, address lists, memory group mapping tables, various read counts, and other information associated with this method), so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0075] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store data written by the host system 10.

[0076] In this embodiment, the rewritable non-volatile memory module 220 has multiple word lines, each of which is electrically connected to multiple memory cells, also called columns (or entity columns). Multiple columns on the same word line form an entity programming unit (also called an entity page). Each entity page corresponds to an entity address to record the location of the data stored in the entity page. Furthermore, multiple entity pages can form an entity block (also called an entity erase unit). Each memory die (chip) in the multiple memory dies of the rewritable non-volatile memory module has multiple planes, and each plane has multiple entity blocks. It should be noted that the present invention is not limited to the size of each entity page and logical page.

[0077] The Channel (CH) pin (also known as the physical channel) is a set of physical pins in the rewritable non-volatile memory module 220, which is responsible for receiving and transmitting data and commands.

[0078] The Chip enable (CE) pin is used to select or deselect a memory chip. Each CE pin corresponds to a physical chip (memory chip). If a chip enable pin is active, the corresponding physical chip is selected.

[0079] In one embodiment, for the rewritable non-volatile memory module 220, read verification is a crucial step in ensuring data integrity. Generally, the read verification process is as follows: First, the memory controller 210 sends a read verification command to the target memory chip via a channel and selects the corresponding physical chip via the chip enable (CE) pin. Then, the controller specifies the physical block and physical page to be verified. The memory sequentially reads the data on each word line of the specified physical page and compares it with the original data. If an error is found during the read verification process, the controller attempts to correct it using an error correction code (ECC). If the error cannot be corrected by ECC, the page is deemed to have failed the read verification operation. At this point, the controller initiates a data recovery procedure, typically including the following steps: First, it attempts to reread the data of the erroneous page; if this still fails, the data of that page is marked as unreliable, and if possible, the data is recovered from other backup sources (such as redundant data or checksums); finally, the recovered data is rewritten to a new physical page or physical block, and the corresponding mapping table is updated. If the data cannot be recovered, the controller marks the area as a bad block to prevent it from being used in future programs. These measures ensure the reliability and data integrity of the storage system.

[0080] Figure 2 This is a flowchart illustrating a memory management method according to an embodiment of the present invention.

[0081] like Figure 2 As shown, the memory management method of the present invention includes the following steps:

[0082] Step S210: Identify multiple first memory groups of the rewritable non-volatile memory module 220. Each first memory group includes multiple first physical units (e.g., physical blocks), and the multiple first memory groups belong to a second memory group. This step lays the foundation for subsequent read count statistics and management. For ease of explanation, the following embodiments will use physical blocks as physical units for description. However, the present invention is not limited to this; for example, the physical unit of the memory management method applied in the present invention can also be a physical page.

[0083] Figure 3 This is a schematic diagram of the architecture of a rewritable non-volatile memory module according to an embodiment of the present invention. Figure 3 A schematic diagram of the architecture of the rewritable non-volatile memory module 220 is shown to illustrate the architectural details of the first and second memory groups defined in step S210.

[0084] like Figure 3 As shown, the rewritable non-volatile memory module 220 includes multiple second memory groups, denoted as 222(1) to 222(M) in the figure. Each second memory group further includes multiple first memory groups, exemplified by 221(1), 221(2), 221(3), and 221(4) in the figure. Each first memory group further includes multiple physical blocks, denoted as BK1, BK2, up to BKN in the figure.

[0085] In this embodiment, 220(1) to 220(4) belong to the same physical architecture, which can be any of Channel, Chip Enable, Chip, or Plane. For example, if 220(1) to 220(4) represent different CEs, then several physical blocks within each CE can constitute a first storage group (e.g., the two physical blocks BK1 and BK2 of CE 220(1) belong to a first storage group). In this case, the first storage groups 221(1), 221(2), 221(3), and 221(4) correspond to different CEs, and each first storage group 221 has the same number of physical blocks.

[0086] Second storage groups 222(1) to 222(M) can be higher-level physical or logical organizational units. For example, if 220(1) to 220(4) represent CEs, then a second storage group can contain a portion of each of the multiple CEs (i.e., each of the multiple CEs corresponds to a first storage group of the second storage group). For example, second storage group 222(1) includes first storage groups 221(1) to 221(4) respectively corresponding to the multiple CEs 220(1) to 220(4).

[0087] Each physical block (such as BK1, BK2, BKN) is the smallest unit that can be erased independently. In the memory management method of this invention, we achieve an efficient read verification operation triggering mechanism by tracking and counting the number of reads of the higher-level first and second memory groups, thus avoiding the resource consumption caused by physical block-level read count counting operations.

[0088] Through this multi-layered storage organization structure, the present invention can manage and monitor read operations at different granular levels. This flexible architecture allows the memory management method of the present invention to adapt to storage devices of various sizes and types, thereby maximizing the performance and lifespan of the storage system while ensuring data integrity.

[0089] Please return Figure 2 Step S220: Count the first read count for each first storage group. The first read count reflects the total number of reads for each first entity block belonging to the corresponding first storage group. This step effectively tracks the usage of each first storage group.

[0090] Step S230: Based on the multiple first read counts of the multiple first storage groups, obtain the target first storage group among the multiple first storage groups. This step can identify the target first storage group that is read most frequently, and this storage group may also include physical blocks that have already experienced read interference.

[0091] Figure 4 This is a schematic diagram illustrating the division into multiple first counting spaces according to an embodiment of the present invention. Please refer to... Figure 4 , continuing Figure 3 For example, based on the number of first storage groups in each second storage group, a predetermined storage space BM is set as a predetermined storage space BM1 (as shown by arrow A41), wherein the predetermined storage space BM1 is divided into a plurality of first counting spaces CS1(1) to CS1(4). The predetermined storage spaces BM and BM1 can be configured via buffer memory 214 and / or rewritable nonvolatile memory module 220, and their size is limited to a preset fixed value.

[0092] The first counting space BM1 is further divided into multiple first counting spaces CS1(1), CS1(2), CS1(3) and CS1(4), each first counting space corresponding to a first storage group 221(1), 221(2), 221(3) and 221(4), used to record the first read count of the corresponding first storage group (as shown by arrow A42).

[0093] Specifically, multiple storage bits in the first counting spaces CS1(1), CS1(2), CS1(3), and CS1(4) are used to record the first read counts of the corresponding first storage groups 221(1), 221(2), 221(3), and 221(4), respectively. The number of storage bits in each first counting space (also called the first number) determines the maximum number of reads that can be recorded. For example, if each first counting space uses 12 bits, then the maximum number of reads that can be recorded is 4095 (i.e., 2^325). 12 -1) times.

[0094] In one embodiment, for example, when any physical block (such as BK1 or BK2) in the first memory group 221(1) is read, the processor 211 increments the first read count recorded in the corresponding first count space (such as CS1(1)). This method allows the system to track the read activity of each first memory group in real time.

[0095] Next, when the number of target first reads recorded in one of the multiple first count spaces (CS1(1) to CS1(4)) reaches the maximum number of reads, the processor 211 will determine the corresponding first storage group as the target first storage group.

[0096] For example, assuming that the first read count recorded in the first counting space CS1(4) first reaches the maximum read count of 4095, then the processor 211 will determine the corresponding first storage group 221(4) as the target first storage group. In addition, the processor 211 will also accumulate the four first read counts recorded in the first counting spaces CS1(1) to CS1(4) as the second read count of the corresponding second storage group. When the predetermined storage space is re-divided into the second counting space and the third counting space, this second read count can be used to set the second counting space as the initial value of the second read count recorded in the second counting space. On the other hand, the first read count (target first read count) recorded in the first counting space CS1(4) can be used to set the third counting space as the initial value of the target first read count recorded in the third counting space.

[0097] This mechanism allows the system to quickly identify the most frequently used storage areas, providing a precise target for subsequent read verification operations. In other words, because the maximum number of reads is reached first, the target first storage group will be judged by the system as the first storage group that is likely to be subject to read interference, and in subsequent management operations, the statistics of the number of reads from the target first storage group will be the primary focus.

[0098] By using this method of pre-defined storage space division and management, the present invention can efficiently track the reading status of a large number of storage units within limited storage resources and efficiently determine the first storage group to which the physical blocks that may cause read interference belong.

[0099] Please return Figure 2In step S240, after acquiring the target first storage group, the target first read count of the target first storage group and the second read count of the second storage group are counted. The second read count reflects the sum of read counts for all first entity blocks belonging to the second storage group. This step emphasizes that the read count is counted for both the target first storage group and the entire second storage group, further narrowing the scope of the read count statistics and omitting the count of first read counts for other first storage groups not belonging to the target first storage group. Because the focus is only on counting the read counts for the target first storage group and the entire second storage group, the limited predetermined storage space can be re-planned.

[0100] Figure 5 This is a schematic diagram illustrating the re-division of a predetermined storage space into a second counting space and a third counting space, according to an embodiment of the present invention.

[0101] like Figure 5 As shown, after acquiring the target first storage group, as indicated by arrow A51, the processor 211 re-divides the predetermined storage space BM into a predetermined storage space BM2, which includes a second counting space CS2 and a third counting space CS3.

[0102] Continued Figure 3 For example, as shown by arrow A52, the second counting space CS2 is used to record the second read count of the second storage group 222(1). The third counting space CS3 is specifically used to record the target first read count of the target first storage group (e.g., the first storage group 221(4) in the second storage group 222(1)).

[0103] It is worth noting that the second number of storage bits in the second counting space CS2 and the third number of storage bits in the third counting space CS3 are both greater than the first number in the first counting space. This design aims to record a wider range of read counts. Furthermore, the number of bits in the second counting space CS2 is greater than the number of bits in the third counting space CS3 because the second memory group typically contains more physical blocks, requiring a larger counting range.

[0104] It should be noted that, in one embodiment, the difference between the number of bits in the second counting space CS2 and the number of bits in the third counting space CS3 can be set according to the total number of the plurality of first storage groups in each second storage group. For example, if the total number of the first storage groups in the second storage group is 4, this difference can be set to 2 so that the difference between the second read count and the target first read count can be at least 4 (2 ≤ 1 ... 2 =4) times.

[0105] In the process of counting the first read count of the first target storage group and the second read count of the second target storage group, the present invention adopts the following strategy:

[0106] Whenever a read operation is performed on any first entity block (such as BK1 or BK2) belonging to the target first storage group 221(4), as shown by arrow A53, the processor 211 increases the target first read count recorded in the third counting space CS3.

[0107] Meanwhile, as shown by arrow A52, whenever a read operation is performed on any first entity block belonging to the second storage group 222(1), the processor 211 increments the second read count recorded in the second counting space CS2.

[0108] This method allows the system to simultaneously track read activity in both the target first storage group and the entire second storage group, providing a more precise triggering basis for subsequent read verification operations. By recording the number of reads at these two levels separately, this invention can more comprehensively evaluate the usage patterns of the storage device.

[0109] For example, in one embodiment, the processor 211 divides the predetermined 48-bit storage space BM into four equal parts of a first counting space (e.g., Figure 4 In the CS1(1) to CS1(4) array, each first counting space contains 12 bits, corresponding to the number of reads of the four CEs (first memory groups). This initial state can be understood as... Figure 4 The state of BM1 in the array. It is worth mentioning that the counting space of this method can also be implemented as a counter.

[0110] As storage device 20 is used, the system continuously records the number of reads for each CE. When the number of reads for a CE reaches the maximum value of 4095 that can be recorded by 12 bits, the system predicts that CE will be the target CE with the most future reads. After identifying the target CE, the system reallocates 48 bits of space. Specifically:

[0111] The processor 211 first adds up the original four 12-bit values ​​(which can be called CE_count1, CE_count2, CE_count3 and CE_count4) to obtain the total number of reads (Unit_cnt) for the entire second memory group.

[0112] Next, the processor 211, for example, partitions 26 bits from the 48-bit space (corresponding to...). Figure 5 CS2 in Figure 5 The second counting space (CS2) in the second storage group is used to record the second read count (Unit_cnt).

[0113] The remaining 22 bits (corresponding to) Figure 5CS3 in the target memory group (target first memory group) is used to record the number of reads of the target CE (target first read count) that is predicted to be read the most in the future (target first read count) (CE_Cnt).

[0114] For example, assuming that a repartition is triggered when CE_count4 corresponding to CE4 reaches 4095, the processor 211 will add up the values ​​of CE_count1, CE_count2, CE_count3 and CE_count4 to obtain Unit_count (stored in the second counting space CS2), and determine CE4 as the target CE. Its subsequent read counts will be recorded in the third counting space CS3.

[0115] This re-partitioning method offers several significant advantages:

[0116] Precise tracking: With CS3 (22-bit), the system can continue to precisely track the number of reads of the target CE without losing information due to bit overflow of the counting space.

[0117] Overall monitoring: Through CS2 (26-bit), the system can monitor the overall read status of the entire second storage unit, providing a basis for global read verification decisions.

[0118] Space efficiency: The 26-bit and 22-bit designs cleverly balance the counting requirements at the Unit and CE levels. The difference of 4 bits results in a difference of 16 (2^3) in the maximum actual data that can be recorded. 4 =16) times, which is sufficient to handle a maximum of 16 CEs, while avoiding premature overflow of the second counting space corresponding to the second memory group.

[0119] Highly adaptable: This dynamic partitioning method can adaptively identify and track frequently used memory regions, making system resources more concentrated on potential problem areas.

[0120] Please return Figure 2 In step S250, the expected block read count is obtained based on at least one of the target first read count and the second read count. This step predicts the possible block read count by comprehensively considering read statistics at different levels.

[0121] Step S260: If the expected number of block reads exceeds a preset read count threshold (also known as a read interference threshold), a read verification operation is performed on the second storage group. This step compares the expected number of block reads with the preset threshold to determine whether a read verification operation needs to be performed, thereby ensuring data integrity and reliability.

[0122] In one embodiment, the present invention provides a flexible and comprehensive method for obtaining the expected number of block reads, which is a further refinement of step S250. This method takes into account different levels of storage organization to achieve a more accurate read verification triggering mechanism.

[0123] This invention provides three methods for obtaining the expected number of block reads (e.g., method 1 to method 3), each based on different statistical data.

[0124] [Method 1] Obtain the first expected block read count based on the target first read count:

[0125] In this approach, the system utilizes Figure 5 The first expected block read count is calculated by recording the number of reads of the target first memory group 221(4) in the third counting space CS3. This method pays special attention to memory areas identified as frequently used, and can respond more quickly to local read pressure.

[0126] More specifically, Method 1 includes the following steps:

[0127] (1) Obtain the target first read count: The processor 211 reads the cumulative target first read count of the target first memory group 221(4) from the third counting space CS3. This value reflects the overall read situation of the area predicted to be a high-frequency use area.

[0128] (2) Determine the number of first entity blocks in the target first storage group: The processor 211 calculates the total number of all first entity blocks (such as BK1, BK2, etc.) belonging to the target first storage group 221(4). This number may be determined during system initialization or obtained through dynamic scanning.

[0129] (3) Calculate the first average block read count: The processor 211 divides the target first read count by the number of first physical blocks to obtain the first average block read count. This value reflects the average read frequency of each physical block in the target first memory group.

[0130] (4) Set the first expected block read count: The processor 211 directly uses the calculated first average block read count as the first expected block read count.

[0131] The advantage of this approach is that it takes into account the overall read pressure distribution of the target first storage group, providing a more balanced and representative expected number of reads.

[0132] The following numerical example illustrates this calculation process:

[0133] Assume the following: the target first storage group 221(4) contains 1000 first entity blocks; the target first read count recorded in the third counting space CS3 is 5,000,000 times.

[0134] The calculation process is as follows:

[0135] Target first read count = 5,000,000

[0136] Number of first entity blocks = 1,000

[0137] First average block read count = Target first read count / Number of first entity blocks

[0138] =5,000,000 / 1,000

[0139] =5,000

[0140] Therefore, the first expected block read count is set to 5,000.

[0141] This result means that, on average, each physical block was read 5,000 times in the target first storage group. The system can use this value to determine whether a read verification operation needs to be triggered. For example, if the preset read count threshold is 10,000, then in this case, the system will not trigger a read verification operation, but will continue to closely monitor read activity in this area.

[0142] In this way, the present invention can accurately reflect the reading pressure in high-frequency usage areas, providing a reliable basis for read verification triggering decisions, thereby achieving a balance between protecting data integrity and maintaining system performance.

[0143] [Method 2] Obtain the second expected block read count based on the second read count:

[0144] This method utilizes Figure 5 The number of reads of the second storage group 222(1) recorded in the second counting space CS2 is used to calculate the number of reads of the second expected block. This method provides a more global perspective, taking into account the usage of the entire second storage group, which helps to balance the overall read load.

[0145] More specifically, Method 2 includes the following steps:

[0146] (1) Obtain the second read count: Processor 211 from Figure 5 The second counting space CS2 in the second memory group 222(1) is used to read the cumulative number of reads. This value reflects the overall read situation of the entire second memory group 222(1).

[0147] (2) Determine the number of second entity blocks in the second storage group: The processor 211 calculates the total number of all first entity blocks belonging to the second storage group 222(1). This number includes all entity blocks in all first storage groups (such as 221(1), 221(2), 221(3), 221(4) etc.) within the second storage group (e.g., each first storage group has 2 entity blocks, for a total of 8 entity blocks).

[0148] (3) Calculate the second average block read count: The processor 211 divides the second read count by the number of second physical blocks to obtain the second average block read count. This value reflects the average read frequency of each physical block in the second memory group.

[0149] (4) Set the second expected block read count: The processor 211 directly uses the calculated second average block read count as the second expected block read count.

[0150] The advantage of this approach is that it provides a more macroscopic perspective, taking into account the read pressure distribution across the entire second storage group, making it suitable for assessing the overall state of the storage system.

[0151] The following numerical example illustrates this calculation process:

[0152] Assume the following: the second storage group 222(1) contains 4 first storage groups, each of which has 500 physical blocks; the second count space CS2 records 20,000,000 reads.

[0153] The calculation process is as follows:

[0154] Second read count = 20,000,000

[0155] Number of second entity blocks = 4 * 500 = 2,000

[0156] Second average block read count = Second read count / Number of second entity blocks

[0157] =20,000,000 / 2,000

[0158] =10,000

[0159] Therefore, the second expected block read count is set to 10,000.

[0160] This result indicates that, on average, each physical block was read 10,000 times across the entire second storage group. The system can use this value to assess the overall read load on the storage system and determine whether a read verification operation needs to be triggered.

[0161] For example, if the preset threshold for the number of reads is 7,000, then the system will trigger a read verification operation in this case.

[0162] This invention enables a comprehensive assessment of the read pressure on the storage system, providing a macro-level reference for read verification triggering decisions and preventing the predicted target first storage group from being the storage group experiencing read interference. This method is particularly suitable for scenarios requiring consideration of the overall storage system status, helping to optimize read verification strategies at the system level and balance data protection and system performance.

[0163] [Method 1 + Method 2] Simultaneously considers the read status of the first and second storage groups of the target.

[0164] In one embodiment, the present invention provides a comprehensive method for obtaining the expected block read count, which selects the most conservative expected block read count (the expected block read count is the larger of the first expected block read count and the second expected block read count) by simultaneously considering the read situation of the target first storage group and the second storage group, so as to ensure the reliability of the data.

[0165] The following numerical example illustrates the calculation process of this synthesis method:

[0166] Assume the current state of the system is as follows: The target first storage group 221(4) contains 1000 first entity blocks, and the target first read count recorded in the third counting space CS3 is 5,000,000. The second storage group 222(1) contains 4 first storage groups, each with 1000 entity blocks, and the second read count recorded in the second counting space CS2 is 32,000,000.

[0167] First, processor 211 uses method 1 to calculate the number of reads for the first expected block:

[0168] Target first read count = 5,000,000

[0169] Number of first entity blocks = 1,000

[0170] First expected block read count = 5,000,000 / 1,000 = 5,000

[0171] Then, processor 211 uses method 2 to calculate the number of reads for the second expected block:

[0172] Second read count = 32,000,000

[0173] Number of second entity blocks = 4 * 1,000 = 4,000

[0174] Second expected block read count = 32,000,000 / 4,000 = 8,000

[0175] Finally, processor 211 compares the number of reads for the two expected blocks:

[0176] First expected block read count: 5,000

[0177] Second expected block read count: 8,000

[0178] Based on the comparison results, processor 211 selected 8,000, which has the larger value, as the final expected number of block reads. This selection reflects the system's conservative strategy for data security, because a larger expected number of block reads means that the system may trigger read verification operations earlier, thereby better protecting data integrity.

[0179] For example, if the preset read count threshold is 7,000, in this case, since the final selected expected block read count (8,000) exceeds the threshold, the system will trigger a read verification operation on the second storage group, even if the read pressure of the target first storage group has not yet reached the trigger condition.

[0180] The advantage of this comprehensive approach lies in its simultaneous consideration of both local (target first storage group) and global (second storage group) read pressure. By selecting a larger value as the final result, it reflects the system's conservative approach to data security, enabling earlier detection of potential read interference issues, improving the reliability of data protection, and avoiding judgment biases that may arise from a single evaluation method.

[0181] [Method 3] Obtain the expected block read count based on the target first and second read counts:

[0182] This is a comprehensive approach that considers both CS3 and CS2 record read counts. By combining local (target first storage group) and global (second storage group) read statistics, this approach provides the most comprehensive estimate of expected block read counts.

[0183] Specifically, method 3 includes the following steps:

[0184] (1) Calculate the first average block read count: from Figure 5 The third counting space CS3 in the target first read count is obtained; the number of the first physical blocks of the target first storage group 221(4) is determined; the first average block read count = target first read count / number of first physical blocks is calculated.

[0185] (2) Calculate the second average block read count: from Figure 5The second counting space CS2 in the second memory group obtains the second read count; determines the number of second entity blocks in the second memory group 222(1) (the total number of all first entity blocks); calculates the second average block read count = second read count / number of second entity blocks.

[0186] (3) Obtain the expected number of block reads: Find the larger value between the first average number of block reads and the second average number of block reads; calculate the absolute difference between the first average number of block reads and the second average number of block reads; add the larger value and the absolute difference to obtain the expected number of block reads.

[0187] The advantage of this method is that it not only considers the read pressure of the high-frequency usage area (target first storage group), but also the state of the overall storage system (second storage group), and reflects the degree of imbalance of read pressure by calculating the difference.

[0188] The following numerical example illustrates this calculation process:

[0189] Suppose the following situation exists:

[0190] The target first storage group 221(4) contains 1,000 first entity blocks, with a cumulative read count of 6,000,000.

[0191] The second storage group 222(1) contains 4 first storage groups, totaling 4,000 physical blocks, with a cumulative read count of 20,000,000.

[0192] The calculation process is as follows:

[0193] First average block read count = 6,000,000 / 1,000 = 6,000

[0194] Second average block read count = 20,000,000 / 4,000 = 5,000

[0195] Larger value = max(6,000, 5,000) = 6,000

[0196] Absolute difference = |6,000 - 5,000| = 1,000

[0197] Number of reads for the third expected block = Larger value + Absolute difference = 6,000 + 1,000 = 7,000

[0198] Therefore, the third expected block read count is set to 7,000.

[0199] This result reflects the following:

[0200] The average read pressure of the target first storage group (6,000) is higher than the overall average (5,000).

[0201] The existence of a 1,000-times difference in read pressure indicates a certain degree of imbalance in the read load.

[0202] The final expected block read count (7,000) takes into account high-pressure areas and overall imbalances. The system can use this value to determine whether a read verification operation needs to be triggered. For example, if the preset read count threshold is 6,500, then in this case, the third expected block read count (7,000) obtained using method 3 will trigger a read verification operation. Conversely, the first expected block read count (6,000) and the second expected block read count (5,000) obtained using methods 1 and 2 respectively will not trigger a read verification operation.

[0203] This invention enables a more comprehensive assessment of the read pressure status of a storage system, providing a more accurate basis for read verification triggering decisions. This method is particularly suitable for scenarios that require simultaneous consideration of local high-pressure areas and the overall system state, helping to achieve a better balance between protecting data integrity and optimizing system performance.

[0204] [Method 4] Calculation method for expected block read count based on imbalance coefficient

[0205] In one embodiment, by introducing a dynamically adjusted imbalance coefficient, the imbalance of read load can be captured more sensitively, thereby providing a more accurate read verification triggering mechanism.

[0206] Specifically, method 4 includes the following steps:

[0207] (1) Calculate the first average block read count:

[0208] from Figure 5 The third counting space CS3 in the middle obtains the first read count of the target;

[0209] Determine the number of the first entity blocks in the target first storage group 221(4);

[0210] Calculate the first average block read count = target first read count / number of first entity blocks.

[0211] (2) Calculate the second average block read count:

[0212] from Figure 5 The second count is obtained from the second counting space CS2;

[0213] Determine the number of the second entity blocks in the second storage group 222(1);

[0214] Calculate the second average block read count = second read count / number of second entity blocks.

[0215] (3) Calculate the maximum expected number of reads (PB_max):

[0216] Find the larger of the first average block read count and the second average block read count.

[0217] Calculate the absolute difference between the two;

[0218] Add the larger value to the absolute difference to get the maximum expected number of reads.

[0219] (4) Calculate the current imbalance coefficient (Current_Ec):

[0220] Current_Ec = Maximum expected number of reads / Second average number of block reads;

[0221] (5) Update the maximum imbalance coefficient (max_Ec):

[0222] Compare the current imbalance coefficient with the historical maximum imbalance coefficient;

[0223] The larger of the two values ​​is taken as the new maximum imbalance coefficient.

[0224] (6) Calculate the expected number of block reads:

[0225] Expected number of block reads = Second average number of block reads × Maximum imbalance coefficient.

[0226] The following is a specific numerical example to illustrate the calculation process. Assume the following: the target first storage group 221(4) contains 1,000 first physical blocks and has a cumulative read count of 6,000,000; the second storage group 222(1) contains 4 first storage groups, with a total of 4,000 physical blocks and a cumulative read count of 20,000,000; the historical maximum imbalance coefficient is 1.6.

[0227] The calculation process is as follows:

[0228] First average block read count = 6,000,000 / 1,000 = 6,000

[0229] Second average block read count = 20,000,000 / 4,000 = 5,000

[0230] PB_max=max(6,000,5,000)+|6,000-5,000|=6,000+1,000=7,000

[0231] Current_Ec=7,000 / 5,000=1.4

[0232] max_Ec = max(1.4, 1.6) = 1.6

[0233] Expected block read count = 5,000 × 1.6 = 8,000

[0234] Therefore, the final expected number of block reads was set to 8,000.

[0235] This result reflects the following:

[0236] The current imbalance coefficient (1.4) is lower than the historical maximum (1.6). The system retains the historical maximum imbalance coefficient and, by multiplying the second average block read count (5,000) by the historical maximum imbalance coefficient (1.6), obtains a more conservative expected block read count (8,000). Even though the current read pattern shows a lower imbalance, the system still adopts a more conservative strategy based on historical experience, enabling the system to trigger read verification operations earlier.

[0237] For example, if the preset read count threshold is 7,500, then in this case, the system will trigger a read verification operation because the expected number of block reads calculated using the historical maximum imbalance coefficient (8,000) exceeds the threshold (while the expected number of block reads calculated using the current maximum imbalance coefficient (7,000) does not exceed the threshold). This demonstrates that the system will refer to historical experience to protect data security, even if the current read pattern appears relatively balanced.

[0238] It is worth mentioning that the processor 211 can choose to use one or more of the above five methods according to actual needs. For example, in some cases, the system may calculate all expected block read counts and then select the maximum value as the final expected block read count to ensure the most conservative data protection strategy is adopted. Alternatively, as long as any expected block read count exceeds a preset read count threshold, the processor 211 will perform a read verification operation on the second storage group.

[0239] like Figure 5 Arrows A52 and A53 indicate that the system can update the second read count and the target first read count in real time, thereby dynamically updating the expected block read count. This dynamic update mechanism enables the present invention to adapt to changes in the usage patterns of storage devices at different times, providing more accurate read verification triggering timing.

[0240] This flexible method for obtaining the expected number of block reads takes into account both the specific needs of local high-frequency use areas and the overall state of the storage system, thus achieving a good balance between data protection and system performance.

[0241] In one embodiment, the specific process for the read verification operation of the second storage group is as follows:

[0242] (1) Trigger the read verification operation

[0243] When the expected number of block reads exceeds a preset read count threshold, processor 211 triggers a read verification operation on the second memory group 222(1). This triggering may be based on any one or a combination of the following three methods:

[0244] (1a) Number of first expected block reads (based on target first read count)

[0245] (1b) Number of second expected block reads (based on the number of second reads)

[0246] (1c) Number of reads for the third expected block (based on a combination of the target first and second read counts)

[0247] (2) Read data from the target area

[0248] Once a read verification operation is triggered, processor 211 instructs memory interface control circuit 213 to read data from the second memory group 222(1). This process involves the following steps:

[0249] (2a) The processor 211 generates a sequence of read command commands.

[0250] (2b) The memory interface control circuit 213 converts the command sequence into a format recognizable by the rewritable non-volatile memory module 220.

[0251] (2c) The memory interface control circuit 213 sends a read command to the target memory chip through the corresponding channel.

[0252] (2d) Select the corresponding physical chip via the chip enable (CE) pin.

[0253] (2e) Read the data on each word line in the specified entity page in sequence.

[0254] (3) Perform ECC verification

[0255] The data management circuit 212 performs error correction code (ECC) checks on the read data. This process includes:

[0256] (3a) Calculate the ECC value of the read data.

[0257] (3b) Compare the calculated ECC value with the stored ECC value.

[0258] (3c) If the two are consistent, the data is considered to be correct.

[0259] (3d) If discrepancies exist, try using ECC to correct errors.

[0260] (4) If the ECC check passes, continue monitoring. A successful ECC check indicates that the current data has not been affected by read interference. In this case:

[0261] (4a) The processor 211 will update the relevant read statistics, such as the target first read count and the second read count.

[0262] (4b) Continue to monitor the read activity of the region (second storage group) using the method of the present invention.

[0263] (4c) The read verification timer or associated counting space of the second storage group can be reset (e.g., the predetermined storage space corresponding to the second storage group is reset to the initial stage).

[0264] (5) If ECC verification fails, attempt data recovery. If ECC verification fails and the error cannot be corrected via ECC, processor 211 will initiate the data recovery procedure:

[0265] (5a) Try to reread the data of the error page, possibly using a different read voltage or other read parameters.

[0266] (5b) If the reread fails, the processor 211 will look for other possible data sources, such as redundant data or checksums.

[0267] (5c) Use this additional information to attempt to reconstruct the original data.

[0268] (6) If necessary, migrate the data to a new storage area.

[0269] If the data recovery is successful or partially successful: (6a) the processor 211 instructs the data management circuit 212 to write the recovered data to a new, reliable storage location; (6b) this new location may be another physical block within the same second storage group 222(1), or another second storage group; (6c) during the writing process, the memory interface control circuit 213 generates new ECC data.

[0270] If the data cannot be recovered: (6a) the processor 211 will mark the corresponding area as a bad block; (6b) update the bad block management table to ensure that the area will not be used in the future.

[0271] (7) Update relevant mapping tables and management information

[0272] After completing the above operations, processor 211 will update various management information in the system:

[0273] (7a) If data is moved, update the logical-to-entity address mapping table to map the relevant logical addresses to the new entity addresses.

[0274] (7b) Update the entity-to-logical address mapping table to reflect the new correspondence between entity addresses and logical addresses.

[0275] (7c) If bad blocks are generated, update the bad block management table.

[0276] (7d) Reset or update the read count statistics associated with the second storage group.

[0277] (7e) Update the storage group mapping table if the data has been moved to a different storage group.

[0278] By executing this detailed read verification process, the present invention can effectively identify and handle data errors caused by frequent read operations, thereby improving the reliability and lifespan of the rewritable non-volatile memory module 220. This method not only promptly detects potential data integrity issues but also minimizes the risk of data loss through intelligent data management strategies, while optimizing the overall performance of the storage system.

[0279] This embodiment also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in the processor of a host system, the processor performs the steps of the memory simulator and storage device testing method described above. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0280] Based on the above, the memory management method and memory controller provided in the embodiments of the present invention can achieve the following effects:

[0281] Storage space saving: Compared with traditional methods, this invention only requires a small amount of additional storage space to manage the read statistics of a large number of storage blocks, which significantly reduces storage overhead.

[0282] Improved management efficiency: By using the concept of multi-level storage groups and dynamic prediction mechanisms, management processes are simplified and system efficiency is improved.

[0283] Precise read verification triggering: By comprehensively considering the read patterns of different storage groups, the accuracy of read verification triggering is improved and unnecessary read verification operations are reduced.

[0284] Enhanced adaptability: Storage groups can be flexibly defined according to the actual storage structure, making it suitable for storage devices of various sizes and types.

[0285] Improved reliability: More precise read verification management effectively reduces the risk of data errors caused by read interference, thereby improving the overall reliability of the storage system.

[0286] Performance optimization: Reduced unnecessary read verification operations minimized the impact on normal read and write operations, thus helping to improve the overall performance of the storage system.

[0287] Extended lifespan: More precise read verification management reduces unnecessary data migration and erasure operations, helping to extend the lifespan of storage devices.

[0288] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, characterized in that, include: Identify a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; The first read count for each first storage group is counted, wherein the first read count reflects the total number of reads of each first entity cell belonging to the corresponding first storage group; Based on the multiple first read counts of the multiple first storage groups, a target first storage group among the multiple first storage groups is obtained, wherein each first storage group corresponds to a first counting space that records the first read counts. When the target first read count recorded in the target first counting space among the multiple first counting spaces reaches the maximum read count, the target first storage group corresponding to the target first counting space is determined. After acquiring the target first storage group, the target first read count of the target first storage group and the second read count of the second storage group are counted, wherein the second read count reflects the sum of the read counts of all first entity units belonging to the second storage group; Based on at least one of the target first read count and the second read count, obtain the expected block read count; and If the expected number of block reads exceeds a preset read count threshold, a read verification operation is performed on the second storage group.

2. The memory management method according to claim 1, characterized in that... The method further includes: During the counting of the first read count for each first storage group, a predetermined storage space is divided into a plurality of first counting spaces, wherein a plurality of storage bits in the plurality of first counting spaces are used to record the first read count for each first storage group, and wherein the first number of the plurality of storage bits in the plurality of first counting spaces reflects the maximum number of reads that can be recorded.

3. The memory management method according to claim 2, characterized in that, The steps for counting the first read count of the first target storage group and the second read count of the second storage group include: After acquiring the target first storage group, the predetermined storage space is re-divided into a second counting space and a third counting space, wherein the second counting space is used to record the second read count, and the third counting space is used to record the target first read count. The second number of multiple storage bits in the second counting space and the third number of multiple storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

4. The memory management method according to claim 3, characterized in that, The method further includes: During the period of counting the first read count for each first storage group, whenever a read operation is performed on any first entity cell belonging to a first storage group, the first read count recorded in the corresponding first counting space is incremented; During the period of counting the first read count of the first target storage group and the second read count of the second storage group: Each time a read operation is performed on any first entity cell belonging to the target first storage group, the target first read count recorded in the third counting space is incremented; and Each time a read operation is performed on any first entity cell belonging to the second storage group, the second read count recorded in the second counting space is incremented.

5. The memory management method according to claim 1, characterized in that, The step of obtaining the expected block read count based on at least one of the target first read count and the second read count includes: Based on the target first read count, obtain the first expected block read count; Based on the second number of reads, obtain the second expected number of block reads; The expected block read count is obtained based on the first expected block read count and the second expected block read count, wherein the expected block read count is the larger of the first expected block read count and the second expected block read count; or Based on the target first read count and the second read count, the expected block read count is obtained.

6. The memory management method according to claim 5, characterized in that, The steps for obtaining the first expected block read count based on the target first read count include: A first average block read count is obtained based on the target first read count and the corresponding number of first entity units in the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; and The first average number of block reads is taken as the first expected number of block reads.

7. The memory management method according to claim 5, characterized in that, The steps for obtaining the second expected block read count based on the second read count include: A second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and The second average number of block reads is used as the second expected number of block reads.

8. The memory management method according to claim 5, characterized in that, The steps for obtaining the expected block read count based on the target first read count and the second read count include: A first average block read count is obtained based on the target first read count and the number of first entity units corresponding to the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; A second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and The expected number of block reads is obtained based on the first average number of block reads and the second average number of block reads.

9. The memory management method according to claim 8, characterized in that, The step of obtaining the expected number of block reads based on the first average number of block reads and the second average number of block reads includes: Obtain the larger value between the first average block read count and the second average block read count; Obtain the absolute difference between the first average block read count and the second average block read count; and The sum of the larger value and the absolute difference is taken as the expected number of block reads.

10. The memory management method according to claim 5, characterized in that, The steps for obtaining the expected block read count based on the target first read count and the second read count include: Obtain an imbalance coefficient, which reflects the degree of imbalance in the number of reads of each first entity unit within the second storage group; The expected number of block reads is obtained by multiplying the imbalance coefficient by the average number of reads of the first entity cell in the second storage group.

11. The memory management method according to claim 10, characterized in that, The steps for obtaining the imbalance coefficient include: The first average block read count is obtained based on the target first read count and the number of first entity units corresponding to the target first storage group; The second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group; Calculate the maximum expected number of reads, wherein the maximum expected number of reads is the sum of the absolute value of the larger of the first average block read count and the second average block read count and the difference between the two; Divide the maximum expected number of reads by the second average number of block reads to obtain the current imbalance coefficient; The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

12. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical cells; and A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: Identify a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; The first read count for each first storage group is counted, wherein the first read count reflects the total number of reads of each first entity cell belonging to the corresponding first storage group; Based on the multiple first read counts of the multiple first storage groups, a target first storage group among the multiple first storage groups is obtained, wherein each first storage group corresponds to a first counting space that records the first read counts. When the target first read count recorded in the target first counting space among the multiple first counting spaces reaches the maximum read count, the target first storage group corresponding to the target first counting space is determined. After acquiring the target first storage group, the target first read count of the target first storage group and the second read count of the second storage group are counted, wherein the second read count reflects the sum of the read counts of all first entity units belonging to the second storage group; Based on at least one of the target first read count and the second read count, obtain the expected block read count; If the expected number of block reads exceeds a preset read count threshold, a read verification operation is performed on the second storage group.

13. The memory controller according to claim 12, characterized in that, The processor is also configured to: During the counting of the first read count for each first storage group, a predetermined storage space is divided into a plurality of first counting spaces, wherein a plurality of storage bits in the plurality of first counting spaces are used to record the first read count for each first storage group, and wherein the first number of the plurality of storage bits in the plurality of first counting spaces reflects the maximum number of reads that can be recorded.

14. The memory controller according to claim 13, characterized in that, The steps for counting the target first read count of the target first storage group and the target second read count of the second storage group include: After acquiring the target first storage group, the predetermined storage space is re-divided into a second counting space and a third counting space, wherein the second counting space is used to record the second read count, and the third counting space is used to record the target first read count. The second number of multiple storage bits in the second counting space and the third number of multiple storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

15. The memory controller according to claim 14, characterized in that, The processor is also configured to: During the period of counting the first read count for each first storage group, whenever a read operation is performed on any first entity cell belonging to a first storage group, the first read count recorded in the corresponding first counting space is incremented; During the period of counting the first read count of the first target storage group and the second read count of the second storage group: Each time a read operation is performed on any first entity unit belonging to the target first storage group, the target first read count recorded in the third counting space is incremented; as well as Each time a read operation is performed on any first entity cell belonging to the second storage group, the second read count recorded in the second counting space is incremented.

16. The memory controller according to claim 12, characterized in that, The step of obtaining the expected block read count based on at least one of the target first read count and the second read count includes: Based on the target first read count, obtain the first expected block read count; Based on the second number of reads, obtain the second expected number of block reads; The expected block read count is obtained based on the first expected block read count and the second expected block read count, wherein the expected block read count is the larger of the first expected block read count and the second expected block read count; or Based on the target first read count and the second read count, the expected block read count is obtained.

17. The memory controller according to claim 16, characterized in that, The steps for obtaining the first expected block read count based on the target first read count include: A first average block read count is obtained based on the target first read count and the corresponding number of first entity units in the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; and The first average number of block reads is taken as the first expected number of block reads.

18. The memory controller according to claim 16, characterized in that, The steps for obtaining the second expected block read count based on the second read count include: A second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and The second average number of block reads is used as the second expected number of block reads.

19. The memory controller according to claim 16, characterized in that, The steps for obtaining the expected block read count based on the target first read count and the second read count include: A first average block read count is obtained based on the target first read count and the number of first entity units corresponding to the target first storage group, wherein the number of first entity units is the total number of the plurality of first entity units belonging to the target first storage group; A second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group, wherein the number of second entity units is the total number of all first entity units belonging to the second storage group; and The expected number of block reads is obtained based on the first average number of block reads and the second average number of block reads.

20. The memory controller according to claim 19, characterized in that, The step of obtaining the expected number of block reads based on the first average number of block reads and the second average number of block reads includes: Obtain the larger value between the first average block read count and the second average block read count; Obtain the absolute difference between the first average block read count and the second average block read count; and The sum of the larger value and the absolute difference is taken as the expected number of block reads.

21. The memory controller according to claim 16, characterized in that, The steps for obtaining the expected block read count based on the target first read count and the second read count include: Obtain an imbalance coefficient, which reflects the degree of imbalance in the number of reads of each first entity unit within the second storage group; The expected number of block reads is obtained by multiplying the imbalance coefficient by the average number of reads of the first entity cell in the second storage group.

22. The memory controller according to claim 21, characterized in that, The steps for obtaining the imbalance coefficient include: The first average block read count is obtained based on the target first read count and the number of first entity units corresponding to the target first storage group; The second average block read count is obtained based on the second read count and the number of second entity units corresponding to the second storage group; Calculate the maximum expected number of reads, wherein the maximum expected number of reads is the sum of the absolute value of the larger of the first average block read count and the second average block read count and the difference between the two; Divide the maximum expected number of reads by the second average number of block reads to obtain the current imbalance coefficient; The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

Images