Chip function verification system and method

Abstract

The invention provides a chip function verification system and method. The system comprises a main board and at least one sub-board, the main board and the at least one sub-board are connected in a physical mode and are detachable; the mainboard is used for simulating the CPU, performing function verification on the at least one daughter board, and obtaining a verification result of the function verification through the at least one daughter board; any one of the at least one daughter board comprises at least one chip function unit and a corresponding verification circuit; and the verification circuit is used for performing function verification on the corresponding chip function unit. The chip function verification system is used for chip function verification, and the convenience and efficiency of chip function verification can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip function verification system and method. Background Art

[0002] Field-Programmable Gate Array (FPGA) prototype verification is a verification technology based on FPGA, which is used to verify the correctness of chip functions and timing in chip design to ensure that the correctness and performance of the design meet the requirements.

[0003] At present, FPGA prototype verification is to synthesize multiple chip IPs and burn them into the FPGA platform for verification in the middle and late stages of the chip design project. Chip IP refers to various functional modules or components used in integrated circuit design. These modules can be used as independent and reusable design units. For a chip design project, it includes the functions to be implemented by the chip design project and the corresponding technical parameters. Engineers usually select chip IPs based on their experience and the functions to be implemented by the project, and then integrate the selected multiple chip IPs into the main system, and test and verify them on the main system in the middle and late stages of the project; if the verification finds that the chip IP has compatibility problems or the index parameters do not meet the standards, the programs or codes corresponding to each chip IP need to be erased from the FPGA platform, and then the replaced chip IP is synthesized and burned into the FPGA platform for testing and verification, which is equivalent to erasing and rewriting the code related to the chip IP on the FPGA platform. The verification process is cumbersome and inefficient.

[0004] If the efficiency of FPGA prototype verification can be improved, it will be of great significance to reducing the risks of chip design projects. Summary of the invention

[0005] The present application provides a chip function verification system and method to improve the convenience and efficiency of FPGA prototype verification.

[0006] In a first aspect, the present application provides a chip function verification system, the system comprising: a main board, and at least one sub-board;

[0007] The main board and the at least one sub-board are physically connected and detachable;

[0008] The mainboard is used to simulate a central processing unit CPU, perform functional verification on the at least one sub-board, and obtain a verification result of the functional verification through the at least one sub-board;

[0009] Any one of the at least one sub-board includes at least one chip functional unit and a corresponding verification circuit; the verification circuit is used to perform functional verification on the corresponding chip functional unit.

[0010] In the existing FPGA prototype verification scheme, the programs corresponding to multiple chip functional units are burned into the mainboard. If the chip functional unit is to be replaced, it is very cumbersome and the code on the mainboard needs to be erased and rewritten, and then the program of the new chip functional unit needs to be burned into the mainboard. The verification circuit of the mainboard also needs to be changed accordingly, which is equivalent to rebuilding the verification circuit. However, in the chip function verification system provided by the present application, the mainboard and at least one sub-board are physically connected and detachable, which is very convenient for replacing the sub-board, and each sub-board includes at least one chip functional unit and a verification circuit for functional verification of the corresponding chip functional unit. That is to say, each sub-board completes its own functional verification and then sends the functional verification to the mainboard. In this way, the mainboard only needs to obtain the verification results of each sub-board without considering whether there are problems inside each sub-board. It only needs to consider system-level problems, such as whether the performance coefficients between the sub-boards match. In addition, after replacing the sub-board, the mainboard does not need to build a new verification circuit, which improves the convenience and efficiency of FPGA prototype verification.

[0011] In one possible design, the main board is a first FPGA; and each of the at least one sub-board is a second FPGA or an analog circuit.

[0012] The main board used to simulate the CPU is the first FPGA, which can be understood as a large FPGA; the chip functional unit included in the daughter board can also be called a chip IP. The chip IP involved in this application includes digital IP and analog IP. When the chip functional unit included in the daughter board is a digital IP, the daughter board is the second FPGA, and the second FPGA can be understood as a small FPGA; when the chip functional unit included in the daughter board is an analog IP, the daughter board is an analog circuit.

[0013] In one possible design, the main board includes at least one first connection interface; the at least one sub-board includes a second connection interface;

[0014] The mainboard establishes a connection with the second connection interface of the at least one daughterboard through the at least one first connection interface;

[0015] The mainboard is used to send a startup verification instruction to the at least one sub-board through the first connection interface, and receive a verification result returned by the at least one sub-board;

[0016] The at least one sub-board is used to receive the startup verification instruction sent by the main board through the second connection interface, and send a verification result to the main board through the second connection interface.

[0017] The main board includes multiple first connection interfaces, and each sub-board includes a second connection interface. The main board is physically connected to at least one main board, that is, the main board establishes a connection with the second connection interface of at least one sub-board through the first connection interface. The main board performs functional verification on at least one sub-board, which means sending a startup verification instruction to at least one sub-board through the first connection interface. After receiving the startup verification instruction, each sub-board performs functional verification and sends the verification result to the main board through the second connection interface. It can be seen that based on the system provided by this application, the functional verification of each sub-board is performed on each sub-board, rather than on the main board, thereby reducing the load and operating pressure of the main board.

[0018] In a possible design, each of the at least one sub-board is provided with a chip functional unit.

[0019] From the perspective of resource conservation, each sub-board can contain multiple chip functional units and corresponding verification circuits; if you want to decouple the functions of the sub-boards, you can also set up only one chip functional unit on each sub-board, which makes testing more convenient.

[0020] In a second aspect, the present application provides a chip function verification method, the method being applied to a system including a mainboard and at least one sub-board, the mainboard being used to simulate a CPU, and any one of the at least one sub-board including at least one chip function unit and a corresponding verification circuit; the method comprising:

[0021] Connecting the at least one daughter board to the main board in a physically connected manner;

[0022] Sending a startup verification instruction to the at least one sub-board through the main board;

[0023] Running the verification circuit and chip function unit in the at least one sub-board corresponding to the startup verification instruction through the at least one sub-board to obtain a verification result, and sending the verification result to the main board;

[0024] The main board receives a verification result returned by the at least one sub-board.

[0025] The chip function verification method provided in the present application is applied to the above-mentioned chip function verification system, in which the main board and at least one sub-board are physically connected and detachable, which is very convenient for replacing the sub-board, and each sub-board includes at least one chip function unit and a verification circuit for performing function verification on the corresponding chip function unit. That is to say, each sub-board completes its own function verification and then sends the function verification to the main board. In this way, the main board only needs to obtain the verification results of each sub-board without considering whether there are problems inside each sub-board. It is only necessary to consider system-level issues, such as whether the performance coefficients of each sub-board match and are compatible. In addition, after replacing the sub-board, the main board does not need to build a new verification circuit, which improves the convenience and efficiency of FPGA prototype verification.

[0026] In a possible design, before physically connecting the at least one daughter board to the main board, the method further includes:

[0027] A chip design requirement is obtained, and the at least one sub-board is determined according to the chip design requirement.

[0028] The chip function verification method provided in this application can be used in the project establishment stage or project feasibility analysis stage of chip design project. Therefore, it is necessary to first obtain the chip design requirements and select the sub-board according to the functions to be achieved by the chip design requirements.

[0029] In one design, after the main board receives the verification result returned by the at least one daughter board, the method further includes:

[0030] If the verification result of at least one of the daughter boards does not meet the preset conditions, the daughter board that does not meet the preset conditions is disconnected from the main board, and a new daughter board is selected to be connected to the main board.

[0031] After the main board receives the verification results returned by each sub-board, if the verification result of a sub-board does not meet the preset conditions, for example, the function does not meet the requirements, or a performance parameter does not meet the requirements, then the sub-board can be disconnected from the main board, that is, removed from the main board, and then a new sub-board can be selected and connected to the main board for functional verification.

[0032] In a possible design, the main board includes at least one first connection interface; the at least one daughter board includes a second connection interface; the main board establishes a connection with the second connection interface of the at least one daughter board through the at least one first connection interface;

[0033] Sending a startup verification instruction to the at least one sub-board through the main board includes:

[0034] Sending the startup verification instruction to the at least one daughter board through the at least one first connection interface of the main board;

[0035] Sending the verification result to the main board includes:

[0036] The verification result is sent to the main board through the second connection interface of the at least one daughter board.

[0037] In one possible design, the main board is a first FPGA; and each of the at least one sub-board is a second FPGA or an analog circuit.

[0038] In a possible design, each of the at least one sub-board is provided with a chip functional unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of the chip function verification system structure provided in an embodiment of the present application;

[0041] Figure 2 A block diagram of the internal structure of the sub-board provided in the embodiment of the present application;

[0042] Figure 3 A schematic flow chart of a chip function verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0044] The application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It is known to those skilled in the art that with the emergence of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0045] According to the background technology section, the existing FPGA prototype verification method is relatively low, and is generally carried out in the later stages of chip design projects, which brings a lot of risks to project decision-making and later project execution. Therefore, this application proposes the following Figure 1 The chip functional verification system shown.

[0046] First, let’s explain the terms that appear below:

[0047] Chip IP: The full name of IP here is Intellectual Property. In the early days, the integration scale of chips was limited, and the design complexity was not high. All the circuits on the chip were completed independently by the chip designer. During this period, regardless of the size of the chip, the chip was designed by the chip company from "head" to "foot". With the increasing requirements for chips in the modern information society, the scale of chips has increased exponentially, and the complexity has increased dramatically. It has become almost impossible for small and medium-sized chip companies to independently complete the design of a complex chip. There are many inspiring ideas to solve this problem. For example: building blocks and jigsaw puzzles, designing large machines from standard parts; designing large software by calling software subroutines (or middleware), building large electronic systems with chips, etc.; the idea is to reuse pre-designed mature components to build more complex systems, eliminating the consideration of internal problems of components, simplifying the complex; reusing components, reducing repetitive work, saving time, and improving the success rate of building the entire complex system. Chip IP is similar to the above-mentioned components. Chip IP is a pre-designed circuit module design with independent functions. In this application, chip IP is also called a chip functional unit.

[0048] The chip IP involved in this application is mainly divided into main processor IP, analog IP and digital IP, among which:

[0049] ① Main processor IP: used to complete operations such as fetching instructions, executing instructions, and exchanging information with external memory and logic components, such as ARM, MIPS, RISC-V, X86 and other processors; some memory IPs closely related to the main processor IP, such as RAM, ROM, etc., are used for data storage and management; the main processor IP and memory IP are usually set on a large FPGA, that is, on the motherboard;

[0050] ②Analog IP: used to provide system control and management functions. Typical analog IPs include: analog-to-digital converters, digital-to-analog converters, reset power supplies, low-dropout regulators, oscillators, amplifiers, and other mixed-signal circuits. It can be said that every chip needs some form of analog IP because digital logic relies on controlled power supply voltages, high-speed clocks, and inputs from other places on the PCB, all of which involve analog signals. By integrating analog IP, the cost of analog components can usually be significantly reduced.

[0051] ③Digital IP: Analog IP is usually used to process analog signals, such as sound, light, temperature, etc., while digital IP is mainly used to process digital signals, such as filters, oscillators, etc. Digital IP usually has high reusability and can be reused between different projects. It plays a role in accelerating development, reducing costs and risks in integrated circuit design.

[0052] FPGA prototype: FPGA prototype refers to a design prototype implemented on an FPGA chip, which is used to verify and test the functions and performance of the design. FPGA prototype design is not a simple chip research, but the use of FPGA models to design products in other industries. FPGA prototype verification platforms can be used to verify large designs, solve capacity limitations and performance requirements, and provide observability support; it should be noted that the chip function verification mentioned in this application includes FPGA prototype verification.

[0053] The chip function verification system proposed in the present application includes a main board and at least one sub-board. Figure 1 As shown in the main board, at least one daughter board is Figure 1 As shown in the sub-boards 1 to n in the figure, the main board and at least one sub-board are physically connected and detachable. The main board is the first FPGA. Since the main board is used to simulate the CPU, a large FPGA should be used as the main board; each of the at least one sub-board is a second FPGA or an analog circuit. When the chip function unit included in the sub-board is a digital IP, the sub-board is a second FPGA, which can also be called a small FPGA; when the chip function unit included in the sub-board is an analog IP, the sub-board is an analog circuit; the structural block diagram of the sub-board can be referred to Figure 2 , Figure 2 The second connection interface is used to connect to the main board. Figure 2 The verification circuit in the sub-board can be used to verify the function of the chip functional unit included in the sub-board. Figure 2 The chip function unit included in the sub-board shown is a chip IP with network function. Figure 2 The physical interface in is the network port, which is used to connect the network cable.

[0054] Figure 1 The main board in the system includes at least one first connection interface. Since the first connection interface of the main board is used to connect to the daughter board, the first connection interface can also be called a daughter board physical interface; each daughter board in at least one daughter board includes a second connection interface, such as Figure 2 The second connection interface shown is a physical connection between the main board and at least one daughter board, that is, the main board is connected to the second connection interface of at least one daughter board through the first connection interface.

[0055] Exemplarily, the main board performs functional verification on at least one sub-board. Specifically, the main board sends a startup verification instruction to at least one sub-board through a first connection interface. Correspondingly, the sub-board receives the startup verification instruction sent by the main board through a second connection interface. After receiving the startup verification instruction, the sub-board can start the verification.

[0056] Further exemplarily, the sub-board includes at least one chip functional unit and a corresponding verification circuit. If the functions of the sub-boards are to be decoupled, only one chip functional unit and a corresponding verification circuit can be set in each sub-board. The verification circuit is used to perform functional verification on the corresponding chip functional unit. After the functional verification is completed, the verification result is sent to the main board through the second connection interface. Accordingly, the main board receives the verification result returned by at least one sub-board through the first connection interface, that is, the verification result of the functional verification is obtained through at least one sub-board.

[0057] based on Figure 1 The chip function verification system shown in the present application proposes the following Figure 3 The chip function verification method shown is applied to a system including a main board and at least one sub-board, wherein the main board is used to simulate a CPU, and any one of the at least one sub-board includes at least one chip function unit and a corresponding verification circuit. The sub-board can be obtained by burning the program or code corresponding to the chip function unit to the hardware physical board. After obtaining multiple sub-boards, they can be classified according to the functions corresponding to the chip function units included in each sub-board, for example, into a main processor IP and various functional IPs, wherein the main processor IP, as described above, includes X86, ARM, etc., and the functional IP includes USB, network port, etc.

[0058] The method specifically includes:

[0059] Step 300: Connect at least one daughter board to the main board in a physically connected manner.

[0060] For example, before physically connecting at least one daughter board to the main board, the daughter board must be selected first. The selection of the daughter board depends on the chip design requirements. Therefore, the chip design requirements must be obtained first, and then the project engineer or relevant technical personnel select the daughter board according to the functions to be achieved by the chip design requirements, and then the at least one selected daughter board is physically connected to the main board.

[0061] Further exemplarily, according to the above content, the main board includes at least one first connection interface, that is, at least one daughter board physical interface; at least one daughter board includes a second connection interface, and the at least one selected daughter board is connected to the main board in a physically connected manner, that is, the second connection interface of the at least one daughter board is connected to the first connection interface corresponding to the main board.

[0062] For example, assuming that after obtaining the chip design requirements, three sub-boards are selected according to the chip design requirements, namely sub-board 1, sub-board 2 and sub-board 3. Then, the second connection interface of sub-board 1 is connected to the first connection interface corresponding to the mainboard, the second connection interface of sub-board 2 is connected to the first connection interface corresponding to the mainboard, and the second connection interface of sub-board 3 is connected to the first connection interface corresponding to the mainboard.

[0063] Step 301: Send a startup verification instruction to at least one daughter board through the main board.

[0064] For example, after at least one daughter board is connected to the main board, verification can be started at the beginning of the project or during the project feasibility analysis phase. Daughter boards that do not meet the project requirements can be detected in the early stages of the project and replaced in a timely manner, effectively reducing the risk of later project execution.

[0065] Exemplarily, unlike the existing verification scheme, the functional verification of each chip is not performed on the main board, but on its own sub-board, which reduces the main board load and operating pressure. The startup verification requires the main board to send a startup verification instruction to at least one sub-board, specifically, the startup verification instruction is sent to at least one sub-board through at least one first connection interface of the main board. One thing that needs to be explained is that the functional verification of each sub-board can be started synchronously or asynchronously according to the actual project requirements, and this application does not limit this; that is, the main board can send a startup verification instruction to at least one sub-board at the same time, or it can send a startup verification instruction to at least one sub-board at different times.

[0066] For example, assuming that the main board is connected to three sub-boards, which are respectively recorded as sub-board 1 to sub-board 3, the main board can send a startup verification instruction to sub-board 1 to sub-board 3 at 10:00, or send a startup verification instruction to sub-board 1 at 10:00, send a startup verification instruction to sub-board 2 at 10:10, and send a startup verification instruction to sub-board 3 at 10:30.

[0067] Step 302: Run the verification circuit and chip functional unit corresponding to the startup verification instruction in at least one daughter board through at least one daughter board to obtain a verification result, and send the verification result to the main board.

[0068] Exemplarily, in step 301, the main board sends a startup verification instruction to at least one sub-board, and correspondingly, at least one sub-board receives the startup verification instruction sent by the main board. After at least one sub-board receives the startup verification instruction, the verification circuit and chip functional unit corresponding to the startup verification instruction in at least one sub-board are run through at least one sub-board to obtain a verification result, that is, the corresponding test program is run to obtain the verification result, and the verification result is sent to the main board through the second connection interface of at least one sub-board.

[0069] Step 303: Receive, through the main board, a verification result returned by at least one sub-board.

[0070] Exemplarily, corresponding to step 302, after each daughter board completes verification and sends the verification result to the main board, the main board obtains the verification result of the daughter board connected to the first connection interface through the first connection interface.

[0071] For example, assuming that the first connection interface 1 of the mainboard is connected to the second connection interface of the daughterboard 1, the first connection interface 2 of the mainboard is connected to the second connection interface of the daughterboard 2, and the first connection interface 3 of the mainboard is connected to the second connection interface of the daughterboard 3, then the mainboard sends a startup verification instruction to the daughterboard 1 through the first connection interface 1, the mainboard sends a startup verification instruction to the daughterboard 2 through the first connection interface 2, and the mainboard sends a startup verification instruction to the daughterboard 3 through the first connection interface 3; when the daughterboard 1 receives the startup verification instruction, it runs the verification circuit and chip function unit corresponding to the startup verification instruction to perform functional verification. After the functional verification is completed, the functional verification result is sent to the first connection interface 1 of the mainboard through the second connection interface of the daughterboard 1, that is, the mainboard sends the startup verification instruction to the daughterboard 2 through the first connection interface 2. The connection interface 1 obtains the functional verification result of the sub-board 1; similarly, when the sub-board 2 receives the startup verification instruction, it runs the verification circuit and chip function unit corresponding to the startup verification instruction to perform functional verification. After the functional verification is completed, the functional verification result is sent to the first connection interface 2 of the main board through the second connection interface of the sub-board 2, that is, the main board obtains the functional verification result of the sub-board 2 through the first connection interface 2; and when the sub-board 3 receives the startup verification instruction, it runs the verification circuit and chip function unit corresponding to the startup verification instruction to perform functional verification. After the functional verification is completed, the functional verification result is sent to the first connection interface 3 of the main board through the second connection interface of the sub-board 3, that is, the main board obtains the functional verification result of the sub-board 3 through the first connection interface 3.

[0072] Further exemplarily, after the main board receives the verification result returned by at least one daughter board, if the verification result of at least one daughter board does not meet the preset conditions, the daughter board that does not meet the preset conditions is disconnected from the main board, and a new daughter board is reselected to be connected to the main board; wherein the preset conditions may be functional requirements, performance parameter requirements, or compatibility requirements, and may be set according to the actual chip design project, and this application does not limit this.

[0073] For example, assuming that after the mainboard receives the verification results of sub-boards 1 to 3, it is determined that the verification result of sub-board 3 does not meet the preset conditions, the second connection interface of sub-board 3 can be disconnected from the first connection interface 3 of the mainboard, and the sub-board can be reselected and then connected to the mainboard.

[0074] In addition, the sub-board in the present application is easy to disassemble and can be reused in multiple chip design requirements. For example, a sub-board including a chip functional unit with a serial port function is basically used in every chip design requirement. Therefore, the sub-board can be reused in each chip design requirement, which is easy to use and has a high utilization rate.

[0075] In the chip function verification method proposed in the present application, a sub-board including a chip function unit and a corresponding verification circuit is physically connected to a main board, and the replacement of the sub-board is very convenient. In addition, the function verification can be started at the early stage of the project or the feasibility analysis stage of the project, reducing the difficulty of decision-making and execution risks in the later stage of the project. In addition, the verification of each chip function unit is carried out on each sub-board. To replace a sub-board, it is only necessary to disconnect the sub-board from the main board, and there is no need to rebuild the verification circuit, which significantly improves the convenience and efficiency of chip function verification.

[0076] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0077] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip function verification system, characterized in that: The system includes: a main board, and at least one sub-board; The main board and the at least one sub-board are physically connected and detachable; The mainboard is used to simulate a central processing unit CPU, perform functional verification on the at least one sub-board, and obtain a verification result of the functional verification through the at least one sub-board; Any one of the at least one sub-board includes at least one chip functional unit and a corresponding verification circuit; the verification circuit is used to perform functional verification on the corresponding chip functional unit.

2. The system according to claim 1, characterized in that The main board is a first field programmable gate array FPGA; each of the at least one sub-board is a second FPGA or an analog circuit.

3. The system according to claim 1, characterized in that The main board includes at least one first connection interface; the at least one sub-board includes a second connection interface; The mainboard establishes a connection with the second connection interface of the at least one daughterboard through the at least one first connection interface; The mainboard is used to send a startup verification instruction to the at least one sub-board through the first connection interface, and receive a verification result returned by the at least one sub-board; The at least one sub-board is used to receive the startup verification instruction sent by the main board through the second connection interface, and send a verification result to the main board through the second connection interface.

4. The system according to any one of claims 1 to 3, characterized in that: Each of the at least one sub-board is provided with a chip functional unit.

5. A chip function verification method, characterized in that: The method is applied to a system including a mainboard and at least one sub-board, wherein the mainboard is used to simulate a CPU, and any one of the at least one sub-board includes at least one chip functional unit and a corresponding verification circuit; the method includes: Connecting the at least one daughter board to the main board in a physically connected manner; Sending a startup verification instruction to the at least one sub-board through the main board; Running the verification circuit and chip function unit in the at least one sub-board corresponding to the startup verification instruction through the at least one sub-board to obtain a verification result, and sending the verification result to the main board; The main board receives a verification result returned by the at least one sub-board.

6. The method according to claim 5, characterized in that Before physically connecting the at least one daughter board to the main board, the method further includes: A chip design requirement is obtained, and the at least one sub-board is determined according to the chip design requirement.

7. The method according to claim 5, characterized in that After the main board receives the verification result returned by the at least one sub-board, the method further includes: If the verification result of at least one of the daughter boards does not meet the preset conditions, the daughter board that does not meet the preset conditions is disconnected from the main board, and a new daughter board is selected to be connected to the main board.

8. The method according to claim 5, characterized in that The main board includes at least one first connection interface; the at least one daughter board includes a second connection interface; the main board establishes a connection with the second connection interface of the at least one daughter board through the at least one first connection interface; Sending a startup verification instruction to the at least one sub-board through the main board includes: Sending the startup verification instruction to the at least one daughter board through the at least one first connection interface of the main board; Sending the verification result to the main board includes: The verification result is sent to the main board through the second connection interface of the at least one daughter board.

9. The method according to any one of claims 5 to 8, characterized in that The main board is a first FPGA; each of the at least one sub-board is a second FPGA or an analog circuit.

10. The method according to any one of claims 5 to 8, characterized in that Each of the at least one sub-board is provided with a chip functional unit.

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