Multi-core consistency testing method, device, electronic device and storage medium

Abstract

The present application provides a multi-core consistency test method, device, electronic device and storage medium, which relate to the field of chip testing technology. The method includes: obtaining at least one set of test parameter combinations, the test parameter combination is used to indicate the identity of the processing core participating in the test, the test model to be used and the attribute information required for the test; parsing the test parameter combination, respectively determining the tester processing core, the checker processing core and the test model; according to the test model and the test parameter combination, respectively controlling the tester processing core and the checker processing core to execute the corresponding test process, and obtaining the test results corresponding to the test parameter combination; according to the test results corresponding to each test parameter combination, analyzing and obtaining the consistency test results between each processing core. This method can control the processing cores participating in the test to execute the consistency test according to the test process of the test model indicated in the test parameter combination, thereby realizing multi-core consistency testing based on software programs, with high test efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a multi-core consistency testing method, device, electronic device and storage medium. Background Art

[0002] With the advancement of CPU (Central Processing Unit) technology and the increasing complexity and diversification of computing needs, traditional single-core processors can no longer meet the requirements of all application scenarios. Against this backdrop, heterogeneous multi-core applications are gaining increasing attention in R&D and production. However, as the number of CPUs increases and their internal complexity grows, ensuring stable and efficient CPU operation in complex heterogeneous multi-core applications has become a crucial and long-term consideration.

[0003] Currently, multi-core consistency testing is often performed through pre-silicon design simulation. This approach is typically used in the early stages of SoC (System on Chip) design, primarily involving the design of cluster, cache, and bus-level cache controllers. Simulation platforms are used to verify that the design complies with pre-defined CPU architecture rules and to perform path consistency testing.

[0004] However, existing methods rely on the real-time simulation capabilities of the simulation platform, resulting in low test efficiency. In addition, due to the differences between the simulation platform and the actual hardware, some consistency indicators may not match the actual hardware, affecting the accuracy of the test results. Summary of the Invention

[0005] The purpose of this application is to provide a multi-core consistency testing method, device, electronic device and storage medium to address the deficiencies in the above-mentioned prior art, so as to improve the efficiency of multi-core consistency testing and reduce implementation costs.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, an embodiment of the present application provides a multi-core consistency testing method, comprising: obtaining at least one set of test parameter combinations, the test parameter combinations being used to indicate the identity of a processing core participating in the test, a test model to be used, and attribute information required for the test;

[0008] parsing the test parameter combination to respectively determine a tester processing core, an inspector processing core, and a test model; the tester processing core and the inspector processing core are different processing cores in a processing device;

[0009] According to the test model and the test parameter combination, the tester processing core and the checker processing core are respectively controlled to execute corresponding test processes to obtain test results corresponding to the test parameter combination, the test model comprising: a first model or a second model, when testing based on the first model, the tester processing core and the checker processing core read and write test addresses indicated by the attribute information; when testing based on the second model, the test addresses indicated by the attribute information are divided into multiple address intervals, and the tester processing core and the checker processing core respectively read and write each address interval;

[0010] According to the test results corresponding to each test parameter combination, the consistency test results between each processing core are analyzed and obtained.

[0011] Optionally, before controlling the tester processing core and the checker processing core to execute corresponding test processes according to the test model and the test parameter combination, the method further includes:

[0012] Based on the parameter conversion function, the test parameter combination is converted into a data format recognizable by each processing core participating in the test, and a converted test parameter combination corresponding to each processing core is obtained;

[0013] Initialization instructions are sent to each processing core participating in the test through the shared memory to control the test parameter combination after initialization conversion of each processing core.

[0014] Optionally, controlling the tester processing core and the checker processing core to execute corresponding test processes according to the test model and the test parameter combination, and obtaining a test result corresponding to the test parameter combination, includes:

[0015] Determine the address range used in the test and whether to perform consistency operations based on the relevant attribute information required by the test;

[0016] If a consistency operation is performed, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test;

[0017] At least one test result corresponding to the test parameter combination is generated according to the result of the data read and write operation.

[0018] Optionally, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test includes:

[0019] If the test model is the first model, controlling the tester processing core to write test data into the address range used for the test; and after the tester processing core completes writing, controlling the checker processing core to read the test data from the address range used for the test;

[0020] Determining a consistency verification result under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core;

[0021] According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

[0022] Optionally, controlling the tester processing core to write test data into the address range used for the test; and after the tester processing core completes writing, controlling the checker processing core to read the test data from the address range used for the test, includes:

[0023] Step A1: Control the current tester processing core to write test data into the address range used for testing, and after the current tester processing core completes writing, control the current checker processing core to read the test data from the address range used for testing;

[0024] Step B1: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read the test data from the address range used for the test. The process continues until all checker processing cores have finished reading data, and then the next tester processing core is controlled to write test data into the address range used for the test.

[0025] Step C1: Execute steps A1 to B1 in a loop until all tester processing cores and all checker processing cores finish reading and writing data.

[0026] Optionally, determining the consistency verification result under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core includes:

[0027] Determine, based on the test data written by the current tester processing core and the test data read by each checker processing core under the current tester processing core, the consistency verification result of each checker processing core when corresponding to the current tester processing core;

[0028] According to the consistency verification results when each inspector's processing core corresponds to each tester's processing core, the consistency verification result under the test parameter combination is obtained.

[0029] Optionally, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test includes:

[0030] If the test model is the second model, dividing the address range used in the test into multiple address intervals;

[0031] Controlling the tester processing core to write test data into each address interval in sequence and controlling the checker processing core to read the test data from each address interval in sequence;

[0032] Determining, based on the test data written by the tester processing core and the test data read by the checker processing core in each address interval, a consistency verification result corresponding to each address interval under the test parameter combination;

[0033] According to the consistency verification results corresponding to each address interval, a test result corresponding to the test parameter combination is generated.

[0034] Optionally, controlling the tester processing core to write test data into each address interval in sequence and controlling the checker processing core to read the test data from each address interval in sequence includes:

[0035] Step A2: Control the current tester processing core to write test data into the current address interval, and after writing is completed, control the current checker processing core to read the test data from the current address interval;

[0036] Step B2: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read test data from the current address interval. This continues until all checker processing cores have read the data results, and then the next tester processing core is controlled to write test data to the current address interval.

[0037] Step C2: cyclically execute steps A2 to B2 until all tester processing cores and all checker processing cores have completed reading and writing data in the current address range, and then proceed to step D.

[0038] Step D: Control the current tester processing core to write test data into the next address interval;

[0039] Step E: Execute steps A2 to D in a loop until all tester processing cores and all checker processing cores have completed reading and writing data in all address ranges.

[0040] Optionally, determining the consistency verification result corresponding to each address interval under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core in each address interval includes:

[0041] Determine, based on the test data written by the current tester processing core and the test data read by each checker processing core in the current address interval, the consistency verification result when each checker processing core corresponds to the current tester processing core in the current address interval;

[0042] Determine the consistency verification result in the current address interval according to the consistency verification results when each checker processing core corresponds to the current tester processing core in the current address interval;

[0043] Determine the consistency verification result under the test parameter combination according to the consistency verification result under each address interval;

[0044] According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

[0045] Optionally, obtaining at least one set of test parameter combinations includes:

[0046] Determine multiple test parameters based on test requirements;

[0047] According to each test parameter and each processing core involved in the test, multi-dimensional parameter iteration is performed to generate at least one set of test parameter combinations.

[0048] Optionally, analyzing the test results corresponding to each test parameter combination to obtain consistency test results between the processing cores includes:

[0049] Based on the test results corresponding to each test parameter combination, the test result data is cleaned from at least one dimension to obtain a set of test results under each dimension;

[0050] Perform data fusion analysis based on the test result sets under each dimension to obtain consistency test results from different analysis angles;

[0051] According to the consistency test results under different analysis angles, the consistency test results between the processing cores are obtained.

[0052] In a second aspect, an embodiment of the present application further provides a multi-core consistency testing device, comprising: an acquisition module, a determination module, a testing module, and an analysis module;

[0053] The acquisition module is configured to acquire at least one set of test parameter combinations, where the test parameter combinations are used to indicate the identity of the processing cores involved in the test, the test model to be used, and attribute information required for the test;

[0054] The determination module is configured to analyze the test parameter combination and determine a tester processing core, an inspector processing core, and a test model; the tester processing core and the inspector processing core are different processing cores in a processing device;

[0055] The testing module is configured to control the tester processing core and the checker processing core to execute corresponding test processes based on the test model and the test parameter combination, and obtain test results corresponding to the test parameter combination, wherein the test model includes: a first model or a second model; when testing based on the first model, the tester processing core and the checker processing core read and write test addresses indicated by the attribute information; when testing based on the second model, the test addresses indicated by the attribute information are divided into multiple address intervals, and the tester processing core and the checker processing core respectively read and write each address interval;

[0056] The analysis module is used to analyze the test results corresponding to each test parameter combination to obtain the consistency test results between the processing cores.

[0057] Optionally, it further includes: an initialization module;

[0058] The initialization module is used to convert the test parameter combination into a data format recognizable by each processing core participating in the test based on a parameter conversion function, and obtain a converted test parameter combination corresponding to each processing core;

[0059] Initialization instructions are sent to each processing core participating in the test through the shared memory to control the test parameter combination after initialization conversion of each processing core.

[0060] Optionally, the test module is specifically configured to determine an address range to be used in the test and whether to perform a consistency operation based on relevant attribute information required for the test;

[0061] If a consistency operation is performed, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test;

[0062] At least one test result corresponding to the test parameter combination is generated according to the result of the data read and write operation.

[0063] Optionally, the test module is specifically configured to, if the test model is the first model, control the tester processing core to write test data into the address range used for the test; and after the tester processing core completes writing, control the checker processing core to read the test data from the address range used for the test;

[0064] Determining a consistency verification result under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core;

[0065] According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

[0066] Optionally, the test module is specifically used for step A1, controlling the current tester processing core to write test data into the address range used for the test, and after the current tester processing core completes writing, controlling the current checker processing core to read the test data from the address range used for the test; step B1, after detecting that the current checker processing core has finished reading data, controlling the next checker processing core to read the test data from the address range used for the test, until all checker processing cores have finished reading data, then controlling the next tester processing core to write test data into the address range used for the test; step C1, looping through steps A1-B1 until all tester processing cores and all checker processing cores have finished reading and writing data.

[0067] Optionally, the test module is specifically used to determine the consistency verification results of each checker processing core when it corresponds to the current tester processing core based on the test data written by the current tester processing core and the test data read by each checker processing core under the current tester processing core; and obtain the consistency verification results under the test parameter combination based on the consistency verification results of each checker processing core when it corresponds to each tester processing core.

[0068] Optionally, the testing module is specifically configured to divide the address range used in the test into a plurality of address intervals if the test model is the second model;

[0069] Controlling the tester processing core to write test data into each address interval in sequence and controlling the checker processing core to read the test data from each address interval in sequence;

[0070] Determining, based on the test data written by the tester processing core and the test data read by the checker processing core in each address interval, a consistency verification result corresponding to each address interval under the test parameter combination;

[0071] According to the consistency verification results corresponding to each address interval, a test result corresponding to the test parameter combination is generated.

[0072] Optionally, the test module is specifically used for step A2, controlling the current tester processing core to write test data to the current address interval, and after writing is completed, controlling the current checker processing core to read test data from the current address interval; step B2, after detecting that the current checker processing core has finished reading data, controlling the next checker processing core to read test data from the current address interval, until all checker processing cores read the data results, and then controlling the next tester processing core to write test data to the current address interval; step C2, looping step A2-step B2 until all tester processing cores and all checker processing cores finish reading and writing data in the current address interval, and continuing to execute step D; step D, controlling the current tester processing core to write test data to the next address interval; step E, looping step A2-step D until all tester processing cores and all checker processing cores finish reading and writing data in all address intervals.

[0073] Optionally, the testing module is specifically configured to determine, based on the test data written by the current tester processing core and the test data read by each checker processing core in the current address interval, a consistency verification result when each checker processing core corresponds to the current tester processing core in the current address interval;

[0074] Determine the consistency verification result in the current address interval according to the consistency verification results when each checker processing core corresponds to the current tester processing core in the current address interval;

[0075] Determine the consistency verification result under the test parameter combination according to the consistency verification result under each address interval;

[0076] According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

[0077] Optionally, the acquisition module is specifically configured to determine a plurality of test parameters according to test requirements;

[0078] According to each test parameter and each processing core involved in the test, multi-dimensional parameter iteration is performed to generate at least one set of test parameter combinations.

[0079] Optionally, the analysis module is specifically configured to clean the test result data from at least one dimension based on the test results corresponding to each test parameter combination to obtain a test result set under each dimension;

[0080] Perform data fusion analysis based on the test result sets under each dimension to obtain consistency test results from different analysis angles;

[0081] According to the consistency test results under different analysis angles, the consistency test results between the processing cores are obtained.

[0082] In a third aspect, an embodiment of the present application provides an electronic device comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to implement the multi-core consistency testing method provided in the first aspect.

[0083] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the multi-core consistency testing method provided in the first aspect is executed.

[0084] The beneficial effects of this application are:

[0085] The present application provides a multi-core consistency testing method, apparatus, electronic device, and storage medium, comprising: obtaining at least one set of test parameter combinations, the test parameter combinations being used to indicate the identity of the processing cores participating in the test, the test model to be used, and the attribute information required for the test; parsing the test parameter combinations to respectively determine a tester processing core, a checker processing core, and the test model; the tester processing core and the checker processing core being different processing cores in a processing device; controlling the tester processing core and the checker processing core to execute corresponding test processes based on the test model and the test parameter combination, thereby obtaining test results corresponding to the test parameter combination; and analyzing the consistency test results between the processing cores based on the test results corresponding to each test parameter combination. The method can parse the test parameter combinations based on multiple sets of test parameter combinations generated by test requirements, thereby controlling the processing cores participating in the test to execute consistency testing based on the test process of the test model indicated in the test parameter combinations, thereby implementing multi-core consistency testing based on software programs, with high test efficiency, and flexible configuration based on test requirements to achieve more comprehensive testing. At the same time, the implementation cost of the software program-based implementation method is relatively low.

[0086] In addition, based on the test parameters set by the test requirements, an iterative strategy is executed to traverse all values ​​of the processing core under different test parameters, generating multiple sets of test parameter combinations that can fully cover all test scenarios, thereby improving the accuracy of consistency testing.

[0087] Finally, by integrating the analysis and visualizing the test results, we can achieve a comprehensive analysis of memory consistency issues, quickly locate the causes of memory inconsistencies, and promote research on memory consistency issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0089] Figure 1 A schematic diagram of a multi-core consistency test system architecture provided in an embodiment of the present application;

[0090] Figure 2 A flowchart of a multi-core consistency testing method provided in an embodiment of the present application;

[0091] Figure 3 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0092] Figure 4 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0093] Figure 5 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0094] Figure 6 A schematic diagram of the test architecture of the first model provided in an embodiment of the present application;

[0095] Figure 7 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0096] Figure 8 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0097] Figure 9 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0098] Figure 10 A schematic diagram of the test architecture of the second model provided in an embodiment of the present application;

[0099] Figure 11 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0100] Figure 12 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0101] Figure 13 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0102] Figure 14 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application;

[0103] Figure 15 A schematic diagram of a multi-core consistency testing device provided in an embodiment of the present application;

[0104] Figure 16 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0106] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0107] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0108] With the advancement of CPU (Central Processing Unit) technology and the increasing complexity and diversification of computing needs, traditional single-core processors can no longer meet the requirements of all application scenarios. Against this backdrop, heterogeneous multi-core applications are gaining increasing attention in R&D and production. However, as the number of CPU cores increases and the internal complexity of CPUs increases, ensuring stable and efficient CPU operation in complex heterogeneous multi-core applications has become a topic that must be considered and requires long-term attention.

[0109] The current status of the stability evaluation methods for multi-core consistency is as follows:

[0110] 1. Method based on pre-silicon design simulation: This method is usually used in the early stages of SOC (System on Chip) design, and mainly involves the design of cluster, cache and bus-level cache controllers. In the pre-silicon design stage, a simulation platform is used to verify whether the design complies with the predetermined CPU architecture rules and to perform consistency path testing. However, the disadvantage of this solution is that it relies on the real-time simulation capability of the simulation platform, resulting in low verification efficiency. In addition, due to the differences between the simulation platform and the actual hardware, some consistency indicators may not match the actual hardware. Therefore, although this method has its application value in the early stages of design, its accuracy may be affected.

[0111] 2. Post-silicon testing based on the Linux operating system: This approach typically features a comprehensive test case library and the ability to design diverse experimental scenarios to comprehensively test multi-core consistency. Its advantage lies in comprehensive system-level coverage, effectively evaluating various combinations of multi-core consistency. However, a disadvantage of this approach is that the use of a complex operating system may affect the real-time evaluation of memory and cache performance. Furthermore, because a Linux system may be running a variety of other processes, these processes may interfere with the main test metrics during consistency testing, affecting efficiency and accuracy.

[0112] 3. Hardware-accelerated test platform solution: This combines the advantages of pre-silicon design and post-silicon testing. It simulates the behavior of multi-core processors using hardware accelerators such as FPGAs (Field-Programmable Gate Arrays) or custom hardware, and performs consistency testing in an environment close to the actual hardware. This solution improves test speed and efficiency while more accurately reflecting the consistency performance of multi-core systems in actual applications. It allows for more flexible test scenario configuration, better simulates real-world application conditions, and improves the practicality of testing. However, the main disadvantage of this approach is its high implementation cost, the requirement for specialized hardware equipment and advanced technical knowledge, and the construction and maintenance of the hardware platform may also limit its application.

[0113] With the increasing number of cores and the diverse customization of CPU architectures, existing technologies for multi-core consistency analysis have become increasingly complex and inefficient. Specifically, these factors are: 1) Pre-silicon design simulation methods are inefficient in complex multi-core environments due to limited simulation capabilities and discrepancies with actual hardware; 2) Linux-based post-silicon testing solutions can affect real-time testing and accuracy due to complex system environments and background processes; and 3) Hardware-accelerated testing platforms, while improving efficiency, are costly and complex to set up and maintain. These factors limit the effectiveness and efficiency of existing technologies for high-core counts and customized CPU architectures.

[0114] Based on this, this solution provides a multi-core consistency testing method, which can generate multiple sets of test parameter combinations based on test requirements. By parsing the test parameter combinations, the processing cores participating in the test can be controlled to perform consistency testing according to the test process of the test model indicated in the test parameter combination, thereby realizing multi-core consistency testing based on software programs, with high test efficiency, and flexible configuration based on test requirements to achieve more comprehensive testing. At the same time, the implementation cost of the implementation method based on software programs is relatively low.

[0115] Figure 1 A schematic diagram of a multi-core consistency test system architecture provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the system may include: a host device and an embedded development board; the embedded development board is equipped with multiple processing cores. Testers can set test parameters and their value ranges based on test requirements. The value ranges of each parameter are input into the host device, where a test program is compiled. The compiled test program is burned into the storage medium of the embedded development board using a burning tool, and then loaded into each processing core involved in the test via initialization instructions. The processing cores in the embedded development board then control each processing core involved in the test to perform consistency testing based on the test program, obtaining test results.

[0116] Figure 2 A flow chart of a multi-core consistency testing method provided in an embodiment of the present application; Figure 2 As shown, the method may include:

[0117] S101. Obtain at least one set of test parameter combinations, where the test parameter combinations are used to indicate the identities of processing cores participating in the test, the test model to be used, and attribute information required for the test.

[0118] Developers can determine the test parameters to focus on during the test process and the value ranges of each test parameter based on the test requirements. They can then execute an iteration strategy based on each test parameter and its value range to iteratively generate all test parameter combinations. The number of iterations of the iteration strategy can be determined based on the value range of each test parameter; each generated test parameter combination includes each test parameter and one of its values. The values ​​of the test parameters in any two test parameter combinations are not exactly the same, allowing multiple test parameter combinations to fully cover all possible test scenarios.

[0119] Optionally, the test parameters and value ranges set in this solution according to the test requirements may include but are not limited to: the value range of the number of cores, the iteration range of the memory shared domain attributes, whether consistency operations are performed before checking the data, whether consistency operations are performed after writing the data, variable combinations of memory attributes, the memory address used in the test and the length of the test, selection of core test objects, test model selection, etc.

[0120] It should be noted that the “core” mentioned in the following embodiments refers to a processing core.

[0121] Exemplarily, a set of test parameter combinations generated may be:

[0122] 1. Number of cores: 2;

[0123] 2. Shared memory attribute: internal sharing (shared between core A and core B);

[0124] 3. Check whether consistency operations are performed before data is processed: both core A and core B require consistency operations;

[0125] 4. Whether to perform consistency operations before writing data: Both core A and core B require consistency operations;

[0126] 5. Memory attributes: cacheable, internally shared;

[0127] 6. Memory address length used in the test: address range 0x1000-0x1FFF, totaling 4KB;

[0128] 7. Confirm that the CPU acts as the tester or checker: Core A acts as the tester and Core B acts as the checker;

[0129] 8. Test model selection: tiled model or hybrid model.

[0130] Another set of test parameter combinations generated may be, for example:

[0131] 1. Number of cores: 4;

[0132] 2. Shared memory attribute: external sharing (core A, B, C, D shared);

[0133] 3. Check whether consistency operations are performed before data is processed: Core A and Core B require consistency operations;

[0134] 4. Whether to perform consistency operations before writing data: Core C and core D require consistency operations;

[0135] 5. Memory attributes: non-cacheable, externally shared;

[0136] 6. Memory address length used in the test: address range 0x2000-0x3FFF, totaling 8KB;

[0137] 7. Confirm that the CPU acts as a tester or checker: Core A and Core C act as testers, and Core B and Core D act as checkers;

[0138] 8. Test model selection: tiled model or hybrid model.

[0139] S102: Analyze the test parameter combination and determine the tester processing core, the checker processing core and the test model respectively.

[0140] The tester processing core and the checker processing core are different processing cores in a processing device, wherein the processing device may be, for example, the aforementioned embedded development board.

[0141] Optionally, each of the aforementioned test parameter combinations may indicate which processing cores on the development board serve as tester processing cores and which serve as checker processing cores. Accordingly, by analyzing the test parameter combinations, the cores on the development board serving as testers, i.e., the tester processing cores, and the cores on the development board serving as checkers, i.e., the checker processing cores, can be determined. Furthermore, the test model used can be determined.

[0142] Among them, the tester processing core needs to write test data into the memory address according to the memory address used for the test indicated in the test parameter combination during the test execution process, and the checker processing core needs to read the test data from the memory address, so as to obtain the test result based on the consistency of the test data written by the tester processing core and the test data read by the checker processing core.

[0143] It is worth noting that each set of test parameter combinations obtained must be used for consistency testing. Since the values ​​of the test parameters in different test parameter combinations are different, the tester processing core, the inspector processing core, the test model used, and the attribute information required for the test may all be different, so each test parameter combination can obtain corresponding test results.

[0144] S103 : According to the test model and the test parameter combination, the tester processing core and the checker processing core are controlled to execute corresponding test processes respectively, and the test results corresponding to the test parameter combination are obtained.

[0145] Among them, the test model includes: a first model or a second model. When testing based on the first model, the tester processing core and the inspector processing core read and write the test address indicated by the attribute information. When testing based on the second model, the test address indicated by the attribute information is divided into multiple address intervals, and the tester processing core and the inspector processing core read and write each address interval respectively.

[0146] In some embodiments, based on the tester processing core, checker processing core, attribute parameters required for the test, and test model indicated in the test parameter combination, the tester processing core and the checker processing core can be controlled to execute the test process corresponding to the test model to obtain the test results corresponding to the test parameter combination.

[0147] This embodiment provides two test models, the first model can also be called a tiled model, and the second model can also be called a hybrid model. In actual applications, there can also be other test models, and the test processes of different test models are different. When the first model is used for testing, the memory address used for the test indicated in the test parameter combination can be used as a complete address. The tester processing core is responsible for writing data to the memory address used for the test, and the checker processing core is responsible for reading data from the memory address used for the test, so that the test result can be obtained based on the consistency of the written data and the read data.

[0148] When using the second model for testing, the memory address used in the test indicated in the test parameter combination can be first divided into intervals to obtain multiple address intervals. Data is read and written in each address interval according to the test method of the first model mentioned above. When the data reading and writing of all address intervals are completed, the final test results are obtained.

[0149] It is worth noting that no matter whether the first model or the second model is used for testing, in a test, there is not only one tester processing core and one checker processing core. In a test, there may be multiple tester processing cores and multiple checker processing cores. Which processing cores serve as tester processing cores and which processing cores serve as checker processing cores are determined based on the number of cores in the test parameter combination and the two parameters of confirming that the CPU serves as a tester or checker.

[0150] S104 : Analyze and obtain consistency test results between the processing cores based on the test results corresponding to the test parameter combinations.

[0151] Optionally, the test results corresponding to each test parameter combination can be sent to an external device, such as to a host computer, where the test results are cleaned and integrated to analyze the consistency test results between the processing cores, and the consistency test results are visualized on the host computer.

[0152] In summary, the multi-core consistency test method provided by this embodiment includes: obtaining at least one set of test parameter combinations, the test parameter combination being used to indicate the identity of the processing cores participating in the test, the test model to be used, and the attribute information required for the test; parsing the test parameter combination to respectively determine the tester processing core, the checker processing core, and the test model; the tester processing core and the checker processing core are different processing cores in the processing device; according to the test model and the test parameter combination, respectively controlling the tester processing core and the checker processing core to execute the corresponding test process to obtain the test results corresponding to the test parameter combination; and analyzing and obtaining the consistency test results between the processing cores based on the test results corresponding to each test parameter combination. This method can parse the test parameter combination based on multiple sets of test parameter combinations generated by the test requirements, so that the processing cores participating in the test can be controlled to execute the consistency test according to the test process of the test model indicated in the test parameter combination, thereby realizing multi-core consistency testing based on the software program, with high test efficiency, and can realize more comprehensive testing based on the flexible configuration of the test requirements. At the same time, the implementation cost of the implementation method based on the software program is relatively low.

[0153] Figure 3 A flowchart of another multi-core consistency testing method provided by an embodiment of the present application is provided. Optionally, in step S102, before controlling the tester processing core and the checker processing core to execute the corresponding test process according to the test model and the test parameter combination, the method may further include:

[0154] S201 : Based on a parameter conversion function, convert the test parameter combination into a data format recognizable by each processing core participating in the test, and obtain a converted test parameter combination corresponding to each processing core.

[0155] In some embodiments, the initially generated test parameter combinations are all general parameter combinations and are not fully adapted to the processing architecture of each processing core. Therefore, a parameter conversion function can be used according to the architecture of each processing core to convert the data format of the generated test parameter combinations so that the generated test parameter combinations can be applicable to processing cores of different architectures, thereby obtaining the converted test parameter combinations corresponding to each processing core.

[0156] For example, shared domain parameters will be converted to inner / None / Outershareable in the ARM architecture processing core. For the X86 architecture processing core, the shared domain parameters will be converted to actual memory barrier avoidance methods.

[0157] S202 : issuing initialization instructions to each processing core participating in the test through the shared memory, and controlling each processing core to initialize the converted test parameter combination.

[0158] Optionally, a parameter initialization instruction may be issued to each processing core participating in the test via the shared memory, so that the converted test parameter combination corresponding to each processing core may be loaded into each processing core.

[0159] Figure 4 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application is provided. Optionally, in step S102, based on the test model and the test parameter combination, the tester processing core and the checker processing core are controlled to execute the corresponding test process to obtain the test result corresponding to the test parameter combination. This may include:

[0160] S301: Determine the address range used in the test and whether to perform a consistency operation based on relevant attribute information required for the test.

[0161] Optionally, the entire consistency test phase can divide the processing core into three different objects: tester, checker and management scheduler; the tester processing core and the checker processing core perform initialization operations based on the test parameter combination; the management scheduling processing core controls the tester processing core and the checker processing core to complete the consistency test according to the test process of the test model based on the address range used in the test in the test parameter combination and whether to perform consistency operations. After the test is completed, the management scheduling processing core formats the test results corresponding to each test parameter combination, and sets timestamps and characteristic values ​​of the test model for the data, and saves it to the storage medium or sends it directly to the host computer.

[0162] Among them, the management scheduling processing core can be any processing core, and the remaining processing cores except the management scheduling processing core serve as response processing cores. During the test process, some response processing cores can serve as tester processing cores and some as checker processing cores.

[0163] S302: If a consistency operation is performed, the tester processing core and the checker processing core are controlled to perform data read and write operations according to the test flow of the test model and the address range used in the test.

[0164] In some embodiments, when the test parameter combination indicates that a consistency operation is required, the tester processing core can be controlled to write data into the address range used for the test according to the test flow of the test model used and the address range used for the test indicated in the test parameter combination. After the tester processing core completes writing the data, the checker processing core can be controlled to read data from the address range used for the test, thereby completing the data reading and writing operations between the tester processing core and the checker processing core.

[0165] S303: Generate at least one test result corresponding to the test parameter combination according to the result of the data read and write operation.

[0166] Optionally, data analysis may be performed based on data written by the tester processing core into the address range used for testing and data read by the checker processing core from the address range used for testing to generate at least one test result corresponding to the test parameter combination.

[0167] Figure 5 A flowchart of another multi-core consistency testing method provided by an embodiment of the present application; optionally, in step S302, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test process of the test model and the address range used in the test may include:

[0168] S401 : If the test model is the first model, control the tester processing core to write test data into the address range used for testing; and after the tester processing core completes writing, control the checker processing core to read the test data from the address range used for testing.

[0169] Figure 6 This is a schematic diagram of the test architecture of the first model provided by an embodiment of the present application. In the first model, for a tester processing core, the tester processing core writes data to the address range used for testing, and all checker processing cores read data from the address range used for testing. Then, the next tester processing core writes data to the address range used for testing, and all checker processing cores read data from the address range used for testing. This loop is executed multiple times until all tester processing cores have finished writing data and all checker processing cores have finished reading data.

[0170] S402 : Determine a consistency verification result under a test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core.

[0171] Optionally, for a test parameter combination, it may indicate that there are multiple tester processing cores and multiple checker processing cores. For a tester processing core, the consistency verification result corresponding to the tester processing core may be determined based on the test data written by the tester processing core and the test data read by all the checker processing cores.

[0172] The consistency verification results corresponding to each tester's processing core can constitute the consistency verification result under the test parameter combination. For example, a possible consistency verification result under the test parameter combination can be: the memory data of processing core a and processing core b are inconsistent or the memory data are consistent.

[0173] S403: Generate a test result corresponding to the test parameter combination according to the consistency verification result under the test parameter combination.

[0174] Optionally, the consistency verification results under the test parameter combination are integrated to obtain the test result corresponding to the test parameter combination. Alternatively, all consistency verification results under the test parameter combination are statistically analyzed to obtain the test result corresponding to the test parameter combination.

[0175] Figure 7 A flowchart of another multi-core consistency testing method provided by an embodiment of the present application; optionally, in step S401, controlling the tester processing core to write test data into the address range used for testing; and after the tester processing core completes writing, controlling the checker processing core to read the test data from the address range used for testing may include:

[0176] S401a, controlling the current tester processing core to write test data into the address range used for testing, and after the current tester processing core completes writing, controlling the current checker processing core to read test data from the address range used for testing.

[0177] Since there may be multiple tester processing cores and checker processing cores, when there are multiple tester processing cores, each tester processing core must complete the process of writing test data into the address range used for testing, and each checker processing core must read the test data written by each tester processing core from the address range used for testing.

[0178] Optionally, the current tester processing core may be the currently traversed tester processing core, and the current tester processing core may be controlled to write test data into the address range used for testing. The test data here may be a pre-agreed specific character array.

[0179] After the current tester processing core finishes writing the test data, the current checker processing core may be controlled to read the test data from the address range used for the test.

[0180] S401b: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read test data from the address range used for testing.

[0181] S401c, determine whether all inspectors have finished processing the core reading data. If so, execute step S401d; if not, execute step S401b.

[0182] S401d: Control the next tester processing core to write test data into the address range used for testing.

[0183] After the current checker processing core finishes reading data, the next checker processing core is controlled to read test data from the address range used for testing, and the process is executed in sequence until all checker processing cores have finished reading test data from the address range used for testing.

[0184] At this time, the next tester processing core can be used as the current new tester processing core and controlled to write test data into the address range used for testing. After the next tester processing core finishes writing test data, each checker processing core is controlled to read test data from the address range used for testing in turn.

[0185] S401e, determine whether all tester processing cores and all checker processing cores have finished reading and writing data; if so, stop executing; if not, execute step S401a.

[0186] The above steps S401a-S401d are executed in a loop until all tester processing cores have completed writing the test data and there are no new tester processing cores; and all checker processing cores have completed reading the test data for all tester processing cores. Then the loop ends, and the consistency verification process for the current test parameter combination under the first model ends.

[0187] Figure 8 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application; optionally, in step S402, determining the consistency verification result under the test parameter combination based on the test data written by the tester processing core and the test data read by the checker processing core may include:

[0188] S501 , determining consistency verification results of each checker processing core corresponding to the current tester processing core based on test data written by the current tester processing core and test data read by each checker processing core under the current tester processing core.

[0189] In some embodiments, the consistency verification result may be determined based on whether the test data written by the tester processing core is consistent with the test data read by the checker processing core.

[0190] For a tester core, the consistency of the test data read by each checker core and the test data written by the tester core can be determined. If the test data read by the checker core is the same as the test data written by the tester core, that is, the data read by the checker core is also a specific character array, then the memory data of the checker core and the tester core are considered consistent. Conversely, if the data read by the checker core is not a specific character array, then the memory data of the checker core and the tester core are considered consistent.

[0191] Based on this, a tester processing core can obtain multiple consistency verification results, each consistency verification result is a consistency verification result between the tester processing core and a checker processing core.

[0192] S502 : Obtain consistency verification results under the test parameter combination according to consistency verification results when each inspector's processing core corresponds to each tester's processing core.

[0193] Then, the consistency verification results corresponding to all tester processing cores under a test parameter combination may constitute the consistency verification result under the test parameter combination.

[0194] Figure 9 A flowchart of another multi-core consistency testing method provided by an embodiment of the present application; optionally, in step S302, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test process of the test model and the address range used in the test may include:

[0195] S601: If the test model is the second model, divide the address range used for the test into multiple address intervals.

[0196] Figure 10 A schematic diagram of the test architecture of the second model provided in the embodiment of the present application is shown as follows: Figure 10 As shown, under the second model, the address range used for the test needs to be divided into multiple address intervals, wherein the address range used for the test can be divided into multiple equally divided intervals. Figure 10 The address range used in the test is schematically divided into three address intervals, including: address interval 1, address interval 2, and address interval 3. In actual applications, the number of divided address intervals is not limited to three.

[0197] S602 : Control the tester processing core to write test data into each address interval in sequence, and control the checker processing core to read test data from each address interval in sequence.

[0198] In the second model, data reading and writing in each address range can be considered independent and completed sequentially. For each address range, each tester processing core and each checker processing core can be controlled to read and write data according to the data reading and writing method in the first model. The process ends when data reading in all address ranges is completed.

[0199] Optionally, the tester processing core may be controlled to write test data to each address interval in sequence. After each tester processing core completes writing test data in an address interval, each checker processing core sequentially reads test data from the address interval. After all checker processing cores have finished reading test data from the address interval, the tester processing core writes test data to the next address interval, and this continues until all tester processing cores have completed writing test data to all address intervals and all checker processing cores have completed reading test data in each address interval for each tester processing core.

[0200] Combine Figure 10 As shown, for a tester processing core, after the tester processing core writes test data to address interval 1, each checker processing core reads the test data from address interval 1 in turn; then the tester processing core writes test data to address interval 2, and each checker processing core reads the test data from address interval 2 in turn; finally, the tester processing core writes test data to address interval 3, and each checker processing core reads the test data from address interval 3 in turn. After this process is completed, the data reading and writing of the tester processing core is completed. Next, the next tester processing core starts to execute the above steps until the data reading and writing process of all tester processing cores and checker processing cores is completed.

[0201] S603 : Determine consistency verification results corresponding to each address interval under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core in each address interval.

[0202] Then, a tester processing core can correspond to multiple consistency verification results in one address range, and the consistency verification results corresponding to each tester processing core in one address range can constitute the consistency verification results in one address range; and the consistency verification results corresponding to each address range can constitute the consistency verification results corresponding to each address range under the test parameter combination.

[0203] S604 : Generate a test result corresponding to the test parameter combination according to the consistency verification result corresponding to each address interval.

[0204] The consistency verification results corresponding to each address interval may constitute the consistency verification results under the address range used in the test, that is, the test results corresponding to the test parameter combination are obtained.

[0205] Figure 11 A flowchart of another multi-core consistency testing method provided by an embodiment of the present application; optionally, in step S602, controlling the tester processing core to sequentially write test data into each address interval and controlling the checker processing core to sequentially read test data from each address interval may include:

[0206] S602a: Control the current tester processing core to write test data into the current address interval, and after writing is completed, control the current checker processing core to read test data from the current address interval.

[0207] The current tester processing core can be any tester processing core, combined with Figure 10 , assuming that the current address interval is address interval 1, the current tester processing core can be controlled to write test data to address interval 1. After the writing is completed, the current checker processing core is controlled to read the test data from address interval 1.

[0208] S602b: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read test data from the current address range.

[0209] S602c, determine whether all inspectors have finished processing and reading data; if so, execute step S602d; if not, execute step S602b;

[0210] S602d: Control the next tester processing core to write test data into the current address range.

[0211] After the current checker processing core finishes reading the test data from address interval 1, the next checker processing core is controlled to read the test data from address interval 1, until all checker processing cores have finished reading the test data from address interval 1, then the next tester processing core is controlled to write the test data to address interval 1, and each checker processing core reads the test data from address interval 1 in turn.

[0212] S602e, determine whether the data reading and writing of all tester processing cores and all checker processing cores in the current address range are completed. If completed, execute step S602f; if not completed, execute step S602a.

[0213] Optionally, if the data reading and writing of all tester processing cores and all checker processing cores in the current address range have not been completed, steps S602a-S602e are executed in a loop to control the tester processing core and the checker processing core to continue to perform data reading and writing operations in the current address range until all tester processing cores have completed writing test data to address range 1 and all checker processing cores have completed reading the test data under each tester processing core from the address range, then the reading and writing operations on address range 1 are terminated.

[0214] S602f, control the current tester processing core to write test data into the next address interval.

[0215] Next, starting from the first tester processing core, control the current tester processing core to write test data to address interval 2, and each checker processing core reads test data from address interval 2. After each checker processing core finishes reading the data, control the next tester processing core to write test data to address interval 2, and each checker processing core reads test data from address interval 2.

[0216] S602g: Determine whether the reading and writing of data in all address ranges by all tester processing cores and all checker processing cores are completed; if so, stop executing; if not, execute step S602a.

[0217] The above steps S602a-S602g are executed in a loop until all the tester processing cores have completed writing the test data to address interval 1, address interval 2 and + address interval 3, and when each checker processing core corresponds to each tester processing core, the test data has been read from each address interval, then the data reading and writing operations are stopped.

[0218] Of course, in another achievable manner, the aforementioned loop process may be as follows: the current tester processing core may be controlled to write test data to address interval 1. After each checker processing core finishes reading test data from address interval 1, the current tester processing core may be controlled to write test data to address interval 2. After each checker processing core finishes reading test data from address interval 2, the current tester processing core may be controlled to write test data to address interval 3. After each checker processing core finishes reading test data from address interval 3, the loop is completed, and the next tester processing core is controlled to write test data to each address interval in sequence according to the aforementioned method. This process continues until all tester processing cores have finished writing test data to each address interval and each checker processing core corresponding to each tester processing core has finished reading test data from each address interval, and the data read and write operations are terminated.

[0219] It is sufficient as long as all the tester processing cores have completed writing the test data into each address interval, and all the checker processing cores have completed reading the test data from each address interval under each tester processing core.

[0220] Figure 12 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application; optionally, in step S603, determining the consistency verification result corresponding to each address interval under the test parameter combination based on the test data written by the tester processing core and the test data read by the checker processing core in each address interval may include:

[0221] S701 , determining consistency verification results of each checker processing core corresponding to the current tester processing core in the current address interval according to test data written by the current tester processing core and test data read by each checker processing core in the current address interval.

[0222] For an address range, multiple consistency verification results corresponding to the tester processing core in the address range can be determined based on the test data written by a tester processing core in the address range and the test data read from the address range by all checker processing cores. Among them, there is one consistency verification result corresponding to the tester processing core and a checker processing core. The consistency verification result is similar to the first model mentioned above, which can be that the memory data is consistent or the memory data is inconsistent, etc.

[0223] S702 : Determine a consistency verification result in the current address interval according to consistency verification results when each checker processing core corresponds to the current tester processing core in the current address interval.

[0224] Then, the consistency verification results corresponding to the tester processing cores in an address range can constitute the consistency verification result in the address range.

[0225] S703 : Determine the consistency verification result under the test parameter combination according to the consistency verification result under each address range.

[0226] The consistency verification results under each address range can constitute the consistency verification results under the test parameter combination.

[0227] S704: Generate a test result corresponding to the test parameter combination according to the consistency verification result under the test parameter combination.

[0228] Similarly, by performing statistical analysis on the consistency verification results under the test parameter combination, the test results corresponding to the test parameter combination can be obtained.

[0229] For example, the test result corresponding to a test parameter combination may be:

[0230] "write core:0,mem attr:NC|NON pa:0xc0000000,va:0xc0004000,length:0x4000,wm 0; check core:1,mem attr:NC|NON pa:0xc0000000,va:0xc0004000,length:0x4000,rm 0;|right|loop cnt:8|test_time_diff:24033|checker_time_diff:163686.

[0231] write core:0,mem attr:NC|NON pa:0xc0000000,va:0xc0000000,length:0x8000,wm 1; check core:1,mem attr:NC|NON pa:0xc0000000,va:0xc0000000,length:0x8000,rm 0;|right|test_time_diff:3916|checker_time_diff:20352".

[0232] Among them, write core is the processing core involved in the test; mem attr represents the memory attribute; pa represents the physical address; va represents the virtual address; length is the size of the test memory in bytes; wm represents whether write software consistency is used during the test; rm represents whether read software consistency is used during the check; check core is the checker processing core.

[0233] Figure 13 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application is provided. Optionally, in step S101, obtaining at least one set of test parameter combinations may include:

[0234] S801. Determine multiple test parameters according to test requirements.

[0235] Optionally, during the test model construction phase, the tester can determine which test parameters are used to verify the consistency results between multiple cores based on the test requirements of this test, thereby determining the required test parameters and the value range of each test parameter.

[0236] In one implementable manner, the test parameters may include but are not limited to: 1. The value range of the number of cores; 2. The iteration range of the memory shared domain attributes; 3. Whether consistency operations are performed before checking data; 4. Whether consistency operations are performed after writing data; 5. Variable combinations of memory attributes; 6. The memory address used in the test and the length of the test; 7. Selection of the core test object; 8. Test model selection.

[0237] According to different test requirements or different indicators concerned by the test, the test parameters or the value range of the test parameters can be adaptively adjusted.

[0238] S802: Perform multi-dimensional parameter iteration according to each test parameter and each processing core involved in the test to generate at least one set of test parameter combinations.

[0239] Optionally, each test parameter may be input as an input parameter into the iteration strategy. The iteration purpose of the iteration strategy is to enable each set test parameter to fully and comprehensively cover all possible test parameter combinations in the consistency test phase.

[0240] Optionally, a multidimensional iterator can be instantiated by a processing core in management scheduling mode, which generates and combines a unique test parameter combination for subsequent consistency test verification based on the above-mentioned test parameters and the processing cores involved in the test.

[0241] For each processing core participating in the test, each test parameter can be used as an attribute of the test core. Then, a processing core can have multiple attributes. Through a recursive calculation mechanism, all possible combinations of the attributes of each processing core are traversed. For each attribute of each processing core, all possible values ​​are tried, thereby traversing each possible parameter combination and obtaining multiple sets of test combination parameters.

[0242] Figure 14 A flowchart of another multi-core consistency testing method provided in an embodiment of the present application; optionally, in step S104, analyzing the consistency test results between the processing cores based on the test results corresponding to each test parameter combination may include:

[0243] S901. Clean the test result data from at least one dimension according to the test results corresponding to each test parameter combination to obtain a test result set under each dimension.

[0244] In one feasible approach, the test results can be cleaned and decomposed from the following dimensions: first dimension: data cleaning based on the adopted test model; second dimension: data cleaning based on the relationship between the tester and the inspector; third dimension: data cleaning based on the results of processing cores in the same cluster and processing cores in different clusters.

[0245] Based on the different dimensions of data cleaning, all test results can be filtered to obtain a set of test results under each dimension.

[0246] S902: Perform data fusion analysis based on the test result sets under each dimension to obtain consistency test results under different analysis angles.

[0247] Based on the obtained test result sets under various dimensions, the test result sets under various dimensions can be integrated from different focus points to obtain consistency test results under different analysis angles.

[0248] Optionally, the test result set under the first dimension can be combined with the test result set under the third dimension, and the results of the consistency test can be integrated with the focus on obtaining the differences and commonalities in the consistency problems between the processing cores of the same cluster and those of different clusters; the test results under the first dimension can be combined with the test result set under the second dimension, and the impact of the test model on consistency can be integrated with the focus on obtaining inconsistencies under which the same tester processing core will have inconsistencies; the test result set under the second dimension can be combined with the test result set under the third dimension to obtain the trend of the time spending of multiple different checker processing cores under the same consistency test model and different memory attribute parameters.

[0249] S903 : Obtain consistency test results between processing cores according to consistency test results at different analysis angles.

[0250] Optionally, based on the consistency test results from each analysis angle, quantitative processing is performed to obtain the relationship between the consistency data results and test parameters between any two processing cores, and finally the consistency test results between the processing cores are displayed in a visual manner.

[0251] In summary, the multi-core consistency test method provided by this embodiment includes: obtaining at least one set of test parameter combinations, the test parameter combination being used to indicate the identity of the processing cores participating in the test, the test model to be used, and the attribute information required for the test; parsing the test parameter combination to respectively determine the tester processing core, the checker processing core, and the test model; the tester processing core and the checker processing core are different processing cores in the processing device; according to the test model and the test parameter combination, respectively controlling the tester processing core and the checker processing core to execute the corresponding test process to obtain the test results corresponding to the test parameter combination; and analyzing and obtaining the consistency test results between the processing cores based on the test results corresponding to each test parameter combination. This method can parse the test parameter combination based on multiple sets of test parameter combinations generated by the test requirements, so that the processing cores participating in the test can be controlled to execute the consistency test according to the test process of the test model indicated in the test parameter combination, thereby realizing multi-core consistency testing based on the software program, with high test efficiency, and can realize more comprehensive testing based on the flexible configuration of the test requirements. At the same time, the implementation cost of the implementation method based on the software program is relatively low.

[0252] In addition, based on the test parameters set by the test requirements, an iterative strategy is executed to traverse all values ​​of the processing core under different test parameters, generating multiple sets of test parameter combinations that can fully cover all test scenarios, thereby improving the accuracy of consistency testing.

[0253] Finally, by integrating the analysis and visualizing the test results, we can achieve a comprehensive analysis of memory consistency issues, quickly locate the causes of memory inconsistencies, and promote research on memory consistency issues.

[0254] The following describes the apparatus, device, storage medium, etc. used to execute the multi-core consistency testing method provided in this application. The specific implementation process and technical effects are described above and will not be repeated below.

[0255] Figure 15 This is a schematic diagram of a multi-core consistency test device provided in an embodiment of the present application. The functions implemented by the multi-core consistency test device correspond to the steps performed by the above method. The device can be understood as the above-mentioned embedded development board, or the processing core deployed on the embedded development board. Figure 15 As shown, the apparatus may include: an acquisition module 150, a determination module 151, a testing module 152, and an analysis module 153;

[0256] An acquisition module 150 is configured to acquire at least one set of test parameter combinations, where the test parameter combinations are used to indicate the identity of the processing cores involved in the test, the test model to be used, and attribute information required for the test;

[0257] The determination module 151 is used to analyze the test parameter combination and determine the tester processing core, the checker processing core and the test model respectively; the tester processing core and the checker processing core are different processing cores in the processing device.

[0258] The testing module 152 is configured to control the tester processing core and the checker processing core to execute the corresponding test process according to the test model and the test parameter combination, and obtain the test result corresponding to the test parameter combination. The test model includes: a first model or a second model. When testing based on the first model, the tester processing core and the checker processing core read and write the test address indicated by the attribute information. When testing based on the second model, the test address indicated by the attribute information is divided into multiple address intervals, and the tester processing core and the checker processing core read and write to each address interval respectively.

[0259] The analysis module 153 is configured to analyze the test results corresponding to each test parameter combination to obtain consistency test results between the processing cores.

[0260] Optionally, it further includes: an initialization module;

[0261] An initialization module is used to convert the test parameter combination into a data format recognizable by each processing core participating in the test based on a parameter conversion function, and obtain a converted test parameter combination corresponding to each processing core;

[0262] Initialization instructions are sent to each processing core participating in the test through the shared memory to control the test parameter combination after initialization conversion of each processing core.

[0263] Optionally, the testing module 152 is specifically configured to determine an address range to be used in the test and whether to perform a consistency operation based on relevant attribute information required for the test;

[0264] If consistency operation is performed, the tester processing core and the checker processing core are controlled to perform data read and write operations according to the test flow of the test model and the address range used in the test;

[0265] At least one test result corresponding to the test parameter combination is generated according to the result of the data read and write operation.

[0266] Optionally, the testing module 152 is specifically configured to control the tester processing core to write test data into the address range used for testing if the test model is the first model; and control the checker processing core to read the test data from the address range used for testing after the tester processing core completes writing the test data.

[0267] Determine the consistency verification result under the test parameter combination based on the test data written by the tester processing core and the test data read by the checker processing core;

[0268] Based on the consistency verification results under the test parameter combination, the test results corresponding to the test parameter combination are generated.

[0269] Optionally, the test module 152 is specifically used for step A1, controlling the current tester processing core to write test data into the address range used for testing, and after the current tester processing core completes writing, controlling the current checker processing core to read test data from the address range used for testing; step B1, after detecting that the current checker processing core has finished reading data, controlling the next checker processing core to read test data from the address range used for testing, until all checker processing cores have finished reading data, then controlling the next tester processing core to write test data into the address range used for testing; step C1, looping through steps A1-B1 until all tester processing cores and all checker processing cores have finished reading and writing data.

[0270] Optionally, the test module 152 is specifically used to determine the consistency verification results of each checker processing core when it corresponds to the current tester processing core based on the test data written by the current tester processing core and the test data read by each checker processing core under the current tester processing core; and obtain the consistency verification results under the test parameter combination based on the consistency verification results of each checker processing core when it corresponds to each tester processing core.

[0271] Optionally, the testing module 152 is specifically configured to divide the address range used for the test into a plurality of address intervals if the test model is the second model;

[0272] Controlling the tester processing core to sequentially write test data into each address interval and controlling the checker processing core to sequentially read test data from each address interval;

[0273] Determine the consistency verification result corresponding to each address interval under the test parameter combination based on the test data written by the tester processing core and the test data read by the checker processing core under each address interval;

[0274] According to the consistency verification results corresponding to each address range, a test result corresponding to the test parameter combination is generated.

[0275] Optionally, the test module 152 is specifically used for step A2, controlling the current tester processing core to write test data to the current address interval, and after writing is completed, controlling the current checker processing core to read test data from the current address interval; step B2, after detecting that the current checker processing core has finished reading data, controlling the next checker processing core to read test data from the current address interval, until all checker processing cores read the data results, and then controlling the next tester processing core to write test data to the current address interval; step C1, looping step A2-step B2 until all tester processing cores and all checker processing cores finish reading and writing data in the current address interval, and continuing to execute step D; step D, controlling the current tester processing core to write test data to the next address interval; step E, looping step A2-step D until all tester processing cores and all checker processing cores finish reading and writing data in all address intervals.

[0276] Optionally, the testing module 152 is specifically configured to determine, based on the test data written by the current tester processing core and the test data read by each checker processing core in the current address interval, a consistency verification result when each checker processing core corresponds to the current tester processing core in the current address interval;

[0277] Determine the consistency verification result in the current address interval according to the consistency verification results when each checker processing core corresponds to the current tester processing core in the current address interval;

[0278] According to the consistency verification results under each address range, determine the consistency verification results under the test parameter combination;

[0279] Based on the consistency verification results under the test parameter combination, the test results corresponding to the test parameter combination are generated.

[0280] Optionally, the acquisition module 150 is specifically configured to determine a plurality of test parameters according to test requirements;

[0281] According to each test parameter and each processing core involved in the test, multi-dimensional parameter iteration is performed to generate at least one set of test parameter combinations.

[0282] Optionally, the analysis module 153 is specifically configured to clean the test result data from at least one dimension according to the test results corresponding to each test parameter combination, to obtain a test result set under each dimension;

[0283] Perform data fusion analysis based on the test result sets under each dimension to obtain consistency test results from different analysis angles;

[0284] According to the consistency test results under different analysis angles, the consistency test results between the processing cores are obtained.

[0285] The above-mentioned device is used to execute the method provided in the above-mentioned embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0286] The above modules can be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), one or more digital singnal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by scheduling program code through a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0287] The above modules can be connected or communicate with each other via a wired connection or a wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection in the form of a LAN, a WAN, Bluetooth, ZigBee, or NFC, or any combination thereof. Two or more modules can be combined into a single module, and any module can be divided into two or more units. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application.

[0288] Figure 16 This is a structural diagram of an electronic device provided in an embodiment of the present application. The electronic device can be deployed with an embedded development board, and multiple processors can be deployed on the embedded development board.

[0289] The electronic device may include: a processor 801 and a storage medium 802 .

[0290] The storage medium 802 is used to store programs, and the processor 801 calls the programs stored in the storage medium 802 to execute the above method embodiment. The specific implementation methods and technical effects are similar and will not be repeated here.

[0291] Among them, the storage medium 802 stores program code, and when the program code is executed by the processor 801, the processor 801 executes various steps in the multi-core consistency testing method according to various exemplary embodiments of the present application described in the above "Exemplary Method" section of this specification.

[0292] The processor 801 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0293] Storage medium 802 is a kind of non-volatile computer readable storage medium, which can be used for storing non-volatile software programs, non-volatile computer executable programs and modules. Storage medium can include at least one type of storage medium, for example, can include flash memory, hard disk, multimedia card, card type storage medium, random access storage medium (Random Access Memory, RAM), static random access storage medium (Static Random Access Memory, SRAM), programmable read-only storage medium (Programmable Read Only Memory, PROM), read-only storage medium (Read Only Memory, ROM), electrically erasable programmable read-only storage medium (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic storage medium, disk, optical disk, etc. Storage medium is any other medium that can be used to carry or store desired program code with instruction or data structure form and can be accessed by computer, but is not limited to this. The storage medium 802 in the embodiment of the present application can also be a circuit or other arbitrarily capable of realizing storage function, for storing program instructions and / or data.

[0294] Optionally, the present application also provides a program product, such as a computer-readable storage medium, comprising a program, which is used to perform the above method embodiment when executed by a processor.

[0295] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0296] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0297] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0298] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor (English: processor) to execute some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only storage medium (English: Read-Only Memory, abbreviated: ROM), a random access storage medium (English: Random Access Memory, abbreviated: RAM), a disk or an optical disk, and other media that can store program code.

Claims

1. A multi-core consistency testing method, characterized in that: include: Acquire at least one set of test parameter combinations, where the test parameter combinations are used to indicate the identity of a processing core participating in the test, a test model to be used, and attribute information required for the test; parsing the test parameter combination to respectively determine a tester processing core, an inspector processing core, and a test model; the tester processing core and the inspector processing core are different processing cores in a processing device; According to the test model and the test parameter combination, the tester processing core and the checker processing core are respectively controlled to execute corresponding test processes to obtain test results corresponding to the test parameter combination, the test model comprising: a first model or a second model, when testing based on the first model, the tester processing core and the checker processing core read and write test addresses indicated by the attribute information; when testing based on the second model, the test addresses indicated by the attribute information are divided into multiple address intervals, and the tester processing core and the checker processing core respectively read and write each address interval; According to the test results corresponding to each test parameter combination, the consistency test results between each processing core are analyzed and obtained.

2. The method according to claim 1, characterized in that Before controlling the tester processing core and the checker processing core to execute corresponding test processes according to the test model and the test parameter combination, the method includes: Based on the parameter conversion function, the test parameter combination is converted into a data format recognizable by each processing core participating in the test, and a converted test parameter combination corresponding to each processing core is obtained; Initialization instructions are sent to each processing core participating in the test through the shared memory to control the test parameter combination after initialization conversion of each processing core.

3. The method according to claim 1, characterized in that The controlling the tester processing core and the checker processing core to execute corresponding test processes according to the test model and the test parameter combination, and obtaining test results corresponding to the test parameter combination, includes: Determine the address range used in the test and whether to perform consistency operations based on the relevant attribute information required by the test; If a consistency operation is performed, controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test; At least one test result corresponding to the test parameter combination is generated according to the result of the data read and write operation.

4. The method according to claim 3, characterized in that The controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test includes: If the test model is the first model, controlling the tester processing core to write test data into the address range used for the test; and after the tester processing core completes writing, controlling the checker processing core to read the test data from the address range used for the test; Determining a consistency verification result under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core; According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

5. The method according to claim 4, characterized in that controlling the tester processing core to write test data into the address range used for the test; After the tester processing core completes writing, controlling the checker processing core to read the test data from the address range used for the test includes: Step A1: Control the current tester processing core to write test data into the address range used for testing, and after the current tester processing core completes writing, control the current checker processing core to read the test data from the address range used for testing; Step B1: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read the test data from the address range used for the test. The process continues until all checker processing cores have finished reading data, and then the next tester processing core is controlled to write test data into the address range used for the test. Step C1: Execute steps A1 to B1 in a loop until all tester processing cores and all checker processing cores finish reading and writing data.

6. The method according to claim 4, characterized in that The determining, based on the test data written by the tester processing core and the test data read by the checker processing core, a consistency verification result under the test parameter combination includes: Determine, based on the test data written by the current tester processing core and the test data read by each checker processing core under the current tester processing core, the consistency verification result of each checker processing core when corresponding to the current tester processing core; According to the consistency verification results when each inspector's processing core corresponds to each tester's processing core, the consistency verification result under the test parameter combination is obtained.

7. The method according to claim 3, characterized in that The controlling the tester processing core and the checker processing core to perform data read and write operations according to the test flow of the test model and the address range used in the test includes: If the test model is the second model, dividing the address range used in the test into multiple address intervals; Controlling the tester processing core to write test data into each address interval in sequence and controlling the checker processing core to read the test data from each address interval in sequence; Determining, based on the test data written by the tester processing core and the test data read by the checker processing core in each address interval, a consistency verification result corresponding to each address interval under the test parameter combination; According to the consistency verification results corresponding to each address interval, a test result corresponding to the test parameter combination is generated.

8. The method according to claim 7, characterized in that The controlling the tester processing core to sequentially write test data into each address interval and controlling the checker processing core to sequentially read the test data from each address interval includes: Step A2: Control the current tester processing core to write test data into the current address interval, and after writing is completed, control the current checker processing core to read the test data from the current address interval; Step B2: After detecting that the current checker processing core has finished reading data, the next checker processing core is controlled to read test data from the current address interval. This continues until all checker processing cores have read the data results, and then the next tester processing core is controlled to write test data to the current address interval. Step C2: cyclically execute steps A2 to B2 until all tester processing cores and all checker processing cores have completed reading and writing data in the current address range, and then proceed to step D. Step D: Control the current tester processing core to write test data into the next address interval; Step E: Execute steps A2 to D in a loop until all tester processing cores and all checker processing cores have completed reading and writing data in all address ranges.

9. The method according to claim 7, characterized in that Determining the consistency verification result corresponding to each address interval under the test parameter combination according to the test data written by the tester processing core and the test data read by the checker processing core under each address interval includes: Determine, based on the test data written by the current tester processing core and the test data read by each checker processing core in the current address interval, the consistency verification result when each checker processing core corresponds to the current tester processing core in the current address interval; Determine the consistency verification result in the current address interval according to the consistency verification results when each checker processing core corresponds to the current tester processing core in the current address interval; Determine the consistency verification result under the test parameter combination according to the consistency verification result under each address interval; According to the consistency verification result under the test parameter combination, a test result corresponding to the test parameter combination is generated.

10. The method according to any one of claims 1 to 9, characterized in that The obtaining of at least one set of test parameter combinations includes: Determine multiple test parameters based on test requirements; According to each test parameter and each processing core involved in the test, multi-dimensional parameter iteration is performed to generate at least one set of test parameter combinations.

11. The method according to any one of claims 1 to 9, characterized in that: The analysis of the consistency test results between the processing cores based on the test results corresponding to the test parameter combinations includes: Based on the test results corresponding to each test parameter combination, the test result data is cleaned from at least one dimension to obtain a set of test results under each dimension; Perform data fusion analysis based on the test result sets under each dimension to obtain consistency test results from different analysis angles; According to the consistency test results under different analysis angles, the consistency test results between the processing cores are obtained.

12. A multi-core consistency testing device, characterized in that: include: Acquisition module, determination module, test module and analysis module; The acquisition module is configured to acquire at least one set of test parameter combinations, where the test parameter combinations are used to indicate the identity of the processing cores involved in the test, the test model to be used, and attribute information required for the test; The determination module is configured to analyze the test parameter combination and determine a tester processing core, an inspector processing core, and a test model; the tester processing core and the inspector processing core are different processing cores in a processing device; The testing module is configured to control the tester processing core and the checker processing core to execute corresponding test processes based on the test model and the test parameter combination, and obtain test results corresponding to the test parameter combination, wherein the test model includes: a first model or a second model; when testing based on the first model, the tester processing core and the checker processing core read and write test addresses indicated by the attribute information; when testing based on the second model, the test addresses indicated by the attribute information are divided into multiple address intervals, and the tester processing core and the checker processing core respectively read and write each address interval; The analysis module is used to analyze the test results corresponding to each test parameter combination to obtain the consistency test results between the processing cores.

13. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor. When the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the program instructions to implement the multi-core consistency testing method as described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by the processor, the multi-core consistency testing method according to any one of claims 1 to 11 is implemented.

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