A power integrity protection method and apparatus

Abstract

The embodiment of the application discloses a power integrity protection method and device. The power integrity protection method comprises the following steps: obtaining historical read-write requests, historical request processing amounts, current read-write requests and current request processing amounts of a target memory; supplying power for the target memory by a power supply; predicting read-write requests and request processing amounts of the target memory at a next moment according to the historical read-write requests, the historical request processing amounts, the current read-write requests and the current request processing amounts; and generating risk warning information according to the read-write requests and the request processing amounts of the target memory at the next moment, so as to protect the power integrity. The power integrity protection method and device provided by the embodiment of the application can protect the power integrity.

Description

Technical Field

[0001] The embodiments of the present invention relate to power supply protection technology, and more particularly to a power supply integrity protection method and device. Background Art

[0002] High-bandwidth memory, a representative of high-speed video memory, is used in many artificial intelligence chips due to its excellent bandwidth and high capacity. However, it has high requirements for power integrity. If power integrity is not reliably protected, the effective bandwidth of high-bandwidth memory may be lost by 10% or even more, which will also affect other aspects such as yield. Summary of the Invention

[0003] Embodiments of the present invention provide a power integrity protection method and device to protect power integrity.

[0004] In a first aspect, an embodiment of the present invention provides a power integrity protection method, comprising:

[0005] Acquiring historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target memory; the power supply supplies power to the target memory;

[0006] Predicting read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume;

[0007] Generate risk warning information based on the read and write requests and the requested processing volume of the target memory at the next moment to protect power integrity.

[0008] Optionally, predicting the read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume includes:

[0009] Based on the historical read / write requests and the historical request processing volume, determining the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume;

[0010] The read and write requests and the requested processing amount at the next moment after the corresponding moment are used as the read and write requests and the requested processing amount of the target memory at the next moment.

[0011] Optionally, generating risk warning information according to the read and write requests and the requested processing volume of the target storage at the next moment includes:

[0012] If the read-write request and the request processing amount of the target memory at the next moment exceed a preset range, a first risk warning information is generated, the first risk warning information being information of occurrence of a warning;

[0013] If the read-write request and the request processing amount of the target memory at the next moment are in a preset range, a second risk warning information is generated, the second risk warning information being information of non-occurrence of a warning.

[0014] Optionally, if the read-write request and the request processing amount of the target memory at the next moment exceed a preset range, a first risk warning information is generated, the first risk warning information being information of occurrence of a warning, comprising:

[0015] If the read-write request and the request processing amount of the target memory at the next moment are lower than a preset first threshold, an uprush voltage risk warning information is generated;

[0016] If the read-write request and the request processing amount of the target memory at the next moment are higher than a preset second threshold, a downrush voltage risk warning information is generated, the preset first threshold being smaller than the preset second threshold.

[0017] Optionally, the generation of the risk warning information comprises:

[0018] If the risk warning information is the downrush voltage risk warning information, the read-write request is throttled in a direction in which the target memory receives the read-write request, so as to protect power integrity.

[0019] Optionally, the generation of the risk warning information comprises:

[0020] If the risk warning information is the uprush voltage risk warning information, the read-write request is throttled in a direction in which the target memory returns the read-write request, so as to protect power integrity.

[0021] Optionally, the number of the target memories is at least one, the target memory is a display memory, and the power supply is a power supply of the display memory.

[0022] In a second aspect, an embodiment of the present application provides a power integrity protection device, comprising:

[0023] An acquisition module is configured to acquire historical read-write requests, historical request processing amounts, current read-write requests and current request processing amounts of a target memory; the power supply is configured to supply power to the target memory.

[0024] a prediction module, configured to predict the read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume;

[0025] The protection module is used to generate risk warning information according to the read and write requests and the requested processing amount of the target memory at the next moment to protect the integrity of the power supply.

[0026] Optionally, the prediction module includes:

[0027] a time determination unit, configured to determine, based on the historical read / write requests and the historical request processing volume, a time corresponding to the current read / write request and the current request processing volume in the historical read / write requests and the historical request processing volume;

[0028] The prediction unit is configured to use the read and write requests and request processing amount at the next moment after the corresponding moment as the read and write requests and request processing amount of the target memory at the next moment.

[0029] Optionally, the protection module includes:

[0030] a first protection unit, configured to generate first risk warning information if the read and write requests and requested processing volume of the target memory at a next moment exceed a preset range, wherein the first risk warning information is information indicating a warning;

[0031] The second protection unit is configured to generate second risk warning information if the read and write requests and the requested processing volume of the target memory at the next moment are within a preset range, wherein the second risk warning information is information that no warning has occurred.

[0032] The power integrity protection method and apparatus provided by an embodiment of the present invention include: obtaining historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target memory; supplying power to the target memory; predicting the read and write requests and request processing volume of the target memory at the next moment based on the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume; and generating risk warning information based on the read and write requests and request processing volume of the target memory at the next moment to protect power integrity. The power integrity protection method and apparatus provided by an embodiment of the present invention generate risk warning information based on the predicted read and write requests and request processing volume of the target memory at the next moment. If the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, an undershoot voltage risk warning information is generated, and throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests to prevent the power integrity from being affected by the lack of throttling control, thereby protecting the power integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a flow chart of a power integrity protection method provided by the first embodiment of the present invention;

[0034] Figure 2 This is a flow chart of a power integrity protection method provided by the second embodiment of the present invention;

[0035] Figure 3 This is a structural block diagram of a power integrity protection device provided by Embodiment 3 of the present invention;

[0036] Figure 4 This is a structural block diagram of another power integrity protection device provided by the third embodiment of the present invention;

[0037] Figure 5 This is a structural block diagram of a connection between an HBM and a MC provided in the third embodiment of the present invention;

[0038] Figure 6 This is a structural block diagram of a connection between a DFI monitor and a risk pattern detector provided by a third embodiment of the present invention;

[0039] Figure 7 This is a structural block diagram of a risk processor connected to a bus provided by the third embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0041] Example 1

[0042] Figure 1 This is a flow chart of a power integrity protection method provided in a first embodiment of the present invention. This embodiment is applicable to aspects such as protecting the power integrity of a memory. The method can be performed by a power integrity protection device, which can be integrated into an electronic device such as a computer. The electronic device can be implemented in the form of software and / or hardware. The method specifically includes the following steps:

[0043] Step 110: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory; and supply power to the target memory.

[0044] The number of target memories is at least one and may be multiple. The target memory may be a video memory, and the power supply is the power supply of the video memory. The historical read and write requests include historical read requests, historical write requests, and historical read and write requests. The historical request processing volume includes historical read request processing volume, historical write request processing volume, and historical read and write request processing volume. The current read and write requests include current read requests, current write requests, and current read and write requests. The current request processing volume includes current read request processing volume, current write request processing volume, and current read and write request processing volume. The power integrity protection device is communicatively connected to the target memory to obtain the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory.

[0045] Step 120 : Predict the read and write requests and request processing volume of the target memory at the next moment based on historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume.

[0046] Specifically, based on historical read and write requests and historical request processing volume, determine the corresponding moments of the current read and write requests and current request processing volume in the historical read and write requests and historical request processing volume, and use the read and write requests and request processing volume at the next moment of the corresponding moment as the read and write requests and request processing volume of the target memory at the next moment.

[0047] Step 130 : Generate risk warning information based on the read and write requests and requested processing volume of the target memory at the next moment to protect power integrity.

[0048] Specifically, if the target memory's read / write requests and requested processing volume at the next moment exceed a preset range, a first risk warning message is generated, indicating a warning. If the target memory's read / write requests and requested processing volume at the next moment are within the preset range, a second risk warning message is generated, indicating no warning. For example, if the target memory's read / write requests and requested processing volume at the next moment are below a preset first threshold, an undershoot voltage risk warning message is generated, and read / write requests are throttled in the direction in which the target memory receives them to protect power integrity.

[0049] It should be noted that, in this embodiment, the size of the preset range and the preset first threshold can be set according to actual protection requirements and are not limited here.

[0050] The power integrity protection method provided in this embodiment includes: obtaining historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target memory; supplying power to the target memory; predicting the read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume; and generating risk warning information based on the read and write requests and request processing volume of the target memory at the next moment to protect power integrity. The power integrity protection method provided in this embodiment generates risk warning information based on the predicted read and write requests and request processing volume of the target memory at the next moment. If the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, an undershoot voltage risk warning information is generated, and throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests to prevent the power integrity from being affected by the lack of throttling control, thereby protecting power integrity.

[0051] Example 2

[0052] Figure 2 This is a flow chart of a power integrity protection method provided in a second embodiment of the present invention. This embodiment is applicable to aspects such as protecting the power integrity of a memory. The method can be performed by a power integrity protection device, which can be integrated into an electronic device such as a computer. The electronic device can be implemented in the form of software and / or hardware. The method specifically includes the following steps:

[0053] Step 210: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory; and supply power to the target memory.

[0054] The number of target memories is at least one and may be multiple. The target memory may be a video memory, and the power supply is the power supply of the video memory. The historical read and write requests include historical read requests, historical write requests, and historical read and write requests. The historical request processing volume includes historical read request processing volume, historical write request processing volume, and historical read and write request processing volume. The current read and write requests include current read requests, current write requests, and current read and write requests. The current request processing volume includes current read request processing volume, current write request processing volume, and current read and write request processing volume. The power integrity protection device is communicatively connected to the target memory to obtain the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory.

[0055] Step 220: Based on the historical read / write requests and the historical request processing volume, determine the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume.

[0056] Specifically, if the read / write requests and request throughput at a time before the current time, such as time k, are the same as the current read / write requests and request throughput, then the corresponding time is determined to be time k. If the current read / write request and request throughput do not have a corresponding time in the historical read / write requests and request throughput, then the time in the historical read / write requests and request throughput that is closest to the current read / write request and request throughput is used as the corresponding time.

[0057] Step 230: The read / write request and request processing amount at the next moment of the corresponding moment are used as the read / write request and request processing of the target memory at the next moment.

[0058] Specifically, if the read / write requests and request processing volume at a certain moment before the current moment, such as moment k, are the same as the current read / write requests and request processing volume, then the read / write requests and request processing volume at moment k+1 will be used as the read / write requests and request processing at the next moment after the current moment.

[0059] Step 240 : If the read and write requests and the requested processing amount of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning message is generated.

[0060] The read / write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, which may be that the total amount of the read / write requests and request processing volume is lower than the preset first threshold. If the read / write requests and request processing volume of the target memory at the next moment are lower than the preset first threshold, it indicates that the read / write requests and request processing volume of the target memory at the next moment are too low, and there is a risk of overshoot voltage, and therefore an overshoot voltage risk warning message is generated.

[0061] Step 250: If the read and write requests and the requested processing volume of the target memory at the next moment are higher than a preset second threshold, an undershoot voltage risk warning message is generated, and the preset first threshold is lower than the preset second threshold.

[0062] The read / write requests and request processing volume of the target memory at the next moment are higher than a preset second threshold, which may be the total amount of the read / write requests and request processing volume being higher than the preset second threshold. If the read / write requests and request processing volume of the target memory at the next moment are higher than the preset second threshold, it indicates that the read / write requests and request processing volume of the target memory at the next moment are too high, and there is a risk of undershoot voltage, and therefore an undershoot voltage risk warning message is generated.

[0063] In addition, if the read and write requests and the requested processing volume of the target memory at the next moment are within a preset range, a message indicating that no warning has occurred is generated.

[0064] Step 260: If the risk warning information is an undershoot voltage risk warning information, throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests to protect power integrity.

[0065] Specifically, throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests, so as to prevent the target memory from receiving too many read and write requests and request processing volume at the next moment and affecting the power integrity of the target memory.

[0066] Step 270: If the risk warning information is an overshoot voltage risk warning information, throttling control is performed on the read and write requests in the direction in which the target memory returns the read and write requests to protect power integrity.

[0067] Specifically, throttling control is performed on the read and write requests in the direction in which the target memory returns the read and write requests, to prevent the target memory from having too low a read and write request and request processing volume at the next moment, thereby affecting the power integrity of the target memory.

[0068] It should be noted that, in this embodiment, the preset range and the size of each preset threshold can be set according to actual protection requirements and are not limited here.

[0069] The power integrity protection method provided in this embodiment generates warning information based on the predicted read and write requests and request processing of the target memory at the next moment. If the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning information is generated, and the read and write requests are throttled in the direction in which the target memory returns the read and write requests. If the read and write requests and request processing volume of the target memory at the next moment are higher than a preset second threshold, an undershoot voltage risk warning information is generated, and the read and write requests are throttled in the direction in which the target memory receives the read and write requests, thereby preventing overshoot voltage risks and undershoot voltage risks and protecting power integrity.

[0070] Example 3

[0071] Figure 3 This is a structural block diagram of a power integrity protection device provided by the third embodiment of the present invention. Figure 3 The power integrity protection device includes: an acquisition module 310, a prediction module 320 and a protection module 330; wherein the acquisition module 310 is used to obtain historical read and write requests, historical request processing volume, current read and write requests and current request processing volume of the target memory; the power supply supplies power to the target memory; the prediction module 320 is used to predict the read and write requests and request processing volume of the target memory at the next moment based on the historical read and write requests, historical request processing volume, current read and write requests and current request processing volume; the protection module 330 is used to generate risk warning information based on the read and write requests and request processing volume of the target memory at the next moment to protect the power integrity.

[0072] Based on the above embodiment, the prediction module 320 includes:

[0073] A time determination unit, configured to determine, based on historical read / write requests and historical request processing amounts, the times corresponding to the current read / write requests and the current request processing amount in the historical read / write requests and historical request processing amounts;

[0074] The prediction unit is configured to use the read and write requests and request processing amount at the next moment of the corresponding moment as the read and write requests and request processing amount of the target memory at the next moment.

[0075] In one embodiment, the protection module 330 includes:

[0076] a first protection unit, configured to generate first risk warning information if the read and write requests and requested processing volume of the target memory at a next moment exceed a preset range, the first risk warning information being information indicating a warning;

[0077] The second protection unit is configured to generate second risk warning information if the read and write requests and the requested processing volume of the target memory at the next moment are within a preset range, where the second risk warning information is information that no warning has occurred.

[0078] Optionally, the above-mentioned first protection unit includes: a first information generation subunit and a second information generation subunit; wherein, the first information generation subunit is used to generate undershoot voltage risk warning information if the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold; the second information generation subunit includes generating overshoot voltage risk warning information if the read and write requests and request processing volume of the target memory at the next moment are higher than a preset second threshold, and the preset first threshold is less than the preset second threshold.

[0079] Optionally, the protection module 330 includes: a first throttling control unit, which is used to throttle the read and write requests in the direction in which the target memory receives the read and write requests if the risk warning information is undershoot voltage risk warning information, so as to protect power integrity.

[0080] Optionally, the protection module 330 includes: a second throttling control unit, which is used to throttle the read and write requests in the direction in which the target memory returns the read and write requests if the risk warning information is an overshoot voltage risk warning information, so as to protect the power integrity.

[0081] Figure 4 This is a structural block diagram of another power integrity protection device provided by the third embodiment of the present invention. Figure 5 This is a structural block diagram of a connection between HBM and MC provided by the third embodiment of the present invention. Figure 6 This is a structural block diagram of a connection between a DFI monitor and a risk pattern detector provided by the third embodiment of the present invention. Figure 7 This is a structural block diagram of a risk processor connected to a bus provided by the third embodiment of the present invention.Figures 4-7 The power integrity protection system includes a DFI (Double Data Rate (DDR PHY) Interface) monitor 10, a risk pattern detector 20, and a risk processor 30. The DFI protocol collects the load (number of instructions) between a specific memory controller (MC) and an HBM PHY (High Bandwidth Memory Physical Interface), ensuring a configurable sampling period. The DFI monitor 10 (equivalent to the acquisition module) collects DFI events, namely read and write requests, and aggregates them for the risk pattern detector. The detection results are then passed to the risk processor, which takes protective measures based on the situation. Each HBM channel corresponds to an independent DFI monitor. Each DFI monitor supports statistics for multiple DFI instructions (read, write, read+write), and each DFI instruction has a separate counter. Each DFI monitor supports a configurable statistics window (e.g., 128, 256, 512, or 1024 cycles), supports infinite periodic statistics, and supports shadow caching. The collected information from the previous cycle is pushed into the shadow cache, and the counter is reset to start statistics for the next cycle. At the end of each DFI monitor statistical cycle, the risk pattern detector 20 (equivalent to the aforementioned prediction module) reads data from the DFI monitor's shadow cache, accumulates the values ​​of different instruction counters in the DFI monitor, selects one of the instruction counters via a selector, updates historical DFI data, which stores DFI data from the past N-1 cycles (N is an integer greater than 1, the specific value being configured based on design requirements), performs risk warning matching, and generates risk prompts. The risk processor 30 (equivalent to the aforementioned protection module) performs protection based on the risk prompts and unreturned bus requests, generating either a first risk warning message or a second risk warning message. The second risk warning message indicates a warning (a value of 1 for the corresponding instruction) or a non-warning message (a value of 0 for the corresponding instruction). When the first risk warning message is an undershoot voltage risk warning message, control logic is inserted in the direction of the target memory receiving read / write requests to throttle the read / write requests. When the first risk warning message is an overshoot voltage risk warning message, control logic is inserted in the direction of the target memory returning read / write requests to throttle the read / write requests to protect power integrity.

[0082] The power integrity protection device provided in this embodiment and the power integrity protection method provided in any embodiment of the present invention belong to the same inventive concept and have corresponding beneficial effects. For technical details not detailed in this embodiment, please refer to the power integrity protection method provided in any embodiment of the present invention.

[0083] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A power integrity protection method, characterized in that: include: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target storage; The power supply supplies power to the target memory; Predicting read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume; generating risk warning information based on the read and write requests and the requested processing volume of the target memory at a next moment to protect power integrity; The risk warning information is generated to protect the integrity of the power supply, including: If the read and write requests and the requested processing amount of the target memory at the next moment are lower than a preset first threshold, generating an overshoot voltage risk warning message; If the read and write requests and the requested processing volume of the target memory at the next moment are higher than a preset second threshold, generating an undershoot voltage risk warning message, and the preset first threshold is lower than the preset second threshold; If the risk warning information is an undershoot voltage risk warning information, throttling the read and write requests in the direction in which the target memory receives the read and write requests to protect power integrity; If the risk warning information is an overshoot voltage risk warning information, throttling control is performed on the read / write request in the direction in which the target memory returns the read / write request to protect power integrity.

2. The power integrity protection method according to claim 1, wherein: The predicting, based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume, of the target memory at a next moment includes: Based on the historical read / write requests and the historical request processing volume, determining the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume; The read and write requests and the requested processing amount at the next moment after the corresponding moment are used as the read and write requests and the requested processing amount of the target memory at the next moment.

3. The power integrity protection method according to claim 1, wherein: Generating risk warning information according to the read and write requests and the requested processing volume of the target storage at the next moment includes: If the read and write requests and requested processing volume of the target storage at the next moment exceed a preset range, generating first risk warning information, the first risk warning information being information indicating a warning; If the read and write requests and the requested processing volume of the target memory at the next moment are within a preset range, a second risk warning message is generated, where the second risk warning message is information that no warning has occurred.

4. The power integrity protection method according to claim 1, wherein: The number of the target memory is at least one, the target memory is a video memory, and the power supply is a power supply of the video memory.

5. A power integrity protection device, characterized in that: include: An acquisition module is used to acquire historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target storage; The power supply supplies power to the target memory; a prediction module, configured to predict the read and write requests and request processing volume of the target memory at a next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume; A protection module, configured to generate risk warning information based on the read and write requests and the requested processing volume of the target memory at a next moment, so as to protect the integrity of the power supply; The protection module includes: a first information generating unit, configured to generate overshoot voltage risk warning information if the read and write requests and the requested processing amount of the target memory at a next moment are lower than a preset first threshold; a second information generating unit, configured to generate an undershoot voltage risk warning message if the read and write requests and the requested processing amount of the target memory at a next moment are higher than a preset second threshold, and the preset first threshold is lower than the preset second threshold; a first throttling control unit, configured to, if the risk warning information is undershoot voltage risk warning information, perform throttling control on the read / write request in a direction in which the target memory receives the read / write request, so as to protect power integrity; The second throttling control unit is configured to, if the risk warning information is overshoot voltage risk warning information, perform throttling control on the read / write request in the direction in which the target memory returns the read / write request, so as to protect power integrity.

6. The power integrity protection device according to claim 5, characterized in that: The prediction module includes: a time determination unit, configured to determine, based on the historical read / write requests and the historical request processing volume, a time corresponding to the current read / write request and the current request processing volume in the historical read / write requests and the historical request processing volume; The prediction unit is configured to use the read and write requests and request processing amount at the next moment after the corresponding moment as the read and write requests and request processing amount of the target memory at the next moment.

7. The power integrity protection device according to claim 5, characterized in that: The protection module includes: a first protection unit, configured to generate first risk warning information if the read and write requests and requested processing volume of the target memory at a next moment exceed a preset range, wherein the first risk warning information is information indicating a warning; The second protection unit is configured to generate second risk warning information if the read and write requests and the requested processing volume of the target memory at the next moment are within a preset range, wherein the second risk warning information is information that no warning has occurred.

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