A digital circuit pattern mining method and system

Abstract

The present invention discloses a method and system for mining digital circuit patterns, the method comprising: S1, extracting logic gate unit information in a netlist, and constructing a directed acyclic graph; S2, traversing all nodes of the directed acyclic graph, and using a preset pattern code to record the patterns and their numbers corresponding to the nodes; S3, merging all isomorphic patterns, and then arranging them in descending order according to the number of patterns; S4, traversing the sorted isomorphic pattern codes in sequence, traversing the nodes at the same time, marking the patterns to which the nodes belong, updating the logic function of the patterns, and eliminating the patterns whose pattern node coverage is lower than a preset threshold; S5, comparing the logic function corresponding to the patterns in the pattern code with the known unit logic function function list one by one, checking whether the logic function is equivalent, and recording the logic function of the new pattern and its pattern code; S6, outputting the new patterns and their numbers in sequence from small to large according to the output number of the patterns. The present invention has the advantages of high mining efficiency.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of integrated circuit electronic design automation, and specifically to a digital circuit pattern mining method and system. Background Art

[0002] Electronic Design Automation (EDA) refers to the use of automated tools to achieve efficient and high-quality design in the process of integrated circuit design (IC design). As the scale of integrated circuits reaches billions of transistors, manual design has become impractical, and EDA technology has become particularly critical. It covers all stages from circuit design, verification to manufacturing, greatly accelerating the design process and improving design accuracy and efficiency. A very important link in integrated circuit design is logic synthesis, which refers to the process of converting register-transfer level (RTL) circuits into gate-level netlists based on standard cell libraries. The quality of the synthesized gate-level netlist has a certain impact on the subsequent process, which depends not only on the algorithm of the synthesis tool, but also on the design of the standard cell library. If a certain pattern appears frequently in the synthesized netlist, then a new logic unit is customized for the logic function of this pattern, and the power consumption, timing, area and other performance of this new unit are significantly optimized compared to the original pattern, then replacing these patterns will significantly improve the performance of the synthesized gate-level netlist. This method of finding suitable circuit patterns is called pattern mining, which mainly requires consideration of two aspects: the mining method and whether the found pattern is suitable for customized design implementation. Summary of the invention

[0003] In view of the technical problems existing in the prior art, the present invention provides a digital circuit pattern mining method and system with high operating efficiency.

[0004] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0005] A digital circuit pattern mining method, comprising the steps of:

[0006] S1, extract the logic gate unit information in the netlist and construct a directed acyclic graph;

[0007] S2, traverse all nodes of the directed acyclic graph, and use the preset pattern code to record the patterns and their quantities corresponding to the nodes;

[0008] S3, performing a circular comparison based on the connection relationship information recorded in the pattern code to determine whether the pattern code is isomorphic, merging all isomorphic patterns, and then arranging the isomorphic pattern codes in descending order according to the number of patterns contained in each pattern code;

[0009] S4, traverse the sorted isomorphic pattern codes in sequence, traverse the nodes at the same time, mark the pattern to which the node belongs, re-record the pattern code and its corresponding quantity, update the logical function of the pattern, and finally filter the obtained results to eliminate the pattern whose pattern node coverage is lower than the preset threshold;

[0010] S5. Compare the logic functions corresponding to the patterns in the pattern code with the known unit logic function list one by one, use the logic paradigm decomposition to find out the logic expressions that are not in the logic function list in advance, use the equivalence check function to check whether the logic function is equivalent, and record the logic function of the new pattern and its pattern code;

[0011] S6. Output new patterns and their quantities in order from small to large according to the output quantity of the patterns.

[0012] Preferably, the specific process of step S2 is: traverse all nodes, regard each node and all nodes connected to its input pins as a pattern, record them with a preset pattern code, and record the number of patterns corresponding to each pattern code; wherein the preset pattern code records the root node, all input pins of the root node, and all child node information connected to the input pin of the root node.

[0013] Preferably, the preset mode code in step S2 is a character string, and its structure is:

[0014] ROOT_NODE: PIN1[SUB_NODE], PIN2[SUB_NODE1, SUB_NODE2];

[0015] Among them, ROOT_NODE is the root node; PIN is all the input pins of the root node; SUB_NODE is the upstream node information connected to each pin.

[0016] Preferably, in step S3, whether the pattern code is isomorphic is determined by an isomorphism check function, and the specific steps are:

[0017] S301, compare the root nodes ROOT_NODE of the two pattern codes by slicing the string. If they are different, it means that the root nodes of the patterns are not the same standard unit, and return failure; if they are the same, proceed to the next step of comparison;

[0018] S302, compare the number of pins of the two mode codes; if they are different, return failure; if they are the same, proceed to the next step of comparison;

[0019] S303, create two dictionaries to store each pin PIN and its corresponding subnode SUB_NODE; the key of the dictionary is the first letter of the pin, and the value of the dictionary is the subnode set; the first letters of the pins with equivalent functions are the same by default, and the first letters of the pins with unequal functions are different, and the specific modification is made according to the internal format of the library file;

[0020] S304, compare the number and content of each element in the two dictionaries, and calculate the number of each type of child nodes of each pin when comparing the content; if there is an inconsistency, it means that the child nodes connected to it are not completely consistent and cannot be regarded as isomorphic patterns, and failure is returned; if they are completely consistent, success is returned.

[0021] Preferably, in step S3, the specific process of merging all isomorphic patterns is as follows: loop through the pattern codes, compare them two by two, and directly merge them if they are isomorphic; use two lists to store the pattern codes that have been processed and all the pattern codes that need to be processed respectively; directly skip the pattern codes that have been processed; the processed pattern codes are regarded as discarded, and the pattern combinations they contain are automatically merged into the pattern combination set contained in another isomorphic pattern code, and finally update the pattern code and its corresponding pattern quantity.

[0022] Preferably, the specific process of step S4 is:

[0023] S401, sequentially use the descending isomorphic pattern codes as the search target pattern codes, traverse all nodes, and check the stopType attribute of the node; if it is True, skip the node directly; if the node is set to be skipped in advance or has been occupied by the previous pattern mark, the node attribute stopType will be set to True, that is, the node is not considered and skipped;

[0024] S402, taking the current node as the root, absorbing the nodes connected to its input pins and creating a pattern, generating a pattern code, and using an isomorphism check function to check the pattern code and the target pattern code. If the pattern code is the same or isomorphic to the currently searched pattern code, proceed to the next step. If not, skip the current node and continue;

[0025] S403, marking the node attribute pattern covered by each pattern in sequence according to the sorting order, and the node whose pattern is not empty will not be repeatedly marked by other patterns; that is, when two patterns cover overlapping nodes, the pattern corresponding to the pattern code sorted later will be discarded;

[0026] S404. If an isomorphic pattern combination is found, the pattern update functions updatePin and setFunction are used simultaneously to update the pins and logic function functions of the pattern to obtain a complete simplified logic expression of the entire pattern.

[0027] Preferably, the specific process of updating using the mode update function setFunction is:

[0028] S4041, traverse the input pins of all nodes covered by the pattern; if the node connected to the input pin is empty or does not belong to the pattern, it means that the pin is the input pin of the entire pattern and is recorded in the pattern input pin set; otherwise, it means that it is an internal pin;

[0029] S4042, traverse the output pins of all nodes covered by the pattern; if the node connected to the output pin is empty or does not belong to the pattern, it means that the pin is the output pin of the entire pattern and is recorded in the pattern output pin set; otherwise, it means that it is an internal pin;

[0030] S4043, traverse the output pins of the pattern, and traverse the nodes that make up the pattern at the same time, and find the node to which the output pin belongs; starting from the node, record it as the root node, explore the input pins towards the input end, if the current input pin is not the input pin of the pattern, replace the node logic expression connected to it to the position of the corresponding pin of the root node, so as to form a new logic expression; if the current input pin is the input pin of the pattern, do not change it; when all the pins of the root node logic expression are replaced with the input pins of the pattern, the loop ends;

[0031] S4044, replace the name of the obtained logical expression, standardize its naming method, and make it consistent with the naming convention of the logical expressions in the existing logical function list, and store it in the pattern attribute oriFunctions; record the original logical expression of the pattern, store it in the pattern attribute oriFunctions, and store the replaced logical expression in the pattern attribute cmpFunctions;

[0032] S4045. Record the found pattern into a pre-created dictionary, where the value of the dictionary is a sub-dictionary, the key of the sub-dictionary is the number of output pins of the pattern, and the key is the corresponding pattern; sort the dictionary in descending order with the number of patterns as the first keyword and the number of output pins as the second keyword; output the original pattern information and the pattern information of all multiple outputs; patterns that are less than the preset coverage threshold will not be output.

[0033] Preferably, the specific process of step S5 is:

[0034] S501, generating a logic function expression for each mode according to the style of the logic expression in the existing logic function list, so that the generated expression conforms to the style of the logic expression in the existing logic function list;

[0035] S502, compare the strings one by one with the logical expressions in the existing logical function list; if the same string is found, it means that the mode is already a standard unit and it is skipped; if the same string is not found, proceed to the next step;

[0036] S503, decomposing the logical paradigm, and comparing the characteristics of the logical paradigm with the logical functions in the existing logical function function list; if they are different, then terminate the comparison with the logical function function in advance, and continue to compare the logical expressions in the next logical function function list; if they are the same, proceed to the next step;

[0037] S504, perform an equivalence check on the logical function to ensure that there are no problems with the equivalence check; if the equivalence check passes, record it in the result and prepare to output; if the equivalence check fails, continue to compare the logical expressions in the next logical function function list; until the logical expressions in all logical function function lists have been compared and are not equivalent to the logical function functions of the pattern, it means that the pattern is a new pattern that has not been recorded, and it is recorded and output.

[0038] Preferably, in step S504, the specific process of equivalence checking is:

[0039] S5041. Compare the string lengths of the two logical expressions; if they are different, it means that the two are not equivalent and the comparison is skipped; if they are the same, further equivalence check is performed;

[0040] S5042, determine whether the logical expression is expressed in the main disjunction form; if so, segment it according to the disjunction symbol; if not, segment it according to the conjunction symbol;

[0041] S5043, compare the lengths of the two lists after segmentation; if they are the same, perform further equivalence check; if they are not the same, it means that the two logical expressions are not equivalent, and skip this mode;

[0042] S5044. Use the sympy library function of Python to perform an equivalence check until all logical expressions in the logical function list have been compared and are not equivalent to the logical function of the pattern. This means that the pattern is a new pattern that has not been recorded. Record this pattern in the result list.

[0043] The present invention also discloses a digital circuit pattern mining system, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, and when the computer program is run by the processor, the steps of the method described above are executed.

[0044] Compared with the prior art, the advantages of the present invention are:

[0045] The digital circuit pattern mining method of the present invention can efficiently extract and analyze the logic gate unit information in the circuit by constructing a directed acyclic graph; the patterns and their numbers corresponding to the nodes are recorded by the designed pattern code to ensure the systematicness and consistency of the analysis process; whether the pattern codes are isomorphic is determined by cyclic comparison, all isomorphic patterns are effectively merged, and redundant information is reduced; and the validity and correctness of the logical expression can be guaranteed by comparing with the known unit logic function list.

[0046] The present invention is based on a novel pattern code expression, which can express the composition structure of the pattern more intuitively, making it convenient for technicians to identify and carry out subsequent work; at the same time, the present invention fully considers the ambiguity of the pattern code, and analyzes the isomorphism between the patterns in detail, and makes targeted changes so that the algorithm can identify isomorphic pattern codes and merge them; in addition, the present invention also extracts pattern combinations with multiple output ports, which has important reference value in screening customized standard units. The present invention considers time overhead in many places and optimizes it, discovers pattern combinations that do not meet the requirements in advance, ends the current cycle and enters the next cycle, effectively improves the operating efficiency, and compared with the algorithm running time before optimization, the optimized algorithm running time is significantly shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a flow chart of a digital circuit pattern mining method in an embodiment of the present invention.

[0048] Figure 2 It is a data structure diagram of the connection relationship of the gate-level netlist units of the present invention.

[0049] Figure 3 This is a flow chart of the pattern logic expression updating method of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0051] like Figure 1 As shown, the digital circuit pattern mining method provided by the embodiment of the present invention includes the steps of:

[0052] S1, extract the logic gate unit information in the netlist and construct a directed acyclic graph;

[0053] S2, traverse all nodes of the directed acyclic graph, and use the designed pattern code to record the patterns and their quantities corresponding to the nodes;

[0054] S3, according to the connection relationship information recorded in the pattern code of the result of step S2, cyclic comparison is performed to determine whether the pattern codes are isomorphic, and all isomorphic patterns are merged (isomorphic patterns refer to patterns with the same logical functions but different actual node connection relationships and connection orders), and the isomorphic pattern codes are arranged in descending order according to the number of patterns contained in each pattern code; wherein an isomorphism check function is used to check whether two pattern codes are isomorphic;

[0055] S4, according to the descending order of the number of patterns corresponding to the isomorphic pattern codes sorted in step S3, traverse the pattern codes in turn, traverse the nodes at the same time, mark the patterns to which the nodes belong, re-record the pattern codes and their corresponding numbers, update the logical function of the pattern, and finally screen the obtained results to eliminate the patterns whose pattern node coverage (the number of patterns multiplied by the number of nodes constituting the pattern divided by the total number of nodes) is lower than the preset threshold;

[0056] S5. Compare the logic functions corresponding to the patterns in the pattern code with the known unit logic function list one by one, use the logic paradigm decomposition to find out the logic expressions that are not in the logic function list in advance, use the equivalence check function to check whether the logic function is equivalent, and record the logic function of the new pattern and its pattern code;

[0057] S6. Output new patterns and their quantities in order from small to large according to the output quantity of the patterns.

[0058] The digital circuit pattern mining method of the present invention can efficiently extract and analyze the logic gate unit information in the circuit by constructing a directed acyclic graph; the patterns and their numbers corresponding to the nodes are recorded by the designed pattern code to ensure the systematicness and consistency of the analysis process; whether the pattern codes are isomorphic is determined by cyclic comparison, all isomorphic patterns are effectively merged, and redundant information is reduced; and the validity and correctness of the logical expression can be guaranteed by comparing with the known unit logic function list.

[0059] In a specific embodiment, the specific process of step S1 includes:

[0060] Parse the netlist file and standard library unit file, and use Figure 2 The data structure shown builds direct connections between units to form a directed acyclic graph.

[0061] The standard library unit file is parsed while the logic function expressions of each unit of the current standard cell library are saved. Specifically, a list is used to save the string form of the logic function expressions of each unit of the current standard cell library, which is recorded as the existing logic function function list.

[0062] Parsing standard library files can be done efficiently and quickly using the python scripts written in Python, or accurately using the liberty library of Python. For netlist files, use the pyverilog library functions of Python for accurate parsing.

[0063] In a specific embodiment, the specific process of step S2 includes:

[0064] Traverse all nodes, treat each node and all nodes connected to its input pins as a pattern, record them with the designed pattern code, and record the number of patterns corresponding to each pattern code. The designed pattern code records the root node, all input pins of the root node, and all child nodes connected to the input pin of the root node.

[0065] Specifically, the pattern code is designed as a string with the following structure:

[0066] ROOT_NODE: PIN1[SUB_NODE], PIN2[SUB_NODE1, SUB_NODE2];

[0067] Specifically, the mode code stores the root node ROOT_NODE, all the input pins PIN of the root node, and the upstream node information SUB_NODE connected to each pin. In this step, the mode overlap between nodes is not considered, so all possible modes and quantities in the current netlist are recorded as the basis for the subsequent formal search mode.

[0068] In a specific embodiment, the specific process of step S3 includes: inputting the pattern code to be compared, decomposing the pattern code according to the designed pattern code feature relationship, cyclically comparing the pattern codes according to the node connection information obtained by the decomposition, using the isomorphism check function to determine whether the pattern codes are isomorphic, and merging the corresponding pattern quantities of the two isomorphic pattern codes to obtain the actual number of patterns represented by the same type of pattern codes, and then sorting the pattern codes in descending order according to the pattern quantity.

[0069] Specifically, the process of the isomorphism check function to determine whether the pattern code is isomorphic is as follows:

[0070] S301. First, compare the root nodes ROOT_NODE of the two pattern codes by slicing the string. If they are different, it means that the root nodes of the patterns are not the same standard unit, and return failure; if they are the same, proceed to the next step of comparison;

[0071] S302, compare the number of pins of the two mode codes. Generally, the number of pins after checking the root node is the same, which is used as program integrity verification; if different, return failure; if the same, proceed to the next step of comparison;

[0072] S303, create two dictionaries to store each pin PIN and its corresponding subnode SUB_NODE; the key of the dictionary is the first letter of the pin, and the value of the dictionary is the subnode set; the first letters of the pins with equivalent functions are the same by default, and the first letters of the pins with unequal functions are different, and the specific modification is made according to the internal format of the library file;

[0073] S304. Finally, compare the number and content of each element in the two dictionaries. When comparing the content, calculate the number of each type of child nodes of each pin. If there is inconsistency, it means that the child nodes connected to it are not completely consistent and cannot be regarded as isomorphic patterns, and return failure. If they are completely consistent, return success.

[0074] S305 , updating the merged dictionary 1, retaining only one isomorphic pattern code, and sorting the pattern codes in descending order according to the number of patterns to obtain a list 1.

[0075] The specific process of merging all isomorphic patterns is as follows: loop through the pattern codes, compare them pairwise, and merge them directly if they are isomorphic; two lists are used to store the pattern codes that have been processed and all the pattern codes that need to be processed respectively; since the time complexity of comparing a list element pairwise is N squared, using a list to record all the pattern codes that have been processed can directly skip the pattern codes that have been processed, which can speed up the program to a certain extent, but the time complexity is still N squared; the pattern codes that have been processed are regarded as discarded, and the pattern combinations they contain are automatically merged into the pattern combination set contained in another isomorphic pattern code, and finally the pattern code and its corresponding pattern quantity are updated.

[0076] In step S4, the pattern codes are extracted from the sorted pattern codes in sequence as the search target pattern codes, and all nodes are traversed; if the currently traversed node is set to be skipped in advance (for example, the node is a macro unit or other unit that is not considered for customization) or has been occupied by the previous pattern mark, the node is not considered and skipped; the currently traversed node is taken as the root, the nodes connected to its input pins are absorbed and created as a pattern, and its pattern code is generated according to the pre-designed design, and the isomorphism check function is used to determine whether the pattern code is isomorphic to the currently searched pattern code. If not, the current node is discarded and the next node is traversed; if the pattern code created by the current node is determined to be isomorphic to the target pattern code, the pattern update function is used to update the pattern to obtain the complete simplified logical expression of the entire pattern. If this pattern has multiple outputs, all outputs will be recorded. A well-designed data structure is used to store the pattern code, pattern, pattern output number and corresponding pattern number. When traversing the pattern code, a coverage threshold is set, and the pattern whose current pattern code coverage is less than the coverage threshold will not be used as output.

[0077] The mode update function is written, including updating the input and output pin list of the entire module and updating the mode logic function; through this update function, each output pin will correspond to a logic function, and all the operation variables of this logic function are composed of the input pins of the entire mode; the obtained logical expression will be name replaced and its naming method will be standardized.

[0078] In specific applications, the specific process of step S4 is:

[0079] S401, taking the pattern codes in List 1 as the search target pattern codes in turn, traversing all nodes, checking the stopType attribute of the node, and directly skipping the node if it is True; if the node is set to be skipped in advance (for example, the node is a macro unit or other unit that is not considered for customization) or has been occupied by a previous pattern mark, the node attribute stopType will be set to True, that is, the node will not be considered and will be skipped;

[0080] S402, taking the current node as the root, absorbing the nodes connected to its input pins and creating a pattern, generating a pattern code, and using an isomorphism check function to check the pattern code and the target pattern code. If the pattern code is the same or isomorphic to the currently searched pattern code, proceed to the next step. If not, skip the current node and continue;

[0081] S403, marking the node attribute pattern covered by each pattern in sequence according to the sorting order, and the node whose pattern is not empty will not be repeatedly marked by other patterns; that is, when the nodes covered by two patterns overlap, the pattern corresponding to the pattern code sorted later in list one will be discarded;

[0082] S404. If an isomorphic pattern combination is found, the pattern update functions updatePin and setFunction are used simultaneously to update the pins and logic function functions of the pattern to obtain a complete simplified logic expression of the entire pattern.

[0083] like Figure 3 As shown, the specific process of updating the mode update function setFunction is as follows:

[0084] S4041, traverse the input pins of all nodes covered by the pattern. If the node connected to the input pin is empty or does not belong to the pattern, it means that the pin is the input pin of the entire pattern and is recorded in the pattern input pin set. Otherwise, it means that it is an internal pin.

[0085] S4042, traverse the output pins of all nodes covered by the pattern. If the node connected to the output pin is empty or does not belong to the pattern, it means that the pin is the output pin of the entire pattern and is recorded in the pattern output pin set. Otherwise, it means that it is an internal pin.

[0086] S4043, traverse the output pins of the pattern, and traverse the nodes that make up the pattern at the same time, and find the node to which the output pin belongs; starting from the node, record it as the root node, and explore the input pins towards the input end. If the current input pin is not the input pin of the pattern, replace the node logic expression connected to it with the position of the corresponding pin of the root node, so as to form a new logic expression. If the current input pin is the input pin of the pattern, no change is made; when all the pins of the root node logic expression are replaced with the input pins of the pattern, the loop ends;

[0087] S4044, replace the name of the obtained logical expression, standardize its naming method, and make it consistent with the naming convention of the logical expressions in the existing logical function list, and store it in the pattern attribute oriFunctions; record the original logical expression of the pattern, store it in the pattern attribute oriFunctions, and store the replaced logical expression in the pattern attribute cmpFunctions;

[0088] S4045. Record the found pattern into the pre-created dictionary 3, where the value of the dictionary is a sub-dictionary, the key of the sub-dictionary is the number of output pins of the pattern, and the key is the corresponding pattern; sort the dictionary 3 in descending order with the number of patterns as the first keyword and the number of output pins as the second keyword; output the original pattern information and the pattern information of all multiple outputs; the pattern less than the preset coverage threshold will not be output. In this example, the coverage threshold is 0.01.

[0089] Optionally, after marking all the modes and nodes involved in a mode code, clear the marks of all nodes. If needed, enabling this option will record the total number of times a single mode appears in the netlist.

[0090] In a specific embodiment, the specific process of step S5 is:

[0091] S501, generating a logic function expression for each mode according to the style of the logic expression in the existing logic function list, and making the generated expression conform to the style of the logic expression in the existing logic function list as much as possible;

[0092] S502, compare the strings one by one with the logical expressions in the existing logical function list; if the same string is found, it means that the mode is already a standard unit and is skipped; if the same string is not found, proceed to the next step of equivalence check;

[0093] S503, decomposing the logical paradigm, and comparing the characteristics of the logical paradigm with the logical functions in the existing logical function function list; if they are different, then terminating the comparison with the logical function function in advance, and continuing to compare the logical expressions in the next logical function function list; if they are the same, then continuing further equivalence check;

[0094] S504. Use the logic function equivalence check algorithm or the relevant python library to perform a complete and detailed equivalence check on the logic function to ensure that there are no problems with the equivalence check; if the equivalence check passes, record it in the result and prepare for output; if the equivalence check fails, continue to compare the logical expressions in the next logic function function list; until the logical expressions in all logic function function lists have been compared and are not equivalent to the logic function of the mode, it means that the mode is an unrecorded new mode, which can guide the customization of the unit, and it is recorded and output.

[0095] Specifically, in step S504, the specific process of equivalence checking is as follows:

[0096] S5041. First, compare the string lengths of the two logical expressions; if they are different, it means that the two are not equivalent and skip; if they are the same, perform further equivalence check;

[0097] S5042, then, determine whether the logical expression is expressed in the main disjunction form; if so, segment it according to the disjunction symbol; if not, segment it according to the conjunction symbol;

[0098] S5043, then, compare the lengths of the two lists after segmentation; if they are the same, perform further equivalence check; if they are not the same, it means that the two logical expressions are not equivalent, and skip this mode;

[0099] S5044. Finally, use the sympy library function of Python to perform an equivalence check (this step is relatively time-consuming, so it is placed at the last step. The previous pre-judgment is used to find inequivalent logical expressions in advance to reduce unnecessary time expenditure);

[0100] S5045. Until all logical expressions in the logical function list have been compared and are not equivalent to the logical function of the pattern, it means that the pattern is a new pattern that has not been recorded, and this pattern is recorded in the result list.

[0101] The present invention is based on a novel pattern code expression, which can express the composition structure of the pattern more intuitively, making it convenient for technical personnel to identify and carry out subsequent work; at the same time, the present invention fully considers the ambiguity of the pattern code, and analyzes the isomorphism between the patterns in detail, and makes targeted changes so that the algorithm can recognize isomorphic pattern codes and merge them; in addition, the present invention also extracts pattern combinations with multiple output ports, which has important reference value in screening customized standard units.

[0102] The algorithm of the present invention takes time overhead into consideration and performs optimization in many places, discovers pattern combinations that do not meet the requirements in advance, ends the current loop and enters the next loop, effectively improving the operating efficiency of the algorithm. Compared with the algorithm running time before optimization, the running time of the optimized algorithm is significantly shortened.

[0103] The present invention also discloses a digital circuit pattern mining system, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is executed by the processor, the steps of the above method are executed. The mining system of the present invention corresponds to the above mining method and also has the advantages described in the above mining method.

[0104] The present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiment can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. Computer-readable storage media include: any entity or device that can carry computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. The memory is used to store computer programs and / or modules. The processor implements various functions by running or executing computer programs and / or modules stored in the memory, and calling data stored in the memory. The memory may include a high-speed random access memory and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0105] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A digital circuit pattern mining method, characterized in that: Includes steps: S1, extract the logic gate unit information in the netlist and construct a directed acyclic graph; S2, traverse all nodes of the directed acyclic graph, and use the preset pattern code to record the patterns and their quantities corresponding to the nodes; S3, performing a circular comparison based on the connection relationship information recorded in the pattern code to determine whether the pattern code is isomorphic, merging all isomorphic patterns, and then arranging the isomorphic pattern codes in descending order according to the number of patterns contained in each pattern code; S4, traverse the sorted isomorphic pattern codes in sequence, traverse the nodes at the same time, mark the pattern to which the node belongs, re-record the pattern code and its corresponding quantity, update the logical function of the pattern, and finally filter the obtained results to eliminate the pattern whose pattern node coverage is lower than the preset threshold; S5. Compare the logic functions corresponding to the patterns in the pattern code with the known unit logic function list one by one, use the logic paradigm decomposition to find out the logic expressions that are not in the logic function list in advance, use the equivalence check function to check whether the logic function is equivalent, and record the logic function of the new pattern and its pattern code; S6, outputting new patterns and their quantities in order from small to large according to the output quantity of the patterns; The specific process of step S2 is: traverse all nodes, regard each node and all nodes connected to its input pin as a mode, record them with a preset mode code, and record the number of modes corresponding to each mode code; wherein the preset mode code records the root node, all input pins of the root node, and all child node information connected to the input pin of the root node; The preset mode code in step S2 is a string, and its structure is: ROOT_NODE: PIN1[SUB_NODE], PIN2[SUB_NODE1, SUB_NODE2]; ROOT_NODE is the root node; PIN is all the input pins of the root node; SUB_NODE is the upstream node information connected to each pin; The specific process of step S4 is: S401, sequentially arrange isomorphic pattern codes in descending order as search target pattern codes, traverse all nodes, and check the stopType attribute of the node; if it is True, directly skip the node; If this node is set to be skipped in advance or has been occupied by the previous mode mark, the node attribute stopType will be set to True, that is, this node will not be considered and skipped; S402, taking the current node as the root, absorbing the nodes connected to its input pins and creating a pattern, generating a pattern code, and using an isomorphism check function to check the pattern code and the target pattern code. If the pattern code is the same or isomorphic to the currently searched pattern code, proceed to the next step. If not, skip the current node and continue; S403, marking the node attribute pattern covered by each pattern in sequence according to the sorting order, and the node whose pattern is not empty will not be repeatedly marked by other patterns; that is, when two patterns cover overlapping nodes, the pattern corresponding to the pattern code sorted later will be discarded; S404. If an isomorphic pattern combination is found, the pattern update functions updatePin and setFunction are used simultaneously to update the pins and logic function functions of the pattern to obtain a complete simplified logic expression of the entire pattern.

2. The digital circuit pattern mining method according to claim 1, characterized in that: In step S3, the isomorphism checking function is used to determine whether the pattern code is isomorphic. The specific steps are as follows: S301, compare the root nodes ROOT_NODE of the two pattern codes by slicing the string. If they are different, it means that the root nodes of the patterns are not the same standard unit, and return failure; If they are the same, proceed to the next step of comparison; S302, compare the number of pins of the two mode codes; if they are different, return failure; if they are the same, proceed to the next step of comparison; S303, create two dictionaries to store each pin PIN and its corresponding subnode SUB_NODE; the key of the dictionary is the first letter of the pin, and the value of the dictionary is the subnode set; the first letters of the pins with equivalent functions are the same by default, and the first letters of the pins with unequal functions are different, and the specific modification is made according to the internal format of the library file; S304, compare the number and content of each element in the two dictionaries, and calculate the number of each type of child nodes of each pin when comparing the content; if there is an inconsistency, it means that the child nodes connected to it are not completely consistent and cannot be regarded as isomorphic patterns, and failure is returned; if they are completely consistent, success is returned.

3. The digital circuit pattern mining method according to claim 2, characterized in that: In step S3, the specific process of merging all isomorphic patterns is as follows: loop through the pattern codes, compare them two by two, and merge them directly if they are isomorphic; use two lists to store the pattern codes that have been processed and all the pattern codes that need to be processed respectively; directly skip the pattern code that has been processed; the processed pattern code is regarded as discarded, and the pattern combination it contains is automatically merged into the pattern combination set contained in another isomorphic pattern code, and finally update the pattern code and its corresponding pattern quantity.

4. The digital circuit pattern mining method according to claim 1, characterized in that: The specific process of updating using the mode update function setFunction is as follows: S4041, traverse the input pins of all nodes covered by the pattern; if the node connected to the input pin is empty or does not belong to the pattern, it means that the pin is the input pin of the entire pattern, and is recorded in the pattern input pin set; On the contrary, it means it is an internal pin; S4042, traverse the output pins of all nodes covered by the pattern; if the node connected to the output pin is empty or does not belong to the pattern, it means that the pin is the output pin of the entire pattern, and is recorded in the pattern output pin set; On the contrary, it means it is an internal pin; S4043, traverse the output pins of the pattern, and at the same time traverse the nodes that constitute the pattern, and find the node to which the output pin belongs; Starting from this node, record it as the root node, explore the input pins towards the input end. If the current input pin is not the input pin of the pattern, replace the node logic expression connected to it to the position of the corresponding pin of the root node to form a new logic expression; if the current input pin is the input pin of the pattern, do not change it; when all the pins of the root node logic expression are replaced with the input pins of the pattern, the loop ends; S4044, replace the name of the obtained logical expression, standardize its naming method, and make it consistent with the naming convention of the logical expressions in the existing logical function list, and store it in the pattern attribute oriFunctions; record the original logical expression of the pattern, store it in the pattern attribute oriFunctions, and store the replaced logical expression in the pattern attribute cmpFunctions; S4045, recording the found pattern into a pre-created dictionary, where the value of the dictionary is a sub-dictionary, the key of the sub-dictionary is the number of output pins of the pattern, and the key is the corresponding pattern; sorting the dictionary in descending order with the number of patterns as the first keyword and the number of output pins as the second keyword; outputting the original pattern information and the pattern information of all multiple outputs; Patterns with coverage less than a preset threshold will not be output.

5. The digital circuit pattern mining method according to claim 4, characterized in that: The specific process of step S5 is: S501, generating a logic function expression for each mode according to the style of the logic expression in the existing logic function list, so that the generated expression conforms to the style of the logic expression in the existing logic function list; S502, performing character string comparison with the logical expressions in the existing logical function list one by one; If the same string is found, it means that the pattern is already a standard unit and is skipped; If no identical string is found, proceed to the next step; S503, decomposing the logic paradigm, and comparing the characteristics of the logic paradigm with the logic functions in the existing logic function list; If they are not the same, the comparison with the logic function is terminated in advance, and the comparison with the logic expression in the next logic function list is continued; if they are the same, the next step is entered; S504, perform an equivalence check on the logical function to ensure that there are no problems with the equivalence check; if the equivalence check passes, record it in the result and prepare to output; if the equivalence check fails, continue to compare the logical expressions in the next logical function function list; until the logical expressions in all logical function function lists have been compared and are not equivalent to the logical function functions of the pattern, it means that the pattern is a new pattern that has not been recorded, and it is recorded and output.

6. The digital circuit pattern mining method according to claim 5, characterized in that: In step S504, the specific process of equivalence checking is as follows: S5041. Compare the string lengths of the two logical expressions; if they are different, it means that the two are not equivalent and the comparison is skipped; if they are the same, further equivalence check is performed; S5042, determine whether the logical expression is expressed in the main disjunction form; if so, segment it according to the disjunction symbol; if not, segment it according to the conjunction symbol; S5043, compare the lengths of the two lists after segmentation; if they are the same, perform further equivalence check; if they are not the same, it means that the two logical expressions are not equivalent, and skip this mode; S5044. Use the sympy library function of Python to perform an equivalence check until all logical expressions in the logical function list have been compared and are not equivalent to the logical function of the pattern. This means that the pattern is a new pattern that has not been recorded. Record this pattern in the result list.

7. A digital circuit pattern mining system, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 6.

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