Device layout method and device of chip layout, computer equipment and storage medium

Abstract

The embodiment of the invention discloses a device layout method and device of a chip layout, computer equipment and a storage medium, and relates to the technical field of chips. Comprising the following steps: acquiring a chip layout on which a first device and a second device are to be arranged; based on a first layout parameter of the first device, determining a deficit area corresponding to the first device in the chip layout, the first layout parameter being a parameter adopted for laying the first device on the chip layout, and the deficit area being a hollow area located in the first device in the chip layout; and under the condition that the layout of the second device is not supported in the deficient area, laying the second device in an area outside the deficient area on the chip layout based on the second layout parameter of the second device and the deficient area. By adopting the method provided by the embodiment of the invention, the second device can be prevented from being arranged in the hollow area in the first device, and the device arrangement quality of the chip layout is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a device layout method, apparatus, computer equipment and storage medium for a chip layout. Background Art

[0002] In order to realize the functions of performing calculations and information processing, different types of core devices (such as superconducting quantum bits, reading cavities, etc.) and auxiliary devices (such as indium pillars, magnetic flux capture holes, through holes in multi-layer stacked chips, etc.) are arranged on the chip.

[0003] In the related art, electronic design automation (EDA) tools are usually used to lay out the core devices and auxiliary devices on the layout. When the core devices are already on the layout, the auxiliary devices are usually evenly laid out on the entire layout in a specific array, and a Boolean difference operation is performed with the core devices, and the result of the operation is used as the layout plan of the auxiliary devices. Summary of the invention

[0004] The present application provides a device layout method, apparatus, computer equipment and storage medium for chip layout. The technical solution is as follows:

[0005] On the one hand, an embodiment of the present application provides a device layout method for a chip layout, the method comprising:

[0006] Acquire a chip layout, on which a first device and a second device are to be arranged;

[0007] Determining a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used to layout the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout;

[0008] When the genus region does not support placement of the second device, the second device is placed in a region outside the genus region on the chip layout based on a second placement parameter of the second device and the genus region.

[0009] On the other hand, an embodiment of the present application provides a device for placing devices in a chip layout, the device comprising:

[0010] An acquisition module, used for acquiring a chip layout, on which the first device and the second device are to be arranged;

[0011] a determination module, configured to determine a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used for laying out the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout;

[0012] A layout module is used to layout the second device in an area outside the genus area on the chip layout based on a second layout parameter of the second device and the genus area when the genus area does not support the layout of the second device.

[0013] On the other hand, an embodiment of the present application provides a computer device, which includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the method described in the above aspect.

[0014] On the other hand, an embodiment of the present application provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement the method described in the above aspects.

[0015] On the other hand, an embodiment of the present application provides a computer program product, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a terminal reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the terminal executes the method described in the above aspects.

[0016] In an embodiment of the present application, based on the first layout parameters of the first device, a defect area corresponding to the first device in the chip layout is determined, wherein the defect area refers to a hollow area located inside the first device in the chip layout, and when the defect area does not support the layout of the second device, based on the second layout parameters of the second device and the defect area, the second device is laid out in an area outside the defect area on the chip layout to avoid laying the second device in the hollow area inside the first device, thereby improving the device layout quality of the chip layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a schematic diagram of a core device provided by an exemplary embodiment of the present application having a genus region inside;

[0019] Figure 2 is a schematic diagram of an exemplary embodiment of the present application in which an auxiliary device is arranged in a genus region inside a core device;

[0020] Figure 3 is a flow chart of a device layout method of a chip layout provided by an exemplary embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a node arrangement sequence provided by an exemplary embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a node arrangement sequence provided by another exemplary embodiment of the present application;

[0023] Figure 6 is a schematic diagram of arranging a second device in an area other than an intersection between the candidate arrangement area and the genus area provided by an exemplary embodiment of the present application;

[0024] Figure 7 It is a schematic diagram of a code for configuring a control with a genus layout control function based on the protobuf protocol provided by an exemplary embodiment of the present application;

[0025] Figure 8 is a flow chart of laying out a second device on a chip layout provided by an exemplary embodiment of the present application;

[0026] Fig. 9 is a schematic diagram of translating a candidate layout adjustment area provided by an exemplary embodiment of the present application;

[0027] Fig.10 is a schematic diagram of adding a second device in a genus region when the area of ​​the genus region is greater than an area threshold, provided by an exemplary embodiment of the present application;

[0028] Fig.11 is a schematic diagram of adding a second device in a genus region when the density of the second devices in the sub-block is less than a density threshold, provided by an exemplary embodiment of the present application;

[0029] Fig.12 It is a structural block diagram of a device layout apparatus for a chip layout provided by an exemplary embodiment of the present application;

[0030] Fig.13 It is a structural diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0032] In order to arrange auxiliary devices on the chip layout, the relevant technology will use electronic design automation tools to evenly lay out the auxiliary devices in an array on the chip layout, and perform Boolean difference operations with the core devices already arranged on the chip layout, and use the results of the operations as the layout plan for the auxiliary devices.

[0033] However, due to the variety of device structures and functions, directly using Boolean difference operations to arrange devices can easily cause device malfunctions.

[0034] In one possible scenario, there may be a genus region inside the core device on the chip layout, where the genus region refers to a hollow area located inside the core device on the chip layout.

[0035] "Genesis" is a definition in topology. For a figure, if there are n mutually non-intersecting closed curves in the figure, and these n mutually non-intersecting closed curves do not separate the figure into different regions, then the genus of the figure is called n.

[0036] See also Figure 1 , Figure 1 It is a schematic diagram of a core device provided by an exemplary embodiment of the present application, in which a genus region exists inside the core device.

[0037] like Figure 1 As shown, there is a rectangular genus region 111 inside the core device 101 , a triangular genus region 112 inside the core device 102 , and an irregular polygonal genus region 113 inside the core device 103 .

[0038] This embodiment is illustrated by taking the genus region as a rectangle, triangle or irregular polygon as an example, but this is not a limitation. In fact, the genus region inside the core device can be of various shapes. For example, there may be a genus region with a "cross" structure inside a superconducting quantum bit, or a genus region with other special structures (such as a "flipmon" structure). All such genus regions of various shapes are within the protection scope of this application.

[0039] When there is a defect area inside the core device, the method of evenly laying out the auxiliary devices in an array on the chip layout and performing Boolean difference operations with the core devices already laid out on the chip layout may cause the auxiliary devices to be laid out in the defect area inside the core device, thereby possibly causing the core device to work abnormally.

[0040] See also Figure 2 , Figure 2 It is a schematic diagram of an exemplary embodiment of the present application in which an auxiliary device is arranged in a genus region inside a core device.

[0041] like Figure 2 As shown, in the case where there is a genus region inside the core device, the auxiliary devices are evenly laid out on the chip layout in an array, and a Boolean difference operation is performed with the core devices already laid out on the chip layout, so that 8 auxiliary devices (including auxiliary device 211) are laid out in the genus region inside the core device 201, 2 auxiliary devices (including auxiliary device 212) are laid out in the genus region inside the core device 202, and 3 auxiliary devices (including auxiliary device 213) are laid out in the genus region inside the core device 203. In some scenarios, the auxiliary devices are laid out in the genus region inside the core device, which may cause the core device 201, the core device 202, and the core device 203 to work abnormally.

[0042] In order to solve the abnormal working problem caused by the auxiliary devices being arranged in the defective area inside the core device, the present application provides a device arrangement method of a chip layout, so that the auxiliary devices can be arranged not in the defective area inside the core device, thereby improving the device arrangement quality of the chip layout and reducing the abnormal working problem.

[0043] See also Figure 3 , Figure 3 This is a flowchart of a device layout method for a chip layout provided by an exemplary embodiment of the present application. The present application embodiment takes the method as an example of a computer device having a chip layout generation function (such as a computer device equipped with an EDA tool). The flowchart includes the following steps:

[0044] Step 301, obtaining a chip layout, on which a first device and a second device are to be arranged.

[0045] The chip layout is a layout that reflects the physical information such as the device type, device size, relative position between devices, and connection relationship between various devices corresponding to various devices in the chip.

[0046] Optionally, the chip layout is a layout corresponding to a superconducting quantum chip.

[0047] In some embodiments, the first device is a core device arranged on the chip layout, and the second device is an auxiliary device arranged on the chip layout.

[0048] Optionally, the first device is a core device such as a superconducting quantum bit, a resonant cavity, a reading cavity or a top sheet test junction.

[0049] Optionally, the second device is an auxiliary device such as an indium pillar, a magnetic flux capturing hole, a through hole in a multi-layer stacked chip, etc.

[0050] In some embodiments, the first device may also be other types of core devices, and the second device may also be other types of auxiliary devices. The embodiments of the present application do not limit the specific types of the first device and the second device.

[0051] The second device is used as an auxiliary device to provide support to the first device as the core device. For example, on a superconducting quantum chip, the indium pillar is a bump made of metal indium, which is used to establish an electrical connection between the bottom sheet and the top sheet; the magnetic flux capture hole is a micron-sized hole or perforation etched in the quantum processor, which is used to capture magnetic flux and prevent it from interfering with quantum bits to reduce errors and the impact on decoherence and improve the accuracy of quantum computing. The through-holes in the multi-layer stacked chips will open up the three-dimensional chips stacked in the vertical direction to achieve vertical interconnection between chips and within the chip.

[0052] Step 302, based on a first layout parameter of the first device, determine a genus region corresponding to the first device in the chip layout, wherein the first layout parameter is a parameter used to layout the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout.

[0053] The first layout parameters are used to indicate how to layout the first device on the chip layout. Exemplarily, the first layout parameters may include the shape, side length, position and size parameters of the first device, or the distance parameters between the first device and the upper, lower, left and right boundaries of the chip layout, or other parameters used to layout the first device.

[0054] In some embodiments, the first layout parameter includes a layout node sequence. The layout node sequence includes a plurality of layout nodes, which are used to represent a plurality of vertices of the first device on the chip layout.

[0055] In some embodiments, the layout node sequence includes a plurality of layout nodes connected in sequence, and the plurality of layout nodes can be connected in sequence to form a connected area where the first device is located.

[0056] The genus region corresponding to the first device refers to the hollow region located inside the first device in the chip layout. Figure 1 The genus region corresponding to the core device 101 is a rectangular region inside the core device 101 (shown in the second color).

[0057] In some embodiments, it may be determined whether the first device has a corresponding genus region based on a first layout parameter of the first device. If the corresponding genus region exists, the genus region may be determined by the first layout parameter.

[0058] Step 303 : When the genus region does not support placement of the second device, place the second device in a region outside the genus region on the chip layout based on a second placement parameter of the second device and the genus region.

[0059] In some embodiments, all or part of the genus region on the chip layout may not support placement of the second device.

[0060] The second layout parameters are parameters used to layout the second device on the chip layout.

[0061] The second layout parameters are used to indicate how to layout the second device on the chip layout. Exemplarily, the second layout parameters may include the shape, side length, position and size parameters of the second device, or the distance parameters between the second device and the upper, lower, left and right boundaries of the chip layout, or other parameters used to layout the second device.

[0062] In some embodiments, the second layout parameters also include a distance limit parameter between the second device and the first device, wherein the distance limit parameter is used to ensure the spacing distance between the first device and the second device to avoid abnormal operation due to the close distance between the devices.

[0063] Optionally, according to the second layout parameter, the second device array is arranged in an area on the chip layout that has no intersection with the genus area.

[0064] In some embodiments, the electronic design automation tool may obtain the first layout parameter or the second layout parameter set by the user, and implement device layout on the chip layout according to the first layout parameter and the second layout parameter.

[0065] To summarize, based on the first layout parameters of the first device, the defect area corresponding to the first device in the chip layout is determined, wherein the defect area refers to the hollow area located inside the first device in the chip layout, and when the defect area does not support the layout of the second device, based on the second layout parameters of the second device and the defect area, the second device is laid out in the area outside the defect area on the chip layout, which can avoid laying the second device in the hollow area inside the first device, thereby improving the device layout quality of the chip layout.

[0066] To determine the genus region corresponding to the first device according to the first layout parameter, in some embodiments, the electronic design automation tool may set the first layout parameter according to a certain rule.

[0067] In some embodiments, the first layout parameter includes a layout node sequence, wherein the layout node sequence includes layout nodes connected in sequence, and a connected area formed by the layout nodes connected in sequence is the layout area of ​​the first device.

[0068] See also Figure 4 , Figure 4 It is a schematic diagram of a node deployment sequence provided by an exemplary embodiment of the present application.

[0069] like Figure 4 As shown, the first layout parameter corresponding to the first device may include a layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> .

[0070] Among them, the connected area 410 formed by sequentially connecting the layout nodes A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 is the layout area of ​​the first device.

[0071] In some embodiments, a first connected node and a second connected node in a layout node sequence may be determined, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside a connected area.

[0072] For example, in the layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> In the example, there are two adjacent nodes A5 and A6, and the line A5A6 formed by A5 and A6 is located inside the connected area, then A5 can be used as the first connected node and A6 can be used as the second connected node; or A5 can be used as the second connected node and A6 can be used as the first connected node.

[0073] In some embodiments, a layout node having the same node coordinates as the head layout node in the layout node sequence may be determined as a first connected node, and an adjacent node of the first connected node may be determined as a second connected node.

[0074] For example, in the layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> In the example, the node coordinates of A5 are the same as the node coordinates of the head layout node A1 in the layout node sequence. Therefore, A5 can be used as the first connected node, and the adjacent node A6 of the first connected node A5 can be determined as the second connected node.

[0075] To determine the genus region corresponding to the first device according to the first layout parameter, in some embodiments, the first connected node can be used as a starting point, and the layout nodes in the layout node sequence can be traversed in sequence along the first direction to obtain a first closed curve formed by connecting the layout nodes.

[0076] For example, starting from the first connected node A5, the node sequence is traversed in reverse order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in the are obtained to obtain a first closed curve S1 formed by connecting the layout nodes A5, A4, A3, A2, and A1.

[0077] Taking the second connected node as the starting point, the layout nodes in the layout node sequence are traversed in sequence along the second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction.

[0078] For example, starting from the second connected node A6, the node sequence is traversed in sequence.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in the are obtained to obtain a second closed curve S2 formed by connecting the layout nodes A6, A7, A8, A9, and A10.

[0079] In some embodiments, the genus region may be determined based on the first closed curve and the second closed curve.

[0080] In some embodiments, when the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as a genus area.

[0081] like Figure 4 As shown, the enclosed area corresponding to the second closed curve S2 (the area shown in the second color) is located within the enclosed area corresponding to the first closed curve S1 (the union of the area shown in the first color and the area shown in the second color). Therefore, the enclosed area corresponding to the second closed curve S2 (the area shown in the second color) can be determined as a genus area.

[0082] Optionally, node coordinates of the layout vertices in the first closed curve S1 and the second closed curve S2 may be compared to determine whether the enclosed area corresponding to the second closed curve S2 is within the enclosed area corresponding to the first closed curve S1.

[0083] In some embodiments, the first connected node or the second connected node may be located on a vertex or a boundary of a layout area of ​​the first device.

[0084] See also Figure 5 , Figure 5 It is a schematic diagram of a node deployment sequence provided by another exemplary embodiment of the present application.

[0085] like Figure 5 As shown, the first layout parameter corresponding to the first device may include a layout node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11> .

[0086] Among them, the connected area 510 formed by sequentially connecting the layout nodes A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, and A11 is the layout area of ​​the first device.

[0087] In the node sequence<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11> In the example, there are two adjacent nodes A6 and A7, and the line A6A7 formed by A6 and A7 is located inside the connected area, then A6 can be used as the first connected node and A7 can be used as the second connected node; or A6 can be used as the second connected node and A7 can be used as the first connected node.

[0088] Alternatively, since the node coordinates of A6 are the same as the node coordinates of the head layout node A1 in the layout node sequence, A6 can be used as the first connected node, and the adjacent node A7 of the first connected node A6 can be determined as the second connected node.

[0089] Starting from the first connected node A6, traverse the node sequence in reverse order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in the are obtained to obtain a first closed curve S1 formed by connecting the layout nodes A6, A5, A4, A3, A2, and A1.

[0090] Starting from the second connected node A7, traverse the node sequence in order.<A1,A2,A3,A4,A5,A6,A7,A8,A9,A10> The layout nodes in the are obtained to obtain a second closed curve S2 formed by connecting the layout nodes A7, A8, A9, A10, and A11.

[0091] In some embodiments, since the enclosed area corresponding to the second closed curve S2 is located within the enclosed area corresponding to the first closed curve S1 , the enclosed area corresponding to the second closed curve S2 can be determined as a genus area.

[0092] In this embodiment, after determining the first connected node and the second connected node based on the layout node sequence, traversal can be performed in opposite directions to determine the first closed curve and the second closed curve, thereby efficiently determining the genus region, thereby improving the efficiency of device layout.

[0093] Based on the second layout parameter of the second device and the genus region, when the second device is laid out on the chip layout, it can be determined whether there is an intersection between the area where the second device is laid out and the genus region. If there is an intersection, the second device is not laid out in the area.

[0094] In some embodiments, a candidate layout region of the second device in the chip layout may be determined based on the second layout parameter.

[0095] Optionally, the candidate layout areas may be determined in a uniform array according to the shape, side length, position and size parameters of the second device in the second layout parameters, and the distance parameters between the second device and the upper, lower, left and right boundaries of the chip layout.

[0096] Optionally, the candidate layout area may also be determined based on a distance limit parameter between the first device and the second device to ensure that the distance between the candidate layout area and the layout area of ​​the first device is greater than or equal to the distance limit parameter.

[0097] Optionally, the candidate layout areas may be determined in a uniform array manner in an area outside the first device on the chip layout.

[0098] When the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, the second device is placed in a region other than the intersection in the candidate placement region.

[0099] See also Figure 6 , Figure 6 1 is a schematic diagram of placing a second device in an area other than an intersection between the candidate placement area and the genus area, provided by an exemplary embodiment of the present application.

[0100] like Figure 6 As shown, on the chip layout, the genus region corresponding to the first device 601 is a rectangular region, the genus region corresponding to the first device 602 is a triangular region, and the genus region corresponding to the first device 603 is an irregular polygonal region.

[0101] In some embodiments, a candidate layout area (shown in a dotted box) of the second device can be determined based on the second layout parameter. Figure 6 In the embodiment, candidate layout regions for the second device exist both outside the layout region of the first device and in the genus region corresponding to the first device.

[0102] In some embodiments, when the genus regions corresponding to the first device 601, the first device 602 and the first device 603 do not support the layout of the second device, the intersection of the candidate layout area of ​​the second device and the genus region (i.e., the area where the dotted box in the genus region is located) can be determined.

[0103] Therefore, the electronic design automation tool places the second device in the area other than the intersection in the candidate placement area to form a placement area for the second device (shown in a solid line box), thereby avoiding placing the second device in the defect area corresponding to the first device and avoiding abnormal working problems.

[0104] In a possible scenario, the genus region corresponding to the first device may support the placement of the second device.

[0105] For example, for some special device structures, such as the "flipmon" structure of a superconducting quantum bit, the genus region supports the layout of indium pillars.

[0106] For example, for some special device functions, such as the pad of the top film test junction, since the resistance of the junction after welding needs to be measured on the bottom film after the top and bottom films are welded, an indium column needs to be arranged in the pad of the top film test junction to play a connecting role; or, when a control line needs to be added from the bottom film to the top film, an indium column also needs to be arranged in the pad of the top film test junction.

[0107] Therefore, in some embodiments, when the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the electronic design automation tool may place the second device in the candidate placement region.

[0108] Determining the support of the genus region corresponding to the first device for the placement of the second device may include at least one of the following methods: The placement support includes that the genus region does not support the placement of the second device or that the genus region supports the placement of the second device.

[0109] (1) Based on at least one of a device type, a device structure, or a device function of the first device, determining a layout support status of a genus region corresponding to the first device for a second device.

[0110] Optionally, the device type of the first device is a type to which the first device belongs, for example, the device type may be a superconducting quantum bit, a reading cavity, or the like.

[0111] Optionally, the device structure of the first device is a morphological structure of the first device, for example, the device structure may be a “cross” structure, a “flipmon” structure, or the like.

[0112] Optionally, the device function of the first device is a function to be implemented by the first device, for example, the device function may be used to measure the resistance of a node after pressure welding, or to add a control line from the bottom film to the top film, etc.

[0113] (2) Based on the switch state of the control having the defect placement control function, determining the placement support of the defect area corresponding to the first device for the second device.

[0114] Optionally, a control with a defect placement control function can be used to control the placement support of the second device by the defect areas corresponding to all the first devices in the chip layout with one click, and can also be used to control the placement support of the second device by the defect areas corresponding to some of the first devices.

[0115] In some embodiments, the electronic design automation tool may configure the control having the genus layout control function based on the protobuf protocol.

[0116] See also Figure 7 , Figure 7 It is a schematic diagram of a code for configuring a control with a genus layout control function based on the protobuf protocol provided by an exemplary embodiment of the present application.

[0117] like Figure 7 As shown, in the configuration file based on the protobuf protocol, the control with the genus placement control function can be configured by setting the parameter value of "cheese_placement_in_genus_region".

[0118] Exemplarily, “cheese_placement_in_genus_region: 0” indicates that all genus regions corresponding to the first devices on the chip layout do not support placement of the second device.

[0119] Exemplarily, “cheese_placement_in_genus_region: 1” indicates that all genus regions corresponding to the first devices on the chip layout support placement of the second device.

[0120] Through the parameter value of "cheese_placement_in_genus_region", it is possible to determine the support of the genus region for the placement of the second device according to user needs.

[0121] In the configuration file based on the protobuf protocol, the first layout parameter or the second layout parameter can also be set. For example, the distance parameters between the second device and the upper, lower, left, and right boundaries of the chip layout can be set based on the parameters in "margin_config" (for example, the parameter values ​​of "left_margin", "right_margin", "up_margin", and "down_margin" are all 4000, indicating that the distance between the second device and the upper, lower, left, and right boundaries of the chip layout must not be less than 4000 microns), the size parameters of the second device in the bottom film and the top film can be set based on "shape_config" (for example, "ubm_edge_length:100" indicates that the side length of the indium housing in the top film is 100 microns, and "indium_edge_length:0" indicates that the indium housing is not set in the bottom film), and the spacing between the second devices and the distance limit parameters between the second device and the first device can be set based on "placement_config" (for example, "step:200" indicates that the spacing between the indium housings is 200 microns, and the distance between the indium housings and the first device does not exceed 50 microns).

[0122] See also Figure 8 , Figure 8 This is a flow chart of laying out a second device on a chip layout provided by an exemplary embodiment of the present application. The flow chart includes the following steps:

[0123] Step 810, obtaining a chip layout, on which a first device and a second device are to be arranged.

[0124] Step 820 , determining a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device.

[0125] Step 830 : Determine a candidate layout region for the second device in the chip layout based on the second layout parameter.

[0126] Optionally, the second layout parameters include size parameters of the second components, spacing parameters between the second components, and distance limit parameters between the second components and the first components.

[0127] Optionally, based on the second layout parameters, candidate layout areas for the second device may be determined in a chip layout according to a uniform array.

[0128] Step 841 : Determine, based on at least one of a device type, a device structure, or a device function of the first device, the support status of the genus region corresponding to the first device for the layout of the second device.

[0129] Exemplarily, when the combination of the device type and the device structure of the first device is a specific combination, the support of the genus region corresponding to the first device for the layout of the second device can be determined. For example, when the device type is a superconducting quantum bit and the device structure is a "cross" structure, the layout support is determined to be that the genus region does not support the layout of the second device.

[0130] Exemplarily, when the device type and device function of the first device are a specific combination, the layout support of the genus region corresponding to the first device for the second device can be determined. For example, when the device type is a gasket for testing the junction of the top sheet, and the device function is used to measure the resistance of the junction after pressure welding on the bottom sheet, the layout support is determined to be that the genus region supports the layout of the second device.

[0131] In some embodiments, the device type may be obtained based on a category to which the first device belongs stored in an electronic design automation tool. In some embodiments, the device function may be obtained based on user input.

[0132] In some embodiments, the device structure of the first device can be determined based on the first layout parameters, such as matching the first layout parameters of the first device with reference layout parameters of the reference device, and if the match is successful, using the device structure corresponding to the reference device as the device structure of the first device.

[0133] The reference device is a device having a corresponding device structure stored therein. For example, the reference device may be a standard device stored in an electronic design automation tool, or another first device having a known device structure.

[0134] Step 842: Determine the support of the genus region corresponding to the first device for the placement of the second device based on the switch state of the control having the genus placement control function.

[0135] Optionally, the parameter value of the parameter "cheese_placement_in_genus_region" corresponding to the switch state of the control with the genus placement control function can be obtained in the configuration file based on the protobuf protocol to determine the support of the genus region corresponding to the first device for the placement of the second device. For example, a parameter value of 0 indicates that the genus regions corresponding to all the first devices on the chip layout do not support the placement of the second device, and a parameter value of 1 indicates that all the genus regions corresponding to the first devices on the chip layout support the placement of the second device.

[0136] After determining the support status of the genus region corresponding to the first device for the layout of the second device, the second device may be laid out in the chip layout based on the support status.

[0137] Step 851 : if the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, place the second device in the region other than the intersection in the candidate placement region.

[0138] Step 852 : if the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or if there is no intersection between the candidate placement region and the genus region, place the second device in the candidate placement region.

[0139] In this embodiment, the support of the defect area for the layout of the second device can be determined through at least one of the device type, device structure or device function of the first device, or through the switch state of a control with a defect layout control function, so as to selectively layout or not layout the second device in the defect area, enriching the device layout function of the chip layout and improving the quality of device layout.

[0140] After the second device is laid out in the chip layout, the layout of the second device may be adjusted in some areas (such as increasing the number of second devices and adjusting the layout area of ​​the second device) to increase the density of the second device and thus improve the quality of device layout.

[0141] In some embodiments, a candidate layout adjustment region of the second device may be determined. The candidate layout adjustment region is a candidate layout region for the second device to be layout adjusted, wherein the density of the second device after the layout adjustment is higher than the density of the second device before the layout adjustment.

[0142] During the layout adjustment process, certain requirements and restrictions need to be met. In some embodiments, the second layout parameter includes a distance limit parameter between the second device and the first device, and after the layout adjustment, the distance between the second device and the first device should still be greater than or equal to the distance limit parameter.

[0143] In a possible scenario, it is necessary to consider the intersection between the candidate layout area and the genus area, and determine the way to adjust the layout of the second device based on the intersection.

[0144] When there is no intersection between the candidate placement adjustment region and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first device is greater than or equal to the distance limit parameter, the second device is placed in the candidate placement adjustment region.

[0145] When there is an intersection between the candidate layout adjustment region and the genus region, or when the distance between the candidate layout adjustment region and the layout region of the first device is less than the distance limit parameter, the layout of the second device is not adjusted.

[0146] In a possible scenario, the candidate layout adjustment area can also be translated according to a certain step size. When there is no intersection between the translated candidate layout adjustment area and the defect area, and the distance between the translated candidate layout adjustment area and the layout area of ​​the first device is greater than or equal to the distance limit parameter, the second device can be laid in the translated candidate layout adjustment area.

[0147] See also Fig. 9 , Fig. 9 It is a schematic diagram of translating a candidate layout adjustment area provided by an exemplary embodiment of the present application.

[0148] like Fig. 9 As shown, there is a genus region inside the first device 901 on the chip layout. After the second device is arranged in the second device arrangement region (shown as a solid line box) on the chip layout, the second device can be adjusted in layout to increase the density of the second device.

[0149] In order to improve the density of the second device, a candidate layout adjustment region (shown by a dotted box) of the second device may be determined.

[0150] Since there is an intersection between the candidate layout adjustment region and the genus region of the first device 901 , the candidate layout adjustment region may be translated according to a certain step length.

[0151] In some embodiments, when there is an intersection between the candidate placement adjustment region and the genus region, or when the distance between the candidate placement adjustment region and the placement region of the first device is less than a distance limit parameter, an adjustment step size set may be determined.

[0152] The adjustment step set includes at least one candidate adjustment step. For example, the adjustment step set may be {10 micrometers, 9 micrometers, ..., 1 micrometer}.

[0153] In some embodiments, the candidate placement adjustment area may be translated based on the i-th candidate adjustment step in the adjustment step set.

[0154] For example, the first candidate adjustment step of 10 microns in the adjustment step set is selected, and the candidate layout adjustment area is shifted 10 microns to the left or right.

[0155] When there is no intersection between the candidate placement adjustment region after translation and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first device is greater than or equal to the distance limit parameter, the second device may be placed in the candidate placement adjustment region after translation.

[0156] When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the first device is less than the distance limit parameter, the candidate layout adjustment area is re-translated based on the i+1th candidate adjustment step in the adjustment step set... until the second device can be laid out in the translated candidate layout adjustment area, or all candidate adjustment steps in the adjustment step set are traversed.

[0157] For example Fig. 9 In the figure, when the candidate layout adjustment area of ​​the second device is shifted to the right based on the candidate adjustment step size of 4 microns, there is no intersection between the candidate layout adjustment area of ​​the second device and the defect area of ​​the first device, and the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter. Therefore, the candidate layout adjustment area after being shifted to the right based on the candidate adjustment step size of 4 microns can be used as the layout area of ​​the second device.

[0158] In this embodiment, by translating the candidate layout adjustment area based on the candidate adjustment step in the adjustment step set, it can be determined whether there is a suitable layout area in the chip layout, which can both increase the density of the second device and meet the distance limit requirement between the first device and the second device.

[0159] In one possible scenario, after the second device is arranged on the chip layout, in order to better realize the function of the second device, if the area of ​​the defect region corresponding to the first device is too large, or the density of the second devices in some areas is low, the electronic design automation tool can appropriately add the second device in the defect region without affecting the normal operation of the first device.

[0160] In some embodiments, when the area of ​​the genus region is greater than an area threshold, a second device is added to the genus region, wherein the number of the added second devices is positively correlated to the area of ​​the genus region.

[0161] See also Fig.10 , Fig.10 It is a schematic diagram of adding a second device in a genus region when the area of ​​the genus region is greater than an area threshold, provided by an exemplary embodiment of the present application.

[0162] like Fig.10As shown, in the chip layout, except for the layout area of ​​the first device and the defect area, the second device is evenly arranged. When the areas of the defect areas corresponding to the first device 1001 and the first device 1002 are both greater than the area threshold, the second device can be added to the defect areas corresponding to the first device 1001 and the first device 1002. Among them, the number of second devices added in the defect area corresponding to the first device 1001 is 2, and the number of second devices added in the defect area corresponding to the first device 1002 is 8, and the number of second devices added is positively correlated with the area of ​​the defect area.

[0163] When adding a second device in a defective area, it is also necessary to consider that the distance between the added second device and the existing first device must be greater than or equal to the distance limit parameter. Therefore, in order to add a second device in a defective area, a candidate area for adding the second device can be determined, and when the distance between the candidate area for adding the second device and the area where the first device is arranged is greater than or equal to the distance limit parameter, the second device is added in the candidate area for adding the second device.

[0164] The candidate additional region may be a region determined from the genus region based on the second layout parameter (such as a size parameter of the second device).

[0165] In the case where there are sub-blocks in the chip layout and the density of the second devices in the sub-blocks is less than the density threshold, all the genus regions in the sub-blocks can be arranged in descending order of area to obtain a genus region sequence. In the case where the density of the second devices in the sub-blocks is less than the density threshold, the second devices are arranged in the genus regions in the genus region sequence in sequence until the density of the second devices is greater than or equal to the density threshold.

[0166] See also Fig.11 , Fig.11 It is a schematic diagram of adding a second device in a genus region when the density of the second devices in a sub-block is less than a density threshold, provided by an exemplary embodiment of the present application.

[0167] like Fig.11 As shown, a first device 1101 , a first device 1102 , a first device 1103 , a first device 1104 , a first device 1105 and a first device 1006 are arranged in the chip layout.

[0168] In the chip layout, there is a sub-block 1110 , wherein a first device 1101 , a first device 1102 , a first device 1103 , and a first device 1104 are all located within the sub-block 1110 .

[0169] Regarding the method of determining the sub-block, in some embodiments, the sub-block may be determined from the chip layout according to a fixed side length, or the chip layout may be divided to determine a plurality of sub-blocks.

[0170] In some embodiments, the placement density of the second device in the sub-block 1110 may be calculated.

[0171] Optionally, the ratio of the layout area of ​​the second device in the sub-block 1110 to the area of ​​the sub-block may be used as the layout density of the second device.

[0172] Assuming that the layout density of the second device in sub-block 1110 is 4.5% and the density threshold is 5%, all the defect regions in sub-block 1110 can be arranged in descending order of area to obtain a defect region sequence: defect region A, defect region B, defect region C and defect region D, wherein defect region A is located inside the first device 1101, defect region B is located inside the first device 1102, defect region C is located inside the first device 1103, and defect region D is located inside the first device 1104.

[0173] In some embodiments, the second devices may be sequentially arranged in the genus regions in the genus region sequence until the density of the second devices is greater than or equal to the density threshold. For example, first, in the genus region A corresponding to the first device 1101, the second device is added based on the second arrangement parameters (such as the size parameters of the second device, the distance limit parameters between the second device and the first device, the interval between the second devices, etc.).

[0174] After the second device is added in the genus region A corresponding to the first device 1101, the layout density of the second device in the sub-block 1110 (assuming it is 4.8%) is calculated. Since the layout density is still less than the density threshold, the second device can be added to the second genus region in the genus region sequence (i.e., the genus region C corresponding to the first device 1103).

[0175] Similarly, a second device may be added in the corresponding genus region C of the first device 1103 based on second layout parameters (such as size parameters of the second device, distance limit parameters between the second device and the first device, intervals between second devices, etc.).

[0176] After adding the second device in the genus region C corresponding to the first device 1103 , the layout density of the second device in the sub-block 1110 (assuming it is 5.1%) is calculated. Since the density threshold has been reached, the second device can be stopped from being added.

[0177] In this embodiment, all defect regions in the sub-block are arranged in descending order of area to obtain a defect region sequence, and second devices are arranged in the defect regions in the defect region sequence in sequence until the density of the second devices is greater than or equal to a density threshold. This can not only improve the density of the second devices in the sub-block on the chip layout, but also reduce the impact of the second devices arranged in the defect region on the first devices. At the same time, the distance requirement between the first device and the second device is also met, so the quality of device arrangement on the chip layout can be improved.

[0178] See also Fig.12 , Fig.12 This is a structural block diagram of a device layout device for a chip layout provided by an exemplary embodiment of the present application. The device includes:

[0179] An acquisition module 1201 is used to acquire a chip layout, on which a first device and a second device are to be arranged;

[0180] A determination module 1202 is configured to determine a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used for laying out the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout;

[0181] The placement module 1203 is configured to place the second device in a region outside the genus region on the chip layout based on a second placement parameter of the second device and the genus region when the genus region does not support placement of the second device.

[0182] Optionally, the first layout parameter includes a layout node sequence, the layout node sequence includes layout nodes connected in sequence, and the connected area formed by the layout nodes connected in sequence is the layout area of ​​the first device. The determination module 1202 is used to:

[0183] Determine a first connected node and a second connected node in the layout node sequence, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside the connected area;

[0184] Taking the first connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a first direction to obtain a first closed curve formed by connecting the layout nodes;

[0185] Taking the second connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction;

[0186] The genus region is determined based on the first closed curve and the second closed curve.

[0187] Optionally, the determination module 1202 is used to:

[0188] Determine a layout node having the same node coordinates as the head layout node in the layout node sequence as the first connected node;

[0189] An adjacent node of the first connected node is determined as the second connected node.

[0190] Optionally, the determination module 1202 is used to:

[0191] When the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as the genus area.

[0192] Optionally, the deployment module 1203 is used to:

[0193] Based on the second layout parameters, determining a candidate layout area for the second device in the chip layout;

[0194] When the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, the second device is placed in a region other than the intersection among the candidate placement regions.

[0195] Optionally, the deployment module 1203 is used to:

[0196] When the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the second device is placed in the candidate placement region.

[0197] Optionally, the deployment module 1203 is used to:

[0198] Based on at least one of the device type, device structure or device function of the first device, determining the support of the layout of the second device by the defective region corresponding to the first device, wherein the layout support includes that the defective region does not support the layout of the second device or the defective region supports the layout of the second device; or

[0199] Based on the switch state of the control having the genus layout control function, the layout support status of the genus area corresponding to the first component to the second component is determined.

[0200] Optionally, the deployment module 1203 is used to:

[0201] The first layout parameters of the first device are matched with reference layout parameters of a reference device, and if the match is successful, the device structure corresponding to the reference device is used as the device structure of the first device, wherein the reference device is a device storing the corresponding device structure.

[0202] Optionally, the second layout parameter includes a distance limit parameter between the second device and the first device, and the layout module 1203 is used to:

[0203] Determine a candidate layout adjustment region of the second device, the candidate layout adjustment region being a candidate layout region for performing layout adjustment on the second device, wherein a density of the second device after the layout adjustment is higher than a density of the second device before the layout adjustment;

[0204] When there is no intersection between the candidate placement adjustment region and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first component is greater than or equal to the distance limit parameter, the second component is placed in the candidate placement adjustment region.

[0205] Optionally, the deployment module 1203 is used to:

[0206] In the case where there is an intersection between the candidate layout adjustment region and the genus region, or the distance between the candidate layout adjustment region and the layout region of the first device is less than the distance limit parameter, determining an adjustment step set, wherein the adjustment step set includes at least one candidate adjustment step;

[0207] Based on the i-th candidate adjustment step in the adjustment step set, translating the candidate layout adjustment area;

[0208] When there is no intersection between the candidate layout adjustment region after translation and the genus region, and the distance between the candidate layout adjustment region and the layout region of the first device is greater than or equal to the distance limit parameter, layout the second device in the candidate layout adjustment region after translation;

[0209] When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter, the candidate layout adjustment area is translated based on the i+1th candidate adjustment step in the adjustment step set.

[0210] Optionally, the deployment module 1203 is used to:

[0211] When the area of ​​the defective region is greater than the area threshold, the second device is added to the defective region, wherein the number of the second devices added is positively correlated with the area of ​​the defective region; or

[0212] A sub-block in the chip layout is determined, wherein the sub-block includes at least one deficient region; and when a density of the second devices in the sub-block is less than a density threshold, the second devices are added in the deficient region.

[0213] Optionally, the deployment module 1203 is used to:

[0214] determining a candidate region for adding the second device;

[0215] When the distance between the candidate additional region and the layout region of the first component is greater than or equal to the distance limit parameter, the second component is added in the candidate additional region.

[0216] Optionally, the deployment module 1203 is used to:

[0217] Arrange all the genus regions in the sub-block in descending order of area to obtain a genus region sequence;

[0218] When the density of the second devices in the sub-block is less than a density threshold, the second devices are arranged in the genus regions in the genus region sequence in sequence until the density of the second devices is greater than or equal to the density threshold.

[0219] See also Fig.13 , Fig.13 13 is a schematic diagram of the structure of a computer device provided by an exemplary embodiment of the present application. Specifically, the computer device 1300 includes a central processing unit (CPU) 1301, a system memory 1304 including a random access memory 1302 and a read-only memory 1303, and a system bus 1305 connecting the system memory 1304 and the central processing unit 1301. The computer device 1300 also includes a basic input / output system (I / O system) 1306 that helps transmit information between various devices in the computer, and a large-capacity storage device 1307 for storing an operating system 1313, application programs 1314 and other program modules 1315.

[0220] The basic input / output system 1306 includes a display 1308 for displaying information and an input device 1309 such as a mouse and a keyboard for user inputting information. The display 1308 and the input device 1309 are connected to the central processing unit 1301 through an input / output controller 1310 connected to the system bus 1305. The basic input / output system 1306 may also include an input / output controller 1310 for receiving and processing inputs from a plurality of other devices such as a keyboard, a mouse, or an electronic stylus. Similarly, the input / output controller 1310 also provides output to a display screen, a printer, or other types of output devices.

[0221] The mass storage device 1307 is connected to the central processing unit 1301 through a mass storage controller (not shown) connected to the system bus 1305. The mass storage device 1307 and its associated computer readable media provide non-volatile storage for the computer device 1300. That is, the mass storage device 1307 may include a computer readable medium (not shown) such as a hard disk or drive.

[0222] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include random access memory (RAM), read-only memory (ROM), flash memory or other solid-state storage technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, cassette, magnetic tape, disk storage or other magnetic storage devices. Of course, those skilled in the art will know that the computer storage medium is not limited to the above. The above-mentioned system memory 1304 and mass storage device 1307 can be collectively referred to as memory.

[0223] The memory stores one or more programs, and the one or more programs are configured to be executed by one or more central processing units 1301. The one or more programs contain instructions for implementing the above-mentioned methods. The central processing unit 1301 executes the one or more programs to implement the methods provided by the above-mentioned various method embodiments.

[0224] According to various embodiments of the present application, the computer device 1300 can also be connected to a remote computer on the network through a network such as the Internet. That is, the computer device 1300 can be connected to the network 1312 through the network interface unit 1311 connected to the system bus 1305, or the network interface unit 1311 can be used to connect to other types of networks or remote computer systems (not shown).

[0225] The memory also includes one or more programs, which are stored in the memory and include steps executed by a computer device in the method provided in the embodiment of the present application.

[0226] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is loaded and executed by a processor to implement the method described in any of the above embodiments.

[0227] Optionally, the computer readable storage medium may include: ROM, RAM, solid state drives (SSD) or optical disks, etc. Among them, RAM may include resistance random access memory (ReRAM) and dynamic random access memory (DRAM).

[0228] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method described in the above embodiment.

[0229] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0230] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A device layout method for a chip layout, characterized in that: The method comprises: Acquire a chip layout, on which a first device and a second device are to be arranged; Determining a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used to layout the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout; When the genus region does not support placement of the second device, the second device is placed in a region outside the genus region on the chip layout based on a second placement parameter of the second device and the genus region.

2. The method according to claim 1, characterized in that: The first layout parameter includes a layout node sequence, the layout node sequence includes layout nodes connected in sequence, and a connected area formed by the layout nodes connected in sequence is a layout area of ​​the first device; The determining, based on the first layout parameter of the first device, a genus region corresponding to the first device in the chip layout includes: Determine a first connected node and a second connected node in the layout node sequence, wherein the first connected node and the second connected node are adjacent nodes in the layout node sequence, and a line connecting the first connected node and the second connected node is located inside the connected area; Taking the first connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a first direction to obtain a first closed curve formed by connecting the layout nodes; Taking the second connected node as a starting point, sequentially traverse the layout nodes in the layout node sequence in a second direction to obtain a second closed curve formed by connecting the layout nodes, wherein the first direction is opposite to the second direction; The genus region is determined based on the first closed curve and the second closed curve.

3. The method according to claim 2, characterized in that The determining of the first connected node and the second connected node in the arranged node sequence comprises: Determine a layout node having the same node coordinates as the head layout node in the layout node sequence as the first connected node; An adjacent node of the first connected node is determined as the second connected node.

4. The method according to claim 2, characterized in that: The determining the genus region based on the first closed curve and the second closed curve comprises: When the enclosed area corresponding to the second closed curve is within the enclosed area corresponding to the first closed curve, the enclosed area corresponding to the second closed curve is determined as the genus area.

5. The method according to claim 1, characterized in that The step of arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region includes: Based on the second layout parameters, determining a candidate layout area for the second device in the chip layout; When the genus region does not support placement of the second device and there is an intersection between the candidate placement region and the genus region, the second device is placed in a region other than the intersection among the candidate placement regions.

6. The method according to claim 5, characterized in that The method further comprises: When the genus region supports placement of the second device and there is an intersection between the candidate placement region and the genus region, or when there is no intersection between the candidate placement region and the genus region, the second device is placed in the candidate placement region.

7. The method according to claim 5 or 6, characterized in that: After determining the candidate layout area of ​​the second device in the chip layout based on the second layout parameter, the method further includes: Based on at least one of the device type, device structure or device function of the first device, determining the support of the layout of the second device by the defective region corresponding to the first device, wherein the layout support includes that the defective region does not support the layout of the second device or the defective region supports the layout of the second device; or Based on the switch state of the control having the genus layout control function, the layout support status of the genus area corresponding to the first component to the second component is determined.

8. The method according to claim 7, characterized in that The determining, based on at least one of a device type, a device structure, or a device function of the first device, a layout support condition of the genus region corresponding to the first device for the second device includes: The first layout parameters of the first device are matched with reference layout parameters of a reference device, and if the match is successful, the device structure corresponding to the reference device is used as the device structure of the first device, wherein the reference device is a device storing the corresponding device structure.

9. The method according to claim 1, characterized in that: The second layout parameter includes a distance limit parameter between the second device and the first device; After arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region, the method further includes: Determine a candidate layout adjustment region of the second device, the candidate layout adjustment region being a candidate layout region for performing layout adjustment on the second device, wherein a density of the second device after the layout adjustment is higher than a density of the second device before the layout adjustment; When there is no intersection between the candidate placement adjustment region and the genus region, and the distance between the candidate placement adjustment region and the placement region of the first component is greater than or equal to the distance limit parameter, the second component is placed in the candidate placement adjustment region.

10. The method according to claim 9, characterized in that The method further comprises: In the case where there is an intersection between the candidate layout adjustment region and the genus region, or the distance between the candidate layout adjustment region and the layout region of the first device is less than the distance limit parameter, determining an adjustment step set, wherein the adjustment step set includes at least one candidate adjustment step; Based on the i-th candidate adjustment step in the adjustment step set, translating the candidate layout adjustment area; When there is no intersection between the candidate layout adjustment region after translation and the genus region, and the distance between the candidate layout adjustment region and the layout region of the first device is greater than or equal to the distance limit parameter, layout the second device in the candidate layout adjustment region after translation; When there is an intersection between the candidate layout adjustment area after translation and the defect area, or when the distance between the candidate layout adjustment area and the layout area of ​​the first device is less than the distance limit parameter, the candidate layout adjustment area is translated based on the i+1th candidate adjustment step in the adjustment step set.

11. The method according to claim 1, characterized in that: After arranging the second device on the chip layout based on the second arrangement parameter of the second device and the genus region, the method further includes: When the area of ​​the defective region is greater than the area threshold, the second device is added to the defective region, wherein the number of the second devices added is positively correlated with the area of ​​the defective region; or A sub-block in the chip layout is determined, wherein the sub-block includes at least one deficient region; and when a density of the second devices in the sub-block is less than a density threshold, the second devices are added in the deficient region.

12. The method according to claim 11, characterized in that The second layout parameter includes a distance limit parameter between the second device and the first device, and the adding of the second device in the genus region includes: determining a candidate region for adding the second device; When the distance between the candidate additional region and the layout region of the first component is greater than or equal to the distance limit parameter, the second component is added in the candidate additional region.

13. The method according to claim 11, characterized in that When the density of the second devices in the sub-block is less than a density threshold, adding the second devices in the genus region comprises: Arrange all the genus regions in the sub-block in descending order of area to obtain a genus region sequence; When the density of the second devices in the sub-block is less than a density threshold, the second devices are arranged in the genus regions in the genus region sequence in sequence until the density of the second devices is greater than or equal to the density threshold.

14. A device for placing devices in a chip layout, characterized in that: The device comprises: An acquisition module, used for acquiring a chip layout, on which the first device and the second device are to be arranged; a determination module, configured to determine a genus region corresponding to the first device in the chip layout based on a first layout parameter of the first device, wherein the first layout parameter is a parameter used for laying out the first device on the chip layout, and the genus region refers to a hollow region located inside the first device in the chip layout; A layout module is used to layout the second device in an area outside the genus area on the chip layout based on a second layout parameter of the second device and the genus area when the genus area does not support the layout of the second device.

15. A computer device, characterized in that: The computer device includes a processor and a memory; the memory stores at least one instruction, and the at least one instruction is used to be executed by the processor to implement the device layout method of the chip layout as described in any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and the instruction is loaded and executed by a processor to implement the device layout method of a chip layout as claimed in any one of claims 1 to 13.

17. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium; a processor of a terminal reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the terminal executes the device layout method of a chip layout as described in any one of claims 1 to 13.

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