Resistance network establishment method and device, computer equipment and medium

Abstract

The invention relates to a resistance network establishment method and device, computer equipment and a medium. The resistance network establishment method comprises the following steps: determining a first equivalent matrix of internal nodes of a first resistance network in an initial circuit, wherein the internal nodes are nodes for electrically connecting resistors; performing reduction processing on the first equivalent matrix to obtain feature information for reflecting a second equivalent matrix, the second equivalent matrix being the reduced first equivalent matrix; constructing a second resistance network comprising a plurality of internal nodes according to the feature information; wherein the first number of the internal nodes in the first resistance network is greater than the second number of the internal nodes in the second resistance network. The second resistance network is constructed through the feature information in the reduced second equivalent matrix, the number of internal nodes is reduced, and a plurality of internal nodes are reserved to effectively reflect the first resistance network, so that the precision of the resistance network is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a method, device, computer equipment and medium for establishing a resistor network. Background Art

[0002] During the design and development process of the circuit, it is necessary to verify through pre-simulation and post-simulation to ensure that the circuit functions meet the requirements. Since the post-simulation circuit contains a large number of electrical components such as resistors and capacitors, the circuit needs to be simplified to reduce the scale of the post-simulation circuit. However, after simplifying the resistor network to a star network, it cannot effectively reflect the resistor network because it only contains one node where the resistor is electrically connected to the resistor, resulting in low accuracy of the resistor network. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a method, device, computer equipment and medium for establishing a resistor network.

[0004] According to a first aspect of an embodiment of the present disclosure, a method for establishing a resistor network is provided, and the method for establishing a resistor network includes:

[0005] Determine a first equivalent matrix of internal nodes of a first resistor network in the initial circuit, wherein the internal nodes are nodes where resistors are electrically connected to each other;

[0006] Simplifying the first equivalent matrix to obtain characteristic information reflecting a second equivalent matrix, where the second equivalent matrix is ​​the simplified first equivalent matrix;

[0007] According to the characteristic information, construct a second resistor network including a plurality of the internal nodes;

[0008] Wherein, a first number of the internal nodes in the first resistor network is greater than a second number of the internal nodes in the second resistor network.

[0009] In some embodiments of the present disclosure, determining a first equivalent matrix of internal nodes of a first resistor network in an initial circuit includes:

[0010] determining an admittance matrix of the initial circuit;

[0011] The first equivalent matrix is ​​determined according to the partial sub-admittance matrix in the admittance matrix.

[0012] In some embodiments of the present disclosure, the simplifying of the first equivalent matrix to obtain characteristic information reflecting the second equivalent matrix includes:

[0013] Performing singular value decomposition on the first equivalent matrix to obtain an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values;

[0014] Screening the singular values ​​in the diagonal matrix in descending order of the singular values ​​to obtain the second number of first singular values;

[0015] Selecting a first singular vector corresponding to the first singular value from the orthogonal matrix;

[0016] The feature information includes the first singular value and the first singular vector.

[0017] In some embodiments of the present disclosure, the step of screening the singular values ​​in the diagonal matrix in descending order of the singular values ​​to obtain the second number of first singular values ​​includes:

[0018] Determining a singular value ratio of each singular value to a maximum singular value;

[0019] The singular values ​​corresponding to each of the singular value ratios greater than a preset ratio and some of the singular value ratios less than the preset ratio are taken as the first singular values.

[0020] In some embodiments of the present disclosure, the characteristic information includes the first singular value and the first singular vector of the second quantity; and constructing a second resistor network including a plurality of the internal nodes according to the characteristic information includes:

[0021] Determine an equivalent resistance between each of the internal nodes and each of the port nodes according to each of the second singular vectors, wherein the second singular vectors are related to the first singular vectors, and the port nodes are nodes where the resistor is electrically connected to a peripheral circuit;

[0022] The second resistor network is constructed, the number of the internal nodes being the second number and only including the equivalent resistors.

[0023] In some embodiments of the present disclosure, before determining the equivalent resistance between each of the internal nodes and each of the port nodes according to each of the second singular vectors, the method for establishing the resistor network further includes:

[0024] Correcting each of the first singular vectors to obtain each of the second singular vectors; and / or,

[0025] The first singular values ​​are corrected to obtain second singular values.

[0026] In some embodiments of the present disclosure, the method for establishing the resistor network further includes:

[0027] Sum each component in each of the first singular vectors to obtain a plurality of correction components;

[0028] The step of correcting the first singular vectors to obtain the second singular vectors includes:

[0029] Correcting the corresponding first singular vectors using the correction components and the first singular values ​​to obtain the second singular vectors; and / or,

[0030] The step of correcting the first singular value to obtain each second singular value includes:

[0031] The corresponding first singular values ​​are corrected by using the correction components to obtain the second singular values.

[0032] According to a second aspect of an embodiment of the present disclosure, a device for establishing a resistor network is provided, the device for establishing a resistor network comprising:

[0033] A determination module, the determination module is used to determine a first equivalent matrix of internal nodes of a first resistor network in an initial circuit, the internal nodes being nodes where resistors are electrically connected to each other;

[0034] A processing module, the processing module is used to simplify the first equivalent matrix to obtain characteristic information reflecting a second equivalent matrix, the second equivalent matrix is ​​the simplified first equivalent matrix;

[0035] A construction module, wherein the construction module is used to construct a second resistor network including a plurality of the internal nodes according to the characteristic information;

[0036] Wherein, a first number of the internal nodes in the first resistor network is greater than a second number of the internal nodes in the second resistor network.

[0037] According to a third aspect of an embodiment of the present disclosure, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in the first aspect are implemented.

[0038] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0039] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0040] Determine a first equivalent matrix of internal nodes of the first resistor network in the initial circuit to obtain an equivalent matrix reflecting the first resistor network. Simplify the first equivalent matrix to simplify the number of internal nodes and obtain characteristic information for reflecting the second equivalent matrix. According to the characteristic information, construct a second resistor network including multiple internal nodes, so that the second number of internal nodes in the second resistor network is less than the first number of internal nodes in the first resistor network. The second resistor network is constructed by the characteristic information in the simplified second equivalent matrix, the number of internal nodes is reduced and a plurality of internal nodes are retained to effectively reflect the first resistor network, thereby improving the accuracy of the resistor network.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0043] Figure 1-1 It is a schematic diagram of the structure of an initial resistance network;

[0044] Figure 1-2 It is a structural diagram of a star resistor network;

[0045] Figure 2 is a flow chart of a method for establishing a resistor network according to an exemplary embodiment;

[0046] Figure 3 is a flow chart of a method for establishing a resistor network according to another exemplary embodiment;

[0047] Figure 4 is a flow chart of a method for establishing a resistor network according to another exemplary embodiment;

[0048] Figure 5 is a flow chart of a method for establishing a resistor network according to another exemplary embodiment;

[0049] Figure 6 is a schematic diagram of a singular value distribution according to an exemplary embodiment;

[0050] Figure 7-1 is a voltage variation curve of a port node when the second number is 1 according to an exemplary embodiment;

[0051] Figure 7-2 is a voltage variation curve of the port node when the second number is 28 according to an exemplary embodiment;

[0052] Figure 7-3 is a voltage variation curve of the port node when the second number is 30 according to an exemplary embodiment;

[0053] Figure 8 is a block diagram of a device for establishing a resistor network according to an exemplary embodiment;

[0054] Fig. 9 It is a block diagram of a computer device according to an exemplary embodiment.

[0055] In the figure:

[0056] 10-determination module; 20-processing module; 30-construction module; 100-computer device; 101-computing unit; 102-ROM; 103-RAM; 104-bus; 105-input / output interface; 106-input unit; 107-output unit; 108-storage unit; 109-communication unit. DETAILED DESCRIPTION

[0057] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of methods consistent with some aspects of the present invention as detailed in the appended claims. It should also be understood that the term "and / or" used in the present invention refers to and includes any or all possible combinations of one or more associated listed items.

[0058] During the design and development of the circuit, it is necessary to verify through pre-simulation and post-simulation to ensure that the circuit functions meet the requirements. Since the parasitic parameters of the layout need to be extracted during the post-simulation of the circuit, a large number of electrical components such as resistors and capacitors are added to describe the mutual influence of voltage and current between traces, resulting in a circuit scale far exceeding the circuit scale during the pre-simulation. In order to reduce the circuit scale during the post-simulation process, it is necessary to simplify the circuit containing a large number of electrical components such as resistors and capacitors, while reducing the circuit scale and ensuring the accuracy of the circuit as much as possible. Among them, in the process of circuit simplification, it is necessary to reduce the internal nodes where resistors are electrically connected to resistors, while keeping the port nodes where resistors are electrically connected to peripheral circuits unchanged.

[0059] In the related art, a method for establishing a resistor network is provided, such as Figure 1-1 and Figure 1-2As shown, the method uses the linear least squares method to fit the equivalent resistance between the ports of the circuit before simplification to obtain the equivalent resistance in the star network, and then constructs the simplified resistance network. Among them, the nodes located at the edge and the middle represent internal nodes, the four nodes located at the four corners represent port nodes, and resistances are set between internal nodes and internal nodes, and resistances are set between internal nodes and port nodes. Since the star-shaped resistance network contains only one internal node, and an equivalent resistance is set between the internal node and each port node, the circuit scale is reduced. However, after the resistance network is simplified to a star network, the resistance network cannot be effectively reflected because it only contains a node where a resistor is electrically connected to a resistor, resulting in low accuracy of the resistance network.

[0060] In order to solve the above technical problems, the present disclosure provides a method for establishing a resistor network, by obtaining characteristic information reflecting a second equivalent matrix by simplifying a first equivalent matrix of internal nodes to construct a second resistor network including multiple internal nodes, and retaining a certain number of internal nodes to reflect the first resistor network while reducing the circuit scale, thereby improving the accuracy of the resistor network.

[0061] The present disclosure provides a method for establishing a resistor network. Figure 2 As shown, the method includes:

[0062] S100, determining a first equivalent matrix of internal nodes of a first resistor network in an initial circuit, wherein the internal nodes are nodes where resistors are electrically connected.

[0063] S200, simplifying the first equivalent matrix to obtain characteristic information used to reflect the second equivalent matrix, the second equivalent matrix being the simplified first equivalent matrix.

[0064] S300: construct a second resistor network including a plurality of internal nodes according to the characteristic information.

[0065] The first number of internal nodes in the first resistor network is greater than the second number of internal nodes in the second resistor network.

[0066] In this embodiment, a first equivalent matrix of the internal nodes of the first resistor network in the initial circuit is determined to obtain an equivalent matrix reflecting the first resistor network. The first equivalent matrix is ​​simplified to simplify the number of internal nodes to obtain characteristic information for reflecting the second equivalent matrix. According to the characteristic information, a second resistor network including multiple internal nodes is constructed, so that the second number of internal nodes in the second resistor network is less than the first number of internal nodes in the first resistor network. The second resistor network is constructed by the characteristic information in the simplified second equivalent matrix, the number of internal nodes is reduced and a plurality of them are retained to effectively reflect the first resistor network, thereby improving the accuracy of the resistor network.

[0067] Exemplarily, in the second resistor network constructed by the resistor network establishment method provided by the present disclosure, the second number of internal nodes of the second resistor network is reduced and the second number is multiple. That is, on the basis of FIG. 1, there are one or more internal nodes located in the middle, and each internal node is electrically connected to each port node with an equivalent resistor, and no resistor is electrically connected between any two internal nodes.

[0068] In one embodiment, if Figure 3 As shown, the first equivalent matrix of the internal nodes of the first resistor network in the initial circuit in step S100 is determined by:

[0069] S110, determining the admittance matrix of the initial circuit.

[0070] S120. Determine a first equivalent matrix according to some sub-admittance matrices in the admittance matrix.

[0071] In this embodiment, the admittance matrix of the initial circuit is determined to obtain the admittance matrix of the interaction between each internal node, between each port node, and between the internal node and the port node. According to the partial sub-admittance matrix in the admittance matrix, the first equivalent matrix is ​​determined, and the scale of the first equivalent matrix is ​​reduced. By determining the first equivalent matrix through the partial sub-admittance matrix in the admittance matrix, the characteristic information can be determined by the first equivalent matrix with a small scale, thereby reducing the complexity of establishing the resistor network.

[0072] Exemplarily, the determination of the admittance matrix of the initial circuit in step S110 may be to number the nodes in the initial circuit in advance, with the numbers of the internal nodes being placed in front and the numbers of the port nodes being placed in the back. For example, the total number of nodes is N, and the number of internal nodes is N. i And the number of port nodes is N p , then N=N i +N p Among them, numbers 1 to N i The node is an internal node, numbered N i The nodes from +1 to N are port nodes. Based on the renumbered nodes, the admittance matrix of the initial circuit is established. The admittance matrix can be expressed in the following form:

[0073]

[0074] Among them, A 11 A represents the sub-admittance matrix of the interaction between internal nodes. 12 A represents the sub-admittance matrix of the interaction between each internal node and each port node. 21 Indicates A 12 The transposed matrix, A 22The sub-admittance matrix represents the interaction between each port node. When there is a resistive electrical connection between two nodes, the four elements at the corresponding position in the sub-admittance matrix are non-zero elements. When there is no resistive electrical connection between two nodes, two elements at the corresponding position in the sub-admittance matrix are non-zero elements and two elements are zero elements.

[0075] Exemplarily, in step S120, the first equivalent matrix is ​​determined according to the partial subadmittance matrix in the admittance matrix, and the first equivalent matrix can be determined by using Gaussian elimination method. The first equivalent matrix can be expressed in the following form:

[0076]

[0077] Wherein, K represents a first equivalent matrix. Since the first equivalent matrix is ​​an equivalent matrix of internal nodes of the first resistor network, the first equivalent matrix is ​​a symmetric matrix.

[0078] In one embodiment, if Figure 4 As shown, the first equivalent matrix is ​​simplified in step S200, and the characteristic information used to reflect the second equivalent matrix is ​​determined in the following manner:

[0079] S210, performing singular value decomposition on the first equivalent matrix to obtain an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values.

[0080] S220. Screen the singular values ​​in the diagonal matrix in descending order to obtain a second number of first singular values.

[0081] S230. Select a first singular vector corresponding to the first singular value from the orthogonal matrix.

[0082] The characteristic information includes a first singular value and a first singular vector.

[0083] In this embodiment, the first equivalent matrix is ​​subjected to singular value decomposition to obtain a unique orthogonal matrix containing singular vectors and a diagonal matrix containing singular values, so as to construct a second resistor network through singular values ​​and singular vectors. The singular values ​​are screened in the diagonal matrix in order from large to small to obtain a second number of first singular values, so as to select the first singular value with a large effect in the first resistor network. The first singular vector corresponding to the first singular value is selected from the orthogonal matrix to construct the second resistor network through the first singular vector with a large effect. By selecting the first singular value and the first singular vector with a large effect as feature information to construct the second resistor network, the effect of the second resistor network is made close to that of the first resistor network while reducing the number of internal nodes, thereby improving the accuracy of the resistor network.

[0084] Exemplarily, the singular value decomposition of the first equivalent matrix in step S210 is performed to obtain an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values, which are expressed by the following formula:

[0085] K=UDV T ;

[0086] Among them, U represents the left singular vector matrix, D represents the diagonal matrix, and V represents the right singular vector matrix. Since the first equivalent matrix is ​​a symmetric matrix, the left singular vector matrix and the right singular vector matrix are the same. An orthogonal matrix is ​​a left singular vector matrix or a right singular vector matrix. The elements of each column in an orthogonal matrix constitute a singular vector, and the elements of the diagonal in a diagonal matrix are singular values.

[0087] In one embodiment, in step S220, singular values ​​are screened in the diagonal matrix in descending order to obtain the second number of first singular values, which are determined in the following manner:

[0088] Determine the singular value ratio of each singular value to the largest singular value.

[0089] The singular values ​​corresponding to the ratios of each singular value greater than the preset ratio and some singular value ratios less than the preset ratio are taken as first singular values.

[0090] In this embodiment, since the size of the singular value affects the effect of the singular value, and the size of the singular value corresponding to each initial circuit is different, it is impossible to screen with the preset singular value. According to the order of the singular values ​​from large to small, the singular value ratio of each singular value to the maximum singular value is determined to determine the degree of effect of each singular value. The singular values ​​corresponding to the ratios of each singular value greater than the preset ratio and the ratios of some singular values ​​less than the preset ratio are taken as the first singular value to retain the singular values ​​with a large degree of effect. By selecting the first singular value in the form of a singular value ratio, a large number of singular values ​​with poor effects can be filtered, thereby reducing the complexity of establishing the resistor network.

[0091] Exemplarily, the preset ratio ranges from 0 to 1. The preset ratio ranges from 0.2, 0.5, 0.8, and the like.

[0092] Exemplarily, the determination of the singular value ratio of each singular value to the maximum singular value in the above step may be to determine the singular value ratio of each singular value to the maximum singular value in the order of the singular values ​​from large to small. The singular value corresponding to each singular value ratio greater than the preset ratio and part of the singular value ratio less than the preset ratio in the above step may be to determine a singular value just less than the preset ratio, and to use the singular value and each singular value before it as the first singular value. That is, the relationship between the singular value ratio and the preset ratio is as follows:

[0093]

[0094] Where M represents the second quantity, d M-1 represents the M-1th singular value, d M represents the Mth singular value, d1 represents the maximum singular value, and ε represents the preset ratio.

[0095] In one embodiment, the feature information includes a second number of first singular values ​​and first singular vectors. Figure 5 As shown, in step S300, the second resistor network including a plurality of internal nodes is constructed according to the characteristic information by the following method:

[0096] S310, determining an equivalent resistance between each internal node and each port node according to each second singular vector, the second singular vector is related to the first singular vector, and the port node is a node where the resistor is electrically connected to a peripheral circuit.

[0097] S320: Construct a second resistor network having a second number of internal nodes and only including equivalent resistors.

[0098] In the present embodiment, since in the constructed second resistance network, there is no resistance electrically connected between each internal node, and there is a resistance electrically connected between each internal node and each port node. According to each second singular vector, the equivalent resistance between each internal node and each port node is determined to obtain the resistance in the second resistance network. A second resistance network is constructed in which the number of internal nodes is the second number and only includes each equivalent resistance, so as to obtain a second resistance network after the number of internal nodes is reduced. By constructing the second resistance network according to each second singular vector, the number of internal nodes in the second resistance network is small and the effect is close to that of the first resistance network, thereby improving the accuracy of the resistance network.

[0099] Exemplarily, in step S310, determining the equivalent resistance between each internal node and each port node according to each second singular vector is expressed by the following formula:

[0100]

[0101] Among them, R ij represents the equivalent resistance between the i-th internal node and the j-th port node, Y i (j) represents the jth component of the i-th second singular vector.

[0102] In one embodiment, before determining the equivalent resistance between each internal node and each port node according to each second singular vector in step S310, the method for establishing a resistor network further includes:

[0103] Each first singular vector is corrected to obtain each second singular vector.

[0104] In this embodiment, since the first singular vectors are partial singular vectors in the orthogonal matrix, if the second resistor network is directly constructed, the accuracy of the second resistor network may be affected. By correcting each first singular vector to obtain each second singular vector, the effect of the second resistor network constructed by the second singular vector is close to that of the first resistor network, thereby improving the accuracy of the resistor network.

[0105] In one embodiment, the method for establishing a resistor network further includes:

[0106] The components in each first singular vector are summed up respectively to obtain a plurality of correction components.

[0107] In the above steps, the first singular vector is corrected, and each second singular vector is determined in the following manner:

[0108] The corresponding first singular vectors are corrected using the correction components and the first singular values ​​to obtain second singular vectors.

[0109] In this embodiment, since the first singular vector is a singular vector selected from the orthogonal matrix for constructing the second resistor network, each component in each first singular vector is summed up respectively, so that each first singular vector corresponds to a correction component. The corresponding first singular vector is corrected with the correction component and the first singular value to obtain each second singular vector to reduce the influence of the filtered singular vector. By correcting the corresponding first singular vector with the correction component and the first singular value, the effect of the second resistor network constructed by the second singular vector is close to that of the first resistor network, thereby improving the accuracy of the resistor network.

[0110] Exemplarily, in the above steps, each component in each first singular vector is summed up to obtain multiple correction components represented by the following formula:

[0111]

[0112] Among them, θ i represents the i-th correction component, X i (p) represents the pth component in the i-th first singular vector.

[0113] Exemplarily, in the above steps, the corresponding first singular vectors are corrected by using the correction component and the first singular value to obtain each second singular vector represented by the following formula:

[0114] Y i =-d i θ i X i ;

[0115] Among them, Y i represents the i-th second singular vector, di represents the first singular value of the i-th order, X i represents the i-th first singular vector.

[0116] It is understandable that, in addition to correcting each first singular vector to obtain each second singular vector, each first singular vector may also be directly used as each second singular vector, which is not limited here.

[0117] In one embodiment, before determining the equivalent resistance between each internal node and each port node according to each second singular vector in step S310, the method for establishing a resistor network further includes:

[0118] Each first singular value is corrected to obtain each second singular value.

[0119] In this embodiment, since the first singular values ​​are some singular values ​​in the diagonal matrix, if they are directly used to reflect the second resistor network, the accuracy of the second resistor network may be affected. By correcting each first singular value to obtain each second singular value, the second singular value can effectively reflect the second resistor network, thereby improving the accuracy of the resistor network.

[0120] In one embodiment, the method for establishing a resistor network further includes:

[0121] The components in each first singular vector are summed up respectively to obtain a plurality of correction components.

[0122] In the above steps, each first singular value is corrected to obtain each second singular value determined by the following method:

[0123] The corresponding first singular values ​​are corrected with the correction components to obtain respective second singular values.

[0124] In this embodiment, since the first singular vector is a singular vector selected from the orthogonal matrix for constructing the second resistor network, each component in each first singular vector is summed up respectively, so that each first singular vector corresponds to a correction component. The corresponding first singular value is corrected with the correction component to obtain each second singular value to reduce the influence of the filtered singular value. By correcting the corresponding first singular value with the correction component, the second singular value can effectively reflect the second resistor network, thereby improving the accuracy of the resistor network.

[0125] Exemplarily, in the above steps, the corresponding first singular values ​​are corrected by the correction components to obtain each second singular value represented by the following formula:

[0126]

[0127] Among them, s i represents the i-th second singular value.

[0128] It is understandable that, in addition to correcting each first singular value to obtain each second singular value, each first singular value may also be directly used as each second singular value, which is not limited here.

[0129] Exemplarily, after constructing the second resistor network including a plurality of internal nodes according to the characteristic information in step S300 , a target circuit including the second resistor network may be constructed to perform post-simulation of the target circuit.

[0130] Exemplarily, taking the total number of nodes being 115301 as an example, the establishment method and effect of the resistor network provided by the present disclosure are described.

[0131] (1) In the initial circuit, the internal node N i The number of port nodes is 115201, p The number of nodes is 100, and the total number of nodes N is 115301. Number each node in the initial circuit. Put the numbers of internal nodes in front and the numbers of port nodes in the back. According to the renumbered nodes, establish the admittance matrix of the initial circuit:

[0132]

[0133] Among them, A 11 A represents the sub-admittance matrix of the interaction between internal nodes. 12 A represents the sub-admittance matrix of the interaction between each internal node and each port node. 21 Indicates A 12 The transposed matrix, A 22 A represents the sub-admittance matrix of the interaction between each port node. 11 The dimension of A is 115201×115201. 12 The dimension is 115201×100, A 22 The dimension is 100×100.

[0134] According to A in the admittance matrix 11 , A 12 and A 21 Sub-admittance matrix, determine the first equivalent matrix:

[0135]

[0136] Wherein, K represents the first equivalent matrix. Since the first equivalent matrix is ​​the equivalent matrix of the internal nodes of the first resistor network, the first equivalent matrix is ​​a symmetric matrix, and the dimension of the first equivalent matrix is ​​100×100.

[0137] (2) Perform singular value decomposition on the first equivalent matrix to obtain an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values:

[0138] K=UDV T ;

[0139] Among them, U represents the left singular vector matrix (orthogonal matrix), D represents the diagonal matrix, and V represents the right singular vector matrix. Since the first equivalent matrix is ​​a symmetric matrix, the left singular vector matrix and the right singular vector matrix are the same. The dimensions of the left singular vector matrix, the diagonal matrix, and the right singular vector matrix are all 100×100.

[0140] Set the preset ratio ε to 0.1. Figure 6 As shown, the first singular value d1 = 99.97, the first 28 singular values ​​are almost identical, and the 29th singular value d 29 =42, the 30th singular value d 30 =1.6. Determine that the singular value that is just less than the preset ratio is the 30th singular value, and use the singular value and each singular value before it as the first singular value. That is, the second number of first singular values ​​is 30. Select the first 30 columns from the orthogonal matrix as 30 first singular vectors. Wherein, the abscissa represents the number of the singular value, and the ordinate represents the singular value.

[0141] (3) Sum the components of each first singular vector separately to obtain multiple correction components:

[0142]

[0143] Among them, θ i represents the i-th correction component, X i (p) represents the pth component in the i-th first singular vector.

[0144] The corresponding first singular values ​​are corrected with the correction component to obtain the second singular values:

[0145]

[0146] Among them, s i represents the second singular value of the i-th order, d i represents the i-th first singular value.

[0147] The corresponding first singular vector is corrected by the correction component and the first singular value, and each second singular vector is expressed by the following formula:

[0148] Y i =-d i θ i X i ;

[0149] Among them, Y i represents the i-th second singular vector, X i represents the i-th first singular vector.

[0150] According to each second singular vector, determine the equivalent resistance between each internal node and each port node:

[0151]

[0152] Among them, R ij represents the equivalent resistance between the i-th internal node and the j-th port node, Y i (j) represents the jth component of the i-th second singular vector.

[0153] A second resistor network having 30 internal nodes and only including equivalent resistors is constructed.

[0154] By using the resistor network establishment method provided by the present disclosure, a first resistor network including 115201 internal nodes can be simplified to a second resistor network including 30 internal nodes. Since an equivalent resistor is provided between each internal node and each port node, a total of 3000 resistors are included.

[0155] In order to verify the accuracy of the second resistor network, a 1A current source is set at each port node, and 0 to 10 -3 Ω -1 The random conductance is then grounded, and the voltage of the 100 port nodes of the first resistor network and the second resistor network is tested. The voltage error is expressed by the following formula:

[0156]

[0157] Where err represents the voltage error, V acc The vector V represents the voltages of the 99 port nodes obtained after the port nodes of the first resistor network are set with current sources. r It represents a vector consisting of voltages of 99 port nodes obtained after current sources are set at the port nodes of the second resistor network, and norm represents taking the norm of the vector.

[0158] The voltage errors under different second quantities may be as shown in Table 1.

[0159] Table 1:

[0160] Second quantity 1 28 30 Voltage Error 60％ 4.9％ 0.08％

[0161] It can be seen that when the second number of internal nodes is 1, the second resistor network cannot reflect the first resistor network at all. When the second number of internal nodes is 28 and 30, the voltage error has a large jump, which is due to Figure 6 The jump of singular values ​​in . Figure 7-1 to Figure 7-3 As shown, when the second number of internal nodes is 1, the voltage of the port node in the second resistor network cannot follow the voltage of the port node in the first resistor network. When the second number of internal nodes is 28, the voltage of the port node in the second resistor network partially follows the voltage of the port node in the first resistor network. When the second number of internal nodes is 30, the voltage of the port node in the second resistor network completely follows the voltage of the port node in the first resistor network. Wherein, accurate represents the voltage of the port node in the first resistor network, svd-reduction represents the voltage of the port node in the second resistor network, the abscissa represents the number of the port node, and the ordinate represents the voltage of the port node.

[0162] In an exemplary embodiment, a device for establishing a resistor network is provided, such as Figure 8 As shown, the resistor network establishment device includes a determination module 10, a processing module 20 and a construction module 30, wherein:

[0163] The determination module 10 is used to determine a first equivalent matrix of internal nodes of a first resistor network in an initial circuit, wherein the internal nodes are nodes where resistors are electrically connected.

[0164] The processing module 20 is used to simplify the first equivalent matrix to obtain characteristic information reflecting the second equivalent matrix, and the second equivalent matrix is ​​the simplified first equivalent matrix.

[0165] The construction module 30 is used to construct a second resistor network including a plurality of internal nodes according to the characteristic information.

[0166] The first number of internal nodes in the first resistor network is greater than the second number of internal nodes in the second resistor network.

[0167] In one embodiment, the determination module 10 is used to:

[0168] Determine the admittance matrix of the initial circuit.

[0169] A first equivalent matrix is ​​determined according to some subadmittance matrices in the admittance matrix.

[0170] In one embodiment, the processing module 20 is used to:

[0171] Performing singular value decomposition on the first equivalent matrix, obtaining an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values.

[0172] The singular values ​​are screened in the diagonal matrix in descending order to obtain a second number of first singular values.

[0173] A first singular vector corresponding to the first singular value is selected from the orthogonal matrix.

[0174] The characteristic information includes a first singular value and a first singular vector.

[0175] In one embodiment, the processing module 20 is used to:

[0176] Determine the singular value ratio of each singular value to the largest singular value.

[0177] The singular values ​​corresponding to the ratios of each singular value greater than the preset ratio and some singular value ratios less than the preset ratio are taken as first singular values.

[0178] In one embodiment, the construction module 30 is used to:

[0179] The equivalent resistance between each internal node and each port node is determined according to each second singular vector, the second singular vector is related to the first singular vector, and the port node is a node where the resistor is electrically connected to the peripheral circuit.

[0180] A second resistor network having a second number of internal nodes and only including equivalent resistors is constructed.

[0181] In one embodiment, the resistor network establishment device further includes a correction module, wherein:

[0182] The correction module is used to correct each first singular vector to obtain each second singular vector.

[0183] In one embodiment, the correction module is used to:

[0184] Each first singular value is corrected to obtain each second singular value.

[0185] In one embodiment, the correction module is used to:

[0186] The components in each first singular vector are summed up respectively to obtain a plurality of correction components.

[0187] In one embodiment, the correction module is used to:

[0188] The corresponding first singular vectors are corrected using the correction components and the first singular values ​​to obtain second singular vectors.

[0189] In one embodiment, the correction module is used to:

[0190] The corresponding first singular values ​​are corrected with the correction components to obtain respective second singular values.

[0191] In an exemplary embodiment, a computer device is provided, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above-mentioned methods for establishing a resistor network are implemented.

[0192] In an exemplary embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above-mentioned methods for establishing a resistor network are implemented. The computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0193] In an exemplary embodiment, a computer program product is provided, comprising a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned methods for establishing a resistor network are implemented.

[0194] refer to Fig. 9 , a block diagram of the structure of a computer device will now be described, the computer device 100 includes a computing unit 101, which can perform various appropriate actions and processes according to a computer program stored in a ROM 102 or a computer program loaded from a storage unit 108 to a RAM 103. In the RAM 103, various programs and data required for the operation of the computer device 100 can also be stored. The computing unit 101, the ROM 102, and the RAM 103 are connected to each other via a bus 104. An input / output (I / O) interface 105 is also connected to the bus 104.

[0195] A plurality of components in the computer device 100 are connected to the I / O interface 105, including: an input unit 106, an output unit 107, a storage unit 108, and a communication unit 109. The input unit 106 may be any type of device capable of inputting information to the computer device 100, the input unit 106 may receive input digital or character information, and generate key signal inputs related to user settings and / or function control of the computer device 100, and may include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 107 may be any type of device capable of presenting information, and may include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 108 may include but is not limited to a disk, an optical disk. The communication unit 109 allows the computer device 100 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and may include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0196] The computing unit 101 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 101 performs the various methods and processes described above, such as the establishment method of the resistor network. For example, in some embodiments, the establishment method of the resistor network may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 108. In some embodiments, part or all of the computer program may be loaded and / or installed on the computer device 100 via ROM 102 and / or a communication unit 109. When the computer program is loaded into RAM 103 and executed by the computing unit 101, one or more steps of the establishment method of the resistor network described above may be performed. Alternatively, in other embodiments, the computing unit 101 may be configured to perform the establishment method of the resistor network by any other appropriate means (e.g., by means of firmware).

[0197] The computer device 100 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components to execute the above-mentioned method for establishing a resistor network.

[0198] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed in this disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present invention are indicated by the claims.

[0199] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for establishing a resistor network, characterized in that: The method for establishing the resistor network includes: Determine a first equivalent matrix of internal nodes of a first resistor network in the initial circuit, wherein the internal nodes are nodes where resistors are electrically connected to each other; Simplifying the first equivalent matrix to obtain characteristic information reflecting a second equivalent matrix, where the second equivalent matrix is ​​the simplified first equivalent matrix; According to the characteristic information, construct a second resistor network including a plurality of the internal nodes; Wherein, a first number of the internal nodes in the first resistor network is greater than a second number of the internal nodes in the second resistor network.

2. The method for establishing a resistor network according to claim 1, characterized in that: The step of determining a first equivalent matrix of internal nodes of a first resistor network in an initial circuit comprises: determining an admittance matrix of the initial circuit; The first equivalent matrix is ​​determined according to the partial sub-admittance matrix in the admittance matrix.

3. The method for establishing a resistor network according to claim 1, characterized in that: The simplifying the first equivalent matrix to obtain characteristic information reflecting the second equivalent matrix includes: Performing singular value decomposition on the first equivalent matrix to obtain an orthogonal matrix containing singular vectors and a diagonal matrix containing singular values; Screening the singular values ​​in the diagonal matrix in descending order of the singular values ​​to obtain the second number of first singular values; Selecting a first singular vector corresponding to the first singular value from the orthogonal matrix; The feature information includes the first singular value and the first singular vector.

4. The method for establishing a resistor network according to claim 3, characterized in that: The step of screening the singular values ​​in the diagonal matrix in descending order of the singular values ​​to obtain the second number of first singular values ​​comprises: Determining a singular value ratio of each singular value to a maximum singular value; The singular values ​​corresponding to each of the singular value ratios greater than a preset ratio and some of the singular value ratios less than the preset ratio are taken as the first singular values.

5. The method for establishing a resistor network according to any one of claims 1 to 4, characterized in that: The characteristic information includes the first singular value and the first singular vector of the second quantity; and constructing a second resistor network including a plurality of the internal nodes according to the characteristic information, comprising: Determine an equivalent resistance between each of the internal nodes and each of the port nodes according to each of the second singular vectors, wherein the second singular vectors are related to the first singular vectors, and the port nodes are nodes where the resistor is electrically connected to a peripheral circuit; The second resistor network is constructed, the number of the internal nodes being the second number and only including the equivalent resistors.

6. The method for establishing a resistor network according to claim 5, characterized in that: Before determining the equivalent resistance between each of the internal nodes and each of the port nodes according to each of the second singular vectors, the method for establishing the resistor network further includes: Correcting each of the first singular vectors to obtain each of the second singular vectors; and / or, The first singular values ​​are corrected to obtain second singular values.

7. The method for establishing a resistor network according to claim 6, characterized in that: The method for establishing the resistor network also includes: Sum each component in each of the first singular vectors to obtain a plurality of correction components; The step of correcting the first singular vectors to obtain the second singular vectors includes: Correcting the corresponding first singular vectors using the correction components and the first singular values ​​to obtain the second singular vectors; and / or, The step of correcting the first singular value to obtain each second singular value includes: The corresponding first singular values ​​are corrected by using the correction components to obtain the second singular values.

8. A device for establishing a resistor network, characterized in that: The resistor network establishment device comprises: A determination module, the determination module is used to determine a first equivalent matrix of internal nodes of a first resistor network in an initial circuit, the internal nodes being nodes where resistors are electrically connected to each other; A processing module, the processing module is used to simplify the first equivalent matrix to obtain characteristic information reflecting a second equivalent matrix, the second equivalent matrix is ​​the simplified first equivalent matrix; A construction module, wherein the construction module is used to construct a second resistor network including a plurality of the internal nodes according to the characteristic information; Wherein, a first number of the internal nodes in the first resistor network is greater than a second number of the internal nodes in the second resistor network.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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