Chip design method and system based on IO multiplexing performance optimization, terminal and medium

Abstract

The invention provides a chip design method and system based on IO multiplexing performance optimization, a terminal and a medium, RTL codes are automatically generated by calling a script according to a constructed IO multiplexing information table and RTL codes of a high-speed IO output multiplexing module written in advance, and then the generated RTL codes are converted into corresponding circuits by utilizing a logic synthesis tool. The method comprises the following steps: firstly, carrying out IO (Input / Output) visualization on the basis of a chip size and a preliminary layout plan, and adjusting a position relationship between each functional module and an IO unit used by the functional module in the preliminary layout plan to obtain an optimized layout plan; and in the physically realized layout and post-layout stage, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the input path and the output path of the functional signal are optimized to obtain a design layout. According to the method, a physical design tool can automatically realize time sequence performance optimization of function multiplexing IO, support is provided for large-scale general chips to realize a high-speed IO protocol, RTL codes can be automatically generated, manpower is reduced, and the condition of wire winding of IO signal wiring is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a chip design method, system, terminal and medium based on IO multiplexing performance optimization. Background Art

[0002] MCU (microcontroller) and other general-purpose chips are widely used, so they generally use IO (input and output) function multiplexing, that is, each IO can be used for multiple different functions. Inside the chip, this is reflected in the connection of up to dozens of modules to the IO unit through complex multiplexing logic.

[0003] Although general-purpose chips such as MCUs have achieved design flexibility and wide application through IO function reuse, IO function reuse also brings challenges in optimizing the timing performance of physical design. Inside the chip, as many as dozens of modules are connected to the IO unit through complex multi-way selection logic, which makes it very difficult to optimize the timing offset between multi-bit data of the parallel data interface. Especially in applications that need to meet high-speed protocol requirements, such as the EMMC protocol requiring 8-bit data IO to achieve double-edge transmission at a frequency of 200MHz, and the DRAM interface requiring 32-bit data to be transmitted at a frequency of 200MHz, the timing performance of IO must meet extremely high standards. However, due to the complexity of IO multiplexing, these requirements are often difficult to meet, resulting in performance bottlenecks in the chip in high-speed data transmission scenarios, or even failure to meet application requirements. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a chip design method, system, terminal and medium based on IO multiplexing performance optimization, which is used to solve the technical problem of difficulty in optimizing physical design timing performance in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a chip design method based on IO multiplexing performance optimization, the method comprising: constructing an IO multiplexing information table; writing the RTL code of a high-speed IO output multiplexing module that cannot be optimized; calling a script to generate an RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module; using a logic synthesis tool to convert the generated RTL code into a corresponding circuit, and obtain a chip size and a preliminary layout plan; based on the chip size and the preliminary layout plan, IO visualization is performed, and the positional relationship between each functional module and the IO unit used by it in the preliminary layout plan is adjusted to obtain an optimized layout plan; in the layout and post-layout stages of physical implementation, the position of the corresponding module in the circuit is limited based on the optimized layout plan, and the functional signal input path and output path are optimized to obtain a design layout.

[0006] In one embodiment of the present invention, the multiplexing information table includes: high-speed function identifiers and IO multiplexing information of each function selection mode; wherein, the IO multiplexing information includes: function module ports associated with each IO in the current function selection mode and options of corresponding ports.

[0007] In one embodiment of the present invention, the RTL code for writing a non-optimizable high-speed IO output multiplexing module includes: defining a non-optimizable high-speed IO output multiplexing module that can receive a fixed number of functional output signals, and writing the RTL code using a hardware description language.

[0008] In one embodiment of the present invention, the conversion circuit includes: an IO unit, an IO control circuit, an IO output multiplexing circuit, a functional module, an IO input multiplexing circuit, an input flag buffer, and an output flag buffer; wherein, there are one or more IO units and functional modules, and each IO unit is connected to an IO output multiplexing circuit; each functional module can be connected to the associated IO unit through a correspondingly set IO input multiplexing circuit and an input flag buffer, or directly connected to the associated IO unit; the functional module is also connected to the IO output multiplexing circuit connected to the corresponding IO unit through an output flag buffer.

[0009] In one embodiment of the present invention, the IO output multiplexing circuit includes: an optimizable IO output multiplexing module and a non-optimizable high-speed IO output multiplexing module; wherein the high-speed IO output multiplexing module has a fixed number of high-speed signal input ports and low-speed signal input ports; the IO output multiplexing module is used to input non-high-speed functional signals from functional modules; the high-speed IO output multiplexing module is used to receive high-speed functional signals from functional modules through high-speed signal input ports; all non-high-speed functional signals transmitted by the IO output multiplexing module are multi-selected, and the non-high-speed functional signals after multi-selection are received through the low-speed signal input port.

[0010] In one embodiment of the present invention, the IO visualization is performed based on the chip size and the preliminary layout plan, and the positional relationship between each functional module and the IO unit used by it is adjusted in the preliminary layout plan to obtain an optimized layout plan, including: determining the IO unit arrangement based on the chip size and the preliminary layout plan, adding the position information of each IO unit to the IO reuse information table, and using a script tool to visualize the IO unit used by each functional module; based on the visualized IO unit position, adjusting the position of the corresponding functional module so that the distance between the functional module and the IO unit position associated with it is moderate, so as to obtain an optimized layout plan.

[0011] In one embodiment of the present invention, in the layout and post-layout stages of physical implementation, the positions of corresponding modules in the circuit are limited based on the optimized layout plan, and the functional signal input path and output path are optimized, including: in the layout stage of physical implementation, the positions of each functional module with high-speed function and its corresponding IO input multiplexing circuit are limited based on the optimized layout plan, and the position of the high-speed IO output multiplexing module is limited to the vicinity of its corresponding connected IO unit; in the post-layout stage of physical implementation, the functional signal output path is optimized by setting a fixed interval insertion buffer in the path between the output flag buffer and the high-speed IO output multiplexing module connected thereto, and the functional signal input path is optimized by setting a fixed interval insertion buffer between the IO unit and the input flag buffer connected thereto.

[0012] To achieve the above-mentioned purpose and other related purposes, the present invention provides a chip design system based on IO multiplexing performance optimization, the system comprising: a table construction module, used to construct an IO multiplexing information table; a high-speed IO output multiplexing module code writing module, used to write the RTL code of the non-optimizable high-speed IO output multiplexing module; an RTL code generation module, connected to the high-speed IO output multiplexing module code writing module, used to call a script to generate RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module; a logic synthesis module, connected to the RTL code generation module, used to generate RTL code using logic synthesis The synthesis tool converts the generated RTL code into the corresponding circuit, and obtains the chip size and the preliminary layout plan; the layout plan optimization module is connected to the logic synthesis module, and is used to perform IO visualization based on the chip size and the preliminary layout plan, and adjust the position relationship between each functional module and the IO unit used by it in the preliminary layout plan to obtain the optimized layout plan; the layout and post-layout module is connected to the layout plan optimization module, and is used to limit the position of the corresponding module in the circuit based on the optimized layout plan in the layout and post-layout stages of physical implementation, and optimize the functional signal input path and output path to obtain the design layout.

[0013] To achieve the above-mentioned purpose and other related purposes, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store computer programs; the one or more processors are connected to the memories and are used to run the computer programs to execute the chip design method based on IO multiplexing performance optimization.

[0014] To achieve the above-mentioned object and other related objects, the present invention provides a computer-readable storage medium, characterized in that a computer program is stored therein, and the computer program is executed by one or more processors to execute the method.

[0015] As described above, the present invention is a chip design method, system, terminal and medium based on IO reuse performance optimization, which has the following beneficial effects: the present invention automatically generates RTL code according to the constructed IO reuse information table and the RTL code of the high-speed IO output reuse module written in advance by calling the script, and then converts the generated RTL code into the corresponding circuit using the logic synthesis tool, and obtains the chip size and the preliminary layout plan, and then performs IO visualization based on the chip size and the preliminary layout plan, and adjusts the position relationship between each functional module and the IO unit used by it in the preliminary layout plan to obtain the optimized layout plan; in the layout and post-layout stage of physical implementation, the position of the corresponding module in the circuit is limited based on the optimized layout plan, and the input path and output path of the functional signal are optimized to obtain the design layout. The present invention enables the physical design tool to automatically optimize the timing performance of the functional reuse IO, provides support for large-scale general-purpose chips to implement high-speed IO protocols, and can also automatically generate RTL code to reduce manpower and avoid the situation where the IO signal routing occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Shown is a flow chart of a chip design method based on IO multiplexing performance optimization in one embodiment of the present invention.

[0017] Figure 2 Shown is a schematic diagram of an IO multiplexing information table in an embodiment of the present invention.

[0018] Figure 3 Shown is a schematic diagram of an optimized circuit in the prior art.

[0019] Figure 4 Shown is a schematic structural diagram of a conversion circuit in an embodiment of the present invention.

[0020] Figure 5 It is a schematic diagram showing the structure of an IO output multiplexing circuit in one embodiment of the present invention.

[0021] Figure 6 Shown is a schematic diagram of IO visualization results in one embodiment of the present invention.

[0022] Figure 7 Shown is a schematic diagram of the structure of a chip design system based on IO multiplexing performance optimization in one embodiment of the present invention.

[0023] Figure 8 Shown is a schematic structural diagram of an electronic terminal in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0025] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0026] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0027] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0028] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0029] The present invention provides a chip design method based on IO reuse performance optimization, which automatically generates RTL code according to the constructed IO reuse information table and the RTL code of the high-speed IO output multiplexing module written in advance by calling a script, and then converts the generated RTL code into a corresponding circuit using a logic synthesis tool, and obtains the chip size and preliminary layout planning, and then performs IO visualization based on the chip size and the preliminary layout planning, and adjusts the positional relationship between each functional module and the IO unit used by it in the preliminary layout planning to obtain an optimized layout planning; in the layout and post-layout stage of physical implementation, the corresponding module position in the circuit is limited based on the optimized layout planning, and the functional signal input path and output path are optimized to obtain a design layout. The present invention enables physical design tools to automatically optimize the timing performance of functional reuse IO, provides support for large-scale general-purpose chips to implement high-speed IO protocols, and can also automatically generate RTL code to reduce manpower, and avoid the situation where IO signal routing occurs winding.

[0030] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0031] like Figure 1 A flowchart of a chip design method based on IO multiplexing performance optimization in an embodiment of the present invention is shown.

[0032] The method comprises:

[0033] Step S1: Construct an IO multiplexing information table.

[0034] In one embodiment, the multiplexing information table includes: high-speed function identifiers of each function selection mode and IO multiplexing information; wherein, the high-speed function identifier of the function selection mode is used to identify whether each function selection mode belongs to a high-speed signal that needs to be optimized. The IO multiplexing information includes: the function module ports associated with each IO in the current function selection mode and the options of the corresponding ports. Among them, each function selection mode corresponds to a module that implements the function, that is, a function module, and each function module may include one or more ports. The options indicate the number of IOs that the same port of the same function module can be connected to, so as to avoid conflicts with IOs of other functions during IO multiplexing.

[0035] For example, Figure 2 , the first row is used to identify the function selection mode of IO multiplexing, and ALT is the abbreviation of Alternative. In this example, we have three function options (ALT1, ALT2, ALT3). The second row is used to identify whether each function option belongs to a high-speed signal that needs to be optimized. The first column is the name of the IO. The main body of the table is filled in from the second column of the third row. Among them, the function 1 module has port 1 and port 2, and port 1 and port 2 have two options, that is, each port can be connected to two IOs; the function 2 module has port 1 and port 2, and port 1 and port 2 have one option, that is, each port can be connected to one IO; the function 3 module has port 1, and port 1 has one option, that is, the port can be connected to one IO; such as Figure 2 , IO1 will be connected to option 2 of port 1 of function 1 module in ALT1 mode, such as the data bit 0 port of the DRAM controller. IO2 will be connected to option 2 of port 2 of function 1 module in ALT1 mode; IO3 will be connected to option 1 of port 1 of function 1 module in ALT1 mode, option 1 of port 1 of function 2 module in ALT2 mode, and option 1 of port 1 of function 3 module in ALT3 mode; IO4 will be connected to option 1 of port 2 of function 1 module in ALT1 mode, and option 1 of port 2 of function 2 module in ALT2 mode.

[0036] Step S2: Write the RTL code of the non-optimizable high-speed IO output multiplexing module.

[0037] In one embodiment, in the current digital circuit design, since the IO output multiplexing circuit of each IO may have different numbers and types of connected functional modules, the logic synthesis tool will optimize the circuit autonomously. The optimization result may be as follows: Figure 3 As shown, different data bit signals of the same function undergo very different logic delays when arriving at the IO unit, which makes it impossible to meet the requirement of low skew rate of high-speed signals.

[0038] In order to solve the above problems, this patent defines a high-speed IO output multiplexing module that can accept a fixed number of functional output signals and realize a multi-way selection function. The high-speed IO output multiplexing module code is written using a synthesizable hardware description language. Unlike traditional RTL descriptions, the code here will directly instantiate the logic gates in the standard cell library (such as AND gates, OR gates, multiplexers, etc.). When instantiating logic gates, faster types are given priority to ensure that the module can meet the requirements of high-speed signal transmission. The high-speed IO output multiplexing module is logically synthesized together with the top layer of the chip. During the logic synthesis process, the synthesis tool is instructed not to optimize the module through constraint files or by directly adding comments to the code. This ensures that all predefined logic gates in the module are retained and the delay size of the logic gates will not be modified. This can also ensure that the delay of signals with the same function is almost the same when passing through each high-speed IO output multiplexing module.

[0039] Step S3: calling a script to generate an RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module.

[0040] In detail, we can design an automated script that will parse the IO reuse information table and generate the final RTL code based on the table content and the predefined RTL code template.

[0041] The script will read each IO entry in the IO reuse information table and automatically generate the corresponding IO unit instantiation code. These IO units may be standard input and output interfaces, such as GPIO, UART, SPI, etc. The script will instantiate each functional module based on the IO reuse information table; the script will automatically generate IO control logic and configuration registers corresponding to each IO. For a single IO reused by multiple functions, the script will automatically generate IO output multiplexing logic based on the RTL code of the non-optimizable high-speed IO output multiplexing module. For the case where a single port of a functional module corresponds to multiple IO options, the script will automatically generate IO input multiplexing logic. In addition, the script can also directly generate input flag buffer and output flag buffer related configuration code, which are buffers in the standard cell library. The unified naming rules of the input flag buffer and the output flag buffer facilitate the constraint that they will not be optimized by the logic synthesis tool.

[0042] Step S4: Use a logic synthesis tool to convert the generated RTL code into a corresponding circuit, and obtain the chip size and preliminary layout plan.

[0043] Specifically, logic synthesis tools (such as Synopsys' Design Compiler, Cadence's Genus, etc.) are used to convert RTL code into a gate-level netlist. This process involves converting high-level RTL descriptions into lower-level logic circuits, including basic circuit elements such as logic gates and flip-flops.

[0044] The complexity of the gate-level netlist and the required resources (such as the number of logic gates, memory size, etc.) are obtained based on the logic synthesis results to estimate the preliminary size of the chip and generate a preliminary layout plan. The preliminary layout plan involves determining the approximate location of the circuit elements on the chip and the interconnection relationship between them, which will be adjusted in the subsequent detailed design stage.

[0045] In one embodiment, the converted circuit includes: an IO unit, an IO control circuit, an IO output multiplexing circuit, a functional module, an IO input multiplexing circuit, an input flag buffer, and an output flag buffer;

[0046] IO units are one or more, and these units are interfaces for interacting with the outside world. Each IO unit is responsible for sending and receiving data. Each IO unit is connected to an IO output multiplexing circuit.

[0047] The IO control circuit implements the IO control logic, including the configuration register and control circuit corresponding to each IO.

[0048] The number of IO output multiplexing circuits is determined by the number of IO units, and each IO output multiplexing circuit is connected to an IO to implement IO output multiplexing logic. When multiple functional modules need to share the same IO unit for output, the IO output multiplexing circuit is responsible for receiving and selecting the corresponding signal for output.

[0049] The functional module is one or more, each module corresponds to a function selection mode, has one or more ports, and each port can be connected to a corresponding number of IO units. The functional module can be connected to the associated IO unit through an IO input multiplexing circuit and an input flag buffer, that is, the functional module is connected to the IO input multiplexing circuit, the IO input multiplexing circuit is connected to the input flag buffer, and the input flag buffer is connected to the IO unit; or directly connected to the IO unit, depending on the specific design requirements. For example, if each port of the functional module has multiple options, it is necessary to connect to the associated IO unit through an IO input multiplexing circuit and an input flag buffer; if each port of the functional module has one option, it only needs to be directly connected to the IO unit. The functional module is also connected to the IO output multiplexing circuit connected to the corresponding IO unit through an output flag buffer to realize the selection of the output signal and the transmission of status information.

[0050] The number of IO input multiplexing circuits is determined by whether the functional module supports connecting multiple IO units to one port to implement the IO input multiplexing logic. When the functional module needs to select input signals from multiple IO units, the IO input multiplexing circuit is responsible for this selection process.

[0051] The output flag buffer is inserted at the output port signal of the functional module, that is, on the path between the functional module and the IO output multiplexing circuit corresponding to the IO unit associated with it. That is, inserting the output flag buffer on the output path of the functional signal optimizes the timing.

[0052] The input flag buffer is inserted before the functional input signal enters the IO input multiplexing circuit, that is, on the path between the IO unit and the corresponding IO input multiplexing circuit. That is, inserting the input flag buffer on the functional signal input path optimizes the timing.

[0053] For example, if Figure 4 , the converted circuit includes: function 1 module, function 2 module, IO control circuit, IO output multiplexing circuit 1, IO output multiplexing circuit 2, IO input multiplexing circuit, IO unit 1, IO unit 2; wherein, the IO unit 1 is connected to an IO output multiplexing circuit 1, and the IO unit 2 is connected to an IO output multiplexing circuit 2 and function 2 module. The function module 1 is connected to the IO input multiplexing circuit. The function 1 module is connected to the output multiplexing circuit 1 through a flag buffer, and is connected to the IO output multiplexing circuit 2 through a flag buffer; the function 2 module is connected to the output multiplexing circuit 2 through a flag buffer; the IO unit 1 is connected to the IO input multiplexing circuit through a flag buffer, and the IO unit 2 is connected to the IO input multiplexing circuit through a flag buffer.

[0054] In one embodiment, in order to solve the problem that different data bit signals of the same function undergo very different logic delays when arriving at the IO unit, resulting in failure to meet the requirement of low skew rate of high-speed signals, such as Figure 5 , the IO output multiplexing circuit is divided into two parts, namely, an optimizable IO output multiplexing module and a non-optimizable high-speed IO output multiplexing module;

[0055] The IO output multiplexing module is used to input non-high-speed functional signals from the functional modules. Since these signals are not high-speed signals, they can be optimized in a logic synthesis tool to reduce the area.

[0056] The high-speed IO output multiplexing module has a fixed number of high-speed signal input ports and low-speed signal input ports. Generally speaking, the number of high-speed signal input ports is much greater than that of low-speed signal input ports. Preferably, one low-speed signal input port is set, and the rest are set as high-speed signal input ports. The high-speed IO output multiplexing module is used to receive high-speed functional signals from functional modules through the high-speed signal input port. All non-high-speed functional signals transmitted by the IO output multiplexing module are multi-selected, and the non-high-speed functional signals after multi-selection are received through the low-speed signal input port. The high-speed IO output multiplexing module is not allowed to be optimized during the logic synthesis process to ensure the minimization and consistency of signal delay.

[0057] It should be noted that in the IO output multiplexing logic implemented by the high-speed IO output multiplexing module, the script tool directly connects the high-speed function signal to the high-speed signal input port of the high-speed IO output multiplexing module according to the information on whether each function selection mode in the IO multiplexing table is high-speed, and makes multiplexing of all other non-high-speed function signals. The multiplexing can be directly described in RTL language and optimized by logic synthesis tools. The result of the multiplexing is connected to the low-speed signal input port of the high-speed IO output multiplexing module.

[0058] For example, an 8-way high-speed IO output multiplexing module is used as an example. The 8-way high-speed IO output multiplexing module has 7 input ports for high-speed functional signals and 1 low-speed signal input port for non-high-speed functional signals. The high-speed functional signals from the functional modules are received through the 7 high-speed signal input ports; all non-high-speed functional signals transmitted by the IO output multiplexing module are multi-selected, and the non-high-speed functional signals after multi-selection are received through the 1 low-speed signal input port.

[0059] Step S5: Perform IO visualization based on the chip size and the preliminary layout plan, and adjust the positional relationship between each functional module and the IO unit used by it in the preliminary layout plan to obtain an optimized layout plan.

[0060] In one embodiment, step S5 includes:

[0061] Determine the IO unit layout based on the chip size and preliminary layout planning, add the location information of each IO unit to the IO reuse information table, and use the script tool to visualize the IO units used by each functional module; specifically, first determine the layout space available for the IO unit based on the overall size and performance requirements of the chip. Then, preliminarily determine the layout position of the IO unit based on the preliminary layout planning of the chip. After preliminarily determining the IO unit layout, add the location information of each IO unit (such as coordinates, relative position with other IO units, etc.) to the IO reuse information table, use the script tool to read the location information in the IO reuse information table, and generate a visual layout diagram of the IO unit in CAD or EDA software.

[0062] Based on the visualized IO unit positions, the positions of the corresponding functional modules are adjusted so that the functional modules are at a moderate distance from the IO units associated with them, so as to obtain an optimized layout plan. Specifically, according to the positions of the IO units in the visualized layout diagram, the positions of the functional modules associated with them are adjusted. The goal is to make the connection path between the functional modules and their associated IO units as short and efficient as possible to reduce signal delay and power consumption. For example, Figure 6 , determine the position of the function 1 module in the visual layout diagram based on the visualized IO position. The principle is that the function 1 module is moderately located from the IO unit position of each option. In the process of adjusting the position of the functional module, multiple iterations and optimization of the layout plan may be required. This can also include re-evaluating the arrangement of the IO unit, adjusting the size and shape of the functional module, optimizing the layout of the signal line, etc. After multiple iterations and optimizations, the final layout plan is obtained.

[0063] Step S6: In the layout and post-layout stages of physical implementation, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the functional signal input paths and output paths are optimized to obtain the design layout.

[0064] In one embodiment, step S6 includes:

[0065] During the layout phase of physical implementation, the location of each functional module with high-speed function and its corresponding IO input multiplexing circuit is limited based on the optimized layout planning, and the location of the high-speed IO output multiplexing module is limited near its corresponding connected IO unit; this helps to reduce the distance that high-speed signals are transmitted inside the chip, thereby reducing the risk of signal attenuation and interference.

[0066] In the post-layout stage of physical implementation, by setting a fixed-interval insertion buffer in the path between the output flag buffer and the high-speed IO output multiplexing module connected to it, the functional signal output path can be optimized and signal attenuation and delay can be reduced; by setting a fixed-interval insertion buffer between the IO unit and the input flag buffer connected to it, the functional signal input path can be optimized, the signal loss during transmission can be reduced, and the overall performance of the system can be improved.

[0067] After the above steps, the final design layout can be generated.

[0068] This optimization process significantly improves the timing consistency between parallel data bits of the chip. Under the 40nm process, the maximum timing offset of 32-bit data was successfully reduced from 10 nanoseconds to hundreds of picoseconds. And this process effectively responds to the increasingly complex challenges of chip RTL design by automatically generating RTL (register transfer level) code. For large chips with more than 200 IO ports, the RTL logic code to implement the IO multi-way selection function may be as high as tens of thousands of lines, which is almost impossible to complete by traditional manpower methods. This process greatly reduces the manpower burden and improves efficiency. The present invention also avoids the winding problem in IO signal routing, thereby ensuring the accuracy and efficiency of chip design.

[0069] Similar to the principle of the above embodiment, the present invention provides a chip design system based on IO multiplexing performance optimization.

[0070] The following provides specific embodiments in conjunction with the accompanying drawings:

[0071] like Figure 7 A schematic diagram of the structure of a chip design system based on IO multiplexing performance optimization in an embodiment of the present invention is shown.

[0072] The system comprises:

[0073] Table construction module 1, used to construct IO reuse information table;

[0074] High-speed IO output multiplexing module code writing module 2 is used to write the RTL code of the non-optimizable high-speed IO output multiplexing module;

[0075] An RTL code generation module 3 is connected to the table construction module 1 and the high-speed IO output multiplexing module code writing module 2, and is used to call a script to generate an RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module;

[0076] A logic synthesis module 4, connected to the RTL code generation module 3, is used to convert the generated RTL code into a corresponding circuit using a logic synthesis tool, and obtain a chip size and a preliminary layout plan;

[0077] A layout planning optimization module 5, connected to the logic synthesis module 4, is used to perform IO visualization based on the chip size and the preliminary layout planning, and to adjust the positional relationship between each functional module in the preliminary layout planning and the IO unit used by it to obtain an optimized layout planning;

[0078] The layout and post-layout module 6 is connected to the layout planning optimization module 5, and is used to define the corresponding module positions in the circuit based on the optimized layout planning during the layout and post-layout stages of physical implementation, and optimize the functional signal input path and output path to obtain the design layout.

[0079] Since the implementation principle of the chip design system based on IO multiplexing performance optimization has been described in the above embodiments, it will not be repeated here.

[0080] The chip design method based on IO multiplexing performance optimization provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the electronic terminal, please refer to Figure 8 , is an optional hardware structure diagram of an electronic terminal 1000 provided in an embodiment of the present invention. The terminal 1000 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010 and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It can be understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1005 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 8 In the specification, various buses are labeled as bus systems.

[0081] The user interface 1009 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0082] It is understood that the memory 1002 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0083] The memory 1002 in the embodiment of the present invention is used to store various categories of data to support the operation of the terminal 1000. Examples of these data include: any executable program for operating on the terminal 1000, such as an operating system 10021 and an application 10022; the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 10022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The chip design method based on IO multiplexing performance optimization provided in the embodiment of the present invention may be included in the application 10022.

[0084] The method disclosed in the above embodiment of the present invention can be applied to the processor 1001, or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 1001 or the instruction in the form of software. The above processor 1001 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 1001 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0085] In an exemplary embodiment, the terminal 1000 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0086] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0087] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0088] In summary, the chip design method, system, terminal and medium based on IO reuse performance optimization of the present invention automatically generate RTL code according to the constructed IO reuse information table and the RTL code of the high-speed IO output multiplexing module written in advance by calling the script, and then convert the generated RTL code into the corresponding circuit using the logic synthesis tool, and obtain the chip size and preliminary layout planning, and then perform IO visualization based on the chip size and preliminary layout planning, and adjust the positional relationship between each functional module and the IO unit used by it in the preliminary layout planning to obtain the optimized layout planning; in the layout and post-layout stage of physical implementation, the corresponding module position in the circuit is limited based on the optimized layout planning, and the functional signal input path and output path are optimized to obtain the design layout. The present invention enables the physical design tool to automatically optimize the timing performance of the functional reuse IO, provides support for large-scale general-purpose chips to realize high-speed IO protocols, and can also automatically generate RTL code to reduce manpower, and avoid the situation where the IO signal routing occurs. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A chip design method based on IO multiplexing performance optimization, characterized in that: The method comprises: Construct IO reuse information table; Write RTL code for the non-optimizable high-speed IO output multiplexing module; Calling a script to generate an RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module; Use logic synthesis tools to convert the generated RTL code into the corresponding circuit and obtain the chip size and preliminary layout plan; Perform IO visualization based on chip size and preliminary layout planning, and adjust the position relationship between each functional module and the IO unit used by it in the preliminary layout planning to obtain an optimized layout planning; In the layout and post-layout stages of physical implementation, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the functional signal input path and output path are optimized to obtain the design layout.

2. The chip design method based on IO multiplexing performance optimization according to claim 1, characterized in that: The multiplexing information table includes: high-speed function identifiers and IO multiplexing information of each function selection mode; wherein the IO multiplexing information includes: function module ports associated with each IO in the current function selection mode and options of the corresponding ports.

3. The chip design method based on IO multiplexing performance optimization according to claim 1, characterized in that: The RTL code for writing the non-optimizable high-speed IO output multiplexing module includes: Define a high-speed IO output multiplexing module that can receive a fixed number of functional output signals and cannot be optimized, and use a hardware description language to write RTL code.

4. The chip design method based on IO multiplexing performance optimization according to claim 2, characterized in that: The conversion circuit includes: an IO unit, an IO control circuit, an IO output multiplexing circuit, a functional module, an IO input multiplexing circuit, an input flag buffer, and an output flag buffer; wherein, there are one or more IO units and functional modules, and each IO unit is connected to an IO output multiplexing circuit; each functional module can be connected to the associated IO unit through a correspondingly set IO input multiplexing circuit and an input flag buffer, or directly connected to the associated IO unit; the functional module is also connected to the IO output multiplexing circuit connected to the corresponding IO unit through an output flag buffer.

5. The chip design method based on IO multiplexing performance optimization according to claim 4, characterized in that: The IO output multiplexing circuit includes: an optimizable IO output multiplexing module and a non-optimizable high-speed IO output multiplexing module; Wherein, the high-speed IO output multiplexing module has a fixed number of high-speed signal input ports and low-speed signal input ports; The IO output multiplexing module is used to input non-high-speed functional signals from the functional module; The high-speed IO output multiplexing module is used to receive high-speed functional signals from the functional module through the high-speed signal input port; perform multi-path selection on all non-high-speed functional signals transmitted by the IO output multiplexing module, and receive the non-high-speed functional signals after multi-path selection through the low-speed signal input port.

6. The chip design method based on IO multiplexing performance optimization according to claim 5, characterized in that: The IO visualization based on the chip size and the preliminary layout plan, and adjusting the positional relationship between each functional module and the IO unit used by it in the preliminary layout plan to obtain an optimized layout plan includes: Determine the IO unit layout based on the chip size and preliminary layout planning, add the location information of each IO unit to the IO reuse information table, and use the script tool to visualize the IO units used by each functional module; Based on the visualized IO unit positions, the positions of the corresponding functional modules are adjusted so that the functional modules are at a moderate distance from the IO unit positions associated with them, so as to obtain an optimized layout plan.

7. The chip design method based on IO multiplexing performance optimization according to claim 6, characterized in that: In the layout and post-layout stages of physical implementation, the positions of corresponding modules in the circuit are limited based on the optimized layout planning, and the functional signal input paths and output paths are optimized, including: In the layout stage of physical implementation, the positions of each functional module with high-speed function and its corresponding IO input multiplexing circuit are limited based on the optimized layout planning, and the position of the high-speed IO output multiplexing module is limited to the vicinity of its corresponding connected IO unit; In the post-layout stage of physical implementation, the functional signal output path is optimized by setting a fixed interval insertion buffer in the path between the output flag buffer and the high-speed IO output multiplexing module connected to it, and the functional signal input path is optimized by setting a fixed interval insertion buffer between the IO unit and the input flag buffer connected to it.

8. A chip design system based on IO multiplexing performance optimization, characterized in that: The system comprises: Table construction module, used to construct IO reuse information table; High-speed IO output multiplexing module code writing module, used to write the RTL code of the non-optimizable high-speed IO output multiplexing module; An RTL code generation module, connected to the table construction module and the high-speed IO output multiplexing module code writing module, is used to call a script to generate an RTL code according to the IO multiplexing information table and the RTL code of the high-speed IO output multiplexing module; A logic synthesis module, connected to the RTL code generation module, is used to convert the generated RTL code into a corresponding circuit using a logic synthesis tool, and obtain a chip size and a preliminary layout plan; A layout planning optimization module, connected to the logic synthesis module, is used to perform IO visualization based on chip size and preliminary layout planning, and adjust the positional relationship between each functional module in the preliminary layout planning and the IO unit used by it to obtain an optimized layout planning; The layout and post-layout module is connected to the layout planning optimization module and is used to define the corresponding module positions in the circuit based on the optimized layout planning during the layout and post-layout stages of physical implementation, and to optimize the functional signal input path and output path to obtain the design layout.

9. An electronic terminal, characterized in that: include: one or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors, connected to the memory, are configured to run the computer program to perform the method according to claim 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored, and when the computer program is executed by one or more processors, the method according to any one of claims 1 to 7 is performed.

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