Output banding circuit for display panel and display panel

Abstract

The application discloses an output load circuit of a display panel and the display panel. The output load circuit comprises a load resistor, a load switch and a control circuit. A target voltage source is connected with the load resistor through the load switch. The control circuit comprises a first signal end and a second signal end. The first signal end and the second signal end are connected with a master control chip. The control circuit is configured to control the load switch to be closed when a termination signal is input to the first signal end, and to control the load switch to be opened when a start signal is input to the second signal end. When the display mode is switched to a low-power mode, the target voltage source is connected with an additional load resistor, so that the load of the target voltage source in the low-power mode is increased, the difference between the loads of the voltage source in the display mode and in the low-power mode is reduced, the jump values of corresponding voltage signals and current signals are reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and more particularly, to an output load circuit of a display panel and the display panel. BACKGROUND

[0002] For each pixel of the display panel, when the display panel displays a frame of picture, the driving circuit outputs a data voltage to drive the pixel to display according to picture data, enters a display mode, and then the driving circuit stops outputting the data voltage, enters a low-power mode, that is, the display panel displays each frame of picture and experiences two time periods of the display mode and the low-power mode. The load of the driving circuit in the display mode is quite different from that in the low-power mode, especially in the case of displaying the heaviest load of the display panel, the corresponding voltage signal and current signal may jump, resulting in serious noise and electromagnetic interference of the display panel. SUMMARY

[0003] The present application provides an output load circuit of a display panel and the display panel.

[0004] The output load circuit of the display panel provided by the present application. The driving circuit of the display panel includes a target voltage source and a master control chip, and the driving circuit drives the display panel to work in a display mode or a low-power mode. In the display mode, the target voltage source is connected to a first load. In the low-power mode, the target voltage source is connected to a second load, and the first load is greater than the second load. In the case of switching from the display mode to the low-power mode, the master control chip is configured to provide a termination signal. In the case of switching from the low-power mode to the display mode, the master control chip is configured to provide a start signal. The output load circuit includes a load resistor, a load switch, and a control circuit. The target voltage source is connected to the load resistor through the load switch. The control circuit includes a first signal end and a second signal end. The first signal end and the second signal end are connected to the master control chip, and the control circuit is configured to control the load switch to be closed in the case of the first signal end accessing the termination signal, and to control the load switch to be opened in the case of the second signal end accessing the start signal.

[0005] The output load circuit provided by the present application increases the load of the target voltage source in the low-power mode in the case of switching from the display mode to the low-power mode, reduces the difference between the load of the voltage source in the display mode and the low-power mode, reduces the jump value of the corresponding voltage signal and current signal, and reduces the noise and electromagnetic interference of the display panel.

[0006] In some embodiments, the control circuit comprises a control unit, a pull-up unit and a pull-down unit. The control unit is connected to the controlled terminal of the load switch. The pull-up unit is connected to the first signal terminal, and the pull-up unit is connected to the control node with the control unit. The pull-up unit is configured to write a first voltage signal to the control node in the case that the first signal terminal accesses the termination signal, so as to control the control unit to control the load switch to be closed. The pull-down unit is connected to the second signal terminal, and the pull-down unit is connected to the control node with the control unit. The pull-down unit is configured to write a second voltage signal to the control node in the case that the second signal terminal accesses the start signal, so as to control the control unit to control the load switch to be opened.

[0007] In some embodiments, the pull-up unit comprises a first voltage source, a first transistor and a second transistor, the control electrode of the first transistor is connected to the first signal terminal, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected to the control electrode of the second transistor, the first electrode of the second transistor is connected to the first voltage source, the second electrode of the second transistor is connected to the control node, and the first voltage source is configured to provide the first voltage signal.

[0008] In some embodiments, within a preset time period after the first signal terminal accesses the termination signal, the second transistor is closed, so that the first voltage source writes the first voltage signal to the control node.

[0009] In some embodiments, the pull-down unit comprises a third transistor, the control electrode of the third transistor is connected to the second signal terminal, the first electrode of the third transistor is grounded, and the second electrode of the third transistor is connected to the control node. The ground terminal is configured to provide the second voltage signal.

[0010] In some embodiments, in the case that the second signal terminal accesses the start signal, the third transistor is closed, so that the ground terminal writes the second voltage signal to the control node.

[0011] In some embodiments, the control unit comprises a fourth transistor, the control electrode of the fourth transistor is connected to the control node, the first electrode of the fourth transistor is grounded, and the second electrode of the fourth transistor is connected to the controlled terminal of the load switch.

[0012] The display panel provided in the present application comprises the output banding circuit provided in the embodiments of the present application.

[0013] In some embodiments, before the display mode is switched to the low power consumption mode, the master chip is configured to provide a pre-trigger signal to the control circuit to make the control circuit control the load switch to be closed.

[0014] In some embodiments, the display panel further comprises a loop capacitor, and the target voltage source is grounded through the loop capacitor.

[0015] The output load circuit of the display panel and the display panel provided by the embodiments of the present application, in the case that the display mode is switched to the low power consumption mode, the target voltage source is connected to an additional load resistor, so that the load of the target voltage source in the low power consumption mode is increased, the difference between the load of the target voltage source in the display mode and the low power consumption mode is reduced, the jump value of the corresponding voltage signal and current signal is reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

[0016] Additional aspects and advantages of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0018] Figure 1 is a schematic diagram of the output load circuit and the display panel of some embodiments of the present application;

[0019] Figure 2 is a schematic diagram of the output load circuit of some embodiments of the present application;

[0020] Figure 3 is a schematic diagram of the output load circuit and the display panel of some embodiments of the present application.

[0021] Main element symbol explanation: target voltage source 110, master chip 120, output load circuit 200, load switch 211, load resistor 212, control circuit 220, first signal end 221, second signal end 222, pull-up unit 223, pull-down unit 224, control unit 225, display panel 1000. DETAILED DESCRIPTION

[0022] The embodiments of the present application are described in detail below, which are shown in the accompanying drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0023] For each pixel of the display panel, when the display panel displays a frame of picture, the driving circuit outputs a data voltage to drive the pixel to display according to picture data, enters a display mode, and then stops outputting the data voltage, enters a low-power mode. That is to say, the display panel displays each frame of picture will experience two time periods of the display mode and the low-power mode. The load difference of the driving circuit in the display mode and the low-power mode is large, especially in the case that the display panel displays the heaviest load picture, the corresponding voltage signal and current signal may jump, resulting in that the display panel generates serious noise and electromagnetic interference.

[0024] To solve the above technical problems, the embodiment of the present application provides an output load circuit of a display panel and the display panel. The output load circuit provided by the embodiment of the present application, in the case that the display mode is switched to the low-power mode, an additional load resistance is connected to the target voltage source, so that the load of the target voltage source in the low-power mode is increased, the load difference of the voltage source in the display mode and the low-power mode is reduced, the jump value of the corresponding voltage signal and current signal is reduced, and the noise and electromagnetic interference generated by the display panel are reduced.

[0025] Reference Figure 1 The output load circuit 200 of the display panel 1000 provided by the embodiment of the present application is provided. The driving circuit of the display panel 1000 includes a target voltage source 110 and a master control chip 120, and the driving circuit drives the display panel 1000 to work in a display mode or a low-power mode. In the display mode, the target voltage source 110 is connected to a first load. In the low-power mode, the target voltage source 110 is connected to a second load, and the first load is greater than the second load. In the case that the display mode is switched to the low-power mode, the master control chip 120 is configured to provide a termination signal. In the case that the low-power mode is switched to the display mode, the master control chip 120 is configured to provide a start signal.

[0026] The output load circuit 200 includes a load resistance 212, a load switch 211 and a control circuit. The target voltage source 110 is connected to the load resistance 212 through the load switch 211. The control circuit includes a first signal end 221 and a second signal end 222. The first signal end 221 and the second signal end 222 are connected to the master control chip 120, and the control circuit is configured to control the load switch 211 to be closed in the case that the termination signal is connected to the first signal end 221, and to be opened in the case that the start signal is connected to the second signal end 222.

[0027] Specifically, the refresh rate and brightness of the display panel 1000 can vary according to the technical type of the display panel 1000 and the use scenario of the device when the display panel 1000 displays dynamic content or static content. In order to optimize the display effect, performance and power consumption of the display panel 1000, the display panel 1000 usually switches the working mode when displaying a frame of image.

[0028] The image displayed by the display panel 1000 can be scanned line by line, and a short time is needed for the display panel 1000 to "return to the top" and prepare for the display of the next frame of image after the display panel 1000 completes the image scanning of a frame (scanning each row from the top to the bottom of the screen), which is the vertical retrace or vertical blanking period (V-Blanking). The V-Blanking can be the time interval when the display panel 1000 returns to the top of the screen to start displaying the next frame of image after completing the scanning of a frame of image.

[0029] When the display panel 1000 performs image scanning, the display panel 1000 works in the display mode, and the driving circuit can output the corresponding data voltage to the pixel. In the V-Blanking period after the display panel 1000 completes the image scanning of a frame, the display panel 1000 can work in the low-power mode, which can reduce the power consumption as much as possible while ensuring the display of the image by the display panel 1000.

[0030] It can be understood that the load difference of the driving circuit in the display panel 1000 is large between the target voltage source 110 in the display mode and the target voltage source 110 in the low-power mode. The driving circuit needs to provide the data voltage to drive the pixel to work in the display mode, and especially in the case that the display panel 1000 displays the most heavily loaded image, the load of the driving circuit for driving the pixel in the display mode is large, and the corresponding voltage signal and current signal can jump, which can cause the display panel 1000 to generate serious noise and electromagnetic interference.

[0031] The target voltage source 110 can be a voltage source with a large load difference connected by the display panel 1000 when switching the working mode. The target voltage source 110 can be an input voltage source Vin in the gate driving circuit (GOA), a high-level voltage source VGH or a low-level voltage source VGL. In the display mode, the target voltage source 110 is connected to a first load. In the low-power mode, the target voltage source 110 is connected to a second load, and the first load is greater than the second load.

[0032] The main control chip 120 can be an integrated circuit chip (Timing Controller IC, Tcon IC) in the display panel 1000. The Tcon IC can generate and adjust the timing signals required by the display panel 1000. The timing signals are used to control the scanning order, row and column signals, and synchronization mode of the driving pixels of the display panel 1000. It can precisely control the display of each frame of image in each row and column to ensure that the image does not tear or misalign. The Tcon IC transmits control signals to the driving circuit of the display panel 1000 to ensure that the voltage of each pixel is correctly adjusted, thereby forming an accurate image.

[0033] The termination signal and the start signal can be timing control signals output by the main control chip 120. When the display mode is switched to low power mode, the main control chip 120 is configured to provide the termination signal. When the low power mode is switched to display mode, the main control chip 120 is configured to provide the start signal.

[0034] When the display mode is switched to low power mode, the main control chip 120 outputs a termination signal, and the control circuit controls the load switch 211 to close, so that the target voltage source 110 is connected to an additional load resistor 212. This increases the load on the target voltage source 110 in low power mode, reduces the difference in load on the target voltage source 110 between display mode and low power mode, reduces the jump values ​​of the corresponding voltage and current signals, and reduces the noise and electromagnetic interference generated by the display panel 1000.

[0035] by Figure 1 For example, load switch 211 can be a switching device M1, load resistor 212 can be a resistive device R1, and target voltage source 110 can be a voltage source AVDDS. Switching device M1 can be a transistor, voltage source AVDDS is connected to the first terminal of switching device M1, the second terminal of switching device M1 is connected to the first terminal of resistive device R1, the second terminal of resistive device R1 is grounded, and control circuit is connected to the control terminal of switching device M1.

[0036] When the display mode is switched to low-power mode, the main control chip 120 outputs a stop signal, the control circuit controls the switch M1 to close, and the voltage source AVDDS is connected to the resistor R1. When the low-power mode is switched back to display mode, the main control chip 120 outputs a start signal, the control circuit controls the switch M1 to open, and the voltage source AVDDS is disconnected from the resistor R1.

[0037] Thus, in low-power mode, the voltage source AVDDS is connected to an additional resistor R1, which reduces the difference in the load connected to the voltage source AVDDS between display mode and low-power mode, reduces the jump values ​​of the voltage and current signals corresponding to the voltage source AVDDS, and reduces the noise and electromagnetic interference generated by the display panel 1000.

[0038] Reference Figure 2 In some embodiments, the control circuit includes a control unit 225, a pull-up unit 223, and a pull-down unit 224. The control unit 225 is connected to the controlled terminal of the load switch 211. The pull-up unit 223 is connected to a first signal terminal 221 and is connected to the control unit 225 at a control node. The pull-up unit 223 is configured to write a first voltage signal to the control node when a stop signal is received at the first signal terminal 221, causing the control unit 225 to control the load switch 211 to close. The pull-down unit 224 is connected to a second signal terminal 222 and is connected to the control unit 225 at the control node. The pull-down unit 224 is configured to write a second voltage signal to the control node when a start signal is received at the second signal terminal 222, causing the control unit 225 to control the load switch 211 to open.

[0039] Specifically, with Figure 2 For example, the control node can be node N. Pull-down unit 224, pull-up unit 223 and control unit 225 are connected to node N. Control unit 225 can control the closing or opening of switching device M1 according to the voltage signal written to node N.

[0040] The first signal terminal 221 can be the signal terminal Tempinate, and the pull-up unit 223 can be connected to the signal terminal Tempinate. When the display mode is switched to low power mode, the main control chip 120 outputs a termination signal to the signal terminal Tempinate, and the pull-up unit 223 provides the first voltage signal to the control unit 225, so that the control unit 225 controls the switching device M1 to close.

[0041] The second signal terminal 222 can be signal terminal STV1, and the pull-down unit 224 can be connected to signal terminal STV1. When switching from low power mode to display mode, the main control chip 120 outputs a start signal to signal terminal STV1, and the pull-up unit 223 provides the first voltage signal to the control unit 225, so that the control unit 225 controls the switching device M1 to open.

[0042] In some embodiments, the pull-up unit 223 comprises a first voltage source, a first transistor and a second transistor, the control electrode of the first transistor is connected with the first signal terminal 221, the first electrode of the first transistor is grounded, the second electrode of the first transistor is connected with the control electrode of the second transistor, the first electrode of the second transistor is connected with the first voltage source, the second electrode of the second transistor is connected with the control node, and the first voltage source is configured to provide a first voltage signal.

[0043] Specifically, taking Figure 2 for example, the first voltage source can be a voltage source HVDD, the first transistor can be a transistor Q1, and the second transistor can be a transistor Q2. The control electrode of the transistor Q1 is connected with the signal terminal Teminate, the first electrode of the transistor Q1 is grounded, the second electrode of the transistor Q1 is connected with the control electrode of the transistor Q2, the first electrode of the transistor Q2 is connected with the voltage source HVDD, the second electrode of the transistor Q2 is connected with the node N, and the voltage source HVDD is configured to provide a first voltage signal.

[0044] In the case that the termination signal is input to the signal terminal Teminate, the transistor Q1 is closed, so that the control electrode of the transistor Q2 is grounded through the transistor Q1, and the transistor Q2 is closed. The closing of the transistor Q2 causes the first voltage signal provided by the voltage source HVDD to be written to the node N.

[0045] In some embodiments, the transistor Q1 is an NMOS transistor, and the transistor Q2 is a PMOS transistor. In the case that the termination signal is input to the signal terminal Teminate, the signal terminal Teminate inputs a high-level voltage.

[0046] In some embodiments, the pull-up unit 223 further comprises a resistor R2, and the second electrode of the transistor Q1 can also be connected with the voltage source HVDD through the resistor R2.

[0047] In some embodiments, within a preset time period after the termination signal is input to the first signal terminal 221, the second transistor is closed to cause the first voltage source to write the first voltage signal to the control node.

[0048] Specifically, within the first preset time period after the termination signal is input to the signal terminal Teminate, the transistor Q2 can be maintained in a closed state due to the parasitic capacitance between the gate and the source of the transistor Q2, so that the first voltage source writes the first voltage signal to the control node, ensuring that the target voltage source 110 inputs a load difference within a preset time period after the display mode is switched to the low-power mode, and reducing the noise and electromagnetic interference generated by the display panel 1000.

[0049] Referring to Figure 2In some embodiments, the pull-down unit 224 includes a third transistor, a control electrode of the third transistor is connected with the second signal terminal 222, a first electrode of the third transistor is grounded, and a second electrode of the third transistor is connected with the control node, and the ground terminal is configured to provide the second voltage signal.

[0050] Specifically, for example, the third transistor can be transistor Q3. The control electrode of the transistor Q3 is connected with the signal terminal STV1, the first electrode of the transistor Q3 is grounded, and the second electrode of the transistor Q3 is connected with the node N, and the ground terminal is configured to provide the second voltage signal. Figure 2

[0051] In some embodiments, the transistor Q3 is an NMOS transistor. When the signal terminal STV1 is connected with the start signal, the signal terminal STV1 is connected with a high voltage level.

[0052] In some embodiments, when the second signal terminal 222 is connected with the start signal, the third transistor is closed to write the second voltage signal from the ground terminal to the control node.

[0053] Specifically, when the signal terminal STV1 is connected with the start signal, the transistor Q3 is closed, and no matter whether the transistor Q2 is in the open or closed state, the second voltage signal provided by the ground terminal can be written to the node N, which ensures that the switch device M1 is open when the display panel 1000 is switched to the display mode.

[0054] In some embodiments, the control unit 225 includes a fourth transistor, a control electrode of the fourth transistor is connected with the control node, a first electrode of the fourth transistor is grounded, and a second electrode of the fourth transistor is connected with the control terminal of the load switch 211.

[0055] Specifically, for example, the fourth transistor can be transistor Q4. The control electrode of the transistor Q4 is connected with the node N, the first electrode of the transistor Q4 is grounded, and the second electrode of the transistor Q4 is connected with the control terminal of the switch device M1. Figure 2 In some embodiments, the control unit 225 further includes a resistor R4, and the second electrode of the transistor Q4 can be connected with the voltage source AVDDS through the resistor R4.

[0056] In some embodiments, the control circuit further includes a resistor R3 and a capacitor C1, a first terminal of the resistor R3 is connected with the node N, a second terminal of the resistor R3 is grounded, a first terminal of the capacitor C1 is connected with the node N, and a second terminal of the capacitor C1 is grounded.

[0057]

[0058] ​​In some embodiments, the transistor Q4 can be a PMOS transistor, and the switch device M1 can be an NMOS transistor. The first voltage signal provided by the voltage source HVDD can be a high-level signal, and the second voltage signal provided by the ground terminal can be a low-level signal.

[0059] In a case where the node N is written with the first voltage signal, the transistor Q4 is closed so that the control electrode of the switch device M1 is grounded, and the switch device M1 is closed so that the voltage source HVDD is in communication with the resistor device R1.

[0060] In a case where the node N is written with the second voltage signal, the transistor Q4 is opened so that the connection between the control electrode of the switch device M1 and the ground terminal is disconnected, and the switch device M1 is opened so that the connection between the voltage source HVDD and the resistor device R1 is disconnected.

[0061] The display panel 1000 provided in the present application includes the output load circuit 200 provided in the embodiments of the present application.

[0062] Specifically, for example, when the display panel 1000 works in the display mode, the signal terminal Teminate in the output load circuit 200 is connected with a low-level signal, and the transistor Q1 and the transistor Q2 are opened. The signal terminal STV1 is connected with a low-level signal, and the transistor Q3 is opened. The transistor Q4 and the switch device M1 are opened. Figure 2

[0063] When the display panel 1000 switches from the display mode to the low-power-consumption mode, the signal terminal Teminate in the output load circuit 200 is connected with a high-level signal, and the transistor Q1 and the transistor Q2 are closed. The signal terminal STV1 is connected with a low-level signal, and the transistor Q3 is opened. The transistor Q4 and the switch device M1 are closed.

[0064] When the display panel 1000 works in the low-power-consumption mode, the signal terminal Teminate in the output load circuit 200 is connected with a low-level signal, and the transistor Q1 is opened. Due to the existence of the parasitic capacitance between the gate electrode and the source electrode of the transistor Q2, the transistor Q2 is closed. The signal terminal STV1 is connected with a low-level signal, and the transistor Q3 is opened. The transistor Q4 and the switch device M1 are closed.

[0065] When the display panel 1000 switches from the low-power-consumption mode to the display mode, the signal terminal Teminate in the output load circuit 200 is connected with a low-level signal, and the transistor Q1 is opened. Due to the existence of the parasitic capacitance between the gate electrode and the source electrode of the transistor Q2, the transistor Q2 is closed. The signal terminal STV1 is connected with a high-level signal, and the transistor Q3 is closed. The transistor Q4 and the switch device M1 are opened.

[0066] ​In some embodiments, before the display mode is switched to the low-power mode, the master chip 120 is configured to provide a pre-trigger signal to the control circuit to make the control circuit control the load switch 211 to be closed within a second preset time period.

[0067] Specifically, the master chip 120 can provide the pre-trigger signal to the signal end Teminate within the second preset time period before the display mode is switched to the low-power mode, so that the target voltage source 110 is connected to the load resistor 212 in advance, which is beneficial to reduce the jump of the current signal and the voltage signal corresponding to the target voltage source 110.

[0068] In some embodiments, the level signal of the termination signal can be pulled high in advance to obtain the pre-trigger signal.

[0069] In some embodiments, the display panel 1000 further includes a loop capacitor, and the target voltage source 110 is grounded through the loop capacitor.

[0070] Specifically, the noise on the display panel 1000 is mainly caused by the piezoelectric effect of the loop capacitor in the voltage loop. After a large amplitude change voltage is applied across the loop capacitor, the piezoelectric effect of the ceramic is reversed, causing the circuit board to resonate and generate noise. The greater the voltage change, the greater the noise.

[0071] The display panel 1000 of the embodiments of the present application is additionally provided with an output load circuit, which can effectively reduce the voltage signal corresponding to the target voltage source 110, reduce the voltage change across the loop capacitor, and thus reduce the noise on the display panel 1000.

[0072] The embodiments of the present application provide a display device, which includes the display panel 1000 of any of the above embodiments.

[0073] In particular, the display device can be any device that displays whether in motion (e.g., a video) or stationary (e.g., a still image) and whether textual or pictorial. More particularly, the display device can be one of a plurality of electronic devices, e.g., but not limited to, a mobile phone, a wireless device, a personal data assistant (PDA), a hand-held or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automobile display (e.g., an odometer display, etc.), a navigation instrument, a cockpit controller and / or display, a camera view display (e.g., a display for a rear view camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, an architectural structure, a packaging and aesthetic structure (e.g., a display for an image of a piece of jewelry), etc. Embodiments of the present disclosure are not particularly limited to a specific form of the display device described above.

[0074] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "certain embodiments", "an example", "a specific example" or "some examples" etc. means that a specific feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The illustrative representations of the above terms in the present specification are not necessarily directed to the same embodiment or example. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction.

[0075] In addition, the term "connection" should be interpreted broadly, for example, it can include fixed connection, or detachable connection, or integrally connected; it can include direct connection, or indirect connection through intermediate medium, or it can include the communication inside two elements. For the person skilled in the art, the specific meaning of the above-mentioned term in the present application can be understood according to the specific circumstances.

[0076] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0077] Any processes or methods described in the flow charts or otherwise described herein can be understood as representing code modules, segments, or portions of code which include one or more executable instructions for implementing specific logic functions (or steps) of the process, and / or that the various processes described herein can be understood as representing executable instructions, code segments, or portions of code which include one or more steps for implementing the functions (or steps) of the processes, and that the various processes described herein can be implemented with or without the use of hardware, software, firmware, or any combination thereof.

[0078] Although the embodiments of the present application have been shown and described above, it should be understood by those ordinary skilled in the art that the above embodiments are exemplary and cannot be understood as limiting the present application, and those ordinary skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. An output load circuit for a display panel, characterized in that, The driving circuit of the display panel includes a target voltage source and a main control chip. The driving circuit drives the display panel to work in display mode or low power mode. In display mode, the target voltage source is connected to a first load. In low power mode, the target voltage source is connected to a second load. The first load is greater than the second load. When the display mode is switched to the low power mode, the main control chip is configured to provide a termination signal. When the low power mode is switched to the display mode, the main control chip is configured to provide a start signal. The output load circuit includes: Load resistance; A load switch, wherein the target voltage source is connected to the load resistor via the load switch; The control circuit includes a first signal terminal and a second signal terminal, the first signal terminal and the second signal terminal are connected to the main control chip, and the control circuit is configured to control the load switch to close when the termination signal is connected to the first signal terminal, and to control the load switch to open when the start signal is connected to the second signal terminal. The control circuit includes: The control unit is connected to the controlled terminal of the load switch; A pull-up unit, connected to the first signal terminal and connected to the control unit at a control node, is configured to write a first voltage signal to the control node when the termination signal is received at the first signal terminal, so that the control unit controls the load switch to close. The pull-down unit, connected to the second signal terminal and the control unit at the control node, is configured to write a second voltage signal to the control node when the start signal is received at the second signal terminal, so that the control unit controls the load switch to disconnect.

2. The output load circuit of the display panel according to claim 1, characterized in that, The pull-up unit includes a first voltage source, a first transistor, and a second transistor. The control electrode of the first transistor is connected to the first signal terminal. The first electrode of the first transistor is grounded. The second electrode of the first transistor is connected to the control electrode of the second transistor. The first electrode of the second transistor is connected to the first voltage source. The second electrode of the second transistor is connected to the control node. The first voltage source is configured to provide the first voltage signal.

3. The output load circuit of the display panel according to claim 2, characterized in that, During a first preset time period after the termination signal is received at the first signal terminal, the second transistor closes, so that the first voltage source writes the first voltage signal into the control node.

4. The output load circuit of the display panel according to claim 1, characterized in that, The pull-down unit includes a third transistor, the control terminal of which is connected to the second signal terminal, the first terminal of which is grounded, the second terminal of which is connected to the control node, and the ground terminal is configured to provide the second voltage signal.

5. The output load circuit of the display panel according to claim 4, characterized in that, When the start signal is connected to the second signal terminal, the third transistor closes, so that the ground terminal writes the second voltage signal into the control node.

6. The output load circuit of the display panel according to claim 1, characterized in that, The control unit includes a fourth transistor, the control electrode of which is connected to the control node, the first electrode of which is grounded, and the second electrode of which is connected to the control terminal of the load switch.

7. A display panel, characterized in that, The display panel includes the output load circuit as described in any one of claims 1-6.

8. The display panel according to claim 7, characterized in that, During a second preset period before the display mode switches to the low-power mode, the main control chip is configured to provide a pre-triggered signal to the control circuit so that the control circuit controls the load switch to close.

9. The display panel according to claim 7, characterized in that, The display panel also includes a loop capacitor, through which the target voltage source is grounded.

Images