Driving method for display devices

Abstract

This application provides a display device and its driving method. The display device includes multiple pixels, each pixel comprising a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel includes a first light-emitting device and a pixel driving circuit, and at least one sub-pixel also includes a second light-emitting device. In a sequence of three consecutive pixels, the second light-emitting device of the first pixel emits red light, the second light-emitting device of the second pixel emits green light, and the second light-emitting device of the third pixel emits blue light. In a low grayscale display mode, the multiple first light-emitting devices and the multiple second light-emitting devices alternately display color images within a continuous multi-frame image driving cycle. Embodiments of this application can reduce the operating temperature of the light-emitting devices and extend their lifespan.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a driving method for a display device. Background Technology

[0002] Existing micro-inorganic light-emitting diode (Micro-LED) display panels typically employ pixel driving circuits with a single display branch. In high-brightness display modes, the light-emitting devices need to operate continuously at high current, resulting in high operating temperatures. Higher operating temperatures accelerate the performance degradation of the light-emitting devices, shortening their lifespan. Simultaneously, high temperatures also affect the performance of the display panel's driving circuitry, reducing display quality.

[0003] Furthermore, in the pixel driving circuits of existing Micro-LED display panels, if a light-emitting device or its driving circuit malfunctions, the corresponding pixel will exhibit display abnormalities, forming dead pixels on the display panel. These display abnormalities not only affect the display quality but also reduce the yield rate of the display panel and increase production costs.

[0004] Therefore, how to effectively reduce the operating temperature of light-emitting devices, extend their service life, and improve the reliability and yield of display panels while ensuring high brightness display performance is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a display device and its driving method to reduce the operating temperature of the light-emitting device.

[0006] An embodiment of this application provides a display device, comprising: a plurality of pixels, each pixel including a red sub-pixel, a green sub-pixel, and a blue sub-pixel, each of the red sub-pixel, the green sub-pixel, and the blue sub-pixel including a first light-emitting device and a pixel driving circuit, at least one of the red sub-pixel, the green sub-pixel, and the blue sub-pixel further including a second light-emitting device, wherein at least one second light-emitting device of the first pixel in a series of three consecutively arranged pixels emits red light, at least one second light-emitting device of the second pixel emits green light, and at least one second light-emitting device of the third pixel emits blue light; in a low grayscale display mode, the plurality of first light-emitting devices and the plurality of second light-emitting devices are configured to alternately display color images within a driving cycle of consecutive multi-frame images.

[0007] In the above-mentioned display device, in the high grayscale display mode, the first light-emitting device and the second light-emitting device emit light simultaneously within the driving cycle of one frame of image, and a plurality of the first light-emitting devices are configured to display a color image, and a plurality of the second light-emitting devices are configured to display a white image.

[0008] In the aforementioned display device, the pixel driving circuit includes: a first transistor, whose gate is electrically connected to a first scan signal input terminal and whose source is electrically connected to a first reset signal input terminal; a second transistor, whose gate is electrically connected to a light emission control signal input terminal and whose source is electrically connected to the first reset signal input terminal; a third transistor, whose source is electrically connected to a first power supply signal input terminal; a fourth transistor, whose gate is electrically connected to a second scan signal input terminal, whose source is electrically connected to a data signal input terminal, and whose drain is electrically connected to the drain of the second transistor; a fifth transistor, whose gate is electrically connected to the light emission control signal input terminal and whose source is electrically connected to the drain of the third transistor; and a sixth transistor, whose gate is electrically connected to the first scan signal input terminal, whose source is electrically connected to the first power supply signal input terminal, and whose drain is electrically connected to the first reset signal input terminal. The drain of the second transistor is electrically connected; the seventh transistor has its gate electrically connected to the second scan signal input terminal, its source electrically connected to the drain of the first transistor, and its drain electrically connected to the drain of the third transistor; the eighth transistor has its gate electrically connected to the first control signal input terminal, its source electrically connected to the drain of the fifth transistor, and its drain electrically connected to the anode of the first light-emitting device; the ninth transistor has its gate electrically connected to the second control signal input terminal, its source electrically connected to the drain of the fifth transistor, and its drain electrically connected to the anode of the second light-emitting device; the first capacitor has one plate electrically connected to the drain of the second transistor and the other plate electrically connected to the gate of the third transistor; the cathodes of both the first and second light-emitting devices are electrically connected to the second power supply signal input terminal.

[0009] In the above-mentioned display device, the pixel driving circuit further includes: a tenth transistor, whose gate is electrically connected to a third control signal input terminal, whose source is electrically connected to a first global signal input terminal, and whose drain is electrically connected to the anode of the first light-emitting device; and an eleventh transistor, whose gate is electrically connected to a fourth control signal input terminal, whose source is electrically connected to a second global signal input terminal, and whose drain is electrically connected to the anode of the second light-emitting device.

[0010] In the above-mentioned display device, the pixel driving circuit further includes: a tenth transistor, whose gate is electrically connected to the first scan signal input terminal, whose source is electrically connected to the second reset signal input terminal, and whose drain is electrically connected to the anode of the first light-emitting device; and an eleventh transistor, whose gate is electrically connected to the second scan signal input terminal, whose source is electrically connected to the second reset signal input terminal, and whose drain is electrically connected to the anode of the second light-emitting device.

[0011] In the above-described display device, the pixel driving circuit is configured to: during the reset phase, selectively turn on the tenth transistor and / or the eleventh transistor by a combination of the third and fourth control signals or a combination of the first and second scan signals to write a reset voltage to the anode of the first light-emitting diode and / or the second light-emitting device; during the data writing phase, selectively turn on the eighth transistor and / or the ninth transistor by the first and second control signals to write display data to the first light-emitting diode and / or the second light-emitting device; and during the light-emitting phase, selectively turn on the eighth transistor and / or the ninth transistor by the first and second control signals to control the first light-emitting diode and / or the second light-emitting device to emit light.

[0012] In the above-described display device, during the driving cycle of the first frame image in the low grayscale display mode, the first light-emitting device is configured to write display data and emit light, while the second light-emitting device is configured not to emit light; during the driving cycle of the second frame image in the low grayscale display mode, the second light-emitting device is configured to write display data and emit light, while the first light-emitting device is configured not to emit light.

[0013] Embodiments of this application also provide a driving method for a display device, comprising: controlling a plurality of first light-emitting devices to display a color image during a driving cycle of a first frame image in a low grayscale display mode, while a plurality of second light-emitting devices do not display a color image; and controlling a plurality of first light-emitting devices to not display a color image during a driving cycle of a second frame image in a low grayscale display mode, while a plurality of second light-emitting devices display a color image.

[0014] In the above driving method, during the driving cycle of the first frame image in the low grayscale display mode, display data is written to the first light-emitting device to control the first light-emitting device to emit light, while controlling the second light-emitting device to not emit light; during the driving cycle of the second frame image in the low grayscale display mode, display data is written to the second light-emitting device to control the second light-emitting device to emit light, while controlling the first light-emitting device to not emit light.

[0015] In the above driving method, controlling multiple first light-emitting devices to display a color image while multiple second light-emitting devices do not display a color image during the driving cycle of the first frame image in low grayscale display mode includes: writing a reset voltage to the anode of the first light-emitting device during the reset phase of the driving cycle of the first frame image; writing first display data to the first light-emitting device during the data writing phase of the driving cycle of the first frame image; and controlling the first light-emitting device to emit light during the emission phase of the driving cycle of the first frame image, while controlling the second light-emitting devices not to emit light. The controlling multiple first light-emitting devices to not display a color image while multiple second light-emitting devices display a color image during the driving cycle of the second frame image in low grayscale display mode includes: writing the reset voltage to the anode of the second light-emitting device during the reset phase of the driving cycle of the second frame image; writing second display data to the second light-emitting device during the data writing phase of the driving cycle of the second frame image; and controlling the second light-emitting device to emit light during the emission phase of the driving cycle of the second frame image, while controlling the first light-emitting device not to emit light.

[0016] In the above driving method, in the high grayscale display mode, within the driving cycle of one frame of image, multiple first light-emitting devices are controlled to display a color image, while multiple second light-emitting devices are controlled to display a white image.

[0017] In the above driving method, the step of controlling multiple first light-emitting devices to display a color image and simultaneously controlling multiple second light-emitting devices to display a white image within a driving cycle of a frame image in high grayscale display mode includes: writing a reset voltage to the anode of the first light-emitting device and the anode of the second light-emitting device during the reset phase of the driving cycle of a frame image; writing third display data to the first light-emitting device and fourth display data to the second light-emitting device during the data writing phase of the driving cycle of a frame image; and controlling the first light-emitting device and the second light-emitting device to emit light during the light emission phase of the driving cycle of a frame image.

[0018] The embodiments of this application employ two light-emitting device branches in the pixel driving circuit of each pixel and use an alternating driving method in low grayscale display mode, allowing each light-emitting device to work alternately within the driving cycle of consecutive multi-frame images. Since each light-emitting device has an inactive interval for a certain period, this alternating operation effectively reduces the cumulative working time of the light-emitting devices, thereby reducing their heat generation. Simultaneously, during the inactive intervals, the light-emitting devices have sufficient time to dissipate heat, significantly reducing their operating temperature. Lower operating temperatures slow down the performance degradation rate of the light-emitting devices, extending their lifespan.

[0019] Furthermore, embodiments of this application employ a method of arranging second light-emitting devices that emit red, green, and blue light in three consecutively arranged pixels. This arrangement not only allows for alternating operation of the light-emitting devices but also enables the display function to be maintained by switching to another light-emitting device when one device or its driving circuit fails. This avoids permanent display defects on the display panel and improves its reliability. Simultaneously, this redundancy design also increases the yield rate of the display panel.

[0020] In high grayscale display mode, the display device provided in the embodiments of this application can simultaneously drive a first light-emitting device and a second light-emitting device to operate, wherein the first light-emitting device displays a color image and the second light-emitting device displays a white image. By superimposing the color image and the white image, the overall brightness of the display panel can be improved, meeting the requirements of high-brightness display. This display method does not require a single light-emitting device to continuously operate in a high-current state, which can avoid excessive heat generated by the light-emitting device due to continuous high-current operation, thereby effectively controlling the operating temperature of the light-emitting device. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0022] Figure 2 This is a circuit diagram of a pixel in the first embodiment of the display device provided in this application.

[0023] Figure 3 This is a waveform diagram of the signal received by the pixel in the first embodiment of the display device provided in this application.

[0024] Figure 4 This is a schematic diagram of a first embodiment of the display device provided in this application, in which only one sub-pixel is provided with a second light-emitting device.

[0025] Figure 5 This is a schematic diagram of a method in which the first and second light-emitting devices of a pixel alternately emit light in two consecutive frames of an image, according to a first embodiment of the display device provided in this application.

[0026] Figure 6 This is a schematic diagram illustrating another way in which the first and second light-emitting devices of a pixel alternately emit light in two consecutive frames of an image, according to the first embodiment of the display device provided in this application.

[0027] Figure 7 This is a schematic diagram showing that in the first embodiment of the display device provided in this application, each of the two sub-pixels of a pixel is provided with a second light-emitting device.

[0028] Figure 8This is a schematic diagram showing that in the first embodiment of the display device provided in this application, each of the three sub-pixels of a pixel is provided with a second light-emitting device.

[0029] Figure 9 and Figure 10 This is a schematic diagram showing that in the first embodiment of the display device provided in this application, each of the four sub-pixels of a pixel is provided with a second light-emitting device.

[0030] Figure 11 This is a waveform diagram of the signal received by the pixel in the second embodiment of the display device provided in this application.

[0031] Figure 12 This is a circuit diagram of a pixel in the third embodiment of the display device provided in this application.

[0032] Figure 13 This is a waveform diagram of the signal received by the pixel in the third embodiment of the display device provided in this application.

[0033] Figure 14 This is a waveform diagram of the signal received by the pixel in the fourth embodiment of the display device provided in this application. Detailed Implementation

[0034] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0036] The embodiments of this application can be combined with each other.

[0037] The display device provided in the embodiments of this application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of this application will be described using a Micro-LED display device as an example.

[0038] like Figure 1 As shown, the display device provided in the embodiments of this application includes a display panel, a timing controller, a source drive circuit, and a power management chip (the power management chip can be integrated with the timing controller into the same chip). The display panel is an organic light-emitting diode display panel.

[0039] The display panel includes a display area and a non-display area. The display area has an array of m×n pixels (PX), where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driving circuits and various signal lines. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), and a gate driving circuit. The multiple scan lines (SCAN) extend along a first direction and are arranged along a second direction, and the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate driving circuit is located in the non-display area and is electrically connected to the multiple scan lines (SCAN). The source driving circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. A timing controller is electrically connected to both the gate driving circuit and the source driving circuit.

[0040] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes scan lines (SCAN), a gate electrode, etc. The second metal layer includes data lines (DATA), a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the OLED array substrate to prevent moisture and oxygen from penetrating the organic light-emitting layer.

[0041] Each pixel (PX) includes a pixel driving circuit and an organic light-emitting diode (OLED). The pixel driving circuit includes at least two thin-film transistors (TFTs) and a storage capacitor. One TFT acts as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line. The other TFT acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the OLED is electrically connected to a second power supply voltage line.

[0042] The gate driving circuit includes n cascaded gate driving units, each electrically connected to a scan line. Under the control of the timing controller, the gate driving units sequentially output scan signals, scanning each row of pixels PX in the display area line by line. The source driving circuit, under the control of the timing controller, generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source driving circuit. The power management chip (PMIC) provides operating voltages to various parts of the display device, including providing a second power supply voltage VSS for the cathode of the organic light-emitting diode (OLED), a first power supply voltage VDD for the first power supply line, and gate driving voltages VGH / VGL for the gate driving circuit.

[0043] Embodiments of this application provide a display device comprising a plurality of pixels PX, such as Figures 4 to 10 As shown, each pixel PX includes at least three sub-pixels, and these at least three sub-pixels include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. For example... Figure 2 and Figure 12 As shown, each sub-pixel includes a first light-emitting device LED1 and a pixel driving circuit, wherein at least one sub-pixel also includes a second light-emitting device LED2. The first light-emitting device LED1, the second light-emitting device LED2, and the pixel driving circuit are electrically connected. The pixel driving circuit has a main branch and an auxiliary branch, wherein the first light-emitting device LED1 is located in the main branch, and the second light-emitting device LED2 is located in the auxiliary branch.

[0044] In three pixels PX arranged consecutively along a row or column, the second light-emitting device LED2 of the first pixel PX emits red light, the second light-emitting device LED2 of the second pixel PX emits green light, and the second light-emitting device LED2 of the third pixel PX emits blue light.

[0045] The main and auxiliary branches of the pixel driving circuit of the display device provided in the embodiments of this application employ different driving methods in different display modes:

[0046] like Figure 5 and Figure 6 As shown, in low grayscale display mode, the main branch and auxiliary branch operate alternately. Specifically, during the driving cycle of the first frame image, the first light-emitting device LED1 of the main branch emits light, while the second light-emitting device LED2 of the auxiliary branch does not emit light; during the driving cycle of the second frame image, the first light-emitting device LED1 of the main branch does not emit light, while the second light-emitting device LED2 of the auxiliary branch emits light. By using this alternating light emission method, the working time of the light-emitting devices can be reduced, thereby reducing the heat generated by the light-emitting devices due to high-frequency refresh, and thus reducing the performance degradation and shortened lifespan caused by heat generation.

[0047] In high grayscale display mode, the main branch and the auxiliary branch operate simultaneously. Specifically, the first light-emitting device (LED1) of the main branch with multiple pixels is used to display red, green, or blue images, while the second light-emitting device (LED2) of the auxiliary branch with multiple pixels is used to display white images with a preset grayscale brightness. By mixing the color image displayed by the main branch with the white image displayed by the auxiliary branch, the overall display brightness of the display device can be improved.

[0048] In the display device provided in the embodiments of this application, by setting a main branch and an auxiliary branch, the problem of temperature rise caused by long-term operation of a single light-emitting device can be reduced, thereby reducing the performance degradation of the light-emitting device due to high temperature; by setting a main branch and an auxiliary branch in the pixel driving circuit, when the light-emitting device of one branch fails, the operation of the light-emitting device of the other branch can be switched, thereby alleviating the display abnormality problem caused by the failure of the light-emitting device; by driving the light-emitting devices of the main branch and the auxiliary branch respectively, the function of the light-emitting device can be verified, and then the display abnormality can be investigated whether it is caused by the failure of the light-emitting device or by other factors (such as substrate abnormality).

[0049] First embodiment:

[0050] like Figure 2 As shown, the pixel driving circuit of the display device provided in the embodiments of this application includes a first transistor PT1 to an eleventh transistor PT11 and a first capacitor C1.

[0051] The gate of the first transistor PT1 is electrically connected to the first scan signal input terminal Scan[n-1], and one of its sources or drains is electrically connected to the first reset signal input terminal ViG. The gate of the second transistor PT2 is electrically connected to the light emission control signal input terminal EM[n], and one of its sources or drains is electrically connected to the first reset signal input terminal ViG. One of the sources or drains of the third transistor PT3 is electrically connected to node S (the first power supply signal input terminal VDD). The gate of the fourth transistor PT4 is electrically connected to the second scan signal input terminal Scan[n], and one of its sources or drains is electrically connected to the data signal input terminal Data, while the other is electrically connected to node B (the other of the sources or drains of the second transistor). The gate of the fifth transistor PT5 is electrically connected to the light emission control signal input terminal EM[n], and one of its sources or drains is electrically connected to node D (the other of the sources or drains of the third transistor PT3). The gate of the sixth transistor PT6 is electrically connected to the first scan signal input terminal Scan[n-1]. One of its source or drain is electrically connected to node S (the first power signal input terminal VDD), and the other is electrically connected to node B (the other of the source or drain of the second transistor PT2). The gate of the seventh transistor PT7 is electrically connected to the second scan signal input terminal Scan[n]. One of its source or drain is electrically connected to node G (the other of the source or drain of the first transistor PT1), and the other is electrically connected to node D (the other of the source or drain of the third transistor PT3). The gate of the eighth transistor PT8 is electrically connected to the first control signal input terminal RW1. One of its source or drain is electrically connected to node E (the other of the source or drain of the fifth transistor PT5), and the other is electrically connected to node A1 (the anode of the first light-emitting device LED1). The gate of the ninth transistor PT9 is electrically connected to the second control signal input terminal RW2. One of its source or drain is electrically connected to node E (the other of the source or drain of the fifth transistor PT5), and the other is electrically connected to node A2 (the anode of the second light-emitting device LED2). The gate of the tenth transistor PT10 is electrically connected to the third control signal input terminal Discharge1. One of its source or drain is electrically connected to the first global signal input terminal Dataglobal1, and the other is electrically connected to node A1 (the anode of the first light-emitting device LED1). The gate of the eleventh transistor PT11 is electrically connected to the fourth control signal input terminal Discharge2. One of its source or drain is electrically connected to the second global signal input terminal Dataglobal2, and the other is electrically connected to node A2 (the anode of the second light-emitting device LED2). One end of the first capacitor C1 is electrically connected to node B (the other of the source or drain of the second transistor PT2), and the other end is electrically connected to node G (the gate of the third transistor PT3). The cathodes of both the first light-emitting device LED1 and the second light-emitting device LED2 are electrically connected to the second power signal input terminal VSS.The first light-emitting device LED1, the eighth transistor PT8, and the tenth transistor PT10 constitute the main branch, while the second light-emitting device LED2, the ninth transistor PT9, and the eleventh transistor PT11 constitute the auxiliary branch.

[0052] like Figure 3 As shown, the driving cycle of one frame of an image in the display device includes a reset phase T1, a data writing and threshold voltage compensation phase T2, and an emission phase T3.

[0053] In the driving cycle of the first frame of the image in low grayscale display mode:

[0054] During the reset phase T1, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] is high, the light emission control signal EM[n] is high, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is low, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is the first level Vref used to reset the anode of the first light-emitting device LED1, and the second global signal Dataglobal2 is the first level Vref used to reset the anode of the second light-emitting device LED2.

[0055] During the data writing and threshold voltage compensation stage T2, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is low, the light emission control signal EM[n] is high, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is low, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0056] During the light emission stage T3, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is high, the light emission control signal EM[n] is low, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is high, the fourth control signal Discharge2 is high, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0057] In the driving cycle of the second frame image in low grayscale display mode:

[0058] During the reset phase T1, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] is high, the light emission control signal EM[n] is high, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is low, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0059] During the data writing and threshold voltage compensation stage T2, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is low, the light emission control signal EM[n] is high, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is low, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0060] During the light emission stage T3, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is high, the light emission control signal EM[n] is low, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is high, the fourth control signal Discharge2 is high, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0061] In each frame's driving cycle of the high grayscale display mode, the first control signal RW1 is low, the second control signal RW2 is high, the eighth transistor PT8 is turned on, and the ninth transistor PT9 is turned off. The third control signal Discharge1 is high, the fourth control signal Discharge2 is low, the tenth transistor PT10 is turned off, and the eleventh transistor PT11 is turned on. Different grayscale signals input at the data signal terminal Data are written to the first light-emitting device LED1. At the same time, the second global signal Dataglobal2 inputs a fixed display data voltage Vdata, which is written to the second light-emitting device LED2 via the eleventh transistor PT11. Thus, the first light-emitting device LED1 displays a color image according to different grayscale signals, and the second light-emitting device LED2 displays a white image according to the fixed display data voltage Vdata.

[0062] like Figure 4 , Figure 5 and Figure 6 As shown, a row of pixels comprises multiple pixels PX, each pixel PX consisting of at least a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, arranged along the row direction. Subpixels in the same column have the same color. The specific arrangement is as follows:

[0063] In the first pixel PX, the pixel driving circuit of the red sub-pixel R has two branches (a red first light-emitting device RLED1 and a red second light-emitting device RLED2), and the pixel driving circuits of the green sub-pixel G and the blue sub-pixel B each have one branch (each with one light-emitting device, namely a green first light-emitting device GLED and a blue first light-emitting device GLED respectively).

[0064] In the second pixel PX, the pixel driving circuit of the green sub-pixel G has two branches (a green first light-emitting device and a green second light-emitting device), and the pixel driving circuits of the red sub-pixel R and the blue sub-pixel B each have one branch (each with one light-emitting device, namely a red first light-emitting device and a blue first light-emitting device respectively).

[0065] In the third pixel PX, the pixel driving circuit of the blue sub-pixel B has two branches (a blue first light-emitting device and a blue second light-emitting device), and the pixel driving circuits of the red sub-pixel R and the green sub-pixel G each have one branch (each with one light-emitting device, namely a red first light-emitting device and a green first light-emitting device respectively).

[0066] This arrangement allows the second light-emitting device, LED2, to independently display a complete color image, thus enabling the first light-emitting device, LED1, and the second light-emitting device, LED2, to work alternately in low grayscale display mode. This allows each light-emitting device sufficient time to dissipate heat and effectively reduces the operating temperature of the device. In high grayscale display mode, the brightness of the two light-emitting devices is superimposed, achieving a high-brightness display effect.

[0067] like Figure 5 and Figure 6 As shown, taking the red sub-pixel R as an example, which includes two branches, the main branch is located on the left and the auxiliary branch is located on the right. Figure 5 As shown, in the driving cycle of the first frame image, the main branch of the red sub-pixel R of the first pixel PX illuminates, while the auxiliary branch does not. Similarly, in the driving cycle of the second pixel PX, the main branch of the red sub-pixel R illuminates, while the auxiliary branch does not. In the driving cycle of the second frame image, the main branch of the red sub-pixel R of the first pixel PX does not illuminate, but the auxiliary branch does; and the main branch of the red sub-pixel R of the second pixel PX does not illuminate, but the auxiliary branch does. Or, as... Figure 6As shown, during the driving cycle of the first frame image, the main branch of the red sub-pixel R of the first pixel PX emits light, while the auxiliary branch does not emit light. The main branch of the red sub-pixel R of the second pixel PX does not emit light, while the auxiliary branch emits light. During the driving cycle of the second frame image, the main branch of the red sub-pixel R of the first pixel PX does not emit light, while the auxiliary branch emits light. The main branch of the red sub-pixel R of the second pixel PX emits light, while the auxiliary branch does not emit light.

[0068] In such Figure 7 In another pixel arrangement shown, the red sub-pixel R, green sub-pixel G, and blue sub-pixel B each have exactly two sub-pixels including two branches. The pixels in the same column have the same color, while the pixels in adjacent columns have different colors. The red sub-pixel R, green sub-pixel G, and blue sub-pixel B are arranged periodically along the row direction.

[0069] In such Figure 8 In the third pixel arrangement shown, the red sub-pixel R, green sub-pixel G, and blue sub-pixel B each include two branches (i.e., each includes two light-emitting devices). The pixels in the same column have the same color, while the pixels in adjacent columns have different colors. The red sub-pixel R, green sub-pixel G, and blue sub-pixel B are arranged periodically along the row direction.

[0070] In such Figure 9 , Figure 10 In the fourth pixel arrangement shown, the display device includes a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. All sub-pixels include two branches (i.e., all include two light-emitting devices). The white sub-pixel W can be located on one side of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B, or it can be located between the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B.

[0071] Second embodiment:

[0072] The pixel driving circuit of the second embodiment of this application is the same as the pixel driving circuit of the first embodiment, except that the driving timing is different, as detailed below:

[0073] like Figure 11 As shown, the driving cycle of one frame of an image in the display device includes a reset phase T1, a data writing and threshold voltage compensation phase T2, and an emission phase T3.

[0074] During the driving cycle of the first frame image:

[0075] In the reset phase T1 of the low grayscale display mode, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] is high, the light emission control signal EM[n] is high, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is low, the fourth control signal Discharge2 is high, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0076] During the data writing and threshold voltage compensation stage T2, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is low, the light emission control signal EM[n] is high, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is low, the fourth control signal Discharge2 is high, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0077] During the light emission stage T3, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is high, the light emission control signal EM[n] is low, the first control signal RW1 is low, the second control signal RW2 is high, the third control signal Discharge1 is high, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the second level Vdata.

[0078] In the driving cycle of the second frame image in low grayscale display mode:

[0079] During the reset phase T1, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] is high, the light emission control signal EM[n] is high, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is high, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0080] During the data writing and threshold voltage compensation stage T2, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is low, the light emission control signal EM[n] is high, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is high, the fourth control signal Discharge2 is low, the first global signal Dataglobal1 is at the first level Vref, and the second global signal Dataglobal2 is at the first level Vref.

[0081] During the light emission stage T3, the first scan signal Scan[n-1] is high, the second scan signal Scan[n] is high, the light emission control signal EM[n] is low, the first control signal RW1 is high, the second control signal RW2 is low, the third control signal Discharge1 is low, the fourth control signal Discharge2 is high, the first global signal Dataglobal1 is at the second level Vdata, and the second global signal Dataglobal2 is at the first level Vref.

[0082] like Figure 11 As shown, relative to Figure 3 In the illustrated technical solution, the third control signal Discharge1 and the fourth control signal Discharge2 have different level states in different stages of the driving cycle of the first and second frames of the image. Specifically, in the reset stage T1 and the data writing and threshold voltage compensation stage T2 of the driving cycle of the first frame of the image, the third control signal Discharge1 is at a low level and the fourth control signal Discharge2 is at a high level; in the light emission stage T3 of the driving cycle of the first frame of the image, the third control signal Discharge1 is at a high level and the fourth control signal Discharge2 is at a low level. In the reset stage T1 and the data writing and threshold voltage compensation stage T2 of the driving cycle of the second frame of the image, the third control signal Discharge1 is at a high level and the fourth control signal Discharge2 is at a low level; in the light emission stage T3 of the driving cycle of the second frame of the image, the third control signal Discharge1 is at a low level and the fourth control signal Discharge2 is at a high level. This avoids the problem of the light-emitting device accidentally lighting up in the data writing and threshold voltage compensation stage T2.

[0083] Furthermore, the level states of the first global signal Dataglobal1 and the second global signal Dataglobal2 are also different during the emission phase T3. Specifically, during the emission phase T3 of the driving cycle of the first frame image, the second global signal Dataglobal2 is at the second level Vdata; during the emission phase T3 of the driving cycle of the second frame image, the first global signal Dataglobal1 is at the second level Vdata. This allows the two light-emitting devices to emit light alternately, thereby reducing the operating time of the light-emitting devices and extending their lifespan.

[0084] Third embodiment:

[0085] The pixel driving circuit of the third embodiment of this application is similar to the driving circuit and driving timing of the first or second embodiment, except that:

[0086] like Figure 12 As shown, the gate of the tenth transistor PT10 is electrically connected to the first scan signal input terminal Scan[n-1], one of its source or drain is electrically connected to the second reset signal input terminal ViA, and the other is electrically connected to node A1 (the anode of the first light-emitting device LED1). The gate of the eleventh transistor PT11 is electrically connected to the second scan signal input terminal Scan[n], one of its source or drain is electrically connected to the second reset signal input terminal ViA, and the other is electrically connected to node A2 (the anode of the second light-emitting device LED2).

[0087] like Figure 13 As shown, in the driving cycle of the first frame image in low grayscale display mode:

[0088] During the reset phase T1, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] and the light emission control signal EM[n] are high. At this time, the first transistor PT1, the sixth transistor PT6 and the tenth transistor PT10 are turned on. Node B writes the first power supply signal VDD, and at the same time, node G writes the reset signal ViG and node A1 writes the reset signal ViA. The first control signal RW1 is low, the eighth transistor PT8 is turned on, the second control signal RW2 is high, and the ninth transistor PT9 is turned off.

[0089] During the data writing and threshold voltage compensation phase T2, the second scan signal Scan[n] is low, the first scan signal Scan[n-1] and the light emission control signal EM[n] are high, the first control signal RW1 is low, the eighth transistor PT8 is turned on, the second control signal RW2 is high, the ninth transistor PT9 is turned off, the data signal data is written to node B through the fourth transistor PT4, the seventh transistor PT7 is turned on, and after the reset phase T1, the third transistor PT3 is turned on, writing VDD+vth to node G. At the same time, the eleventh transistor PT11 is turned on, and the anode reset signal ViA is written to node A2, ensuring that the light-emitting device LED has no current conduction during the non-light emission phase.

[0090] During the light-emitting stage T3, the light-emitting control signal EM[n] is low, the first scan signal Scan[n-1] and the second scan signal Scan[n] are high, the second transistor PT2 and the fifth transistor PT5 are turned on, the first control signal RW1 is low, the second control signal RW2 is high, the eighth transistor PT8 is turned on, and the remaining transistors are turned off. Node B writes the reset signal ViG. Due to the coupling effect of capacitor C1, node G is coupled to VDD+vth+ViG-data. The first power supply signal VDD flows into the cathode of the first light-emitting device LED1 through the third transistor PT3, the fifth transistor PT5 and the tenth transistor PT10, and the first light-emitting device LED1 emits light.

[0091] In the driving cycle of the second frame image in low grayscale display mode:

[0092] During the reset phase T1, the first scan signal Scan[n-1] is low, the second scan signal Scan[n] and the light emission control signal EM[n] are high. At this time, the first transistor PT1, the sixth transistor PT6 and the tenth transistor PT10 are turned on. Node B writes the first power supply signal VDD, and at the same time, node G writes the reset signal ViG and node A1 writes the reset signal ViA. The first control signal RW1 is high, the eighth transistor PT8 is turned off, the second control signal RW2 is low, and the ninth transistor PT9 is turned on.

[0093] During the data writing and threshold voltage compensation phase T2, the second scan signal Scan[n] is low, the first scan signal Scan[n-1] and the light emission control signal EM[n] are high, the first control signal RW1 is high, the eighth transistor PT8 is off, the second control signal RW2 is low, the ninth transistor PT9 is on, the data signal data is written to node B through the fourth transistor PT4, the seventh transistor PT7 is on, and after the reset phase T1, the third transistor PT3 is on, writing VDD+vth to node G. At the same time, the eleventh transistor PT11 is on, and the anode reset signal ViA is written to node A2, ensuring that the light-emitting device LED has no current conduction during the non-light emission phase.

[0094] During the light-emitting stage T3, the light-emitting control signal EM[n] is low, the first scan signal Scan[n-1] and the second scan signal Scan[n] are high, the second transistor PT2 and the fifth transistor PT5 are turned on, the first control signal RW1 is high, the second control signal RW2 is low, the ninth transistor PT9 is turned on, and the remaining transistors are turned off. Node B writes the reset signal ViG. Due to the coupling effect of capacitor C1, node G is coupled to VDD+vth+ViG-data. The first power supply signal VDD flows into the cathode of the second light-emitting device LED2 through the third transistor PT3, the fifth transistor PT5 and the eleventh transistor PT11, and the second light-emitting device LED2 emits light.

[0095] In each frame of the image driving cycle in the high grayscale display mode, the first control signal RW1 is low, the second control signal RW2 is high, the eighth transistor PT8 is turned on, and the ninth transistor PT9 is turned off.

[0096] The first scan signal Scan[n-1] is high, the second scan signal Scan[n] is low, the tenth transistor PT10 is off, and the eleventh transistor PT11 is on. Different grayscale signals input at the data signal terminal Data are written to the first light-emitting device LED1. At the same time, the anode reset signal ViA, as the second global signal Dataglobal2, is written to the second light-emitting device LED2 via the eleventh transistor PT11. Thus, the first light-emitting device LED1 displays a color image according to different grayscale signals, and the second light-emitting device LED2 displays a white image according to a fixed display data voltage Vdata.

[0097] Fourth embodiment:

[0098] The pixel driving circuit of the fourth embodiment of this application is the same as that of the third embodiment, except for the driving timing, which is described in detail below:

[0099] like Figure 14As shown, the driving cycle of one frame of an image in the display device includes a reset phase T1, a data writing and threshold voltage compensation phase T2, and a light emission phase T3. Relative to... Figure 13 In the technical solution shown, the first control signal RW1 and the second control signal RW2 have different level states in each stage of the driving cycle of the first frame image and the driving cycle of the second frame image.

[0100] Specifically, in the driving cycle of the first frame of the image in low grayscale display mode:

[0101] During the reset phase T1 and the data writing and threshold voltage compensation phase T2, both the first control signal RW1 and the second control signal RW2 are at a high level, causing the eighth transistor PT8 and the ninth transistor PT9 to be turned off, thereby disconnecting the current path between the first light-emitting device LED1 and the second light-emitting device LED2 and the first power supply signal VDD. During the light-emitting phase T3, the first control signal RW1 is at a low level and the second control signal RW2 is at a high level, causing the eighth transistor PT8 to be turned on and the ninth transistor PT9 to be turned off, thereby causing the first light-emitting device LED1 to emit light and the second light-emitting device LED2 to not emit light.

[0102] In the driving cycle of the second frame image in low grayscale display mode:

[0103] During the reset phase T1 and the data writing and threshold voltage compensation phase T2, both the first control signal RW1 and the second control signal RW2 are at a high level, causing the eighth transistor PT8 and the ninth transistor PT9 to be turned off, thereby disconnecting the current path between the first light-emitting device LED1 and the second light-emitting device LED2 and the first power supply signal VDD. During the light-emitting phase T3, the first control signal RW1 is at a high level and the second control signal RW2 is at a low level, causing the eighth transistor PT8 to be turned off and the ninth transistor PT9 to be turned on, thereby causing the second light-emitting device LED2 to emit light and the first light-emitting device LED1 to not emit light.

[0104] By using the above control method, during the data writing and threshold voltage compensation stage T2, since both the eighth transistor PT8 and the ninth transistor PT9 are turned off, the problem of the light-emitting device being falsely lit due to the formation of a current path between the first power signal VDD and the second power signal VSS is avoided, thus improving the display effect of the display device.

[0105] Through the above technical solutions, the embodiments of this application can reduce the problem of reduced lifespan of light-emitting devices caused by heat generated in the display device due to high-frequency refresh rates. Furthermore, the dual-light-emitting device structure provides display redundancy; when one light-emitting device fails, the other can continue to operate, avoiding display dead spots. In high grayscale display mode, higher display brightness can be obtained through brightness superposition, while simultaneously preventing a single light-emitting device from continuously operating in a high-current state.

[0106] The technical solutions provided in the embodiments of this application can be applied to electronic devices such as miniature LED mobile phones, displays, and televisions.

[0107] like Figures 2 to 14 As shown, an embodiment of this application provides a display device, which includes a plurality of pixels PX. Each pixel PX includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Each of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B includes a first light-emitting device LED1 and a pixel driving circuit. At least one of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B also includes a second light-emitting device LED2. The color emitted by at least one second light-emitting device LED2 of the first pixel PX in a series of three consecutively arranged pixels PX is red, the color emitted by at least one second light-emitting device LED2 of the second pixel PX is green, and the color emitted by at least one second light-emitting device LED2 of the third pixel PX is blue.

[0108] The area of ​​the first light-emitting device LED1 may be equal to or different from the area of ​​the second light-emitting device LED2.

[0109] Red subpixels R, green subpixels G, and blue subpixels B are arranged along either the row or column direction.

[0110] In the low grayscale display mode, multiple first light-emitting devices LED1 and multiple second light-emitting devices LED2 are configured to alternately display color images within the driving cycle of two consecutive frames.

[0111] Specifically, such as Figure 3 , Figure 11 , Figure 13 and Figure 14 As shown, during the driving cycle of the first frame image in the low grayscale display mode, the first light-emitting device LED1 is configured to write display data and emit light, while the second light-emitting device LED2 is configured not to emit light. During the driving cycle of the second frame image in the low grayscale display mode, the second light-emitting device LED2 is configured to write display data and emit light, while the first light-emitting device LED1 is configured not to emit light.

[0112] In high grayscale display mode, the first light-emitting device LED1 and the second light-emitting device LED2 emit light simultaneously within the driving cycle of one frame of image. Multiple first light-emitting devices LED1 are configured to display a color image, and multiple second light-emitting devices LED2 are configured to display a white image. The light from the white image and the color image are mixed, the color image has a first brightness, the white image has a second brightness, and the first brightness and the second brightness are superimposed.

[0113] Each red sub-pixel R, green sub-pixel G, and blue sub-pixel B in each pixel PX includes a first light-emitting device LED 1; however, exactly one sub-pixel in each red sub-pixel R, green sub-pixel G, and blue sub-pixel B in each pixel PX includes a second light-emitting device LED 2, such as... Figure 4 , Figure 5 and Figure 6 As shown; or each red sub-pixel R, green sub-pixel G, and blue sub-pixel B in pixel PX all include the first light-emitting device LED1, but only two sub-pixels in each red sub-pixel R, green sub-pixel G, and blue sub-pixel B in pixel PX include the second light-emitting device LED2, such as... Figure 7 As shown; or each red sub-pixel R, green sub-pixel G, and blue sub-pixel B in pixel PX includes a first light-emitting device LED1 and a second light-emitting device LED2, as shown. Figure 8 As shown.

[0114] Furthermore, the display device also includes a white sub-pixel W, which includes a first light-emitting device LED1 and a second light-emitting device LED2, such as... Figure 9 and Figure 10 As shown.

[0115] like Figure 2 , Figure 12 As shown, the pixel driving circuit includes a first transistor PT 1, a second transistor PT 2, a third transistor PT 3, a fourth transistor PT 4, a fifth transistor PT 5, a sixth transistor PT 6, a seventh transistor PT 7, an eighth transistor PT 8, a ninth transistor PT 9, a tenth transistor PT 10, an eleventh transistor PT 11, and a first capacitor C1.

[0116] The gate of the first transistor PT1 is electrically connected to the first scan signal input terminal Scan[n-1], and the source of the first transistor PT1 is electrically connected to the first reset signal input terminal ViG; the gate of the second transistor PT2 is electrically connected to the light emission control signal input terminal Em[n], and the source of the second transistor PT2 is electrically connected to the first reset signal input terminal ViG; the source of the third transistor PT3 is electrically connected to the first power supply signal input terminal VDD; the gate of the fourth transistor PT4 is electrically connected to the second scan signal input terminal Scan[n], the source of the fourth transistor PT4 is electrically connected to the data signal input terminal Data, and the drain of the fourth transistor PT4 is electrically connected to the drain of the second transistor PT2; the gate of the fifth transistor PT5 is electrically connected to the light emission control signal input terminal EM[n], and the source of the fifth transistor PT5 is electrically connected to the drain of the third transistor PT3; the gate of the sixth transistor PT6 is electrically connected to the first scan signal input terminal Scan[n-1], and the source of the sixth transistor PT6 is electrically connected to the first power supply signal input terminal VDD, and the source of the sixth transistor PT5 is electrically connected to the first reset signal input terminal ViG; The drain of transistor PT6 is electrically connected to the drain of transistor PT2; the gate of transistor PT7 is electrically connected to the second scan signal input terminal Scan[n], the source of transistor PT7 is electrically connected to the drain of transistor PT1, and the drain of transistor PT7 is electrically connected to the drain of transistor PT3; the gate of transistor PT8 is electrically connected to the first control signal input terminal RW1, the source of transistor PT8 is electrically connected to the drain of transistor PT5, and the drain of transistor PT8 is electrically connected to the anode of the first light-emitting device LED1; the gate of transistor PT9 is electrically connected to the second control signal input terminal RW2, the source of transistor PT9 is electrically connected to the drain of transistor PT5, and the drain of transistor PT9 is electrically connected to the anode of the second light-emitting device LED2.

[0117] The gate of the tenth transistor PT10 is electrically connected to the third control signal input terminal Discharge1, the source of the tenth transistor PT10 is electrically connected to the first global signal input terminal Dataglobal1, and the drain of the tenth transistor PT10 is electrically connected to the anode of the first light-emitting device LED1. The gate of the eleventh transistor PT11 is electrically connected to the fourth control signal input terminal Discharge2, the source of the eleventh transistor PT11 is electrically connected to the second global signal input terminal Dataglobal2, and the drain of the eleventh transistor PT11 is electrically connected to the anode of the second light-emitting device LED2. At this time, the tenth transistor T10 is connected to the first global signal Dataglobal1 to control the light-emitting state of the first light-emitting device LED1, and the eleventh transistor T11 is connected to the second global signal Dataglobal2 to control the light-emitting state of the second light-emitting device LED2.

[0118] Alternatively, the gate of the tenth transistor PT10 is electrically connected to the first scan signal input terminal Scan[n-1], the source of the tenth transistor PT10 is electrically connected to the second reset signal input terminal ViA, and the drain of the tenth transistor PT10 is electrically connected to the anode of the first light-emitting device LED1; the gate of the eleventh transistor PT11 is electrically connected to the second scan signal input terminal Scan[n], the source of the eleventh transistor PT11 is electrically connected to the second reset signal input terminal ViA, and the drain of the eleventh transistor PT11 is electrically connected to the anode of the second light-emitting device LED2. In this case, the tenth transistor T10 is connected to the second reset signal ViA to reset the anode of the first light-emitting device LED1, and the eleventh transistor T11 is connected to the second reset signal ViA to reset the anode of the second light-emitting device LED2.

[0119] One plate of the first capacitor C1 is electrically connected to the drain of the second transistor PT2, and the other plate of the first capacitor C1 is electrically connected to the gate of the third transistor PT3; the cathodes of the first light-emitting device LED1 and the second light-emitting device LED2 are both electrically connected to the second power signal input terminal VSS.

[0120] The first transistor T1 and the second transistor T2 are used to initialize the circuit nodes. During the reset phase, when the first scan signal Scan[n-1] is low, the first transistor T1 is turned on, transmitting the first reset signal ViG to node G; when the light emission control signal EM[n] is low, the second transistor T2 is turned on, transmitting the first reset signal ViG to node B.

[0121] The third transistor, T3, acts as a driver transistor, and its gate voltage controls the current flowing through the light-emitting device. The fourth transistor, T4, acts as a data write switch; it is turned on when the second scan signal Scan[n] is low, writing the data signal Data into the storage node.

[0122] The fifth transistor, T5, controls the transmission path of the drive current. The sixth transistor, T6, and the seventh transistor, T7, are used for voltage compensation to eliminate the influence of the threshold voltage deviation of the drive transistor T3.

[0123] The eighth transistor T8 and the ninth transistor T9 control the light-emitting channels of the first light-emitting device LED1 and the second light-emitting device LED2, respectively. When the first control signal RW1 is low, the eighth transistor T8 is turned on, and the driving current flows to the first light-emitting device LED1. When the second control signal RW2 is low, the ninth transistor T9 is turned on, and the driving current flows to the second light-emitting device LED2. The first capacitor C1 is used to store the data voltage and compensation voltage to ensure that the gate voltage of the driving transistor T3 is stable during the light-emitting stage.

[0124] The tenth transistor T10 and the eleventh transistor T11 are used to control whether to reset the anode of the first light-emitting device LED1 and the second light-emitting device LED2, and to control whether to output a fixed display data voltage Vdata to one of the first light-emitting device LED1 and the second light-emitting device LED2.

[0125] like Figure 3 , Figure 11 , Figure 13 and Figure 14 As shown, the pixel driving circuit is configured as follows:

[0126] During the reset phase, the tenth transistor PT10 and / or the eleventh transistor PT11 are selectively turned on by a combination of the third control signal Discharge1 and the fourth control signal Discharge2 or a combination of the first scan signal Scan[n-1] and the second scan signal Scan[n], so as to write a reset voltage to the anode of the first light-emitting device LED1 and / or the second light-emitting device LED2.

[0127] During the data writing stage, the eighth transistor PT8 and / or the ninth transistor PT9 are selectively turned on by the first control signal RW1 and the second control signal RW2 to write display data to the first light-emitting device LED1 and / or the second light-emitting device LED2.

[0128] During the light-emitting stage, the eighth transistor PT8 and / or the ninth transistor PT9 are selectively turned on by the first control signal RW1 and the second control signal RW2 to control the first light-emitting device LED1 and / or the second light-emitting device LED2 to emit light.

[0129] During the driving cycle of the first frame image in the low grayscale display mode, the first light-emitting device LED1 is configured to write display data and emit light, while the second light-emitting device LED2 is configured not to emit light.

[0130] During the driving cycle of the second frame image in the low grayscale display mode, the second light-emitting device LED2 is configured to write display data and emit light, while the first light-emitting device LED1 is configured not to emit light.

[0131] Embodiments of this application also provide a driving method for a display device, comprising:

[0132] During the driving cycle of the first frame image in the low grayscale display mode, multiple first light-emitting devices LED1 are controlled to display a color image, while multiple second light-emitting devices LED2 do not display a color image.

[0133] During the driving cycle of the second frame image in the low grayscale display mode, multiple first light-emitting devices LED1 are controlled not to display color images, while multiple second light-emitting devices LED2 display color images.

[0134] During the driving cycle of the first frame image in the low grayscale display mode, display data is written to the first light-emitting device LED1 to control the first light-emitting device LED1 to emit light, while controlling the second light-emitting device LED2 to not emit light.

[0135] During the driving cycle of the second frame image in the low grayscale display mode, display data is written to the second light-emitting device LED2 to control the second light-emitting device LED2 to emit light, while controlling the first light-emitting device LED1 to not emit light.

[0136] like Figure 3 , Figure 11 , Figure 13 and Figure 14 As shown, during the driving cycle of the first frame image in low grayscale display mode, multiple first light-emitting devices (LED1) are controlled to display a color image, while multiple second light-emitting devices (LED2) do not display a color image, including:

[0137] During the reset phase of the driving cycle of the first frame image, a reset voltage is written to the anode of the first light-emitting device LED1;

[0138] During the data writing phase of the driving cycle of the first frame image, first display data is written to the first light-emitting device LED1; and

[0139] During the light-emitting phase of the driving cycle of the first frame image, the first light-emitting device LED1 is controlled to emit light, while the second light-emitting device LED2 is controlled not to emit light.

[0140] like Figure 3 , Figure 11 , Figure 13 and Figure 14 As shown, during the driving cycle of the second frame image in low grayscale display mode, controlling multiple first light-emitting devices LED1 to not display a color image while multiple second light-emitting devices LED2 display a color image includes:

[0141] During the reset phase of the driving cycle of the second frame image, a reset voltage is written to the anode of the second light-emitting device LED2;

[0142] During the data writing phase of the driving cycle of the second frame image, second display data is written to the second light-emitting device LED2; and

[0143] During the light-emitting phase of the driving cycle of the second frame image, the second light-emitting device LED2 is controlled to emit light, while the first light-emitting device LED1 is controlled not to emit light.

[0144] In high grayscale display mode, within the driving cycle of one frame of image, multiple first light-emitting devices LED1 are controlled to display a color image, while multiple second light-emitting devices LED2 are controlled to display a white image.

[0145] In high grayscale display mode, within the driving cycle of one frame of image, controlling multiple first light-emitting devices LED1 to display a color image, and simultaneously controlling multiple second light-emitting devices LED2 to display a white image includes:

[0146] During the reset phase of the driving cycle of a frame image, a reset voltage is written to the anode of the first light-emitting device LED1 and the anode of the second light-emitting device LED2.

[0147] During the data writing phase of a frame's driving cycle, third display data is written to the first light-emitting device LED1, and fourth display data (reference data) is written to the second light-emitting device LED2; and

[0148] During the light-emitting phase of the driving cycle of a frame image, the first light-emitting device LED1 and the second light-emitting device LED2 are controlled to emit light.

[0149] As an improvement, the driving method provided in the embodiments of this application further includes:

[0150] Detect the display status of the main branch and auxiliary branch;

[0151] Determine if there is a display abnormality based on the display status;

[0152] When a display abnormality occurs in the main branch, control the operation of the auxiliary branch;

[0153] When an abnormality occurs in the auxiliary branch, the operation of the main branch is controlled.

[0154] The embodiments of this application employ two light-emitting device branches in the pixel driving circuit of each pixel and use an alternating driving method in low grayscale display mode, allowing each light-emitting device to work alternately within the driving cycle of consecutive multi-frame images. Since each light-emitting device has an inactive interval for a certain period, this alternating operation effectively reduces the cumulative working time of the light-emitting devices, thereby reducing their heat generation. Simultaneously, during the inactive intervals, the light-emitting devices have sufficient time to dissipate heat, significantly reducing their operating temperature. Lower operating temperatures slow down the performance degradation rate of the light-emitting devices, extending their lifespan.

[0155] Furthermore, embodiments of this application employ a method of arranging second light-emitting devices (LEDs) emitting red, green, and blue light respectively in three consecutively arranged pixels (PX). This arrangement not only allows for alternating operation of the light-emitting devices but also enables the display function to be maintained by switching to another light-emitting device when one device or its driving circuit fails. This avoids permanent display defects on the display panel and improves its reliability. Simultaneously, this redundancy design also increases the yield rate of the display panel.

[0156] In high grayscale display mode, the display device provided in the embodiments of this application can simultaneously drive the first light-emitting device LED1 and the second light-emitting device LED2 to work, wherein the first light-emitting device LED1 displays a color image and the second light-emitting device LED2 displays a white image. By superimposing the color image and the white image, the overall brightness of the display panel can be improved, meeting the requirements of high brightness display. This display method does not require a single light-emitting device to continuously operate in a high-current state, which can avoid the light-emitting device generating excessive heat due to continuous high-current operation, thereby effectively controlling the operating temperature of the light-emitting device.

[0157] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, include: Multiple pixels, each pixel including a red sub-pixel, a green sub-pixel and a blue sub-pixel, each of the red sub-pixel, the green sub-pixel and the blue sub-pixel including a first light-emitting device and a pixel driving circuit, at least one of the red sub-pixel, the green sub-pixel and the blue sub-pixel further including a second light-emitting device, at least one second light-emitting device of the first pixel of three consecutively arranged pixels emits red light, at least one second light-emitting device of the second pixel emits green light, and at least one second light-emitting device of the third pixel emits blue light; In the low grayscale display mode, a plurality of the first light-emitting devices and a plurality of the second light-emitting devices are configured to alternately display color images within a driving cycle of consecutive multi-frame images; The pixel driving circuit is configured as follows: During the reset phase, the tenth transistor and / or the eleventh transistor are selectively turned on by a combination of the third control signal and the fourth control signal or a combination of the first scan signal and the second scan signal, so as to write a reset voltage to the anode of the first light-emitting device and / or the second light-emitting device. During the data writing phase, the eighth transistor and / or the ninth transistor are selectively turned on by the first control signal and the second control signal to write display data to the first light-emitting device and / or the second light-emitting device. During the light-emitting phase, the eighth transistor and / or the ninth transistor are selectively turned on by the first control signal and the second control signal to control the first light-emitting device and / or the second light-emitting device to emit light.

2. The display device as claimed in claim 1, characterized in that, In high grayscale display mode, the first light-emitting device and the second light-emitting device emit light simultaneously within the driving cycle of one frame of image, and multiple first light-emitting devices are configured to display color images, and multiple second light-emitting devices are configured to display white images.

3. The display device as claimed in claim 1, characterized in that, The pixel driving circuit includes: The first transistor has its gate electrically connected to the first scan signal input terminal and its source electrically connected to the first reset signal input terminal. The second transistor has its gate electrically connected to the light-emitting control signal input terminal and its source electrically connected to the first reset signal input terminal. The source of the third transistor is electrically connected to the first power signal input terminal. The fourth transistor has its gate electrically connected to the second scan signal input terminal, its source electrically connected to the data signal input terminal, and its drain electrically connected to the drain of the second transistor. The fifth transistor has its gate electrically connected to the light-emitting control signal input terminal, and its source electrically connected to the drain of the third transistor. The sixth transistor has its gate electrically connected to the first scan signal input terminal, its source electrically connected to the first power supply signal input terminal, and its drain electrically connected to the drain of the second transistor. The seventh transistor has its gate electrically connected to the second scan signal input terminal, its source electrically connected to the drain of the first transistor, and its drain electrically connected to the drain of the third transistor. The eighth transistor has its gate electrically connected to the first control signal input terminal, its source electrically connected to the drain of the fifth transistor, and its drain electrically connected to the anode of the first light-emitting device. The ninth transistor has its gate electrically connected to the second control signal input terminal, its source electrically connected to the drain of the fifth transistor, and its drain electrically connected to the anode of the second light-emitting device. The first capacitor has one plate electrically connected to the drain of the second transistor and the other plate electrically connected to the gate of the third transistor. The cathodes of both the first and second light-emitting devices are electrically connected to the second power signal input terminal.

4. The display device as claimed in claim 1, characterized in that, The pixel driving circuit also includes: The tenth transistor has its gate electrically connected to the third control signal input terminal, its source electrically connected to the first global signal input terminal, and its drain electrically connected to the anode of the first light-emitting device. The eleventh transistor has its gate electrically connected to the fourth control signal input terminal, its source electrically connected to the second global signal input terminal, and its drain electrically connected to the anode of the second light-emitting device.

5. The display device as claimed in claim 1, characterized in that, The pixel driving circuit also includes: The tenth transistor has its gate electrically connected to the first scan signal input terminal, its source electrically connected to the second reset signal input terminal, and its drain electrically connected to the anode of the first light-emitting device. The eleventh transistor has its gate electrically connected to the second scan signal input terminal, its source electrically connected to the second reset signal input terminal, and its drain electrically connected to the anode of the second light-emitting device.

6. The display device as claimed in claim 1, characterized in that, During the driving cycle of the first frame image in the low grayscale display mode, the first light-emitting device is configured to write display data and emit light, while the second light-emitting device is configured not to emit light. During the driving cycle of the second frame image in the low grayscale display mode, the second light-emitting device is configured to write display data and emit light, while the first light-emitting device is configured not to emit light.

7. A driving method for a display device, characterized in that, include: During the driving cycle of the first frame image in the low grayscale display mode, multiple first light-emitting devices are controlled to display a color image, while multiple second light-emitting devices do not display a color image. as well as During the driving cycle of the second frame image in the low grayscale display mode, multiple first light-emitting devices are controlled not to display color images, while multiple second light-emitting devices display color images. Wherein, during the driving cycle of the first frame image in the low grayscale display mode, controlling multiple first light-emitting devices to display a color image while multiple second light-emitting devices do not display a color image includes: During the reset phase of the driving cycle of the first frame image, a reset voltage is written to the anode of the first light-emitting device. During the data writing phase of the driving cycle of the first frame image, first display data is written to the first light-emitting device; and During the light emission phase of the driving cycle of the first frame image, the first light-emitting device is controlled to emit light, while the second light-emitting device is controlled not to emit light. During the driving cycle of the second frame image in the low grayscale display mode, controlling multiple first light-emitting devices not to display color images while multiple second light-emitting devices display color images includes: During the reset phase of the driving cycle of the second frame image, the reset voltage is written to the anode of the second light-emitting device; During the data writing phase of the driving cycle of the second frame image, second display data is written to the second light-emitting device; and During the light emission phase of the driving cycle of the second frame image, the second light-emitting device is controlled to emit light, while the first light-emitting device is controlled not to emit light.

8. The driving method as described in claim 7, characterized in that, During the driving cycle of the first frame image in the low grayscale display mode, display data is written to the first light-emitting device to control the first light-emitting device to emit light, while controlling the second light-emitting device not to emit light. During the driving cycle of the second frame image in the low grayscale display mode, display data is written to the second light-emitting device to control the second light-emitting device to emit light, while controlling the first light-emitting device not to emit light.

9. The driving method as described in claim 7, characterized in that, In high grayscale display mode, within the driving cycle of one frame of image, multiple first light-emitting devices are controlled to display a color image, while multiple second light-emitting devices are controlled to display a white image.

10. The driving method as described in claim 7 or 9, characterized in that, In high grayscale display mode, within the driving cycle of one frame of image, controlling multiple first light-emitting devices to display a color image while simultaneously controlling multiple second light-emitting devices to display a white image includes: During the reset phase of the driving cycle of a frame image, a reset voltage is written to the anode of the first light-emitting device and the anode of the second light-emitting device. During the data writing phase of the driving cycle of the image frame, third display data is written to the first light-emitting device, and fourth display data is written to the second light-emitting device; and During the light emission phase of the driving cycle of the image frame, the first light-emitting device and the second light-emitting device are controlled to emit light.

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