Novel analysis and test method for DRAM SWD PC missing failure

Abstract

The invention discloses a new analysis and test method for DRAM SWD PC missing failure. The method comprises the following steps: S1, enabling a DRAM to enter a global test mode; s2, writing a value into a known DRAM position through up-down movement of a DRAM address, and then reading and testing; s3, if the SWD PC missing failure occurs in the DRAM, the fault is not detected, and if the SWD PC missing failure occurs in the DRAM, the fault is not detected; and S4, if other conventional repairable WL faults are detected by the basic function test, the faults are still detected. According to the method, the non-repairable fault of DRAM SWD PC missing failure can be identified, so that the scrapped chips can be screened out in advance, and the economic cost is saved.

Description

Technical Field

[0001] The invention relates to a new analysis and testing method for DRAM SWD PC missing fail. Background Art

[0002] DRAM (Dynamic Random Access Memory) plays a very important role in today's integrated circuit products and is widely used in personal computers, various mobile terminal devices and data centers. However, with the continuous advancement of its process technology, it is becoming increasingly difficult to ensure the high yield of DRAM products. In order to improve the product yield, DRAM testing and failure analysis are essential links. The purpose of failure analysis is to find out the root cause of chip failure, draw conclusions to assist the process and design departments to improve the design and manufacturing, thereby improving the yield and reliability of the product. Chip testing covers as many chip failures as possible, and promptly repairs or discards the faulty DRAM chips through redundancy to ensure that the chips do not fail during normal use, and on this basis shorten the test time to reduce the test cost.

[0003] At present, in the industry, the mainstream method for implementing chip testing and failure analysis is to test wafers or chip particles through specific ATE (automatic test equipment) machines. The ATE machine inputs different test vectors into the chip and compares the test output with the normal output to implement various test items. In order to enable the product to be put on the market as soon as possible, it is increasingly important to establish a standardized, fast and comprehensive test process. According to the order of memory chip testing, memory testing can be divided into wafer testing, aging testing, and packaging testing. The test process diagram is as follows Figure 2 shown.

[0004] In order to maximize economic benefits, chip faults should be accurately identified by the test items and judged whether they can be repaired. Since packaging may introduce additional faults, DRAM chips are difficult to repair after packaging, and chip packaging will incur additional costs, the wafer test phase should try to correctly identify and repair the faults of the wafer itself, and screen out the chips that cannot be repaired to prevent them from flowing into the packaging phase and generating unnecessary costs.

[0005] In order to achieve a higher fault coverage rate, the March8n algorithm is often used when testing the basic functions of the chip. This algorithm simulates the normal reading and writing methods of the memory and can be used to detect common memory fault types. The fault coverage rate for the memory is above 95%. The process is as follows: Address increment: Write 0, the address sequence increases; Read 0, write 1, address sequence increases; Read 1, the address sequence increases; Address decrement: Write 0, address order descending; Read 0, write 1, address order descending; Read 1 in descending order; Currently, most industry standards use a combination of March8n and a checkerboard algorithm (black and white pieces represent 0 and 1 respectively), such as Figure 3 As shown, it is usually called SMarchCKBD algorithm. This algorithm enables the MBIST controller to perform fast row or column access to detect memory failures.

[0006] Although the basic functional test of current chips can achieve a high fault coverage rate by using a combination of March8n and the checkerboard algorithm, this test method cannot accurately identify faults caused by different manufacturing defects, and thus cannot distinguish between repairable faults and unrepairable faults. For example, the SWD pc missing fault of DRAM is an unrepairable fault, but it will be identified as a repairable fault by the basic functional test using March8n and the checkerboard algorithm. This will cause the fault with this defect to flow into the packaging stage after being repaired, resulting in unnecessary economic losses.

[0007] Therefore, a new analysis and testing method for DRAM SWD PC missing fail (dynamic random access memory serial debug PC missing failure) is provided. Summary of the invention

[0008] The purpose of the present invention is to overcome the existing defects and provide a new analysis and testing method for DRAM SWD PC missing fail, which can realize fault identification of DRAM SWD PC missing fail, an unrepairable fault, thereby realizing early screening of scrapped chips and saving economic costs.

[0009] The technical solution to achieve the above purpose is: A new analysis and testing method for DRAM SWD PC missing fail, including: Step S1, making the DRAM enter a global test mode; Step S2, writing the value to a known DRAM location by moving the DRAM address up and down, and then reading it for testing; Step S3, if the DRAM has SWD PC missing fail, no fault will be detected; Step S4, if other conventional repairable WL (row circuit) faults detected by the basic functional test, the faults will still be detected.

[0010] Preferably, in step S1, after the DRAM enters the global test mode, both the gate voltage and the substrate voltage of the MOS tube of the DRAM storage unit are reduced.

[0011] Preferably, in step S2, the value is written into a known DRAM location by moving the DRAM address up and down, and then read. The specific test process includes: Address increment: Turn off SA and force BL (column circuit) to 0, thereby writing 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl (word line) address increases sequentially, and short TRP is used; Address decrement: Turn off SA, force BL to 0, and thus write 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl address sequence decreases, and short TRP is used.

[0012] Preferably, in step S4, if a WL fault is detected in the DRAM during the basic function test, and no WL fault is detected using the process of step S2, it can be determined that an unrepairable SWD PC missing fail occurs in the DRAM, and the chip should be scrapped immediately.

[0013] The beneficial effects of the present invention are as follows: the present invention combines the test method with the basic functional test commonly used in the industry to realize the fault identification of the unrepairable fault of DRAM SWD PC missing fail, thereby realizing the early screening of scrapped chips and saving economic costs; and also has a positive impact on the failure analysis work of the chip back-end; and the test method can be used in combination with the basic functional test commonly used in the industry to achieve the purpose of chip screening. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow chart of a new analysis and testing method for DRAM SWD PC missing fail of the present invention; Figure 2 It is a test flow diagram of the traditional method that can divide the memory test into wafer test, aging test, and packaging test according to the order of memory chip testing; Figure 3 It is a test chart of the traditional checkerboard algorithm; Figure 4 This is the SWD circuit schematic; Figure 5This is a schematic diagram of PC missing fail in SWD circuit. DETAILED DESCRIPTION

[0015] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0016] The present invention will be further described below in conjunction with the accompanying drawings.

[0017] The principle of repair in DRAM is to replace the faulty row circuit and column circuit with redundant WL (row circuit) and BL (column circuit). The faulty row circuit and column circuit need to be permanently turned off. The circuit module that controls the WL switch in DRAM is SWD, as shown in the schematic diagram. Figure 4 shown.

[0018] The PMOS tube controls the opening of the word line (wl), and the two NMOS tubes below it control the closing of WL.

[0019] When PC missing fail occurs in SWD, the electrical connection of the two NMOS tubes controlling the wl shutdown will fail, causing WL to fail to shut down normally. The schematic diagram is as follows: Figure 5 As shown; Therefore, when PC missing fail occurs in SWD, WL fail will occur during the DRAM basic function test. Since the WL cannot be closed normally, the fault cannot be repaired. Moreover, since the basic function test using March8n and the checkerboard algorithm cannot identify the fault as an unrepairable fault, it will be repaired normally and flow into the backend, causing unnecessary economic losses. Therefore, a new analysis and testing method for DRAM SWD PC missing fail is provided.

[0020] like Figure 1 As shown, a new analysis and testing method for DRAM SWD PC missing fail includes: Step S1, making the DRAM enter a global test mode.

[0021] In the embodiment, after the DRAM enters the global test mode, the gate voltage and substrate voltage of the MOS tube of the DRAM storage unit are both reduced.

[0022] Step S2, write the value to a known DRAM location by moving the DRAM address up and down, and then read it for testing.

[0023] In the embodiment, the value is written into a known DRAM location by moving the DRAM address up and down, and then read and tested. The specific test process includes: Address increment: Turn off SA, force BL to 0, and thus write 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl address increases sequentially, and short TRP is used; Address decrement: Turn off SA, force BL to 0, and thus write 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl address sequence decreases, and short TRP is used.

[0024] In step S3, if the DRAM has SWD PC missing fail, no fault will be detected.

[0025] Step S4: If other conventional repairable WL faults are detected by the basic functional test, the faults will still be detected.

[0026] In the embodiment, if a WL fault is detected in the DRAM during the basic function test, and no WL fault is detected during the process of step S2, it can be determined that an unrepairable SWD PC missing fail occurs in the DRAM, and the chip should be scrapped immediately.

[0027] Combining this test method with the basic functional tests commonly used in the industry can realize the fault identification of DRAM SWD PC missing fail, which is an unrepairable fault, so as to achieve early screening of scrapped chips and save economic costs. It also has a positive impact on the failure analysis work of the chip backend.

[0028] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments may still be modified, or some or all of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A new analysis and testing method for DRAM SWD PC missing fail, characterized in that: include: Step S1, making the DRAM enter a global test mode; Step S2, writing the value to a known DRAM location by moving the DRAM address up and down, and then reading it for testing; Step S3, if the DRAM has a SWD PC missing fault, the fault will not be detected; Step S4: If other conventional repairable WL faults are detected by the basic functional test, the faults will still be detected.

2. A new analysis and testing method for DRAM SWD PC missing fail according to claim 1, characterized in that: In the step S1, after the DRAM enters the global test mode, the gate voltage and substrate voltage of the DRAM storage unit MOS tube are both reduced.

3. A new analysis and testing method for DRAM SWD PC missing fail according to claim 1, characterized in that: In step S2, the value is written into a known DRAM location by moving the DRAM address up and down, and then read and tested. The specific test process includes: Address increment: Turn off SA, force BL to 0, and write 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl address increases sequentially, and short TRP is used; Address decrement: Turn off SA, force BL to 0, and write 0 to DRAM; Long Tras; SA and BL return to normal, read 0, wl address sequence decreases, and short TRP is used.

4. A new analysis and testing method for DRAM SWD PC missing fail according to claim 1, characterized in that: In step S4, if the DRAM detects a WL fault in the basic function test and the WL fault is not detected using the process of step S2, it can be determined that the DRAM has an unrepairable SWD PC missing fail, and the chip should be scrapped immediately.

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