Packaging structure and forming method thereof

Abstract

The invention provides a packaging structure and a forming method thereof, in the forming method, a bridge chip assembly is firstly formed, a silicon through hole of a bridge chip is exposed in a mode of firstly depositing a protection layer and then thinning the silicon through hole, the protection layer can protect a substrate in the thinning process, and the substrate is prevented from being damaged. Metal ions generated by thinning the silicon through hole can be prevented from being migrated and diffused into the substrate, so that the problem of reliability failure of the packaging structure caused by migration and diffusion of the metal ions is avoided; meanwhile, when the bridge chip assembly is plastically packaged, the bottom surface of the bridge chip assembly is provided with an adhesion layer, the adhesion layer is removed after plastic packaging, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer, and after bottom rewiring layers are formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the bottom rewiring layers are formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly. The thickness of the bottom rewiring layer located on the bottom face of the bridge chip assembly is larger than that of the bottom rewiring layer located on the bottom face of the first plastic packaging layer, namely, the bottom of the bridge chip assembly is provided with a thicker dielectric layer, so that the connection strength of all connection points of the bridge chip assembly is guaranteed, higher stress buffering is provided for the bridge chip, and the reliability of the bridge chip assembly is improved. And the reliability of the packaging structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging structure and a forming method thereof. Background Art

[0002] Advanced Packaging is a new type of electronic packaging technology that aims to integrate multiple chips or other electronic components with higher integration, smaller size, lower power consumption and higher reliability through innovative technical means.

[0003] Wafer Level Package (WLP) is a packaging process in which most of the process steps are performed on wafers. The demand for wafer level packaging is not only limited by the requirements of smaller package size and height, but also must meet the requirements of simplifying the supply chain, reducing overall costs, and improving overall performance.

[0004] Fan-out wafer-level packaging can be divided into die first and die last according to the process. The die first process simply means putting the chip on first and then wiring (Redistribution layer, referred to as RDL), while the die last process means wiring first and then putting the chip on after the unit passes the test. In the advanced packaging structure using the die last, a bridge chip (Si Bridge Die) needs to be buried in the wiring insertion layer (interposer), and the bridge chip is a structure with TSV and DTC functions. However, the reliability of this advanced packaging structure needs to be improved.

[0005] Therefore, how to improve the reliability of the packaging structure of the embedded bridge chip has become the focus of current research. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a packaging structure and a forming method thereof, which can improve the reliability of the packaging structure.

[0007] In order to solve the above problems, an embodiment of the present invention provides a method for forming a packaging structure, comprising: forming a bridge chip component, the bridge chip component comprising: a bridge chip, a protective layer and an adhesion layer, the bridge chip comprising a substrate and a silicon through hole penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the silicon through hole, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole, the adhesion layer covers the bottom surface of the protective layer and the bottom surface of the silicon through hole; the bridge chip component is arranged on the top surface of a carrier board, the adhesion layer is in contact with the top surface of the carrier board; plastic sealing to form a first plastic sealing layer, the first plastic sealing layer The sealing layer covers the side surface of the bridge chip assembly and the top surface of the carrier; a chip packaging assembly is formed on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, and the bridge chip assembly is electrically connected to the chip packaging assembly; the adhesion layer of the carrier and the bridge chip assembly is removed, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer; a bottom redistribution layer is formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

[0008] An embodiment of the present invention also provides a packaging structure, which includes: a bridge chip assembly, the bridge chip assembly includes a bridge chip and a protective layer, the bridge chip includes a substrate and a silicon through hole penetrating the substrate, the protective layer is arranged on the bottom surface of the substrate and exposes the bottom surface of the silicon through hole, and the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer; a first plastic sealing layer, the first plastic sealing layer covers the side surface of the bridge chip assembly, and the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic sealing layer; a chip packaging assembly, arranged on the top surface of the first plastic sealing layer and the top surface of the bridge chip assembly, the bridge chip assembly is electrically connected to the chip packaging assembly; a bottom redistribution layer, arranged on the bottom surface of the first plastic sealing layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic sealing layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

[0009] The packaging structure and the forming method thereof provided by the embodiment of the present invention first form a bridge chip component, wherein the silicon through hole of the bridge chip is exposed by first depositing a protective layer and then thinning the silicon through hole. In the thinning process, the protective layer can protect the substrate, and the metal ions (such as copper ions) generated by the thinning of the silicon through hole can be prevented from migrating and diffusing into the substrate, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions; at the same time, when the bridge chip component is plastic-sealed, the bottom surface of the bridge chip component has an adhesion layer, and the adhesion layer is removed after plastic sealing, so that the bottom surface of the bridge chip component is higher than the bottom surface of the first plastic sealing layer. After the bottom redistribution layer is formed on the bottom surface of the first plastic sealing layer and the bottom surface of the bridge chip component, the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip component is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic sealing layer, that is, the bottom of the bridge chip component has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip component is guaranteed, and a higher stress buffer is provided for the bridge chip, thereby improving the reliability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 is a schematic diagram of steps of a method for forming a packaging structure provided by an embodiment of the present invention;

[0012] Figure 2 to Figure 16 is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention;

[0013] Fig.17 is a schematic diagram of a semiconductor structure in a method for forming a packaging structure provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0014] The specific implementation manner of the packaging structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 is a schematic diagram of the steps of a method for forming a packaging structure provided by an embodiment of the present invention. Figure 1The formation method comprises: step S10, forming a bridge chip assembly, the bridge chip assembly comprises: a bridge chip, a protective layer and an adhesive layer, the bridge chip comprises a substrate and a silicon through hole penetrating the substrate, the protective layer is arranged on the bottom surface of the substrate, and the bottom surface of the silicon through hole is exposed, wherein the bottom surface of the silicon through hole is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the silicon through hole, and the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the silicon through hole; step S11, arranging the bridge chip assembly on the top surface of a carrier, and the adhesive layer contacts the top surface of the carrier; step S12, plastic encapsulation, forming a first plastic encapsulation layer, and the first plastic encapsulation layer covers the bridge chip assembly The step S13 comprises forming a chip packaging assembly on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, and the bridge chip assembly is electrically connected to the chip packaging assembly; the step S14 comprises removing the adhesion layer of the carrier and the bridge chip assembly, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer; the step S15 comprises forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

[0016] The packaging structure and the forming method thereof provided by the embodiment of the present invention first form a bridge chip component, wherein the silicon through hole of the bridge chip is exposed by first depositing a protective layer and then thinning the silicon through hole. In the thinning process, the protective layer can protect the substrate, and the metal ions (such as copper ions) generated by the thinning of the silicon through hole can be prevented from migrating and diffusing into the substrate, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of the metal ions; at the same time, when the bridge chip component is plastic-sealed, the bottom surface of the bridge chip component has an adhesion layer, and the adhesion layer is removed after plastic sealing, so that the bottom surface of the bridge chip component is higher than the bottom surface of the first plastic sealing layer. After the bottom redistribution layer is formed on the bottom surface of the first plastic sealing layer and the bottom surface of the bridge chip component, the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip component is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic sealing layer, that is, the bottom of the bridge chip component has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip component is guaranteed, and a higher stress buffer is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0017] Figure 2 to Figure 16 It is a process flow chart of a method for forming a packaging structure provided by an embodiment of the present invention.

[0018] See also Figure 1 and Fig.10, step S10, forming a bridge chip component 100, the bridge chip component 100 includes: a bridge chip 110, a protective layer 120 and an adhesion layer 140, the bridge chip 110 includes a substrate 111 and a silicon through hole 112 penetrating the substrate 111, the protective layer 120 is arranged on the bottom surface of the substrate 111, and the bottom surface of the silicon through hole 112 is exposed, wherein the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120 by first depositing the protective layer 120 and then thinning the silicon through hole 112, and the adhesion layer 140 covers the bottom surface of the protective layer 120 and the bottom surface of the silicon through hole 112.

[0019] In the bridge chip assembly 100 provided in the embodiment of the present invention, the bottom surface of the silicon through via 112 is flush with the bottom surface of the protective layer 120. When manufacturing the bridge chip assembly 100, the protective layer 120 is first deposited, and then the bottom surface of the silicon through via 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through via 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions.

[0020] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, and the protective layer 120 is a single layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitrogen silicon dioxide. In one embodiment, a passivation layer 113 (marked at Figure 2 ), the passivation layer 113 is used to isolate the through silicon via 112 from the substrate 111 to prevent the metal ions in the through silicon via from diffusing into the substrate 111.

[0021] In one embodiment, the bridge chip assembly 100 further includes a bottom pad 130, which is disposed on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112. In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 is disposed on the bottom surface of the through silicon via 112, so that the first plastic encapsulation layer 401 (refer to FIG. 1 ) covering the bridge chip assembly 100 can be reduced in the packaging structure using the bridge chip assembly 100. Fig.12 ) thickness, thereby reducing the warpage of the partial structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 130 is larger than the cross-sectional area of ​​the through silicon via 112, so as to ensure that the through silicon via 112 can be fully in contact with the bottom pad 130, reduce the contact resistance, and further reduce the delay of the electrical signal.

[0022] The embodiment of the present invention further provides a method for forming a bridge chip assembly 100. Specifically, the steps of forming the bridge chip assembly 100 include:

[0023] See also Figure 2 , providing a device wafer, the device wafer comprising a bridge chip 110, the bridge chip 110 comprising an initial substrate 300, an initial silicon through via 310 extending from the top surface of the initial substrate 300 to the inside of the initial substrate 300, and the side and bottom surfaces of the initial silicon through via 310 are covered with a passivation layer 113. The passivation layer 113 includes but is not limited to silicon oxide, silicon nitride and a combination thereof.

[0024] In some embodiments, the bridge chip 110 further includes a deep trench capacitor (DTC) 180, and the deep trench capacitor 180 is disposed in the initial substrate 300. In some embodiments, the deep trench capacitor 180 extends from the top surface of the initial substrate 300 to the inside of the initial substrate 300. In one embodiment, the device wafer further includes an internal redistribution layer 160 and a conductive column 170, the internal redistribution layer 160 is disposed on the top surface of the initial substrate 300, the conductive column 170 is disposed on the top surface of the internal redistribution layer 160, and the deep trench capacitor 180 is electrically connected to the internal redistribution layer 160.

[0025] In some embodiments, the step of providing a device wafer specifically includes: providing an initial wafer, the initial wafer including an initial substrate 300, an initial silicon through hole 310 extending from the top surface of the initial substrate 300 to the inside of the initial substrate 300, and a deep trench capacitor 180; forming an internal redistribution layer 160 and a conductive column 170 on the top surface of the initial substrate 300, the internal redistribution layer 160 is electrically connected to the top surface of the initial silicon through hole 310, and the conductive column 170 is arranged on the top surface of the internal redistribution layer 160 and is electrically connected to the internal redistribution layer 160. The internal redistribution layer 160 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the initial silicon through hole 310, and the other side is electrically connected to the conductive column 170. The initial silicon through hole 310 includes but is not limited to a copper column, the conductive column 170 includes but is not limited to a copper column, and the dielectric layer includes but is not limited to a silicon dioxide layer or a silicon nitride layer. The initial substrate 300 includes but is not limited to a silicon substrate. In some embodiments, the top surfaces of the initial through silicon via 310 and the deep trench capacitor 180 are flush with the top surface of the initial substrate 300 .

[0026] Optionally, in some embodiments, in order to support the device wafer in the subsequent step of processing the bottom surface of the device wafer (for example, thinning the initial substrate 300), the step of providing the device wafer further includes: Figure 3 , bonding the support substrate 320 to the front side of the device wafer. The support substrate 320 includes but is not limited to a glass substrate. Further, the step of bonding the support substrate 320 to the front side of the device wafer includes: bonding the support substrate 320 to a side of the device wafer having the conductive pillar 170. Specifically, this step includes: forming a covering layer 330 on the front side of the device wafer, the covering layer 330 covering the conductive pillar 170 and covering the surface of the internal redistribution layer 160; bonding the support substrate 320 to the device wafer using the surface of the support substrate 320 and the surface of the covering layer 330 as bonding surfaces.

[0027] See also Figure 4 and Figure 5 , a portion of the initial substrate 300 is removed from the bottom surface of the initial substrate 300 to form the substrate 111 , and the initial silicon through vias 310 protrude from the bottom surface of the substrate 111 .

[0028] In some embodiments, this step may include the following two steps:

[0029] See also Figure 4 , a portion of the initial substrate 300 is removed from the bottom surface of the initial substrate 300 to a set distance from the passivation layer 113 of the bottom surface of the initial silicon via 310. Specifically, the initial substrate 300 is processed by the thinning and flattening process method from the bottom surface of the initial substrate 300 to close to the initial silicon via 310, the initial silicon via 310 is covered by the passivation layer 113, the passivation layer 113 is covered by the initial substrate 300, and the initial silicon via 310 is still not exposed, which can prevent the initial silicon via 310 from exposing copper ions to contaminate the substrate 111. During the thinning process, the supporting substrate 320 supports the device wafer. Figure 4 As shown, in this step, the support substrate 320 is facing downward, and the device wafer is located above the support substrate 320 .

[0030] See also Figure 5 , continue to remove part of the initial substrate 300 from the bottom surface of the initial substrate 300 to form a substrate 111, and the initial silicon through-holes 310 protrude from the bottom surface of the substrate 111. Figure 5As shown, when performing this step, the support substrate 320 is facing downward, and the device wafer is located above the support substrate 320. In this step, the initial silicon through via 310 is not removed, so that the initial silicon through via 310 protrudes from the bottom surface of the substrate 111. In some embodiments, a dry etching process can be used to remove part of the initial substrate 300. The dry etching material can etch the initial substrate 300 without etching the passivation layer 113 on the surface of the initial silicon through via 310, thereby preventing copper ions from contaminating the substrate 111 and the cavity of the subsequent process.

[0031] See also Figure 6 , forming a protective layer 120 on the bottom surface of the substrate 111. In this embodiment, the protective layer 120 also covers the surface of the passivation layer 113. In this step, the protective layer 120 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) and other processes. The protective layer 120 is a single-layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitrogen silicon dioxide. In other embodiments, the protective layer 120 may also only cover the bottom surface of the substrate 110.

[0032] See also Figure 7 , the passivation layer 113 and the initial silicon via 310 are thinned from the bottom surface of the initial silicon via 310 to form a silicon via 112, so that the bottom surface of the silicon via 112 is flush with the bottom surface of the protective layer 120, and the side surface of the silicon via 112 is covered with the passivation layer 113. In this step, when the initial silicon via 310 is thinned, the passivation layer 113 on the bottom surface of the initial silicon via 310 is thinned first, and when the initial silicon via 310 is further thinned, the passivation layer 113 on the side surface of the initial silicon via 310 is also removed synchronously. In this step, the initial silicon via 310 can be polished by a chemical mechanical polishing process until the formed silicon via 112 meets the preset height requirement. In some embodiments, the bottom surface of the protective layer 120 is polished at the same time to provide a flat surface for subsequent processes. In this step, when grinding the initial silicon through via 310, the surface of the substrate 111 is covered by the protective layer 120, and the metal ions generated during grinding cannot diffuse into the substrate 111, thereby avoiding reliability failure problems of the packaging structure caused by the migration and diffusion of metal ions.

[0033] In some embodiments, after the step of thinning the passivation layer 113 and the initial silicon via 310 from the bottom surface of the initial silicon via 310 to form the silicon via 112, the step further includes: Figure 8, forming a bottom pad 130, the bottom pad 130 is arranged on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112. The bottom pad 130 serves as a structure for connecting the through silicon via 112 to the outside. In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 can be formed by a photolithography process and an electroplating process.

[0034] In some embodiments, the step of forming the bottom pad 130 further includes: forming a seed layer 150 on the bottom surface of the protection layer 120 and the bottom surface of the through silicon via 112; and forming the bottom pad 130 on the seed layer 150 on the bottom surface of the through silicon via 112 by electroplating. The seed layer 150 may be a copper layer or a titanium layer or a multi-layer metal layer. Figure 8 As shown, the forming method further includes: removing the seed layer 150 not covered by the bottom pad 130, and only retaining the seed layer 150 located in the bottom pad 130 area. Fig.17 , the seed layer 150 may not be removed after the bottom pad 130 is formed, but may be removed in a subsequent process.

[0035] See also Fig. 9 , forming an adhesion layer 140, the adhesion layer 140 covers the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. Specifically, in this step, the adhesion layer 140 is formed on the bottom surface of the protective layer 120 and the bottom surface of the bottom pad 130. The bridge chip assembly 100 is fixed on the wafer ring 350 (Waferring) by the adhesion layer 140. In some embodiments, the bottom surface of the device wafer is fixed on the wafer ring 350 through the adhesion layer 140, and the supporting substrate 320 faces upward. The adhesion layer 140 is made of a material with a certain viscosity, such as an acrylic resin series (acrylic). In some embodiments, the adhesion layer 140 is a die attachment film (Die Attachment Film, DAF for short), which has excellent thermal conductivity and adhesion. In some embodiments, such as Fig.17 After the bottom pad 130 is formed, the seed layer 150 is not removed, and the adhesion layer 140 covers the bottom surface of the seed layer 150 and the bottom surface of the bottom pad 130 .

[0036] In some embodiments, the step of forming the adhesion layer 140 further includes: Fig.10, debonding the support substrate 320, and singulating the device wafer to form the bridge chip assembly 100. In this step, after debonding the support substrate 320, the cover layer 330 on the front side of the device wafer is also removed, and the conductive pillar 170 is exposed. In some embodiments, a suitable debonding process can be selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc. The device wafer is singulated to form a plurality of independent bridge chip assemblies 100.

[0037] The above is an embodiment of forming the bridge chip assembly 100 .

[0038] See also Figure 1 as well as Fig.11 , step S11 , disposing the bridge chip assembly 100 on the top surface of a carrier 600 , and the adhesive layer 140 is in contact with the top surface of the carrier 600 .

[0039] In some embodiments, the carrier 600 is a glass substrate, and its surface has a temporary bonding layer 601 and a buffer metal layer 602. The bridge chip assembly 100 is disposed on the buffer metal layer 602 through a die attach or die bonding (DA) process. In some embodiments, this step further includes disposing a metal column 402 on the surface of the carrier 600.

[0040] See also Figure 1 and Fig.12 , step S12, plastic encapsulation, forming a first plastic encapsulation layer 401, the first plastic encapsulation layer 401 covers the side of the bridge chip component 100 and the top surface of the carrier 600. Specifically, this step further includes: using plastic encapsulation material to cover the bridge chip component 100, the metal column 402 and the surface of the buffer metal layer 602 covering the carrier 600; preliminarily thinning the plastic encapsulation material to expose the metal column 402 and the conductive column 170 on the top surface of the bridge chip component 100; etching the metal column 402 and the conductive column 170 on the top surface of the bridge chip component 100 to a preset height; continuing to thin the plastic encapsulation material to form the first plastic encapsulation layer 401, the top surface of the first plastic encapsulation layer 401 is flush with the top surface of the metal column 402 and the top surface of the conductive column 170, and the top surface of the metal column 402 and the top surface of the conductive column 170 are not covered by the first plastic encapsulation layer 401. After initially thinning the molding compound, the metal column 402 and the conductive column 170 are etched. On the one hand, a preset height can be formed. On the other hand, the oxide layer on the surface of the metal column 402 and the conductive column 170 can be removed to expose the substrate, thereby reducing the contact resistance between the metal column 402 and the conductive column 170 and other device layers (such as the top redistribution layer 430).

[0041] See also Figure 1 and Fig.13 , step S13, forming a chip packaging component 400 on the top surface of the first plastic packaging layer 401 and the top surface of the bridge chip component 100, and the bridge chip component 100 is electrically connected to the chip packaging component 400.

[0042] In one embodiment, the chip package assembly 400 includes a top redistribution layer 430, a top pad 440, and a top device 450. The steps of forming the chip package assembly 400 on the top surface of the first plastic packaging layer 401 and the top surface of the bridge chip assembly 100 include:

[0043] A top redistribution layer 430 is formed on the top surface of the first plastic packaging layer 401 and the top surface of the bridge chip assembly 100. The top redistribution layer 430 includes a dielectric layer 431 and a plated wire 432 located in the dielectric layer 431, wherein the plated wire 432 is in contact with and connected to the conductive column 170 of the bridge chip assembly 100, wherein the plated wire 432 is formed by an electroplating process. In one embodiment, the top redistribution layer 430 can be formed by a photolithography process and an electroplating process, for example, by adding layers and stacking them through processes such as coating, exposure, development, electroplating, and degumming to form the top redistribution layer 430.

[0044] A top pad 440 is formed on a top surface of the top redistribution layer 430 , and the top pad 440 is electrically connected to the top redistribution layer 430 .

[0045] A top device 450 is disposed on the top redistribution layer 430, and the top device 450 is soldered to the top pad 440. In some embodiments, the top device 450 is flip-chip mounted on the top redistribution layer 430. The top device 450 is soldered to the top pad 440 via a conductive bump.

[0046] The top device 450 is encapsulated to form a second encapsulation layer 470, and the second encapsulation layer 470 covers the top device 450. In some embodiments, before encapsulating the top device 450, the method further includes filling a filling layer 460 between the bottom of the top device 450 and the top redistribution layer 430, and the second encapsulation layer 470 also covers the filling layer 460.

[0047] See also Figure 1 and Fig.14 Step S14, removing the carrier board 600 and the adhesive layer 140 of the bridge chip assembly 100, wherein the bottom surface of the bridge chip assembly 100 is higher than the bottom surface of the first plastic packaging layer 401. The bottom surface of the first plastic packaging layer 401, the bottom surface of the metal pillar 402, and the bottom surface of the bridge chip 110 are also exposed.

[0048] In this step, a suitable debonding process is selected according to the characteristics of the temporary bonding adhesive, such as laser debonding, thermal debonding, etc., to remove the carrier 600. After removing the carrier 600, the buffer metal layer 602 on the surface of the substrate is also removed by etching. In this step, a suitable etching process is selected according to the material characteristics and molecular system of the adhesion layer 140 to remove the adhesion layer 140 and expose the bottom pad 130 on the back of the bridge chip 110.

[0049] Optionally, in some embodiments, the bridge chip assembly 100 further includes a seed layer 150, the seed layer 150 covers the bottom surface of the protection layer 120 and the bottom surface of the through silicon via 112 of the bridge chip assembly 100, the bottom pad 130 is disposed on the seed layer 150, and the adhesion layer 140 also covers the bottom surface of the seed layer 150 (see Fig.17 ), after the step of removing the adhesion layer 140, it also includes: removing the seed layer 150 outside the bottom pad 130 area, so that the residual adhesion layer 140 can be completely removed, thereby improving the reliability of the packaging structure.

[0050] Optionally, after removing the carrier 600 , the adhesion layer 140 or the seed layer 150 , a cleaning process is further included to remove residues.

[0051] Optionally, in the step of removing the adhesion layer 140 and the seed layer 150, if a dry etching process is used, the bottom surface of the first plastic encapsulation layer 401 will be too rough. In this case, the formation method further includes: polishing the bottom surface of the first plastic encapsulation layer 401 to form a surface with a roughness that meets the requirements.

[0052] See also Figure 1 and Fig.15 , step S15, forming a bottom redistribution layer 410 on the bottom surface of the first plastic packaging layer 401 and the bottom surface of the bridge chip assembly 100, wherein the thickness of the bottom redistribution layer 410 located on the bottom surface of the bridge chip assembly 100 is greater than the thickness of the bottom redistribution layer 410 located on the bottom surface of the first plastic packaging layer 401, and the bridge chip assembly 100 is electrically connected to the bottom redistribution layer 410. The through silicon via 112 of the bridge chip 110 is electrically connected to the bottom redistribution layer 410.

[0053] In this step, the thickness of the bottom redistribution layer 410 located at the bottom surface of the bridge chip assembly 100 is greater than the thickness of the bottom redistribution layer 410 located at the bottom surface of the first plastic packaging layer 401. The bottom of the bridge chip assembly 100 has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip assembly 100 is guaranteed, and a higher stress buffer is provided for the bridge chip 110, thereby improving the reliability of the packaging structure.

[0054] In some embodiments, the step of forming a bottom redistribution layer 410 on the bottom surface of the first plastic encapsulation layer 401 and the bottom surface of the bridge chip assembly 100 further includes:

[0055] A dielectric layer 411 is formed on the bottom surface of the first plastic packaging layer 401 and the bottom surface of the bridge chip assembly 100 .

[0056] A through hole exposing the bottom pad 130 of the bottom surface of the bridge chip 110 is formed on the dielectric layer 411 by a single exposure or double exposure process. In some embodiments, if the surface of the bottom pad 130 is too far away from the bottom surface of the first plastic packaging layer 401, the through hole may not be able to fully expose the bottom pad 130 by using a single exposure process, and then a through hole exposing the bottom pad 130 of the bottom surface of the bridge chip 110 may be formed on the dielectric layer 411 by a double exposure process, so that the through hole can fully expose the bottom pad 130. In some embodiments, when the bottom pad 130 is not provided on the bottom surface of the through silicon via 112, the through hole exposing the bottom surface of the through silicon via 112 is formed on the dielectric layer 411 by a single exposure or double exposure process according to the distance from the bottom surface of the through silicon via 112 to the bottom surface of the first plastic packaging layer 401.

[0057] The through hole is sputtered and / or electroplated to form a plated bump 412, and the plated bump 412 is in contact with the bottom pad 130 of the bridge chip 110. In this step, the plated bump 412 is formed by sputtering and electroplating, and tin (Sn) welding is not required, which eliminates the aging problem of tin welding during the process, and there is no problem of voids and cracks in the welding point, which improves the reliability of the packaging structure, and the combination of sputtering and electroplating can take into account both efficiency and cost.

[0058] Optionally, after the step of forming the bottom redistribution layer 410 on the bottom surface of the first plastic packaging layer 401 and the bottom surface of the bridge chip assembly 100, the following step is further included: Fig.16 , a conductive connection structure 630 is formed on the bottom surface of the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 is formed on the bottom surface of the bottom redistribution layer 410. The conductive connection structure 630 is electrically connected to the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 includes but is not limited to a controlled collapse chip connection bump (C4).

[0059] Optionally, after or before forming the conductive connection structure 630, the second plastic encapsulation layer 470 is thinned to expose the top surface of the top device 450, which is useful for device heat dissipation. Optionally, after forming the conductive connection structure 630, singulation is performed to form a plurality of independent package structures, each of which may include a plurality of the bridge chip components 100 and a plurality of the top devices 450.

[0060] The method for forming a packaging structure provided by an embodiment of the present invention first forms a bridge chip component, wherein the silicon through hole of the bridge chip is exposed by first depositing a protective layer and then thinning the silicon through hole. In the thinning process, the protective layer can protect the substrate, and can prevent the metal ions (such as copper ions) generated by the thinning of the silicon through hole from migrating and diffusing into the substrate, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions; at the same time, when the bridge chip component is plastic-sealed, the bottom surface of the bridge chip component has an adhesion layer, and the adhesion layer is removed after plastic sealing, so that the bottom surface of the bridge chip component is higher than the bottom surface of the first plastic sealing layer. After the bottom redistribution layer is formed on the bottom surface of the first plastic sealing layer and the bottom surface of the bridge chip component, the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip component is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic sealing layer, that is, the bottom of the bridge chip component has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip component is guaranteed, and a higher stress buffer is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0061] Based on the same inventive concept, an embodiment of the present invention also provides a packaging structure formed by the above-mentioned forming method. Figure 2 to Figure 16 As shown, the packaging structure includes: a bridge chip component 100, the bridge chip component 100 includes a bridge chip 110 and a protective layer 120, the bridge chip 110 includes a substrate 111 and a silicon-through hole 112 penetrating the substrate 111; the protective layer 120 is arranged on the bottom surface of the substrate 111, and exposes the bottom surface of the silicon-through hole 112, wherein the bottom surface of the silicon-through hole 112 is flush with the bottom surface of the protective layer 120; a first plastic sealing layer 401, the first plastic sealing layer 401 covers the side of the bridge chip component 100, and the bottom surface of the bridge chip component 100 is higher than the first plastic sealing layer 401 bottom surface; a chip packaging component 400, which is arranged on the top surface of the first plastic packaging layer 401 and the top surface of the bridge chip component 100, and the bridge chip component 100 is electrically connected to the chip packaging component 400; a bottom redistribution layer 410, which is arranged on the bottom surface of the first plastic packaging layer 401 and the bottom surface of the bridge chip component 100, wherein the thickness of the bottom redistribution layer 410 located on the bottom surface of the bridge chip component 100 is greater than the thickness of the bottom redistribution layer 410 located on the bottom surface of the first plastic packaging layer 401, and the bridge chip component 100 is electrically connected to the bottom redistribution layer 410.

[0062] In the packaging structure provided by the embodiment of the present invention, the bottom surface of the silicon through hole 112 is flush with the bottom surface of the protective layer 120, wherein, when manufacturing the bridge chip component 100, the protective layer 120 is first formed, and then the bottom surface of the silicon through hole 112 is ground. During the grinding process, the protective layer 120 can protect the substrate 111, and can prevent the metal ions (such as copper ions) generated by grinding the silicon through hole 112 from migrating and diffusing into the substrate 111, thereby avoiding the reliability failure problem of the packaging structure caused by the migration and diffusion of metal ions. In addition, the thickness of the bottom rewiring layer located at the bottom surface of the bridge chip component is greater than the thickness of the bottom rewiring layer located at the bottom surface of the first plastic sealing layer, that is, the bottom of the bridge chip component has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip component is guaranteed, and a higher stress buffer is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0063] In one embodiment, the substrate 111 is a silicon substrate, the through silicon via 112 is a copper column, and the protective layer 120 is a single layer structure or a composite layer structure, and its material includes but is not limited to silicon nitride, silicon dioxide or nitride silicon dioxide.

[0064] In one embodiment, the bridge chip assembly 100 further includes a bottom pad 130, the bottom pad 130 is disposed on the bottom surface of the through silicon via 112 and is electrically connected to the through silicon via 112, and the bottom redistribution layer 410 is electrically connected to the bottom pad 130, that is, the through silicon via 112 is electrically connected to the bottom redistribution layer 410 through the bottom pad 130. In one embodiment, the bottom pad 130 is a micro pad (μPad). The bottom pad 130 is disposed on the bottom surface of the through silicon via 112, so that in the packaging structure using the bridge chip assembly 100, the thickness of the first plastic sealing layer 401 covering the bridge chip assembly 100 can be reduced, thereby reducing the warping of this part of the structure, which is more conducive to production and yield. In this embodiment, the cross-sectional area of ​​the bottom pad 130 is larger than the cross-sectional area of ​​the TSV 112 to ensure that the TSV 112 can all contact the bottom pad 130, thereby reducing contact resistance and further reducing the delay of the electrical signal.

[0065] In one embodiment, the bridge chip assembly 100 further includes a seed layer 150 disposed between the bottom pad 130 and the bottom surface of the through silicon via 112, and the bottom pad 130 is formed by electroplating on the surface of the seed layer 150. The seed layer 150 may be a copper layer or a titanium layer or a multi-layer metal layer. Figure 8As shown, the seed layer 150 is located in the area corresponding to the bottom pad 130 , and the bottom pad 130 is disposed on the seed layer 150 , that is, the seed layer 150 is not disposed in other areas of the protection layer 120 .

[0066] In one embodiment, a passivation layer 113 is further disposed on the side of the TSV 112 , and the passivation layer 113 is used to isolate the TSV 112 from the substrate 111 to prevent metal ions in the TSV from diffusing into the substrate 111 .

[0067] In one embodiment, the bridge chip assembly 100 further includes an internal redistribution layer 160 and a conductive column 170. The internal redistribution layer 160 is disposed on the top surface of the substrate 111 and is electrically connected to the top surface of the through silicon via 112. The conductive column 170 is disposed on the top surface of the internal redistribution layer 160 and is electrically connected to the internal redistribution layer 160. The chip packaging assembly 400 is electrically connected to the conductive column 170. The internal redistribution layer 160 includes a dielectric layer and a conductive circuit located in the dielectric layer, one side of the conductive circuit is electrically connected to the top surface of the through silicon via 112, and the other side is electrically connected to the conductive column 170. The conductive column 170 includes but is not limited to a copper column, and the dielectric layer may be a silicon dioxide layer or a silicon nitride layer.

[0068] In one embodiment, the bridge chip 110 further includes a deep trench capacitor (DTC) 180, which is disposed in the substrate 111. In some embodiments, the deep trench capacitor 180 extends from the top surface of the substrate 111 to the inside of the substrate 111, and the deep trench capacitor 180 is electrically connected to the internal redistribution layer 160.

[0069] In one embodiment, the bottom surface of the silicon through via 112 is electrically connected to other structural layers (such as the bottom redistribution layer 410) through the bottom pad 130, thereby reducing the thickness of the first plastic packaging layer 401 covering the bridge chip assembly 100, thereby reducing the warping of this part of the structure, which is more conducive to production and yield.

[0070] In some embodiments, the first plastic encapsulation layer 401 covers the side surface of the bridge chip assembly 100 , the surface of the internal redistribution layer 160 , and the side surface of the conductive pillar 170 .

[0071] In some embodiments, the packaging structure further includes a metal column 402, the metal column 402 penetrates the first plastic packaging layer 401, and the bottom surface of the metal column 402 is flush with the bottom surface of the first plastic packaging layer 401. In one embodiment, the top surface of the metal column 402 is flush with the top surface of the conductive column 170. The metal column 402 and the conductive column 170 can be made of the same material, for example, both are copper. The packaging structure may include a plurality of the bridge chip components 100 and a plurality of the metal columns 402, the metal columns 402 are distributed around the bridge chip components 100 and between two adjacent bridge chip components 100.

[0072] In some embodiments, the bottom redistribution layer 410 also covers the bottom surface of the metal column 402, the metal column 402 is electrically connected to the bottom redistribution layer 410, and the thickness of the bottom redistribution layer 410 located in the metal column 402 area is the same as the thickness of the bottom redistribution layer 410 located in the first plastic encapsulation layer 401 area.

[0073] In some embodiments, the bottom rewiring layer 410 includes a dielectric layer 411 and a plated bump 412 located in the dielectric layer 411, and the plated bump 412 is in contact with the bottom pad 130 of the bridge chip 110. The material of the dielectric layer 411 can be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI) to further relieve stress. The plated bump 412 refers to a bump formed by an electroplating process. In one embodiment, the plated bump 412 is formed on the surface of the bottom pad 130 by an electroplating process, without the need for tin (Sn) welding, eliminating the aging problem of tin welding during process processing, and there is no problem of voids (Void) and cracks (Crack) at the welding point, thereby improving the reliability of the packaging structure.

[0074] In some embodiments, the chip package assembly 400 includes a top redistribution layer 430 , a top pad 440 , a top device 450 , and a second plastic layer 470 .

[0075] The top redistribution layer 430 is arranged on the top surface of the first plastic encapsulation layer 401 and the top surface of the bridge chip assembly 100. The top redistribution layer 430 includes a dielectric layer 431 and a plated wire 432 located in the dielectric layer 431. The plated wire 432 is in contact with and connected to the conductive column 170 of the bridge chip assembly 100. In some embodiments, the top surface of the metal column 402 is in contact with and connected to the plated wire 432. In some embodiments, the material of the dielectric layer 431 can be a polymer material such as polystyrene butyrate (PBO) and polyimide (PI). The plated wire 432 refers to a wire formed by an electroplating process. In one embodiment, the plated wire 432 is formed on the surface of the through silicon via 112 and the metal column 402 by an electroplating process, and there is no need to use tin (Sn) welding, which eliminates the aging problem of tin welding during process processing, and there is no problem of voids and cracks in the welding points, thereby improving the reliability of the packaging structure.

[0076] The top pad 440 is disposed on the top surface of the top redistribution layer 430 and is electrically connected to the top redistribution layer 430. In one embodiment, the top pad 440 is a micro pad (μPad).

[0077] The top device 450 is disposed on the top redistribution layer 430 and is welded to the top pad 440. The top device 450 may be flip-chip disposed on the top redistribution layer 430 and is welded to the top pad 440. The top device 450 may be a SOC device or the like.

[0078] The second plastic encapsulation layer 470 covers the top device 450. In some embodiments, the package structure further includes a filling layer 460 filled between the bottom of the top device 450 and the top redistribution layer 430, and the filling layer 460 is used to protect the conductive structure of the top device 450 and the top pad 440. The second plastic encapsulation layer 470 covers the top device 450, the surface of the top redistribution layer 430, and the surface of the filling layer 460.

[0079] Optionally, the package structure further includes a conductive connection structure 630, and the conductive connection structure 630 is disposed on the bottom surface of the bottom redistribution layer 410. In some embodiments, the conductive connection structure 630 includes but is not limited to a controllably collapsed chip connection bump (C4).

[0080] The packaging structure provided by the embodiment of the present invention prevents the metal ions (such as copper ions) generated by grinding the silicon through vias 112 from migrating and diffusing into the substrate by setting the protective layer 120, thereby improving the reliability of the packaging structure. In the packaging structure provided by the embodiment of the present invention, the bridge chip adopts a positive installation method, the chip thickness is thinner, and the thickness of the first plastic sealing layer is thinner, so that the length of the silicon through vias and the metal columns is shorter, the electrical signal delay is smaller, and the restrictions on the size and aspect ratio of the bridge chip are smaller. At the same time, the thickness of the bottom rewiring layer located on the bottom surface of the bridge chip component is greater than the thickness of the bottom rewiring layer located on the bottom surface of the first plastic sealing layer, that is, the bottom of the bridge chip component has a thicker dielectric layer, so that the connection strength of each connection point of the bridge chip component is guaranteed, and a higher stress buffer is provided for the bridge chip, thereby improving the reliability of the packaging structure.

[0081] It should be noted that the terms "including" and "having" and their variations involved in the document of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged under appropriate circumstances. The term "one or more" depends at least in part on the context, and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe features, structures or combinations of features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0082] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a packaging structure, characterized in that: include: Forming a bridge chip assembly, the bridge chip assembly comprising: a bridge chip, a protective layer and an adhesive layer, the bridge chip comprising a substrate and a through silicon via penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through silicon via, wherein the bottom surface of the through silicon via is flush with the bottom surface of the protective layer by first depositing the protective layer and then thinning the through silicon via, and the adhesive layer covers the bottom surface of the protective layer and the bottom surface of the through silicon via; The bridge chip assembly is arranged on a top surface of a carrier board, wherein the adhesive layer is in contact with the top surface of the carrier board; Plastic encapsulation to form a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the side surface of the bridge chip component and the top surface of the carrier; a chip packaging component is formed on the top surface of the first plastic encapsulation layer and the top surface of the bridge chip component, and the bridge chip component is electrically connected to the chip packaging component; Removing the adhesive layer of the carrier board and the bridge chip assembly, wherein the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer; A bottom redistribution layer is formed on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic encapsulation layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

2. The method for forming a packaging structure according to claim 1, characterized in that: The steps of forming the bridge chip assembly include: Providing a device wafer, the device wafer comprising a bridge chip, the bridge chip comprising an initial substrate, an initial through silicon via extending from the top surface of the initial substrate to the inside of the initial substrate, the side and bottom surfaces of the initial through silicon via being covered with a passivation layer; Removing a portion of the initial substrate from the bottom surface of the initial substrate to form the substrate, wherein the initial through silicon vias protrude from the bottom surface of the substrate; forming a protective layer on the bottom surface of the substrate; Thinning the passivation layer and the initial through silicon via from the bottom surface of the initial through silicon via to form the through silicon via, so that the bottom surface of the through silicon via is flush with the bottom surface of the protection layer, and the side surface of the through silicon via is covered with the passivation layer; The adhesion layer is formed.

3. The method for forming a packaging structure according to claim 2, wherein: After the step of thinning the passivation layer and the initial through silicon via from the bottom surface of the initial through silicon via to form the through silicon via, the method further comprises: forming a bottom pad, wherein the bottom pad is disposed on the bottom surface of the through silicon via and is electrically connected to the through silicon via; In the step of forming the adhesion layer, the adhesion layer covers the surface of the bottom solder pad and the bottom surface of the protective layer; in the step of forming a bottom redistribution layer on the bottom surface of the first plastic encapsulation layer and the bottom surface of the bridge chip assembly, the silicon through hole is electrically connected to the bottom redistribution layer through the bottom solder pad.

4. The method for forming a packaging structure according to claim 3, characterized in that: The step of forming the bottom pad further includes: forming a seed layer on the bottom surface of the protection layer and the bottom surface of the through silicon via; and forming the bottom pad on the seed layer on the bottom surface of the through silicon via by using an electroplating process.

5. The method for forming a packaging structure according to claim 4, characterized in that: After the step of forming the bottom pad, the method further includes: removing the seed layer not covered by the bottom pad.

6. The method for forming a packaging structure according to claim 4, characterized in that: In the step of forming the adhesion layer, the adhesion layer covers the surface of the bottom pad and the bottom surface of the seed layer; After the step of removing the adhesion layer, the method further includes: removing the seed layer.

7. The method for forming a packaging structure according to claim 2, wherein: After the step of providing the device wafer, the step further includes: bonding the support substrate to the front side of the device wafer; after the step of forming the adhesion layer, the step further includes: debonding the support substrate and singulating the device wafer to form the bridge chip assembly.

8. The method for forming a packaging structure according to claim 7, characterized in that: The step of providing a device wafer further includes: forming an internal redistribution layer and a conductive column on the top surface of the initial substrate, wherein the internal redistribution layer is electrically connected to the top surface of the initial through silicon via, and the conductive column is disposed on the top surface of the internal redistribution layer and is electrically connected to the internal redistribution layer; The step of bonding the support substrate to the front side of the device wafer includes: bonding the support substrate to a side of the device wafer having the conductive pillars.

9. The method for forming a packaging structure according to claim 1, wherein: The step of arranging the bridge chip assembly on the top surface of a carrier board also includes: arranging a metal column on the top surface of the carrier board; and in the step of plastic encapsulation, the first plastic encapsulation layer also covers the side surface of the metal column.

10. The method for forming a packaging structure according to claim 1, wherein: The step of forming a chip packaging component on the top surface of the first plastic packaging layer and the top surface of the bridge chip component comprises: A top redistribution layer is formed on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, wherein the top redistribution layer includes a dielectric layer and an electroplated wire located in the dielectric layer, wherein the electroplated wire is electrically connected to the bridge chip assembly, wherein the electroplated wire is formed by an electroplating process; forming a top pad on a top surface of the top redistribution layer, wherein the top pad is electrically connected to the top redistribution layer; Disposing a top device on the top redistribution layer, wherein the top device is welded to the top pad; Plastic encapsulation is performed to form a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the top device.

11. The method for forming a packaging structure according to claim 1, wherein: The step of forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly comprises: forming a dielectric layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly; Forming a through hole exposing the bottom surface of the through silicon via or a bottom pad of the bottom surface of the through silicon via on the dielectric layer by a single exposure or a double exposure process; A plated bump is formed by sputtering and / or electroplating in the through hole, and the plated bump is in contact with and connected to the through silicon via or the bottom pad.

12. The method for forming a packaging structure according to claim 1, wherein: After the step of forming a bottom redistribution layer on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the method further includes: forming a conductive connection structure on the bottom surface of the bottom redistribution layer.

13. A packaging structure, characterized in that: include: A bridge chip assembly, the bridge chip assembly comprising a bridge chip and a protective layer, the bridge chip comprising a substrate and a through silicon via penetrating the substrate, the protective layer being arranged on the bottom surface of the substrate and exposing the bottom surface of the through silicon via, and the bottom surface of the through silicon via is flush with the bottom surface of the protective layer; A first plastic sealing layer, wherein the first plastic sealing layer covers the side surface of the bridge chip component, and the bottom surface of the bridge chip component is higher than the bottom surface of the first plastic sealing layer; A chip packaging component, arranged on the top surface of the first plastic packaging layer and the top surface of the bridge chip component, the bridge chip component is electrically connected to the chip packaging component; A bottom redistribution layer is arranged on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, wherein the thickness of the bottom redistribution layer located on the bottom surface of the bridge chip assembly is greater than the thickness of the bottom redistribution layer located on the bottom surface of the first plastic packaging layer, and the bridge chip assembly is electrically connected to the bottom redistribution layer.

14. The packaging structure according to claim 13, characterized in that: The bridge chip assembly further includes a bottom pad, which is disposed on the bottom surface of the through silicon via and electrically connected to the through silicon via, and the bottom redistribution layer is electrically connected to the bottom pad.

15. The packaging structure according to claim 14, characterized in that: The bridge chip assembly further includes a seed layer disposed between the bottom pad and a bottom surface of the through silicon via.

16. The packaging structure according to claim 13, characterized in that: A passivation layer is also provided on the side of the through silicon via.

17. The packaging structure according to claim 13, characterized in that: The bridge chip assembly also includes: An internal redistribution layer is disposed on the top surface of the substrate and is electrically connected to the top surface of the through silicon via; A conductive column is disposed on the top surface of the internal redistribution layer and is electrically connected to the internal redistribution layer. The chip packaging component is electrically connected to the conductive column.

18. The packaging structure according to claim 13, characterized in that: The bridge chip further includes a deep trench capacitor, which is disposed in the substrate.

19. The packaging structure according to claim 13, characterized in that: The bottom redistribution layer includes a dielectric layer and electroplated bumps located in the dielectric layer, and the electroplated bumps are in contact and connected with the bottom surface of the through silicon via or the bottom surface of the bottom pad.

20. The packaging structure according to claim 13, characterized in that: The chip packaging assembly comprises: A top redistribution layer is disposed on the top surface of the first plastic packaging layer and the top surface of the bridge chip assembly, the top redistribution layer includes a dielectric layer and electroplated wires located in the dielectric layer, and the electroplated wires are electrically connected to the bridge chip assembly; A top pad, disposed on the top redistribution layer and electrically connected to the top redistribution layer; A top device is disposed on the top redistribution layer, and the top device is welded to the top pad; The second plastic packaging layer covers the top device.

21. The packaging structure according to claim 13, characterized in that: The packaging structure further includes a metal column, which penetrates the first plastic packaging layer, and the bottom surface of the metal column is flush with the bottom surface of the first plastic packaging layer.

22. The packaging structure according to claim 13, characterized in that: The packaging structure further includes a conductive connection structure, which is disposed on the bottom surface of the bottom redistribution layer.

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