Semiconductor device and forming method thereof

Abstract

In an embodiment, a device includes: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die with a dielectric-to-dielectric bonding region and with a metal-to-metal bonding region; a first buffer layer around the upper integrated circuit die, the first buffer layer comprising a buffer material having a first thermal conductivity, the buffer material having a columnar crystal structure comprising crystal columns having a substantially uniform orientation in a direction extending away from the lower integrated circuit die; and a gap-fill dielectric over the first buffer layer and around the upper integrated circuit die, the gap-fill dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity. Some embodiments of the present application also relate to a semiconductor device and a method of forming the same.

Description

Technical Field

[0001] Some embodiments of the present application provide semiconductor devices and methods for forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, the demand for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a lower integrated circuit die; an upper integrated circuit die, bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding area and a metal-to-metal bonding area; a first buffer layer, located around the upper integrated circuit die, the first buffer layer including a buffer material having a first thermal conductivity, the buffer material having a columnar crystal structure, the columnar crystal structure including crystal columns having a substantially uniform orientation in a direction extending away from the lower integrated circuit die; and a gap-filling dielectric, located above the first buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a lower integrated circuit die; an upper integrated circuit die, bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding area and using a metal-to-metal bonding area; a buffer layer, located around the upper integrated circuit die, the buffer layer comprising a buffer material having a first thermal conductivity; a gap-filling dielectric, located above the buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity; a supporting substrate, located above the gap-filling dielectric and the upper integrated circuit die; and a heat dissipation layer, located above the supporting substrate, the heat dissipation layer comprising a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a die structure by the following steps: bonding an upper integrated circuit die to a lower integrated circuit die using a dielectric-to-dielectric bonding area and using a metal-to-metal bonding area; depositing a buffer material over the upper integrated circuit die and the lower integrated circuit die using a sputtering process, the buffer material having a first thermal conductivity and a first crystal structure; and depositing a gap-filling dielectric over the buffer material using a chemical deposition process, the gap-filling dielectric having a second thermal conductivity and a second crystal structure, the first thermal conductivity being greater than the second thermal conductivity, and the first crystal structure being different from the second crystal structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 It is a cross-sectional view of an integrated circuit die.

[0008] Figures 2 to 12 is a cross-sectional view of an intermediate stage in the fabrication of a die structure according to some embodiments.

[0009] Figures 13 to 15 is a cross-sectional view of an intermediate stage in the fabrication of a die structure according to some embodiments.

[0010] FIG. 16A to FIG. 16D is a cross-sectional view of a portion of a die structure according to various embodiments.

[0011] Fig.17 is a cross-sectional view of a die structure according to some other embodiments.

[0012] Fig.18 is a cross-sectional view of a die structure according to some other embodiments.

[0013] Fig.19 is a cross-sectional view of an integrated circuit package according to some embodiments.

[0014] Fig. 20 is a cross-sectional view of an integrated circuit package according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] According to various embodiments, the die structure includes a buffer layer for gap-filling dielectric. The buffer layer is formed of a material having a columnar crystal structure, which can increase the thermal conductivity of the buffer layer. Therefore, the thermal path for conducting heat out of the die structure can be improved. Optionally, the die structure can include a heat dissipation layer formed of a material having a large thermal conductivity and a high compressibility. The heat dissipation layer can help reduce the warping of the die structure. Reducing the warping of the die structure can improve the yield and / or performance of an integrated circuit package in which the die structure is subsequently packaged.

[0018] Figure 1 5 is a cross-sectional view of an integrated circuit die 50. The integrated circuit die 50 will be bonded to other dies in subsequent processing to form a die structure. The integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC) die, an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a bridge die (e.g., a local silicon interconnect (LSI) die), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof.

[0019] The integrated circuit die 50 can be formed in a wafer, which can include different device regions that can be segmented to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 can include a semiconductor substrate 52, which can be a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1 upward-facing surface) and non-active surfaces (e.g. Figure 1 Surfaces facing downward in the semiconductor substrate 52). Devices (not shown separately) may be formed in and / or on the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, inductors, resistors, etc.). The inactive surface may be free of devices.

[0020] The interconnect structure 54 is disposed above the active surface of the semiconductor substrate 52 and electrically connects the devices of the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. The dielectric layer may be, for example, a low-k dielectric layer. The metallization layer may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The metallization layer of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0021] Optionally, the conductive via 56 extends into the interconnect structure 54 and / or the semiconductor substrate 52. The conductive via 56 is electrically coupled to the metallization layer of the interconnect structure 54. As an example of forming the conductive via 56, a groove can be formed in the interconnect structure 54 and / or the semiconductor substrate 52 by, for example, etching, milling, laser technology, a combination thereof, etc. A thin barrier layer can be conformally deposited in the groove, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, etc. The barrier layer can be formed of an oxide, a nitride, a combination thereof, etc. A conductive material can be formed over the barrier layer and in the groove. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, etc. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, etc. Excess conductive material and the barrier layer are removed from the surface of the interconnect structure 54 or the semiconductor substrate 52 by, for example, chemical mechanical polishing (CMP). The remaining portion of the barrier layer and the conductive material located in the groove forms the conductive via 56. After its initial formation, the conductive via 56 may be buried in the semiconductor substrate 52. The semiconductor substrate 52 may be thinned in subsequent processing to expose the conductive via 56 at the inactive surface of the semiconductor substrate 52. After the exposure process, the conductive via 56 is a through substrate via (TSV) extending through the semiconductor substrate 52, such as a through silicon via.

[0022] The dielectric layer 62 is located above the interconnect structure 54 at the front side of the integrated circuit die 50. The dielectric layer 62 can be formed of: an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc.; a nitride such as silicon nitride, etc.; a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer, etc.; a combination thereof; etc. The dielectric layer 62 can be formed, for example, by CVD, spin coating, lamination, etc. Optionally, one or more passivation layers (not separately shown) are disposed between the dielectric layer 62 and the interconnect structure 54.

[0023] The die connector 64 extends through the dielectric layer 62. The die connector 64 may include conductive pillars, pads, etc. that may be made into external connections. In some embodiments, the die connector 64 includes a bonding pad at the front side of the integrated circuit die 50, and includes a bonding pad via that connects the bonding pad to the upper metallization layer of the interconnect structure 54. The die connector 64 (including the bonding pad and the bonding pad via) may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 64 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc., which may be formed, for example, by plating, etc.

[0024] Optionally, a chip probe (CP) test may be performed on the integrated circuit die 50. For example, a chip probe may be attached to a test pad (not separately shown). The CP test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only the integrated circuit die 50 (which is a KGD) undergoes subsequent processing and packaging, while dies that do not pass the chip probe test are not packaged.

[0025] Figures 2 to 12 is a tube core structure 100 according to some embodiments (see Fig.12 ). The die structure 100 is a cross-sectional view of an intermediate stage in the manufacture of an integrated circuit die 50 (including a first integrated circuit die 50A and a second integrated circuit die 50B). The die structure 100 is formed by bonding the integrated circuit dies 50 together in a device region 102D. The device region 102D is segmented to form the die structure 100. The processing of one device region 102D is shown, but it should be understood that any number of device regions 102D can be processed simultaneously to form any number of die structures 100.

[0026] The die structure 100 (see Fig.12 ) is a component that can be subsequently packaged to form an integrated circuit package. The integrated circuit die of the die structure 100 can be a heterogeneous die. Instead of individually packaged die, the packaged die structure 100 can allow heterogeneous dies to be integrated to have a small footprint. The die structure 100 can be an integrated system on chip (SoIC) device, but other types of devices can be formed.

[0027] exist Figure 2 102D, the first integrated circuit die 50A is attached to the carrier substrate 102 in a face-down manner so that the front side of the first integrated circuit die 50A is attached to the carrier substrate 102. The dielectric layer 62A of the first integrated circuit die 50A is attached to the carrier substrate 102. The first integrated circuit die 50A can be placed by, for example, a pick-and-place process. In the illustrated embodiment, two first integrated circuit dies 50A are placed in the device area 102D, but any desired number of first integrated circuit dies 50A can be placed in the device area 102D. The first integrated circuit die 50A can be a logic device, such as a CPU, a GPU, a SOC, a microcontroller, etc.

[0028] The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, such that a plurality of die structures may be formed on the carrier substrate 102 at the same time.

[0029] The first integrated circuit die 50A can be attached to the carrier substrate 102 by bonding the first integrated circuit die 50A to the carrier substrate 102 with a bonding layer 104. The bonding layer 104 is located on the front side of the first integrated circuit die 50A and on the surface of the carrier substrate 102. In some embodiments, the bonding layer 104 includes an oxide layer, such as a silicon oxide layer. In some embodiments, the bonding layer 104 includes an adhesive, such as a suitable epoxy, a die attach film (DAF), etc. The bonding layer 104 can include any desired number of oxide layers, adhesive films, etc. The bonding layer 104 can be applied to the front side of the first integrated circuit die 50A, can be applied above the surface of the carrier substrate 102, etc. For example, before being segmented to separate the first integrated circuit die 50A, the bonding layer 104 can be applied to the front side of the first integrated circuit die 50A.

[0030] exist Figure 3 In the embodiment of the present invention, a buffer layer 106 is deposited on the first integrated circuit die 50A. The buffer layer 106 is a liner layer on which the above gap filling dielectric will be formed. When the gap filling dielectric is subsequently formed, the buffer layer 106 can protect the first integrated circuit die 50A from damage. In addition, the buffer layer 106 is formed of a buffer material having a large thermal conductivity. Therefore, the buffer layer 106 protects the first integrated circuit die 50A and forms a thermal path to conduct heat from the first integrated circuit die 50A.

[0031] The buffer layer 106 is formed of a buffer material having a large thermal conductivity. In some embodiments, the buffer material of the buffer layer 106 has a thermal conductivity in the range of 2W / mK to 150W / mK. Acceptable buffer materials include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, gallium nitride, zinc oxide, combinations thereof, and the like. The buffer material can be formed by: a sputtering process, such as physical vapor deposition (PVD); a chemical deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like; a spraying process; and the like. The buffer material of the buffer layer 106 may have a polycrystalline structure. The buffer material of the buffer layer 106 has a heterogeneous microstructure, which can help the buffer material have a large thermal conductivity. Specifically, the buffer material has a columnar crystal structure. The columnar crystal structure includes crystal columns having a substantially uniform orientation in the same direction (such as a direction extending away from the carrier substrate 102). The crystal columns form a thermal path; therefore, the buffer layer 106 has an increased thermal conductivity along the direction in which the crystal columns extend compared to other directions in which the crystal columns do not extend. In addition, the columnar crystal structure helps the subsequently formed upper material to have a better crystal structure and provides good protection for the first integrated circuit die 50A. The buffer material can be formed to have a columnar crystal structure by depositing the buffer material using a sputtering process (such as PVD).

[0032] A gap-fill dielectric 108 is formed on the buffer layer 106. The gap-fill dielectric 108 and the buffer layer 106 are located around and between the first integrated circuit die 50A in the device region 102D. Initially, the gap-fill dielectric 108 and the buffer layer 106 may bury or cover the first integrated circuit die 50A such that top surfaces of the gap-fill dielectric 108 and the buffer layer 106 are located above the top surface of the first integrated circuit die 50A.

[0033] The gap filling dielectric 108 is formed of a dielectric material having a low k value (or relative dielectric constant), thereby providing good electrical insulation. The k value of the gap filling dielectric 108 may be greater than the k value of the buffer layer 106. The gap filling dielectric 108 may have a thermal conductivity of at least 5W / mK. In some embodiments, the gap filling dielectric 108 has a thermal conductivity in the range of 5W / mK to 300W / mK. Acceptable gap filling dielectric materials include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, zinc oxide, boron nitride, beryllium oxide, combinations thereof, and the like. Other gap filling materials such as gallium nitride may be utilized. The material of the gap filling dielectric 108 may have a thermal conductivity greater than other dielectric materials such as silicon oxide. The thermal conductivity of the buffer layer 106 is greater than the thermal conductivity of the gap filling dielectric 108. The gap-filling dielectric 108 may be formed by: a sputtering process, such as physical vapor deposition (PVD); a chemical deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.; a spraying process; etc. The gap-filling dielectric 108 may have a polycrystalline structure. The gap-filling dielectric 108 has a microstructure different from that of the buffer material of the buffer layer 106. Specifically, the gap-filling dielectric 108 has a non-columnar crystal structure. The non-columnar crystal structure includes grains with varying orientations (also referred to as non-uniform orientations or random orientations), which are not arranged in columns. The gap-filling dielectric 108 may be formed to have a non-columnar crystal structure by depositing the gap-filling dielectric 108 with a spraying process or with a chemical deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.).

[0034] exist Figure 4 In the process, a removal process is performed to make the top surface of the gap-fill dielectric 108 and the buffer layer 106 flush with the non-active surface of the first integrated circuit die 50A. In some embodiments, a planarization process is utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the planarization process, the gap-fill dielectric 108, the buffer layer 106, and the surface of the first integrated circuit die 50A (including the semiconductor substrate 52A) are substantially coplanar (within process variations). The conductive via 56A of the first integrated circuit die 50A can remain buried by the semiconductor substrate 52A after the removal process.

[0035] exist Figure 5 5. In the embodiment of the present invention, the semiconductor substrate 52A is thinned to expose the conductive via 56A. Portions of the gap filling dielectric 108 and the buffer layer 106 may also be removed by a thinning process. The thinning process may be, for example, a grinding process, a chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc., and the thinning process is implemented at the back side of the first integrated circuit die 50A. Then, the semiconductor substrate 52A is recessed to expose portions of the sidewalls of the conductive via 56A. The recessing may be implemented by an etching process, such as dry etching, wet etching, or a combination thereof. After the recessing, the conductive via 56A protrudes from the non-active surface of the semiconductor substrate 52A.

[0036] A bonding layer 112 is then formed on the back side of the gap-filling dielectric 108, the buffer layer 106, and the first integrated circuit die 50A. The bonding layer 112 is located around a portion of the sidewall of the conductive via 56A of the first integrated circuit die 50A. The bonding layer 112 can bury or cover the conductive via 56A so that the top surface of the bonding layer 112 is located above the surface of the conductive via 56A and the semiconductor substrate 52A. The bonding layer 112 will be used for subsequent bonding processes and can help to electrically isolate the conductive vias 56A from each other, thus avoiding short circuits. The bonding layer 112 is formed of a dielectric material. The dielectric material can be an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, etc., which can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0037] exist Figure 6 In the embodiment of the present invention, a die connector 114 is formed in the bonding layer 112. The die connector 114 is connected to the conductive via 56A. The die connector 114 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 114 can be formed of a conductive material, such as a metal, such as copper, aluminum, etc., which can be formed by, for example, plating, etc. In some embodiments, a planarization process is performed on the die connector 114 and the bonding layer 112, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the planarization process, the surfaces of the die connector 114 and the bonding layer 112 are substantially coplanar (within process variations).

[0038] exist Figure 7, the second integrated circuit die 50B is attached to the first integrated circuit die 50A via the bonding layer 112 and the die connector 114 so that the front side of the second integrated circuit die 50B faces the back side of the first integrated circuit die 50A. In the illustrated embodiment, one second integrated circuit die 50B is attached to each first integrated circuit die 50A, but any desired number of second integrated circuit dies 50B can be attached to each first integrated circuit die 50A. The second integrated circuit die 50B can be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The second integrated circuit die 50B can be a logic device, such as a CPU, a GPU, a SOC, a microcontroller, etc.

[0039] The second integrated circuit die 50B can be attached to the bonding layer 112 and the die connector 114 by placing the second integrated circuit die 50B on the bonding layer 112 and the die connector 114; and then bonding the second integrated circuit die 50B to the first integrated circuit die 50A via the bonding layer 112 and the die connector 114. The second integrated circuit die 50B can be placed by, for example, a pick-and-place process. As an example of a bonding process, the second integrated circuit die 50B can be bonded to the bonding layer 112 and the die connector 114 by hybrid bonding. The dielectric layer 62B of the second integrated circuit die 50B is directly bonded to the bonding layer 112 by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film). The die connector 64B of the second integrated circuit die 50B is directly bonded to the die connector 114 by metal-to-metal bonding without using any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the second integrated circuit die 50B against the bonding layer 112. The pre-bonding is performed at a low temperature, such as about room temperature, and after the pre-bonding, the dielectric layer 62B is bonded to the bonding layer 112. The bond strength is then improved in a subsequent annealing step, in which the bonding layer 112, the die connector 114, the dielectric layer 62B, and the die connector 64B are annealed. Thus, a dielectric to dielectric bond, such as a fusion bond, is formed, thereby bonding the bonding layer 112 to the dielectric layer 62B. For example, the bond can be a covalent bond between the material of the bonding layer 112 and the material of the dielectric layer 62B. The die connector 114 can be connected to the die connector 64B in a one-to-one correspondence. The die connector 114 and the die connector 64B can be in physical contact after the pre-bonding, or can be extended to make physical contact during the annealing. Furthermore, during the annealing, the materials (eg, copper) of the die connector 114 and the die connector 64B mix so that a metal-to-metal bond is also formed. Thus, the resulting bond includes a dielectric-to-dielectric bonding region and a metal-to-metal bonding region.

[0040] In this embodiment, the second integrated circuit die 50B does not include the conductive vias 56 (previously described with reference to FIG. Figure 1 1 ). The die structure 100 will include two layers of the integrated circuit die 50, and the conductive vias 56 are excluded from the second integrated circuit die 50B because the second integrated circuit die 50B is an upper layer of the integrated circuit die 50 in the die structure 100. In other embodiments, the die structure 100 includes more than two layers of the integrated circuit die 50, such as three layers of the integrated circuit die 50, and the conductive vias 56 can be formed in other layers of the integrated circuit die 50 in addition to the upper layer of the integrated circuit die 50.

[0041] exist Figure 8In the embodiment of the present invention, a buffer layer 116 is deposited on the second integrated circuit die 50B. The buffer layer 116 is a liner layer on which the above gap filling dielectric will be formed. When the gap filling dielectric is subsequently formed, the buffer layer 116 can protect the second integrated circuit die 50B from damage. In addition, the buffer layer 116 is formed of a buffer material having a large thermal conductivity. Therefore, the buffer layer 116 protects the second integrated circuit die 50B and forms a thermal path to conduct heat from the second integrated circuit die 50B.

[0042] The buffer layer 116 may be formed of one of the candidate materials of the buffer layer 106, which may be formed by one of the candidate methods of forming the buffer layer 106. The buffer layer 116 may be formed of the same material as the buffer layer 106, or may include a material different from the buffer layer 106. The material of the buffer layer 116 has a columnar crystal structure. The columnar crystal structure includes crystal columns having a substantially uniform orientation in the same direction (such as a direction extending away from the carrier substrate 102). The crystal columns form a thermal path; therefore, the buffer layer 116 has an increased thermal conductivity along the direction in which the crystal columns extend compared to other directions in which the crystal columns do not extend.

[0043] A gap-fill dielectric 118 is formed on the buffer layer 116. The gap-fill dielectric 118 and the buffer layer 116 are located around and between the second integrated circuit die 50B in the device region 102D. Initially, the gap-fill dielectric 118 and the buffer layer 116 may bury or cover the second integrated circuit die 50B so that the top surfaces of the gap-fill dielectric 118 and the buffer layer 116 are located above the top surface of the second integrated circuit die 50B. The gap-fill dielectric 118 has a different microstructure than the buffer material of the buffer layer 116.

[0044] The gap-fill dielectric 118 may be formed of one of the candidate materials of the gap-fill dielectric 108, which may be formed by one of the candidate methods of forming the gap-fill dielectric 108. The gap-fill dielectric 118 may be formed of the same material as the gap-fill dielectric 108, or may include a different material than the gap-fill dielectric 108. The thermal conductivity of the material of the buffer layer 116 is greater than the thermal conductivity of the gap-fill dielectric 118.

[0045] exist Fig. 9 In the embodiment of the present invention, a removal process is performed to make the top surfaces of the gap-fill dielectric 118 and the buffer layer 116 flush with the non-active surface of the second integrated circuit die 50B. In some embodiments, a planarization process is utilized, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the planarization process, the gap-fill dielectric 118, the buffer layer 116, and the surface of the second integrated circuit die 50B (including the semiconductor substrate 52B) are substantially coplanar (within process variations).

[0046] exist Fig.10 , a support substrate 124 is attached to the gap-fill dielectric 118, the buffer layer 116, and the second integrated circuit die 50B. The support substrate may be a glass support substrate, a ceramic support substrate, a semiconductor substrate (e.g., a silicon substrate), a wafer (e.g., a silicon wafer), etc. The support substrate 124 may provide structural support during subsequent processing steps and in the completed device. The support substrate 124 may be substantially free of any active or passive devices.

[0047] The support substrate 124 may be attached to the gap-fill dielectric 118, the buffer layer 116, and the second integrated circuit die 50B by bonding the support substrate 124 to the gap-fill dielectric 118, the buffer layer 116, and the second integrated circuit die 50B with a bonding layer 122. The bonding layer 122 is located on the surface of the support substrate 124, the gap-fill dielectric 118, the buffer layer 116, and the second integrated circuit die 50B. The bonding layer 122 may be formed of one of the candidate materials of the bonding layer 104, which may be formed by one of the candidate methods of forming the bonding layer 104. The bonding layer 122 may be formed of the same material as the bonding layer 104, or may include a different material than the bonding layer 104.

[0048] A buffer layer 126 is deposited on the support substrate 124. In this embodiment, the buffer layer 126 physically contacts the support substrate 124. The buffer layer 126 is a liner layer on which the upper heat dissipation layer will be formed. The buffer layer 126 is formed of a buffer material having a large thermal conductivity. Therefore, the buffer layer 126 forms a thermal path to conduct heat from the support substrate 124.

[0049] The buffer layer 126 may be formed of one of the candidate materials of the buffer layer 106, and may be formed by one of the candidate methods of forming the buffer layer 106. The buffer layer 126 may be formed of the same material as the buffer layer 106, or may include a material different from the buffer layer 106. The material of the buffer layer 126 has a columnar crystal structure.

[0050] A heat dissipation layer 128 is formed on the buffer layer 126. The heat dissipation layer 128 is a warpage control layer. The heat dissipation layer 128 is formed of a highly compressible heat dissipation material and has a high thermal conductivity. The heat dissipation layer 128 can apply a compressive strain on the support substrate 124. When the first integrated circuit die 50A and the second integrated circuit die 50B are both logic devices, they may be large, which may increase the risk of warpage of the die structure 100. Specifically, the second integrated circuit die 50B can apply a compressive strain on the support substrate 124. The heat dissipation layer 128 and the integrated circuit die 50B apply their respective compressive strains to the opposite sides of the support substrate 124. The compressive strain applied by the heat dissipation layer 128 on the support substrate 124 is opposite to the compressive strain applied by the second integrated circuit die 50B on the support substrate 124 (and therefore cancels out), thereby reducing the warpage of the die structure 100. Reducing the warpage of the die structure 100 can reduce the risk of forming a cold solder joint and / or increase the flatness of the top surface for matching the heat sink. Thus, the yield and / or performance of an integrated circuit package in which the die structure 100 is subsequently packaged may be improved.

[0051] The heat dissipation layer 128 is formed of a heat dissipation material having a large stiffness. In some embodiments, the heat dissipation material of the heat dissipation layer 128 has a stiffness in the range of 150 GPa to 500 GPa, such as about 300 GPa. The heat dissipation layer 128 is formed of a heat dissipation material having a large thermal conductivity, such as a thermal conductivity of at least 50 W / mK, such as a thermal conductivity of at least 150 W / mK. In some embodiments, the heat dissipation material of the heat dissipation layer 128 has a thermal conductivity in the range of 150 W / mK to 300 W / mK. Acceptable heat dissipation materials include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, gallium nitride, zinc oxide, combinations thereof, and the like. The heat dissipation material can be formed by: a sputtering process, such as physical vapor deposition (PVD); a chemical deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like; a spraying process; and the like. The heat dissipation material can be a non-conductive material, such as a porous dielectric material or a semiconductor material. The thermal conductivity of the heat dissipation layer 128 is greater than the thermal conductivity of the buffer layers 106, 116, and 126. The heat dissipation material of the heat dissipation layer 128 may have a polycrystalline structure. The heat dissipation material of the heat dissipation layer 128 has a microstructure different from that of the buffer materials of the buffer layers 106, 116, and 126. Specifically, the heat dissipation material has a non-columnar crystal structure. The non-columnar crystal structure includes grains with varying orientations (also referred to as non-uniform orientations or random orientations). The heat dissipation material may be formed to have a non-columnar crystal structure by depositing the heat dissipation material using a spraying process or using a chemical deposition process (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.).

[0052] The buffer layers 106, 116, 126; the gap-filling dielectrics 108, 118; and the heat dissipation layer 128 may be formed of the same material. For example, they may each be formed of aluminum nitride. The buffer material of the buffer layers 106, 116, 126 may have a first crystal structure (e.g., a columnar crystal structure), while the heat dissipation material of the gap-filling dielectrics 108, 118 and the heat dissipation layer 128 may each have a second crystal structure different from the first crystal structure (e.g., a non-columnar crystal structure). In addition, the method of forming the buffer layers 106, 116, 126 may be different from the method of forming the gap-filling dielectrics 108, 118 and the heat dissipation layer 128. The buffer layers 106, 116, 126 may be formed by a sputtering process, while the gap-filling dielectrics 108, 118 and the heat dissipation layer 128 may each be formed by a spraying process or a chemical deposition process. In some embodiments, the buffer material of the buffer layers 106, 116, 126 is formed of aluminum nitride having a columnar crystal structure by PVD, while the heat dissipation material of the gap-fill dielectrics 108, 118 and the heat dissipation layer 128 is formed of aluminum nitride having a non-columnar crystal structure by a spraying process.

[0053] Optionally, a protective layer 130 may be formed on the heat dissipation layer 128. The protective layer 130 protects the components below. The protective layer 130 is formed of a protective material having a large hardness. The hardness of the protective material may be greater than the hardness of the first integrated circuit die 50A and the second integrated circuit die 50B. In some embodiments, the protective material of the protective layer 130 has a hardness in the range of 5GPa to 50GPa, such as at least 8GPa. The protective material may have a thermal conductivity of at least 100W / mK. In some embodiments, the protective material of the protective layer 130 has a thermal conductivity in the range of 2W / mK to 150W / mK. Acceptable protective materials include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, aluminum nitride, gallium nitride, zinc oxide, combinations thereof, and the like. The protective material may be formed by: a sputtering process, such as physical vapor deposition (PVD); a chemical deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.; a spraying process; etc.

[0054] exist Fig.11 In some embodiments, carrier substrate stripping is performed to separate (or "strip") the carrier substrate 102 from the first integrated circuit die 50A. Thus, the buffer layer 106 and the front side of the first integrated circuit die 50A may be exposed. In some embodiments where the bonding layer 104 includes an oxide layer, stripping includes applying a removal process (such as a grinding process) to the carrier substrate 102 and the bonding layer 104. The structure is then flipped over and placed on a tape (not separately shown).

[0055] Then, a redistribution structure 140 is formed on the active surface of the first integrated circuit die 50A and on the bottom surface of the buffer layer 106. The redistribution structure 140 includes a dielectric layer 142 and a metallization layer 144 (sometimes referred to as a redistribution layer or a redistribution line) between the dielectric layers 142. For example, the redistribution structure 140 may include a plurality of metallization layers 144 separated from each other by respective dielectric layers 142. The metallization layers 144 of the redistribution structure 140 may be electrically coupled to the die connector 64A of the first integrated circuit die 50A.

[0056] In some embodiments, dielectric layer 142 is formed of a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB-based polymer, etc. In other embodiments, dielectric layer 142 is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, PSG; etc. Dielectric layer 142 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After forming each dielectric layer 142, dielectric layer 142 is then patterned to form openings that expose underlying conductive features, such as portions of underlying die connector 64A or metallization layer 144. Patterning may be implemented by an acceptable process, such as by exposing the dielectric layer to light when dielectric layer 142 is a photosensitive material, or by etching using, for example, anisotropic etching. If dielectric layer 142 is a photosensitive material, dielectric layer 142 may be developed after exposure.

[0057] The metallization layer 144 includes a conductive via and a conductor. The conductive via extends through the corresponding dielectric layer 142, and the conductor extends along the corresponding dielectric layer 142. As an example of forming the metallization layer 144, a seed layer (not shown separately) is formed above the corresponding underlying conductive component (e.g., the underlying die connector 64A or a portion of the metallization layer 144). For example, the seed layer can be formed on the corresponding dielectric layer 142 and in an opening through the corresponding dielectric layer 142. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using a deposition process, such as PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from the seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc. or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a metallization layer 144 for the redistribution structure 140.

[0058] The redistribution structure 140 is shown as an example. More or fewer dielectric layers 142 and metallization layers 144 than shown may be formed in the redistribution structure 140 by performing the previously described steps a desired number of times.

[0059] exist Fig.12 In the embodiment shown, a separation process is performed along the scribe line area, for example, between the device area 102D and the adjacent device area (not shown separately). The separation process may include a sawing process, a laser cutting process, etc. The separation process separates the device area 102D from the adjacent device area. The resulting, separated die structure 100 is from the device area 102D. The die structure 100 includes multiple layers of the integrated circuit die 50. In the illustrated embodiment, the die structure 100 includes a first layer T1 of the first integrated circuit die 50A and a second layer T2 of the second integrated circuit die 50B, but any number of layers of the integrated circuit die 50 may be included in the die structure 100.

[0060] Optionally, additional features for attaching the die structure 100 to a package component may be formed. In some embodiments, an under bump metallization (UBM) 146 is formed for external connection to the redistribution structure 140. In addition, a conductive connector 148 may be formed on the UBM 146. The conductive connector 148 may be used to connect the UBM 146 to a package component, such as an interposer, a package substrate, etc.

[0061] The UBM 146 may be formed to pass through the lower dielectric layer 142 of the redistribution structure 140. The UBM 146 has a bump portion located on and extending along a major surface of the lower dielectric layer 142, and has a via portion extending through the lower dielectric layer 142 to physically and electrically couple the lower metallization layer 144 of the redistribution structure 140. Thus, the UBM 146 is electrically coupled to the integrated circuit die 50. The UBM 146 may be formed of the same material as the metallization layer 144. In some embodiments, the UBM 146 has a different size than the metallization layer 144.

[0062] Conductive connector 148 can be formed on UBM 146. Conductive connector 148 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. Conductive connector 148 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, conductive connector 148 is formed by initially forming a reflowable material layer (e.g., solder) by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 148 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, which may be formed by a plating process.

[0063] Figures 13 to 15 is a cross-sectional view of an intermediate stage in the manufacture of a die structure 100 according to some other embodiments. Figures 2 to 12 The embodiment of the present invention is different in that the removal process for the gap filling dielectric 118 and the buffer layer 116 is omitted (previously for Fig. 9 1. As described above, the gap-fill dielectric 118 and the top surface of the buffer layer 116 are disposed above the inactive surface of the second integrated circuit die 50B. In addition, the support substrate 124 is omitted.

[0064] exist Fig.13 and from Figure 8 Starting with the step of depositing a buffer layer 126 on the gap filling dielectric 118. In this embodiment, the buffer layer 126 physically contacts the gap filling dielectric 118. The buffer layer 126 can be deposited in the same manner as described above for Fig.10 Formed in a similar manner as described.

[0065] exist Fig.14 In the embodiment, a heat dissipation layer 128 is formed on the buffer layer 126. The heat dissipation layer 128 can be formed in the same manner as previously described. Fig.10 Optionally, a protective layer 130 may be formed on the heat dissipation layer 128. The protective layer 130 may be formed in the same manner as previously described. Fig.10 Formed in a similar manner as described.

[0066] exist Fig.15 In the embodiment, appropriate steps as previously described are performed to complete the fabrication of the die structure 100. Because the die structure 100 is carrier-less in this embodiment, it can be thinner than a die structure 100 including a support substrate 124.

[0067] FIG. 16A to FIG. 16D 1 are cross-sectional views of portions of a die structure 100 according to various embodiments. These are simplified views of the layout of an integrated circuit die 50 for the die structure 100. For clarity of illustration, some components of the die structure 100 are omitted. In these embodiments, the die structure 100 may include a first layer of a first integrated circuit die 50A, a second layer of a second integrated circuit die 50B, and (optionally) a third layer of a third integrated circuit die 50C. The die structure 100 may be carrierless or may include a supporting substrate.

[0068] In some embodiments, Fig.16A As shown in , the front side of a single first integrated circuit die 50A is bonded to the front sides of a plurality of second integrated circuit dies 50B. Fig. 16B As shown in , the front side of a single first integrated circuit die 50A is bonded to the back side of a plurality of second integrated circuit dies 50B. Fig. 16C As shown in , the front side of a single first integrated circuit die 50A is bonded to the front sides of a plurality of second integrated circuit dies 50B, and the back sides of the second integrated circuit dies 50B are bonded to the front sides of corresponding third integrated circuit dies 50C. Fig.16D As shown in FIG. 5 , the front side of a single first integrated circuit die 50A is bonded to the front side of a single second integrated circuit die 50B, while the back side of the second integrated circuit die 50B is bonded to the front sides of a plurality of third integrated circuit dies 50C.

[0069] In these embodiments, the outer sidewalls of the integrated circuit dies 50 in different layers are aligned with each other. In other embodiments (not separately shown), the outer sidewalls of the integrated circuit dies 50 in different layers are offset relative to each other. For example, the outer sidewall of the second integrated circuit die 50B can be located within the area of ​​the first integrated circuit die 50A.

[0070] Fig.17 is a cross-sectional view of a die structure 100 according to some other embodiments. Fig.12 The embodiment of the present invention is different in that the die structure 100 includes only one first integrated circuit die 50A, and the first integrated circuit die 50A is laterally coterminal with the gap fill dielectric 118. In addition, the gap fill dielectric 108 and the buffer layer 106 are omitted. In addition, the front side of the second integrated circuit die 50B faces the front side of the first integrated circuit die 50A. The redistribution structure 140 is formed on the non-active surface of the first integrated circuit die 50A. The metallization layer 144 is electrically coupled to the conductive via 56A of the first integrated circuit die 50A.

[0071] The second integrated circuit die 50B may be bonded to the first integrated circuit die 50A by hybrid bonding. The dielectric layer 62B of the second integrated circuit die 50B is directly bonded to the dielectric layer 62A of the first integrated circuit die 50A by dielectric-to-dielectric bonding without using any adhesive material (e.g., die attach film). The die connector 64B of the second integrated circuit die 50B is directly bonded to the die connector 64A of the first integrated circuit die 50A by metal-to-metal bonding without using any eutectic material (e.g., solder).

[0072] Fig.18 is a cross-sectional view of a die structure 100 according to some other embodiments. Fig.15 1, except that the die structure 100 includes only one first integrated circuit die 50A, and the first integrated circuit die 50A laterally coterminates with the gap fill dielectric 118. In addition, the gap fill dielectric 108 and the buffer layer 106 are omitted. In addition, the front side of the second integrated circuit die 50B faces the front side of the first integrated circuit die 50A. The redistribution structure 140 is formed on the non-active surface of the first integrated circuit die 50A. The second integrated circuit die 50B can be formed in the same manner as previously described for Fig.17 A similar manner as described is used to bond to the first integrated circuit die 50A by hybrid bonding.

[0073] The previously described die structure 100 is an assembly that can be subsequently implemented in an integrated circuit package. The integrated circuit die 50 of the die structure 100 can be a heterogeneous die. Instead of or in addition to individually packaged integrated circuit dies, the packaged die structure 100 can allow heterogeneous dies to be integrated into a small footprint. In some embodiments (such as for subsequent implementations of Fig.19 ), an integrated circuit package is formed by attaching the die structure 100 to a wiring structure. In some embodiments (such as subsequently for Fig. 20 As described above, an integrated circuit package is formed by encapsulating the die structure 100 and forming redistribution lines on the encapsulant to fan out connections from the die structure 100.

[0074] Fig.19 2 is a cross-sectional view of an integrated circuit package 200 according to some embodiments. The integrated circuit package 200 includes a die structure 100 (including a first die structure 100A and a second die structure 100B) attached to a wiring structure 202. In the integrated circuit package 200, the die structure 100 includes a conductive connector 148. The first die structure 100A may be different from the second die structure 100B. For example, the first die structure 100A may be a memory device, and the second die structure 100B may be a logic device. The wiring structure 202 may be an interposer, a redistribution structure, etc. In the illustrated embodiment, the die structure 100 is attached to the wiring structure 202 with a conductive connector 148. The conductive connector 148 may be reflowed to attach the UBM of the die structure 100 to the die connector of the wiring structure 202. An underfill (not shown separately) may be formed around the conductive connector 148 and between the wiring structure 202 and the die structure 100. After the die structure 100 is attached to the wiring structure 202, an encapsulant 204 is formed on and around the various components. The encapsulant 204 seals the die structure 100. Subsequently, the wiring structure 202 may be attached to a package substrate 206.

[0075] Fig. 202 is a cross-sectional view of an integrated circuit package 200 according to some embodiments. The integrated circuit package 200 includes a die structure 100 (including a first die structure 100A and a second die structure 100B) sealed in an encapsulant 204. In the integrated circuit package 200, the conductive connector 148 is omitted from the die structure 100. The first die structure 100A may be different from the second die structure 100B. For example, the first die structure 100A may be a memory device, and the second die structure 100B may be a logic device. After the die structure 100 is sealed in the encapsulant 204, a wiring structure 202 is formed on the die structure 100 and / or the encapsulant 204. The wiring structure 202 may be a redistribution structure including redistribution lines established on the die structure 100 and / or the encapsulant 204. The redistribution lines of the wiring structure 202 are connected to the die structure 100 and fan out electrical connections from the die structure 100. Subsequently, the wiring structure 202 may be attached to the package substrate 206 .

[0076] Optionally, the integrated circuit package 200 may further include a through-hole 208 adjacent to the die structure 100. The through-hole 208 extends through the encapsulant 204. The redistribution line of the wiring structure 202 is connected to the through-hole 208. In addition, the integrated circuit package 200 may include a stacked integrated circuit device 210. The stacked integrated circuit device 210 may be a die structure, a separate die, etc. The stacked integrated circuit device 210 may be connected to the through-hole 208, and thus connected to the wiring structure 202.

[0077] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0078] Embodiments can achieve advantages. Forming the buffer layers 106, 116, 126 from a material having a columnar crystal structure can help them have a large thermal conductivity. Therefore, the thermal path for conducting heat from the integrated circuit die 50 can be improved. In addition, the protective layer 130 having a greater hardness than the integrated circuit die 50 can provide good protection for the integrated circuit die 50. Therefore, the reliability of the die structure 100 can be improved. In addition, including a heat dissipation layer 128 in the die structure 100 can help reduce the warping of the die structure 100. Reducing the warping of the die structure 100 can improve the yield and / or performance of the integrated circuit package in which the die structure 100 is subsequently packaged.

[0079] In an embodiment, the device includes: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding region and a metal-to-metal bonding region; a first buffer layer located around the upper integrated circuit die, the first buffer layer including a buffer material having a first thermal conductivity, the buffer material having a columnar crystal structure, the columnar crystal structure including crystal columns having a substantially uniform orientation in a direction extending away from the lower integrated circuit die; and a gap-filling dielectric located above the first buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity. In some embodiments, the device also includes: a supporting substrate located above the gap-filling dielectric and the upper integrated circuit die, the upper integrated circuit die applying a compressive strain on the supporting substrate; and a heat dissipation layer located above the supporting substrate, the heat dissipation layer applying a compressive strain on the supporting substrate, the heat dissipation layer including a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity, the heat dissipation material having a non-columnar crystal structure, the non-columnar crystal structure including grains having varying orientations. In some embodiments, the device further comprises: a second buffer layer located above the gap filling dielectric, the second buffer layer comprising a buffer material; and a heat dissipation layer located above the second buffer layer, the heat dissipation layer comprising a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity, the heat dissipation material having a non-columnar crystal structure, the non-columnar crystal structure comprising grains having a varying orientation. In some embodiments of the device, the gap filling dielectric has a non-columnar crystal structure, the non-columnar crystal structure comprising grains having a varying orientation. In some embodiments of the device, the gap filling dielectric is aluminum nitride, and the buffer material is aluminum nitride. In some embodiments of the device, the top surface of the gap filling dielectric is coplanar with the top surface of the upper integrated circuit die. In some embodiments of the device, the top surface of the gap filling dielectric is disposed above the top surface of the upper integrated circuit die.

[0080] In an embodiment, a device includes: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding region and using a metal-to-metal bonding region; a buffer layer located around the upper integrated circuit die, the buffer layer including a buffer material having a first thermal conductivity; a gap-filling dielectric located above the buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity; a supporting substrate located above the gap-filling dielectric and the upper integrated circuit die; and a heat dissipation layer located above the supporting substrate, the heat dissipation layer including a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity. In some embodiments of the device, the heat dissipation layer applies a compressive strain to a first side of the supporting substrate, and the upper integrated circuit die applies a compressive strain to a second side of the supporting substrate, the second side being opposite to the first side. In some embodiments, the device also includes: a protective layer located above the heat dissipation layer, the protective layer including a protective material having a first hardness, the upper integrated circuit die having a second hardness, the first hardness being greater than the second hardness. In some embodiments of the device, the buffer material has a columnar crystal structure, the gap filling dielectric has a non-columnar crystal structure, and the heat dissipation material has a non-columnar crystal structure. In some embodiments of the device, the heat dissipation material is a porous dielectric material. In some embodiments of the device, the heat dissipation material is a semiconductor material.

[0081] In an embodiment, the method includes: forming a die structure by the following steps: bonding an upper integrated circuit die to a lower integrated circuit die using a dielectric to dielectric bonding area and using a metal to metal bonding area; depositing a buffer material over the upper integrated circuit die and the lower integrated circuit die using a sputtering process, the buffer material having a first thermal conductivity and a first crystal structure; and depositing a gap filling dielectric over the buffer material using a chemical deposition process, the gap filling dielectric having a second thermal conductivity and a second crystal structure, the first thermal conductivity being greater than the second thermal conductivity, and the first crystal structure being different from the second crystal structure. In some embodiments of the method, the buffer material and the gap filling dielectric include the same dielectric material. In some embodiments of the method, the first crystal structure is a columnar crystal structure, and the second crystal structure is a non-columnar crystal structure. In some embodiments of the method, forming the die structure also includes: bonding a support substrate to the gap filling dielectric and the upper integrated circuit die; and depositing a heat dissipation material over the support substrate using a chemical deposition process, the heat dissipation material having a third thermal conductivity and a third crystal structure, the third thermal conductivity being greater than the first thermal conductivity, and the third crystal structure being different from the first crystal structure. In some embodiments of the method, forming the die structure further comprises: depositing a heat sink material over the gap fill dielectric using a chemical deposition process, the heat sink material having a third thermal conductivity and a third crystal structure, the third thermal conductivity being greater than the first thermal conductivity, and the third crystal structure being different from the first crystal structure. In some embodiments, the method further comprises: attaching the die structure to the wiring structure; and sealing the die structure in an encapsulant. In some embodiments, the method further comprises: sealing the die structure in an encapsulant; and forming the wiring structure over the encapsulant.

[0082] Some embodiments of the present application provide a semiconductor device, including: a lower integrated circuit die; an upper integrated circuit die, bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding area and a metal-to-metal bonding area; a first buffer layer, located around the upper integrated circuit die, the first buffer layer including a buffer material having a first thermal conductivity, the buffer material having a columnar crystal structure, the columnar crystal structure including crystal columns having a substantially uniform orientation in a direction extending away from the lower integrated circuit die; and a gap-filling dielectric, located above the first buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity.

[0083] In some embodiments, the semiconductor device further comprises: a support substrate located above the gap filling dielectric and the upper integrated circuit die, the upper integrated circuit die applying compressive strain on the support substrate; and a heat dissipation layer located above the support substrate, the heat dissipation layer applying compressive strain on the support substrate, the heat dissipation layer comprising a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity, the heat dissipation material having a non-columnar crystal structure, the non-columnar crystal structure comprising grains with varying orientations. In some embodiments, the semiconductor device further comprises: a second buffer layer located above the gap filling dielectric, the second buffer layer comprising the buffer material; and a heat dissipation layer located above the second buffer layer, the heat dissipation layer comprising a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity, the heat dissipation material having a non-columnar crystal structure, the non-columnar crystal structure comprising grains with varying orientations. In some embodiments, the gap filling dielectric has a non-columnar crystal structure, the non-columnar crystal structure comprising grains with varying orientations. In some embodiments, the gap filling dielectric is aluminum nitride, and the buffer material is aluminum nitride. In some embodiments, a top surface of the gap-fill dielectric is coplanar with a top surface of the upper integrated circuit die. In some embodiments, a top surface of the gap-fill dielectric is disposed above a top surface of the upper integrated circuit die.

[0084] Other embodiments of the present application provide a semiconductor device, comprising: a lower integrated circuit die; an upper integrated circuit die, bonded to the lower integrated circuit die using a dielectric-to-dielectric bonding area and using a metal-to-metal bonding area; a buffer layer, located around the upper integrated circuit die, the buffer layer comprising a buffer material having a first thermal conductivity; a gap-filling dielectric, located above the buffer layer and around the upper integrated circuit die, the gap-filling dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity; a supporting substrate, located above the gap-filling dielectric and the upper integrated circuit die; and a heat dissipation layer, located above the supporting substrate, the heat dissipation layer comprising a heat dissipation material having a third thermal conductivity, the third thermal conductivity being greater than the first thermal conductivity.

[0085] In some embodiments, the heat dissipation layer applies compressive strain to a first side of the supporting substrate, and the upper integrated circuit die applies compressive strain to a second side of the supporting substrate, the second side being opposite to the first side. In some embodiments, the semiconductor device further comprises: a protective layer located above the heat dissipation layer, the protective layer comprising a protective material having a first hardness, the upper integrated circuit die having a second hardness, the first hardness being greater than the second hardness. In some embodiments, the buffer material has a columnar crystal structure, the gap filling dielectric has a non-columnar crystal structure, and the heat dissipation material has a non-columnar crystal structure. In some embodiments, the heat dissipation material is a porous dielectric material. In some embodiments, the heat dissipation material is a semiconductor material.

[0086] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a die structure by the following steps: bonding an upper integrated circuit die to a lower integrated circuit die using a dielectric-to-dielectric bonding area and using a metal-to-metal bonding area; depositing a buffer material over the upper integrated circuit die and the lower integrated circuit die using a sputtering process, the buffer material having a first thermal conductivity and a first crystal structure; and depositing a gap-filling dielectric over the buffer material using a chemical deposition process, the gap-filling dielectric having a second thermal conductivity and a second crystal structure, the first thermal conductivity being greater than the second thermal conductivity, and the first crystal structure being different from the second crystal structure.

[0087] In some embodiments, the buffer material and the gap filling dielectric include the same dielectric material. In some embodiments, the first crystal structure is a columnar crystal structure, and the second crystal structure is a non-columnar crystal structure. In some embodiments, forming the die structure further includes: bonding a support substrate to the gap filling dielectric and the upper integrated circuit die; and depositing a heat dissipation material over the support substrate using a chemical deposition process, the heat dissipation material having a third thermal conductivity and a third crystal structure, the third thermal conductivity being greater than the first thermal conductivity, and the third crystal structure being different from the first crystal structure. In some embodiments, forming the die structure further includes: depositing a heat dissipation material over the gap filling dielectric using a chemical deposition process, the heat dissipation material having a third thermal conductivity and a third crystal structure, the third thermal conductivity being greater than the first thermal conductivity, and the third crystal structure being different from the first crystal structure. In some embodiments, the method further includes: attaching the die structure to a wiring structure; and sealing the die structure in an encapsulant. In some embodiments, the method further includes: sealing the die structure in an encapsulant; and forming a wiring structure over the encapsulant.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die using dielectric-to-dielectric bonding regions and using metal-to-metal bonding regions; a first buffer layer disposed around the upper integrated circuit die, the first buffer layer comprising a buffer material having a first thermal conductivity, the buffer material having a columnar crystal structure, the columnar crystal structure comprising crystal columns having a substantially uniform orientation in a direction extending away from the lower integrated circuit die; as well as A gap-fill dielectric is located above the first buffer layer and around the upper integrated circuit die, the gap-fill dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity.

2. The semiconductor device according to claim 1, further comprising: a support substrate over the gap-fill dielectric and the upper integrated circuit die, the upper integrated circuit die exerting a compressive strain on the support substrate; as well as A heat dissipation layer is located above the supporting substrate, the heat dissipation layer applies compressive strain on the supporting substrate, the heat dissipation layer includes a heat dissipation material with a third thermal conductivity, the third thermal conductivity is greater than the first thermal conductivity, the heat dissipation material has a non-columnar crystal structure, and the non-columnar crystal structure includes grains with varying orientations.

3. The semiconductor device according to claim 1, further comprising: a second buffer layer, located above the gap-filling dielectric, the second buffer layer comprising the buffer material; as well as A heat dissipation layer is located above the second buffer layer, the heat dissipation layer includes a heat dissipation material with a third thermal conductivity, the third thermal conductivity is greater than the first thermal conductivity, the heat dissipation material has a non-columnar crystal structure, and the non-columnar crystal structure includes grains with varying orientations.

4. The semiconductor device according to claim 1, wherein: The gap-fill dielectric has a non-columnar crystal structure including grains having varying orientations.

5. The semiconductor device according to claim 4, wherein: The gap-fill dielectric is aluminum nitride, and the buffer material is aluminum nitride.

6. The semiconductor device according to claim 1, wherein A top surface of the gap-fill dielectric is coplanar with a top surface of the upper integrated circuit die.

7. The semiconductor device according to claim 1, wherein A top surface of the gap-fill dielectric is disposed above a top surface of the upper integrated circuit die.

8. A semiconductor device comprising: a lower integrated circuit die; an upper integrated circuit die bonded to the lower integrated circuit die using dielectric-to-dielectric bonding regions and using metal-to-metal bonding regions; a buffer layer disposed around the upper integrated circuit die, the buffer layer comprising a buffer material having a first thermal conductivity; a gap-fill dielectric over the buffer layer and around the upper integrated circuit die, the gap-fill dielectric having a second thermal conductivity, the first thermal conductivity being greater than the second thermal conductivity; a support substrate over the gap-fill dielectric and the upper integrated circuit die; as well as A heat dissipation layer is located above the support substrate, wherein the heat dissipation layer includes a heat dissipation material having a third thermal conductivity, and the third thermal conductivity is greater than the first thermal conductivity.

9. The semiconductor device according to claim 8, wherein: The heat spreader layer applies a compressive strain to a first side of the support substrate, and the upper integrated circuit die applies a compressive strain to a second side of the support substrate, the second side being opposite to the first side.

10. A method of forming a semiconductor device, comprising: The die structure is formed by the following steps: bonding the upper integrated circuit die to the lower integrated circuit die using a dielectric-to-dielectric bonding region and using a metal-to-metal bonding region; depositing a buffer material over the upper integrated circuit die and the lower integrated circuit die using a sputtering process, the buffer material having a first thermal conductivity and a first crystal structure; as well as A gap-fill dielectric is deposited over the buffer material using a chemical deposition process, the gap-fill dielectric having a second thermal conductivity and a second crystal structure, the first thermal conductivity being greater than the second thermal conductivity, the first crystal structure being different from the second crystal structure.

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