Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a method for fabricating the same, and relates to the field of semiconductor technology. The semiconductor device comprises a substrate, a semiconductor epitaxial layer, an electrode layer, a source field plate, and a conductive block. The semiconductor epitaxial layer comprises a first channel layer, a first barrier layer, a second channel layer, and a second barrier layer. The electrode layer comprises a source electrode, a gate electrode, and a drain electrode. The source field plate is disposed on a side of the second barrier layer away from the substrate. The conductive block is disposed between the first channel layer and the first barrier layer. A first two-dimensional electron gas (2DEG) is formed between the first channel layer and the first barrier layer, insulated from the drain electrode, and the conductive block is electrically connected to the source electrode via the first two-dimensional electron gas. Compared to the prior art, the embodiments of the present invention, through the additional design of the conductive block, can shield electric field lines originating from the epitaxial layer and the substrate, reduce the electric field strength at the gate electrode foot, avoid threshold voltage instability, improve device stability, and reduce self-oscillation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating a semiconductor device. Background Art

[0002] The development trend of GaN-based RF power devices is towards higher operating frequencies and higher power gains. However, this leads to problems such as insufficient device stability, susceptibility to self-oscillation, and ultimately, failure. Specifically, when an RF signal is applied to the gate electrode, the drain electrode voltage will exhibit a certain swing. This change in drain electrode voltage will increase the electric field strength at the gate electrode edge, resulting in unstable threshold voltage and a tendency for self-oscillation. Summary of the Invention

[0003] The purpose of this application is to provide a semiconductor device and a method for fabricating the semiconductor device, which can improve the stability of the device and reduce self-oscillation.

[0004] To achieve the above objectives, the present invention is implemented through the following solution:

[0005] In a first aspect, the present invention provides a semiconductor device, comprising:

[0006] Substrate;

[0007] A semiconductor epitaxial layer, the semiconductor epitaxial layer comprising a first channel layer, a first barrier layer, a second channel layer and a second barrier layer sequentially stacked on the substrate;

[0008] An electrode layer, comprising a source electrode, a gate electrode, and a drain electrode, wherein the source electrode, the gate electrode, and the drain electrode are spaced apart on the side of the second barrier layer away from the substrate;

[0009] A source field plate is disposed on the side of the second barrier layer away from the substrate and located between the gate electrode and the drain electrode;

[0010] A conductive block is disposed between the first channel layer and the first barrier layer;

[0011] A first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, and a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer in the active region of the semiconductor epitaxial layer. The first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas.

[0012] In an optional embodiment, the projection of the conductive block on the substrate is located between the projection of the gate electrode on the substrate and the projection of the drain electrode on the substrate, and the projection of the conductive block on the substrate is spaced apart from the projection of the drain electrode on the substrate.

[0013] In an optional embodiment, the distance L1 between the projection of the conductive block on the substrate and the projection of the drain electrode on the substrate is greater than or equal to half the distance L2 between the projection of the source field plate on the substrate and the projection of the drain electrode on the substrate.

[0014] In an optional embodiment, the distance between the surface of the conductive block away from the substrate and the second channel layer is less than the thickness of the first barrier layer;

[0015] The distance between the conductive block and the substrate on the side closest to the substrate is less than the thickness of the first channel layer.

[0016] In an optional embodiment, the projection of the conductive block onto the substrate is rectangular, curved, or serrated.

[0017] In an optional embodiment, the two ends of the conductive block extend out of the active region, and the first two-dimensional electron gas is located outside the active region.

[0018] In an optional embodiment, the semiconductor epitaxial layer further includes a cap layer disposed on the second barrier layer away from the substrate, the source electrode, the gate electrode and the drain electrode disposed on the side surface of the cap layer away from the substrate, and the source field plate disposed on the side of the cap layer away from the substrate.

[0019] In an optional embodiment, a dielectric layer is further disposed between the source field plate and the surface of the cap layer away from the substrate.

[0020] In an optional embodiment, both the first barrier layer and the second barrier layer are AlGaN layers, and the Al content of the first barrier layer is less than the Al content of the second barrier layer.

[0021] In a second aspect, the present invention provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in the foregoing embodiments, the method comprising:

[0022] Provide a carrier;

[0023] A first channel layer, a first barrier layer, a second channel layer, and a second barrier layer are sequentially grown on the carrier.

[0024] A source electrode, a gate electrode, and a drain electrode are disposed at intervals on the side of the second barrier layer away from the carrier;

[0025] A source field plate is disposed on the side of the second barrier layer away from the carrier, and the source field plate is located between the gate electrode and the drain electrode;

[0026] Peel off the carrier to expose the first channel layer;

[0027] A conductive block is formed by ion implantation between the first channel layer and the first barrier layer;

[0028] The first channel layer is bonded to the substrate;

[0029] Wherein, a first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, and a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer in the active region of the semiconductor epitaxial layer. The first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas.

[0030] In an optional embodiment, the step of forming a conductive block by ion implantation between the first channel layer and the first barrier layer includes:

[0031] An ion implantation is performed on the surface of the first channel layer, and a first two-dimensional electron gas is patterned to form it.

[0032] A secondary ion implantation is performed on the surface of the first channel layer to form a conductive block.

[0033] Through the above technical solution, after the source electrode, gate electrode, and drain electrode are fabricated, a source field plate is set, and a conductive block is formed between the first channel layer and the first barrier layer. A first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, and a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer within the active region of the semiconductor epitaxial layer. The first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas. Compared to the prior art, this embodiment of the invention, by additionally designing the conductive block, can shield electric field lines originating from the epitaxial layer and substrate, reduce the electric field strength at the gate electrode pin, avoid threshold voltage instability, improve device stability, and reduce self-oscillation phenomena.

[0034] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the semiconductor device provided in the embodiments of this application from a first-view perspective;

[0037] Figure 2 A partial structural perspective view of a semiconductor device provided in an embodiment of this application from a second perspective;

[0038] Figure 3 Schematic diagrams of the structure of semiconductor devices provided in other preferred embodiments of this application;

[0039] Figures 4 to 9 A process step diagram illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;

[0040] Figure 10 for Figure 9 A structural schematic diagram from another perspective of step S6.

[0041] icon:

[0042] 100 - Semiconductor device; 110 - Substrate; 120 - Semiconductor epitaxial layer; 121 - First channel layer; 122 - First barrier layer; 123 - Second channel layer; 124 - Second barrier layer; 125 - Active region; 126 - Cap layer; 127 - Dielectric layer; 130 - Electrode layer; 131 - Source electrode; 132 - Drain electrode; 133 - Gate electrode; 140 - Source field plate; 150 - Conductive block; 160 - First two-dimensional electron gas; 170 - Second two-dimensional electron gas. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0044] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0045] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0046] As disclosed in the background section, existing GaN-based RF power devices are unstable and prone to self-oscillation in high-frequency, high-gain applications. Specifically, current devices typically incorporate a source field plate, which significantly increases the device's breakdown voltage. Without the source field plate, most of the drain electrode's electric field lines are concentrated directly on the right side of the gate electrode, which, due to its small size, easily leads to breakdown failure. With the source field plate, its potential is zero, and most of the electric field lines concentrate on the source field plate, sharing the load on the gate electrode. However, since the source field plate is located above the 2DEG, some electric field lines passing through the epitaxial layer and substrate cannot be effectively shielded, which also leads to threshold voltage instability and a tendency for self-oscillation.

[0047] To address the above situation, the conventional approach is to use external matching circuits to adjust the chip impedance to a suitable level, thereby improving device stability and reducing self-oscillation. However, this method requires circuit-level design and external debugging, resulting in a large circuit area and low integration density.

[0048] In addition, existing device substrates are usually fixed substrates, meaning that the substrate used for growth is usually the same type as the substrate of the final device. However, different application scenarios have different requirements for the substrate, making it difficult to meet the usage needs.

[0049] To address the aforementioned problems, embodiments of the present invention provide a semiconductor device and a method for fabricating a semiconductor device. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other.

[0050] See also Figure 1 and Figure 2This invention provides a semiconductor device 100 that can improve device stability, reduce self-oscillation, and reduce the difficulty of debugging matching circuits.

[0051] The semiconductor device 100 provided in this embodiment of the invention includes a substrate 110, a semiconductor epitaxial layer 120, an electrode layer 130, a source field plate 140, and a conductive block 150. The semiconductor epitaxial layer 120 can be epitaxially grown on the substrate 110, wherein the semiconductor epitaxial layer 120 includes a first channel layer 121, a first barrier layer 122, a second channel layer 123, and a second barrier layer 124 sequentially stacked on the substrate 110; the electrode layer 130 includes a source electrode 131, a gate electrode 133, and a drain electrode 132, wherein the source electrode 131, the gate electrode 133, and the drain electrode 132 are spaced apart from the second barrier layer 124 away from the substrate 110. On one side; the source field plate 140 is disposed on the side of the second barrier layer 124 away from the substrate 110 and is located between the gate electrode 133 and the drain electrode 132; the conductive block 150 is disposed between the first channel layer 121 and the first barrier layer 122; wherein, a first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122, and a second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120; the first two-dimensional electron gas 160 is insulated from the drain electrode 132, and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron gas 160.

[0052] It should be noted that in this embodiment, the second two-dimensional electron gas 170 is used to realize the conventional conductivity function of the device, realizing the electrical connection between the source electrode 131 and the drain electrode 132, and is controlled by the gate electrode 133. The first two-dimensional electron gas 160 is located below the second two-dimensional electron gas 170, enabling the electrical connection between the source electrode 131 and the conductive block 150. Furthermore, the second two-dimensional electron gas 170 is isolated from the drain electrode 132, preventing the drain electrode 132 from directly connecting to the source electrode 131. The source field plate 140 can significantly improve the breakdown voltage of the device. Without the source field plate 140, most of the electric field lines of the drain electrode 132 would be directly concentrated on the right side of the gate electrode 133. Because the gate electrode 133 is very small, this would easily lead to breakdown failure. With the source field plate 140 added, the potential of the source field plate 140 is zero, and most of the electric field lines will be concentrated on the source field plate 140, sharing the burden on the gate electrode 133. However, since the source field plate 140 is located above the 2DEG, some electric field lines passing through the epitaxial layer and substrate 110 cannot be effectively shielded, which can also lead to unstable threshold voltage and easy self-oscillation. In this embodiment, an additionally designed conductive block 150 is used, which is connected to the source electrode 131 through the first two-dimensional electron gas 160 formed between the first barrier layer 122 and the first channel layer 121. Together with the source field plate 140, this can reduce the electric field strength at the gate foot and reduce the impact of the voltage change of the drain electrode 132 on the electric field strength at the edge of the gate electrode 133, thereby improving the stability of the device and reducing self-oscillation.

[0053] It is worth noting that during device operation, the source electrode 131 is at GND, the gate electrode 133 is at a negative voltage, and the drain electrode 132 is at a positive voltage. Therefore, the potential difference between the gate and drain is the largest, resulting in a spike electric field at the gate pin. Generally, the source field plate 140 of a device can shield the upper half of the electric field lines between the gate and drain, but it cannot shield the electric field lines passing through the epitaxial layer and substrate 110. Therefore, by placing a conductive block 150 between the first channel layer 121 and the first barrier layer 122, the electric field lines originating from the semiconductor epitaxial layer 120 and the substrate 110 can be shielded, reducing the electric field strength at the gate pin. To prevent the conductive block 150 from connecting to the drain electrode 132, additional isolation is required to prevent the generation of a two-dimensional electron gas between the conductive block 150 and the drain electrode 132.

[0054] In some embodiments, the projection of the conductive block 150 onto the substrate 110 is located between the projections of the gate electrode 133 and the drain electrode 132 onto the substrate 110, and the projections of the conductive block 150 onto the substrate 110 are spaced apart from the projections of the drain electrode 132 onto the substrate 110. Specifically, if the conductive block 150 is too close to the drain electrode 132, the breakdown voltage will be reduced. Therefore, the conductive block 150 needs to be correspondingly disposed between the area defined by the gate electrode 133 and the drain electrode 132, and spaced apart from the drain electrode 132.

[0055] Furthermore, the distance L1 between the projection of the conductive block 150 on the substrate 110 and the projection of the drain electrode 132 on the substrate 110 is greater than or equal to half the distance L2 between the projection of the source field plate 140 on the substrate 110 and the projection of the drain electrode 132 on the substrate 110. Specifically, the side of the projection of the conductive block 150 on the substrate 110 away from the drain electrode 132 does not exceed the side of the projection of the gate electrode 133 on the substrate 110 close to the drain electrode 132, therefore the distance between the projection of the conductive block 150 and the projection of the drain electrode 132 is greater than or equal to 0. The side of the projection of the conductive block 150 on the substrate 110 close to the drain electrode 132 does not exceed the midline of the projection gap between the source field plate 140 and the drain electrode 132, that is, the distance between the projection of the conductive block 150 and the projection of the drain electrode 132 is greater than half the projection distance between the source field plate 140 and the drain electrode 132, which can effectively shield the electric field lines while avoiding a reduction in breakdown voltage.

[0056] It should be noted that in this embodiment, the width of the conductive block 150 can preferably be slightly smaller than the width of the source field plate 140. If the conductive block 150 is too large, the parasitic effect will increase, while if it is too small, the shielding effect will be worse.

[0057] In some embodiments, the distance between the surface of the conductive block 150 away from the substrate 110 and the second channel layer 123 is less than the thickness of the first barrier layer 122; the distance between the surface of the conductive block 150 near the substrate 110 and the substrate 110 is less than the thickness of the first channel layer 121. Specifically, the conductive block 150 needs to extend to the interface between the first channel layer 121 and the second channel layer 123 to ensure connection with the first two-dimensional electron gas 160. Furthermore, the thickness of the conductive block 150 is less than or equal to the sum of the thicknesses of the first channel layer 121 and the first barrier layer 122. Preferably, the thickness of the conductive block 150 is equal to the sum of the thicknesses of the first channel layer 121 and the first barrier layer 122, that is, both sides of the conductive block 150 are bonded to the second channel layer 123 and the substrate 110 respectively, ensuring sufficient thickness to shield the electric field lines.

[0058] In some embodiments, the projection of the conductive block 150 onto the substrate 110 is rectangular, curved, or sawtooth. Preferably, the conductive block 150 has a three-dimensional shape, which may be elongated, and its projection onto the substrate 110 is an elongated rectangle, thereby achieving a better shielding effect.

[0059] In some embodiments, the conductive block 150 extends into active regions 125 at both ends, and the first two-dimensional electron gas 160 is located outside the active regions 125. Specifically, the conductive block 150 may be parallel to the gate, and the conductive block 150 extends from the edge of the active region 125 at both ends perpendicular to the gate-drain direction. The first two-dimensional electron gas 160 is connected to both ends of the conductive block 150 and, after patterning, can be located outside the active region 125, so that no two-dimensional electron gas is generated below the active region 125, thereby minimizing the parasitic capacitance caused by the first two-dimensional electron gas 160.

[0060] Of course, in other preferred embodiments of the present invention, the first two-dimensional electron gas 160 may also extend to the active region 125, which can make the electrical connection effect better.

[0061] In some embodiments, both the first barrier layer 122 and the second barrier layer 124 are AlGaN layers, and the Al content of the first barrier layer 122 is lower than that of the second barrier layer 124. Specifically, the substrate 110 can be a material such as Si, SiC, or diamond, and both the first channel layer 121 and the second channel layer 123 can be GaN layers. Since the second barrier layer 124 forms the two-dimensional electron gas required for the actual operation of the device, high density and high mobility are pursued, while the first barrier layer 122 only needs to form a layer of conductive two-dimensional electron gas. Therefore, the Al content of the second barrier layer 124 is higher than that of the first barrier layer 122. Preferably, the Al content of the second barrier layer 124 is between 15% and 30%, which can ensure the actual operating performance of the device.

[0062] In some embodiments, the semiconductor epitaxial layer 120 further includes a cap layer 126 disposed on the second barrier layer 124 away from the substrate 110. A source electrode 131, a gate electrode 133, and a drain electrode 132 are disposed on the surface of the cap layer 126 away from the substrate 110, and a source field plate 140 is disposed on the same side of the cap layer 126 away from the substrate 110. Specifically, the cap layer 126 may be a GaN layer grown on the surface of the second barrier layer 124. The source electrode 131, gate electrode 133, and drain electrode 132 are disposed on the surface of the cap layer 126, and the epitaxial layer below the source electrode 131 and drain electrode 132 is ohmized through ion implantation or a high-temperature ohmic process. Specific processes can be referenced from existing GaN power devices.

[0063] See Figure 3 In some embodiments, a dielectric layer 127 is further disposed between the source field plate 140 and the surface of the cap layer 126 away from the substrate 110. Specifically, the dielectric layer 127 can be SiN, SiO2, or air dielectric; in this embodiment, it can be a SiN layer, which can achieve protection of the epitaxial material.

[0064] This invention also provides a method for fabricating a semiconductor device 100, used to fabricate the semiconductor device 100 as described above, the method comprising:

[0065] S1: Provide a carrier.

[0066] See Figure 4 Specifically, a carrier for epitaxial growth is first provided. The material of this carrier can be the same as the material of the subsequent substrate 110, or it can be another material that is conducive to epitaxial growth. Furthermore, this carrier needs to facilitate the subsequent peeling operation.

[0067] S2: The first channel layer 121, the first barrier layer 122, the second channel layer 123, and the second barrier layer 124 are sequentially grown on the carrier.

[0068] See Figure 5 Specifically, a first channel layer 121, a first barrier layer 122, a second channel layer 123, and a second barrier layer 124 are sequentially deposited on the surface of a carrier using epitaxial growth processes, such as chemical vapor deposition or physical vapor deposition. The first channel layer 121 and the second channel layer 123 are both GaN layers, while the first barrier layer 122 and the second barrier layer 124 can be AlGaN layers. The Al content of the second barrier layer 124 can be increased by changing the process parameters. The purpose of the first barrier layer 122 is to connect the conductive block 150 to the source electrode 131, and the purpose of the second barrier layer 124 is to provide a two-dimensional electron gas for the source-drain connection.

[0069] After the deposition of the second barrier layer 124 is completed, the cap layer 126 can be deposited on the second barrier layer 124 to complete the epitaxial operation.

[0070] S3: A source electrode 131, a gate electrode 133, and a drain electrode 132 are disposed at intervals on the side of the second barrier layer 124 away from the carrier.

[0071] See Figure 6 Specifically, ion implantation can first be performed on the surface away from the substrate 110 to disrupt the lattice of the non-channel region, so that no two-dimensional electron gas is generated in the non-channel region, thus defining the active region 125 and ensuring that no two-dimensional electron gas is generated outside the active region 125. Then, a gate electrode 133, a source electrode 131, and a drain electrode 132, all of which are metal electrodes, are disposed on the surface of the cap layer 126.

[0072] S4: A source field plate 140 is disposed on the side of the second barrier layer 124 away from the carrier.

[0073] See Figure 7In this process, the source field plate 140 is located between the gate electrode 133 and the drain electrode 132. After the electrode layer 130 is fabricated, an insulating dielectric layer 127 can be covered, then the source field plate 140 is set, and finally an insulating dielectric material is covered again to complete the front-side process of the device.

[0074] S5: Peel off the carrier to expose the first trench layer 121.

[0075] See Figure 8 Specifically, the carrier is removed through a stripping process; of course, the carrier can also be removed by grinding.

[0076] S6: Ion implantation is performed between the first channel layer 121 and the first barrier layer 122 to form a conductive block 150.

[0077] See Figure 9 and Figure 10 Specifically, an ion implantation is performed on the surface that was originally in contact with the substrate 110, i.e., the exposed surface of the first channel layer 121, so that no two-dimensional electron gas is generated in the active region 125 between the first channel layer 121 and the first barrier layer 122. At the same time, the first two-dimensional electron gas 160 is patterned so that the first two-dimensional electron gas 160 can connect to the source and be isolated from the drain (where patterning defines the region with and without two-dimensional electron gas). Then, a second ion implantation, i.e., a large dose of ion implantation, is performed on the surface of the first channel layer 121 to form a conductive block 150, which can be connected to the source through the first two-dimensional electron gas 160.

[0078] S7: Bond the first channel layer 121 to the substrate 110.

[0079] Please continue reading Figure 1 Specifically, the epitaxial structure can be transferred to different substrate materials, such as Si, SiC, diamond, etc., by bonding as needed.

[0080] The first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122, and the second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120. The first two-dimensional electron gas 160 is insulated from the drain electrode 132, and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron gas 160.

[0081] Through the above technical solution, after the source electrode 131, gate electrode 133, and drain electrode 132 are fabricated, a source field plate 140 is set up, and a conductive block 150 is formed between the first channel layer 121 and the first barrier layer 122. A first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122, and a second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120. The first two-dimensional electron gas 160 is insulated from the drain electrode 132, and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron gas. Compared with the prior art, this embodiment of the invention, by additionally designing the conductive block 150, can shield the electric field lines originating from the epitaxial layer and the substrate 110, reduce the electric field strength at the gate foot of the gate electrode 133, avoid threshold voltage instability, improve device stability, and reduce self-oscillation phenomena.

[0082] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate (110); Semiconductor epitaxial layer (120), the semiconductor epitaxial layer (120) includes a first channel layer (121), a first barrier layer (122), a second channel layer (123) and a second barrier layer (124) sequentially stacked on the substrate (110); An electrode layer (130) is provided, comprising a source electrode (131), a gate electrode (133), and a drain electrode (132), wherein the source electrode (131), the gate electrode (133), and the drain electrode (132) are disposed at intervals on the side of the second barrier layer (124) away from the substrate (110); A source field plate (140) is disposed on the side of the second barrier layer (124) away from the substrate (110) and located between the gate electrode (133) and the drain electrode (132); A conductive block (150) is disposed between the first channel layer (121) and the first barrier layer (122); Wherein, a first two-dimensional electron gas (160) is formed between the first channel layer (121) and the first barrier layer (122), and a second two-dimensional electron gas (170) is formed between the second channel layer (123) and the second barrier layer (124) in the active region (125) of the semiconductor epitaxial layer (120). The first two-dimensional electron gas (160) is insulated from the drain electrode (132), and the conductive block (150) is electrically connected to the source electrode (131) through the first two-dimensional electron gas (160).

2. The semiconductor device according to claim 1, characterized in that, The projection of the conductive block (150) on the substrate (110) is located between the projection of the gate electrode (133) on the substrate (110) and the projection of the drain electrode (132) on the substrate (110), and the projection of the conductive block (150) on the substrate (110) and the projection of the drain electrode (132) on the substrate (110) are spaced apart.

3. The semiconductor device according to claim 2, characterized in that, The distance L1 between the projection of the conductive block (150) on the substrate (110) and the projection of the drain electrode (132) on the substrate (110) is greater than or equal to half the distance L2 between the projection of the source field plate (140) on the substrate (110) and the projection of the drain electrode (132) on the substrate (110).

4. The semiconductor device according to claim 1, characterized in that, The distance between the side surface of the conductive block (150) away from the substrate (110) and the second channel layer (123) is less than the thickness of the first barrier layer (122); The distance between the conductive block (150) and the substrate (110) on the side surface of the conductive block (150) is less than the thickness of the first channel layer (121).

5. The semiconductor device according to claim 1, characterized in that, The projection of the conductive block (150) onto the substrate (110) is rectangular, curved, or sawtooth.

6. The semiconductor device according to claim 1, characterized in that, The conductive block (150) extends from both ends of the active region (125), and the first two-dimensional electron gas (160) is located outside the active region (125).

7. The semiconductor device according to claim 1, characterized in that, The semiconductor epitaxial layer (120) further includes a cap layer (126) disposed on the second barrier layer (124) away from the substrate (110), the source electrode (131), the gate electrode (133) and the drain electrode (132) are disposed on the side surface of the cap layer (126) away from the substrate (110), and the source field plate (140) is disposed on the side surface of the cap layer (126) away from the substrate (110); a dielectric layer (127) is also disposed between the source field plate (140) and the side surface of the cap layer (126) away from the substrate (110).

8. The semiconductor device according to claim 1, characterized in that, Both the first barrier layer (122) and the second barrier layer (124) are AlGaN layers, and the Al content of the first barrier layer (122) is less than the Al content of the second barrier layer (124).

9. A method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in claim 1, characterized in that, The preparation method includes: Provide a carrier; A first channel layer (121), a first barrier layer (122), a second channel layer (123), and a second barrier layer (124) are sequentially grown on the carrier. A source electrode (131), a gate electrode (133), and a drain electrode (132) are disposed at intervals on the side of the second barrier layer (124) away from the carrier; A source field plate (140) is disposed on the side of the second barrier layer (124) away from the carrier, and the source field plate (140) is located between the gate electrode (133) and the drain electrode (132); Peel off the carrier to expose the first channel layer (121); A conductive block (150) is formed by ion implantation between the first channel layer (121) and the first barrier layer (122); The first channel layer (121) is bonded to the substrate (110); Wherein, a first two-dimensional electron gas (160) is formed between the first channel layer (121) and the first barrier layer (122), and a second two-dimensional electron gas (170) is formed between the second channel layer (123) and the second barrier layer (124) in the active region (125) of the semiconductor epitaxial layer (120). The first two-dimensional electron gas (160) is insulated from the drain electrode (132), and the conductive block (150) is electrically connected to the source electrode (131) through the first two-dimensional electron gas (160).

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The step of forming a conductive block (150) by ion implantation between the first channel layer (121) and the first barrier layer (122) includes: An ion implantation is performed on the surface of the first channel layer (121), and a first two-dimensional electron gas (160) is patterned. A secondary ion implantation is performed on the surface of the first channel layer (121) to form a conductive block (150).

Images