Semiconductor device

Abstract

A semiconductor device includes: an insulating structure; a first interconnection pattern having a first through hole and disposed on an upper surface of the insulating structure; and a conductive via passing through the first through hole of the first interconnection pattern and contacting the first interconnection pattern on an inner side wall of the first through hole, the first interconnection pattern includes a material having a first resistivity in a first direction parallel to the upper surface of the insulating structure and a second resistivity in a second direction different from the first direction and not parallel to the upper surface of the insulating structure, and the first resistivity is lower than the second resistivity.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device including an interconnect structure and a method of manufacturing the same. Background Art

[0002] As semiconductor devices become smaller and more highly integrated, the width of the interconnect is also becoming smaller. However, as the width of the interconnect decreases, the resistance increases, and when a fine pattern of the interconnect is applied, the resistance value increases rapidly, causing the problem of increased signal resistance-capacitance (RC) delay. For example, for commonly used interconnect materials such as copper (Cu), the resistance increases rapidly as the width of the interconnect decreases. Materials with a smaller amount of electron mean free path (such as ruthenium (Ru), iridium (Ir), etc.) may have a smaller resistance change compared to copper (Cu) when the width of the interconnect is reduced, but as the miniaturization of semiconductor devices continues and the width of the interconnect becomes about 10nm or less, the resistance of the material with a smaller amount of electron mean free path also increases rapidly, causing the problem of increased RC delay. Summary of the invention

[0003] Embodiments of the inventive concept provide a semiconductor device including an interconnect structure having improved reliability.

[0004] Embodiments of the inventive concept provide a method of manufacturing the semiconductor device.

[0005] According to an embodiment conceived in the present invention, a semiconductor device includes: an insulating structure; a first interconnection pattern, the first interconnection pattern having a first through-hole and arranged on an upper surface of the insulating structure; and a conductive path, the conductive path passing through the first through-hole of the first interconnection pattern and contacting the first interconnection pattern on an inner side wall of the first through-hole, wherein the first interconnection pattern includes a material having a first resistivity in a first direction parallel to the upper surface of the insulating structure and having a second resistivity in a second direction different from the first direction and not parallel to the upper surface of the insulating structure, and the first resistivity is lower than the second resistivity.

[0006] According to an embodiment of the present invention, a semiconductor device includes: an active area; an interlayer insulating layer, which is arranged on the active area; a contact structure, which is connected to the active area and passes through the interlayer insulating layer; an intermediate insulating structure, which has a first hole and is arranged on the interlayer insulating layer; a first interconnection pattern, which has a second hole aligned with the first hole, is arranged on the intermediate insulating structure and has an anisotropic resistance characteristic; and a conductive path, which passes through the first hole and the second hole to connect to the contact structure, and is connected to the first interconnection pattern through the inner side wall of the second hole.

[0007] According to an embodiment conceived in the present invention, a semiconductor device includes: an insulating structure, the insulating structure including an intermediate insulating layer, a first etch stop layer located on the intermediate insulating layer, and a second etch stop layer located below the intermediate insulating layer, and including a lower through hole exposing the intermediate insulating layer, the first etch stop layer, and the second etch stop layer; a first interconnection pattern, the first interconnection pattern having a first through hole aligned with the lower through hole and arranged on an upper surface of the first etch stop layer; an upper etch stop layer, the upper etch stop layer having a second through hole aligned with the first through hole and arranged on the first interconnection pattern; and a conductive path, the conductive path including a material different from that of the first interconnection pattern, filling the first through hole, the second through hole, and the lower through hole, and having an upper surface coplanar with the upper surface of the upper etch stop layer and directly contacting a side surface of the first interconnection pattern through an inner side wall of the first through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects and features of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 , Figure 2A and Figure 2B is a view schematically illustrating an example of a semiconductor device according to an embodiment of the inventive concept;

[0010] Figure 3 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0011] Figure 4 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0012] Figure 5 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0013] Figure 6 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0014] Figure 7 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0015] Figure 8 is a cross-sectional view schematically illustrating a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0016] Fig. 9 is a view schematically showing a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0017] Fig.10 is a view schematically showing a modified example of a semiconductor device according to an embodiment of the inventive concept;

[0018] FIG. 11A to FIG. 11M is a cross-sectional view schematically illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the inventive concept;

[0019] FIG. 12A to FIG. 12I is a cross-sectional view schematically illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0020] because Figures 1 to 12I The drawings in the drawings are intended for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. DETAILED DESCRIPTION

[0021] Hereinafter, terms such as "upper", "middle", "lower", etc. may be replaced with other terms such as "first", "second", "third", etc., and may also be used to describe elements of the specification. Terms such as "first", "second", "third", etc. may be used to describe various components, but the components are not limited by the terms. These terms are only used to distinguish one element or component from another element or component, and for example, a "first component" may be referred to as a "second component".

[0022] As used herein, "about" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0023] refer to Figure 1 , Figure 2A and Figure 2B , an illustrative example of a semiconductor device 1 according to an embodiment of the inventive concept will be described. Figure 1 , Figure 2A and Figure 2B is a view schematically showing an illustrative example of a semiconductor device 1 according to an embodiment of the inventive concept, Figure 1 is a top view schematically showing an illustrative example of a semiconductor device 1 according to an embodiment of the inventive concept, Figure 2A It schematically shows a view taken along line II'. Figure 1 a cross-sectional view of a portion of Figure 2B It is schematically shown that the Figure 1 Cross-sectional view of a portion of.

[0024] refer to Figure 1 , Figure 2A and Figure 2B , a semiconductor device 1 according to an embodiment of the inventive concept may include a lower structure LS and an upper structure US located on the lower structure LS.

[0025] The lower structure LS may include a base 5 , a first lower insulating layer 6 located on the base 5 , and a lower interconnection structure 13 formed in the first lower insulating layer 6 .

[0026] The first lower insulating layer 6 may include silicon oxide (SiO 2 ) or low-κ dielectrics.

[0027] The lower interconnect structure 13 may include an interconnect material layer 13b and a barrier material layer 13a covering the side surface and the bottom surface of the interconnect material layer 13b. The interconnect material layer 13b may include copper (Cu), and the barrier material layer 13a may include, for example, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

[0028] The upper structure US located on the lower structure LS may include a first insulating structure 16 and a first interconnection structure ( 23 and 25 ) located on the first insulating structure 16 .

[0029] The first insulating structure 16 may include an intermediate insulating layer 20 , a first etch stop layer 19 on the intermediate insulating layer 20 , and a second etch stop layer 18 under the intermediate insulating layer 20 .

[0030] In the upper structure US, the first etch stop layer 19 and the second etch stop layer 18 may be disposed on and below the intermediate insulating layer 20, respectively, to serve as etch stop layers during etching of the conductive path 25 and the first interconnect pattern 23. The first interconnect structure (23 and 25) may include two main components: the first interconnect pattern 23 that transmits current within the same device layer; and the conductive path 25 that transmits current between different device layers.

[0031] The intermediate insulating layer 20 may be, for example, silicon oxide (SiO 2 ), tetraethyl orthosilicate (TEOS) oxide, carbon-doped silicon oxide (SiOCH), or silicon oxycarbide (SiOC), but the inventive concept is not limited thereto.

[0032] The first etch stop layer 19 and the second etch stop layer 18 may include the same material, and, for example, may be an insulating material including at least one of aluminum nitride (AlN), silicon nitride (SiN), silicon boronitride (SiBN), or silicon carbonitride (SiCN).

[0033] The first and second etch stop layers 19 and 18 may have the same thickness, but the inventive concept is not limited thereto, and the intermediate insulating layer 20 may be formed thicker than the first and second etch stop layers 19 and 18 .

[0034] The first interconnect structure ( 23 and 25 ) may be disposed on the first insulating structure 16 , for example, on the first etch stop layer 19 .

[0035] The first interconnection structure ( 23 and 25 ) may include a first interconnection pattern 23 on the first etch stop layer 19 .

[0036] The first interconnection pattern 23 may extend in one direction parallel to an upper surface of the first insulating structure 16 (eg, an upper surface of the intermediate insulating layer 20 ) on a plane (XY plane).

[0037] The first interconnection pattern 23 may be cut into an island shape in some regions, but the inventive concept is not limited thereto. The first interconnection pattern 23 may have a predetermined thickness or less and a predetermined width or less on the XY plane, for example, less than or equal to about 10 nm.

[0038] The first interconnect pattern 23 may include a material having anisotropic resistance characteristics. The material having anisotropic resistance characteristics may be defined as a first resistivity value of the first interconnect pattern 23 in a direction parallel to the XY plane (in-plane) (referred to as the first direction) being different from a second resistivity value of the first interconnect pattern 23 in a direction not parallel to the XY plane (out-of-plane) (referred to as the second direction). For example, the second resistivity value may be several tens to several hundred times greater than the first resistivity value. Because the first interconnect pattern 23 may transmit current within the same device layer on the XY plane, when the first interconnect pattern 23 includes a material having anisotropic resistance characteristics so that the electron mobility in the same layered structure on the XY plane is very high, the first resistivity may be rapidly reduced. Therefore, the signal RC delay may be reduced.

[0039] The first interconnect pattern 23 may be a multi-element material having anisotropic resistance characteristics, and may be a material in which multiple elements in the material form a hierarchical structure and combine to have different characteristics between layers. For example, the first interconnect pattern 23 may include a conductive material including, for example, at least one of an intermetallic compound, an oxide, a carbide, a nitride, or a boride.

[0040] The first interconnect pattern 23 may be a carbide or a nitride, and may be a material having a MAX phase. For example, the first interconnect pattern 23 may be a material satisfying the structural formula M n+1 AX n , wherein n=1, 2, 3 or 4. For example, the first interconnection pattern 23 may be a material having M 2 AX phase, M 3 AX 2 Phase or M 4 AX 3 Phase material.

[0041] In such MAX phase materials, M (metal type) is a transition metal, A is one of elements of Groups 10, 11, 12, 13 and 14, and X is carbon (C) and / or nitrogen (N).

[0042] In an embodiment of the present inventive concept, in the material of the MAX phase, M may include, for example, scandium (Sc), yttrium (Y), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), iron (Fe), cobalt (Co) and / or nickel (Ni), A may include, for example, aluminum (Al), gallium (Ga), indium (In), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), cadmium (Cd), copper (Cu), zinc (Zn), nickel (Ni), platinum (Pt), palladium (Pd), silver (Ag) and / or gold (Au), and X may include carbon (C) and / or nitrogen (N).

[0043] In the bonding of each layer, both covalent bonding properties and metallic bonding properties may exist between MX to have a very strong bond, relatively weak bonds may exist between MA, and a very large state density may exist at the Fermi level through the orbital function of M. Therefore, electrons can easily move around M, so that anisotropic low resistance characteristics can be presented.

[0044] In an embodiment of the present invention, M 2 The material of the AX phase can be, for example, titanium aluminum carbide (Ti 2 AlC), titanium aluminum nitride (Ti 2 AlN), titanium carbide silicon (Ti 2 SiC), titanium gallium nitride (Ti 2 GaN), titanium germanium carbide (Ti 2 GeC), titanium germanium nitride (Ti 2 GeN), titanium indium carbide (Ti 2 InC), titanium indium nitride (Ti 2 InN), vanadium aluminum carbide (V 2 AlC), vanadium aluminum nitride (V 2 AlN), vanadium silicon carbide (V 2 SiC), vanadium silicon nitride (V 2 SiN), vanadium gallium carbide (V 2 GaC), gallium vanadium nitride (V 2 GaN), Vanadium Germanium Carbide (V 2 GeC), vanadium arsenic nitride (V 2 AsN), vanadium cadmium carbide (V 2 CdC), vanadium cadmium nitride (V 2 CdN), vanadium indium carbide (V 2 InC), vanadium tin nitride (V 2 SnN), chromium carbide aluminum (Cr 2 AlC), chromium carbide silicon (Cr 2 SiC), chromium silicon nitride (Cr2 SiN), chromium gallium carbide (Cr 2 GaC), chromium germanium nitride (Cr 2 GeN), chromium carbide arsenic (Cr 2 AsC), chromium arsenic nitride (Cr 2 AsN), chromium indium nitride (Cr 2 InN), chromium tin nitride (Cr 2 SnN), Tantalum Aluminum Carbide (Ta 2 AlC), Tantalum Silicon Carbide (Ta 2 SiC), Tantalum Gallium Carbide (Ta 2 GaC) or Tantalum Indium Carbide (Ta 2 InC). Alternatively, with M 3 AX 2 The material of the phase can be, for example, titanium aluminum carbide (Ti 3 AlC 2 ), titanium silicon carbide (Ti 3 SiC 2 ), titanium gallium nitride (Ti 3 GaN 2 ), titanium germanium carbide (Ti 3 G JZ 2 ), titanium germanium nitride (Ti 3 N 2 ), titanium indium carbide (Ti 3 InC 2 ), titanium indium nitride (Ti 3 InN 2 ), titanium tin carbide (Ti 3 S N 2 ), vanadium aluminum carbide (V 3 AlC 2 ), vanadium aluminum nitride (V 3 AlN 2 )、Vanadium Silicon Carbide (V 3 SiC 2 ), Vanadium Silicon Nitride (V 3 S N 2 ), vanadium gallium carbide (V 3 C 2 ), vanadium gallium nitride (V 3 GaN 2 ), Vanadium Germanium Carbide (V 3 G JZ 2 ), Vanadium Germanium Nitride (V 3 N 2 ), vanadium arsenic carbide (V 3 A 2 ), Vanadium Arsenic Nitride (V 3 AA 2 ), vanadium cadmium carbide (V 3CdC 2 ), Vanadium Cadmium Nitride (V 3 CdN 2 ), Vanadium Indium Carbide (V 3 InC 2 ), Vanadium Indium Nitride (V 3 InN 2 ), Vanadium Tin Carbide (V 3 S N 2 ), Vanadium Tin Nitride (V 3 Sn 2 ), Tantalum Aluminum Carbide (Ta 3 AlC 2 ), chromium carbide aluminum (Cr 3 AlC 2 ), chromium gallium carbide (Cr 3 C 2 ), chromium gallium nitride (Cr 3 GaN 2 ), chromium germanium carbide (Cr 3 G JZ 2 ), chromium germanium nitride (Cr 3 N 2 ), chromium arsenic nitride (Cr 3 AA 2 ), chromium cadmium nitride (Cr 3 CdN 2 ), chromium indium nitride (Cr 3 InN 2 ), chromium tin nitride (Cr 3 Sn 2 ), Tantalum Aluminum Nitride (Ta 3 AlN 2 ) or Tantalum Silicon Carbide (Ta 3 SiC 2 ). Or, with M 4 AX 3 The material of the phase can be, for example, titanium aluminum carbide (Ti 4 AlC 3 ), titanium silicon carbide (Ti 4 SiC 3 ), titanium gallium carbide (Ti 4 C 3 ), titanium germanium nitride (Ti 4 N 3 ), titanium indium carbide (Ti 4 InC 3 ), titanium indium nitride (Ti 4 InN 3 ), vanadium aluminum carbide (V 4 AlC 3 ), vanadium aluminum nitride (V 4 AlN 3), Vanadium Silicon Nitride (V 4 SiC 3 ), vanadium gallium carbide (V 4 C 3 ), vanadium gallium nitride (V 4 GaN 3 ), Vanadium Germanium Carbide (V 4 G JZ 3 ), Vanadium Arsenic Nitride (V 4 AA 3 ), vanadium cadmium carbide (V 4 CdC 3 ), Vanadium Cadmium Nitride (V 4 CdN 3 ), Vanadium Indium Carbide (V 4 InC 3 ), Vanadium Indium Nitride (V 4 InN 3 ), Vanadium Tin Carbide (V 4 S N 3 ), Vanadium Tin Nitride (V 4 Sn 3 ), chromium carbide aluminum (Cr 4 AlC 3 ), chromium silicon nitride (Cr 4 S N 3 ), chromium germanium nitride (Cr 4 N 3 ), Tantalum Aluminum Carbide (Ta 4 AlC 3 ) or Tantalum Silicon Carbide (Ta 4 SiC 3 ), but the inventive concept is not limited thereto.

[0045] The first interconnection pattern 23 may be an oxide including a delafossite-based material. For example, the first interconnection pattern 23 may be an oxide having a structural formula of ABO. 2 Delafossite as an oxide. Delafossite can be composed of stacked edge-shared octahedral layers (BO 2 )- between the linear coordination A + layer formed by the hierarchical structure. Material A can be, for example, one of platinum (Pt), palladium (Pd), silver (Ag) or copper (Cu), and material B can be a transition metal such as chromium (Cr), cobalt (Co), iron (Fe), rhodium (Rh), aluminum (Al), gallium (Ga), scandium (Sc), indium (In), thallium (Tl), etc.

[0046] In an embodiment of the present inventive concept, the first interconnection pattern 23 may be, for example, platinum cobalt oxide (PtCoO 2 ), palladium cobalt oxide (PdCoO 2), strontium molybdenum oxide (SrMoO 3 ), strontium ruthenium oxide (Sr 2 RuO 4 ), platinum chromium oxide (PtCrO 2 ), palladium rhodium oxide (PdRhO 2 ), palladium chromium oxide (PdCrO 2 ), copper iron oxide (CuFeO 2 ), sodium cobalt oxide (NaCoO 2 ), lithium cobalt oxide (LiCoO 2 ), silver iron oxide (AgFeO 2 ), silver chromium oxide (AgCrO 2 ), copper chromium oxide (CuCrO 2 ) or silver nickel oxide (AgNiO 2 ), but the inventive concept is not limited thereto.

[0047] The first interconnection pattern 23 may be an intermetallic compound, and may include a topological semimetal material or the like.

[0048] Topological semimetal materials may have an electronic gapless phase with topological band crossing near the Fermi level. Topological semimetal materials may have surface states induced by such topology, and topological Dirac semimetals or topological Weyl semimetals may have a three-dimensional structure of graphene to have very high conductivity for each two-dimensional layer. Topological semimetal materials may have properties such as T 3 X, T 3 X 2 , TX, etc., wherein T is, for example, at least one of sodium (Na), cadmium (Cd), platinum (Pt), nickel (Ni), lanthanum (La), molybdenum (Mo), tungsten (W), aluminum (Al), iron (Fe), manganese (Mn) or cobalt (Co), and X is, for example, at least one of germanium (Ge), tin (Sn) or tellurium (Te), but the inventive concept is not limited thereto.

[0049] In an embodiment of the inventive concept, the first interconnection pattern 23 may be, for example, sodium bismuth (Na 3 Bi), cadmium arsenide (Cd 3 As 2 ), platinum telluride (PtTe 2 ), nickel telluride (NiTe 2 ), lanthanum strontium copper oxide (La 1.77 Sr 0.23 CuO 4 ), thallium molybdenum selenide (Tl(MoSe) 3), cerium antimony telluride (CeSbTe), tantalum arsenide (TaAs), tantalum selenide iodide (TaSe 4 ) 2 I), molybdenum tungsten telluride (Mo 1-x W x Te 2 ), lanthanum aluminum germanium (LaAlGe), tantalum iridium telluride (TaIrTe 4 ), molybdenum phosphide (MoP 2 ), Ytterbium manganese bismuth (YbMnBi 2 ), manganese germanium (Mn 3 Ge), gadolinium platinum bismuth (GdPtBi), cobalt tin sulfide (Co 3 Sn 2 S 2 ), europium cadmium arsenide (EuCd 2 As 2 ), molybdenum phosphide (MoP), tungsten carbide (WC), cobalt silicide (CoSi), rhodium silicide (RhSi), aluminum platinum (AlPt), palladium gallium (PdGa), palladium bismuth selenide (PdBiSe), calcium silver arsenide (CaAgAs), magnesium boride (MgB 2 ), platinum tin (PtSn 4 ), SrAs 3 ), lead tantalum selenide (PbTaSe 2 ), zirconium silicon sulfide (ZrSiS), indium bismuth (InBi), iridium oxide (IrO 2 ), ruthenium oxide (RuO 2 ), titanium boride (TiB 2 ), magnesium bismuth (Mg 3 Bi 2 ), cobalt manganese gallium (Co 2 MnGa) or tantalum silicon telluride (Ta 3 SiTe 6 ), but the inventive concept is not limited thereto.

[0050] The first interconnection pattern 23 may be a material having a hierarchical structure among boride materials, and may be, for example, osmium tungsten boride (BO 4 OsW), manganese boride (Mn 2 B), rhenium boride (ReB 2 ), Hafnium Cobalt Boride (HfCo 3 B 2 ), zirconium cobalt boride (ZrCo 3 B 2 ), yttrium cobalt boride (YCo 3 B 2 ), niobium iron boride (NbFeB), scandium cobalt boride (SCo 3 B 2) or any one of tantalum iron boride (TaFeB), but the inventive concept is not limited thereto.

[0051] In an embodiment of the present inventive concept, the first interconnect pattern 23 may be mainly one of a topological semimetal or a boride, and may include, for example, osmium ruthenium (OsRu), niobium platinum (NbPt), osmium tungsten boride (Bt), or a combination thereof. 4 OsW), Hafnium Nickel Antimonide (Hf 6 Nb 2 )、Zr-Aluminum-Cobalt (Zr 6 Al 2 Co), zirconium aluminum nickel (Zr 6 Al 2 Ni), manganese boride (Mn 2 B), scandium germanium rhodium (ScGeRh), rhenium boride (ReB 2 ), cobalt tin (CoSn), hafnium iron germanium (HfFeGe), titanium aluminum platinum (TiAlPt), hafnium aluminum platinum (Hf 6 Al 2 Pt), hafnium cobalt boride (HfCo 3 B 2 ), niobium gold (NbAu 2 ), copper telluride (CuTe), zirconium cobalt boride (ZrCo 3 B 2 ), hafnium germanium ruthenium (HfGeRu), yttrium cobalt boride (YCo 3 B 2 ), niobium iron boride (NbFeB), scandium phosphide ruthenium (ScPRu), titanium gallium palladium (TiGaPd), hafnium germanium osmium (HfGeOs), titanium gallium platinum (TiGaPt), hafnium silicon ruthenium (HfSiRu), scandium cobalt boride (ScCo 3 B 2 ), hafnium silicon osmium (HfSiOs), zirconium germanium osmium (ZrGeOs), zirconium silicon ruthenium (ZrSiRu) or tantalum iron boride (TaFeB) materials.

[0052] The material forming the first interconnect pattern 23 can form the same layered structure in a direction parallel to the XY plane (in-plane), and can have a layered structure in the Z direction perpendicular to the XY plane. The XY plane can be the upper surface of the lower insulating structure, for example, the deposition surface of the first interconnect pattern 23.

[0053] The electron mobility within the same layered structure can be very high, thereby rapidly reducing the resistivity, and the electron mobility between layers can be very low, thereby rapidly increasing the resistivity in directions other than the XY plane (out-of-plane).

[0054] A material having a hierarchical structure may be applied to the first interconnection pattern 23 to prevent an increase in resistance of a fine pattern by utilizing a significantly low resistivity in a direction (in-plane) parallel to the XY plane.

[0055] The first interconnection pattern 23 may include a first through hole 23 o therein.

[0056] The first through-hole 23 o may pass through from the upper surface to the lower surface of the first interconnection pattern 23 , and the diameter of the first through-hole 23 o may become smaller and smaller downward in the Z direction.

[0057] The first interconnection structure ( 23 and 25 ) may further include a conductive via 25 for connecting the first interconnection pattern 23 and the lower interconnection structure 13 of the lower structure LS.

[0058] The conductive via 25 may pass through the first through-hole 23 o and may directly contact the side surface of the first interconnection pattern 23 on the inner sidewall of the first through-hole 23 o .

[0059] The conductive path 25 may include a material different from that of the first interconnect pattern 23, and may be a material having an isotropic resistance characteristic. For example, the conductive path 25 may include, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), or tungsten (W) as a material having a resistivity in a similar range regardless of the stacking direction. Because the conductive path 25 includes a material having an isotropic resistance characteristic, the resistivity value of the conductive path 25 in a direction parallel to the XY plane (in-plane) (referred to as a first direction) is the same as the resistivity value of the conductive path 25 in a direction not parallel to the XY plane (out-of-plane) (referred to as a second direction). Therefore, the conductive path 25 can transmit current between different layers with low resistance, and therefore, the signal RC delay can be reduced.

[0060] The conductive path 25 and the first interconnection pattern 23 may have a contact interface that directly contacts the inner side wall of the first through hole 23o to contact the conductive path 25 in a first direction where the resistivity of the first interconnection pattern 23 is low, thereby significantly reducing the contact resistance. Therefore, the signal RC delay can be reduced. In other words, because the interconnection material of the first interconnection pattern 23 has an anisotropic resistance characteristic in which the resistivity is low in a plane (e.g., XY plane) and the resistivity is sharply high out of the plane, the contact surface with the conductive path 25 is formed in the plane of the first interconnection pattern 23 to have a low contact resistance. For example, the first interconnection pattern 23 may contact the conductive path 25 in a direction (in-plane) parallel to the XY plane (referred to as the first direction) to have a low contact resistance.

[0061] The conductive path 25 may also have a width that decreases in the downward direction depending on the shape of the first through hole 23o. The conductive path 25 may include an upper surface 25b, a lower surface 25c, and a side surface 25a connecting the upper surface 25b and the lower surface 25c.

[0062] Due to the area difference between the upper surface 25b and the lower surface 25c, the side surface 25a can be inclined at a predetermined angle (which can be a constant angle) in the first direction, and the horizontal height of the upper surface 25b can be equal to or higher than the upper surface of the first interconnection pattern 23, while the horizontal height of the lower surface 25c can be lower than the lower surface of the first interconnection pattern 23.

[0063] An upper etch stop layer 28 may be further included on the first interconnection pattern 23 .

[0064] When the conductive via 25 is formed by chemical mechanical polishing (CMP), the upper etch stop layer 28 may serve as a polishing stop layer.

[0065] The upper etch stop layer 28 may include a third through hole through which the conductive via 25 passes, and the third through hole may be aligned with the first through hole 23 o. An upper surface of the upper etch stop layer 28 may be coplanar with an upper surface 25 b of the conductive via 25.

[0066] The conductive path 25 may successively pass through the upper etch stop layer 28, the first interconnection pattern 23, and the first etch stop layer 19, and may directly contact the inner sidewall of the first through hole 23o of the first interconnection pattern 23 and the side surface 25a of the conductive path 25 to form a contact interface. In this case, the contact interface is a contact surface between the first interconnection pattern 23 and the conductive path 25, and the first interconnection pattern 23 and the conductive path 25 may contact each other in a direction (in-plane) parallel to the XY plane (referred to as a first direction) to have a low contact resistance.

[0067] The first interconnection insulating layer 21 may be disposed in a space between the first interconnection patterns 23 .

[0068] The first interconnection insulating layer 21 may be embedded to space the first interconnection patterns 23 apart from each other, and the first interconnection insulating layer 21 may have a top surface coplanar with a top surface of the upper etch stop layer 28. The first interconnection insulating layer 21 may be formed of the same material as that of the intermediate insulating layer 20, or may be formed of a silicon oxide (SiO 2 ) and other insulating materials.

[0069] The lower surface of the first interconnection insulating layer 21 may be located at a level lower than that of the lower surface of the first interconnection pattern 23. When the first etch stop layer 19 includes a first region located below the first interconnection pattern 23 and a different region (e.g., a second region disposed below the first interconnection insulating layer 21), a portion of the second region may be removed, thereby forming a step difference of a predetermined depth h1. For example, the first region may be located below the first interconnection pattern 23 and the second region may exclude the first region. Therefore, the thickness of the first etch stop layer 19 may vary depending on the region, so that the level of the upper surface of the first region is higher than the level of the upper surface of the second region, and the level of the lower surface of the first region is equal to the level of the lower surface of the second region.

[0070] Due to the step difference of the first etch stop layer 19, the lower surface of the first interconnection insulating layer 21 may be formed to be lower than the lower surface of the first interconnection pattern 23, thereby generating insulation so that there is no residual metal between the first interconnection patterns 23. In this case, during the process of removing a portion of the interconnection layer to form the first interconnection pattern 23, an etching process may be performed to first remove a portion of the interconnection layer until the upper surface of the first etch stop layer 19, and secondly, additional etching may be performed to over-etch the first etch stop layer 19, thereby forming a step difference of the depth h1.

[0071] The first interconnection pattern 23 and the first interconnection insulating layer 21 may further include a second insulating structure ( 29 , 30 , and 31 ).

[0072] Like the first insulating structure 16 , the second insulating structure ( 29 , 30 , and 31 ) may have a stack structure of an intermediate insulating layer 30 , a first etch stop layer 31 on the intermediate insulating layer 30 , and a second etch stop layer 29 below the intermediate insulating layer 30 .

[0073] The second insulating structure ( 29 , 30 , and 31 ) may further include an upper interconnection structure 36 .

[0074] The thickness and material of each layer of the second insulating structure (29, 30, and 31) may be the same as those of each layer of the first insulating structure 16. For example, the first etch stop layer 31 and the second etch stop layer 29 may have the same thickness, but the inventive concept is not limited thereto, and the intermediate insulating layer 30 may be formed thicker than the first etch stop layer 31 and the second etch stop layer 29.

[0075] When the interconnect structure connected by the conductive via 25 is the lower interconnect structure 13 disposed below the first interconnect pattern 23 , the conductive via 25 may pass through the first interconnect pattern 23 and may extend in a downward direction.

[0076] In order to allow the conductive via 25 to pass through, a through hole aligned with the first through hole 23o and exposing the upper surface of the lower interconnect structure 13 may be provided in the first insulating structure 16. For example, the first etch stop layer 19, the intermediate insulating layer 20, and the second etch stop layer 18 may include a through hole aligned with the first through hole 23o and through which the conductive via 25 passes.

[0077] The conductive path 25 may integrally extend from the upper etch stop layer 28 to the upper surface of the lower interconnection structure 13, and a contact interface with the first interconnection pattern 23 may be provided in a first through-hole 23o that passes through the first interconnection pattern 23 to form a wedge-shaped conductive structure (23 and 25). The conductive path 25 having a wedge-shaped structure may provide a low contact resistance with the first interconnection pattern 23 at a contact interface provided in the first through-hole 23o that passes through the first interconnection pattern 23.

[0078] When the interconnection structure connected to the conductive via 25 is an upper interconnection structure 36 disposed above the first interconnection pattern 23 , an upper conductive via 35 passing through the first interconnection pattern 23 to be connected to the upper interconnection structure 36 may be further included.

[0079] An upper through-via aligned with the first through-via 23 o of the first interconnection pattern 23 may be provided in the second insulating structure ( 29 , 30 , and 31 ) so that the upper conductive via 35 extends in an upward direction.

[0080] The upper conductive path 35 can extend integrally from the first etch stop layer 19 to the first etch stop layer 31 of the second insulating structure (29, 30 and 31), and the contact interface with the first interconnection pattern 23 can be set on the inner side wall of the first through hole 23o of the first interconnection pattern 23, thereby forming a wedge-shaped conductive structure.

[0081] When upper conductive via 35 extends in an upward direction to connect to upper interconnect structure 36, a lower surface of upper conductive via 35 may be coplanar with a lower surface of first etch stop layer 19, and when conductive via 25 extends in a downward direction to connect to lower interconnect structure 13, an upper surface of conductive via 25 may be coplanar with an upper surface of upper etch stop layer 28.

[0082] Various modification examples of the components of the above-described embodiments will be described below. Various modification examples of the components of the above-described embodiments described below will be explained focusing on the components to be modified or replaced. In addition, the components that may be modified or replaced below may be described with reference to the drawings mentioned below, but the components that may be modified or replaced may be combined with each other or with the above-described components to constitute the semiconductor device 1 according to the embodiments conceived by the present invention.

[0083] Figure 3 It can be schematically shown along Figure 1The section taken from line II' is shown Figure 2A and Figure 2B sectional view of a modified example of the conductive path shown in FIG.

[0084] In the modified example, refer to Figure 3 ,like Figure 2A and Figure 2B The conductive path 25 shown in FIG. 2 may include a barrier material layer 25d and a path material layer 25e. For example, the barrier material layer 25d may be a conductive barrier layer formed on the side surface of the path material layer 25e. For example, the conductive barrier layer is disposed between the inner sidewall of the first through hole 23o and the path material layer 25e to directly contact the first interconnection pattern 23 and the path material layer 25e.

[0085] The passage material layer 25e may be formed by filling the through hole in which the first to third through holes and the through hole of the first insulating structure 16 are integrally connected, and may be a metal material such as ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), tungsten (W), aluminum (Al), etc. A barrier material layer 25d may be further completely included on the side surface 25a and the lower surface 25c of the passage material layer 25e. The barrier material layer 25d may be formed to protect the insulating layers 18, 19 and 20 from the diffusion of certain metals, and may include, for example, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN). In this case, the contact interface is a contact surface between the first interconnection pattern 23 and the barrier material layer 25d, and the first interconnection pattern 23 and the barrier material layer 25d may contact each other in a direction (in-plane) parallel to the XY plane (referred to as a first direction) to have a low contact resistance.

[0086] Figure 4 It can be schematically shown along Figure 1 The section taken from line II' is shown Figure 2A and Figure 2B sectional view of a modified example of the conductive path shown in FIG.

[0087] In the modified example, refer to Figure 4 ,like Figure 2A and Figure 2B The conductive via 25 shown in FIG. 2 may include a barrier material layer 25d and a via material layer 25e.

[0088] The path material layer 25e may be formed by filling the through hole in which the first to third through holes and the through hole of the first insulating structure 16 are integrally connected, and may be a metal material such as ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), tungsten (W), aluminum (Al), etc. A barrier material layer 25d may be further completely included on a portion of the side surface 25a of the path material layer 25e and the lower surface 25c. The barrier material layer 25d may not be disposed on the side surface of the first through hole 23o, but may be selectively disposed in a region facing the insulating layer. For example, the barrier material layer 25d may be formed on the side surface of the path material layer 25e from the first etch stop layer 19 to the second etch stop layer 18 to protect the insulating layer from the diffusion of certain metals, and may include, for example, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). Therefore, the barrier material layer 25d may prevent the increase of the contact resistance on the contact surface between the first interconnect pattern 23 and the conductive path 25. In this case, the contact interface is a contact surface between the first interconnection pattern 23 and the via material layer 25e, and the first interconnection pattern 23 and the via material layer 25e may contact each other in a direction (in-plane) parallel to the XY plane (referred to as a first direction) to have low contact resistance.

[0089] Figure 5 It can be schematically shown along Figure 1 The section taken from line II' is shown Figure 2A and Figure 2B 2 is a cross-sectional view of a modified example of the first interconnection pattern 23 shown in FIG.

[0090] In the modified example, refer to Figure 5 , in such Figure 2A and Figure 2B 2 is removed, the upper surface of the first interconnection pattern 23 may be coplanar with the upper surface of the conductive path 25. In this case, during the planarization process of etching the insulating layer until the upper etch stop layer 28 is exposed, when the planarization is further performed until the upper surface of the first interconnection pattern 23 is exposed, the upper etch stop layer 28 may be completely removed.

[0091] In this way, when the upper surface of the first interconnection pattern 23 and the upper surface of the conductive path 25 are coplanar, the thickness of the semiconductor device 1 can be reduced, miniaturization thereof can be achieved, and the length of the conductive path 25 can be minimized.

[0092] Figure 6 It can be schematically shown along Figure 1 The section taken from line II' is shown Figure 2A and Figure 2B2 is a cross-sectional view of a modified example of the first interconnection pattern 23 shown in FIG.

[0093] In the modified example, refer to Figure 6 ,like Figure 2A and Figure 2B The first interconnection pattern 23 shown in FIG. 2 may further include an interconnection seed layer 23 a on a lower surface thereof.

[0094] The first interconnection pattern 23 may include a stack structure in which an interconnection seed layer 23 a and a first interconnection material layer 23 b located on the interconnection seed layer 23 a are arranged.

[0095] As described above, the first interconnect material layer 23 b may include a material forming a hierarchical structure to have anisotropic resistance characteristics.

[0096] The first interconnection pattern 23 may further include an interconnection seed layer 23 a for controlling a growth direction of crystals of the first interconnection material layer 23 b during deposition in a process for forming the hierarchical structure.

[0097] The interconnect seed layer 23 a may be implemented with a crystalline material, and may be a polycrystalline material layer such as polycrystalline silicon (p-Si) or the like.

[0098] In this manner, after forming the interconnect seed layer 23a, deposition can be performed to reduce the number of times electrons cross the crystal plane when moving in the plane, and thus, further reduction in the in-plane resistivity can be achieved.

[0099] Figure 7 It can be schematically shown along Figure 1 The section taken from line II' is shown Figure 2A and Figure 2B 2 is a cross-sectional view of a modified example of the first etching stopper layer 19 shown in FIG.

[0100] In the modified example, refer to Figure 7 , the first etch stop layer 19 may be selectively disposed only under the first interconnection pattern 23 .

[0101] The first etch stop layer 19 may not be disposed in the spaced region between the first interconnection patterns 23, so that the upper first interconnection insulating layer 21 and the lower intermediate insulating layer 20 may directly contact each other. In this case, during the process of removing a portion of the interconnection layer to form the first interconnection pattern 23, an etching process may be performed to first remove a portion of the interconnection layer until the upper surface of the first etch stop layer 19, and secondly, additional etching may be performed to completely remove the first etch stop layer 19, thereby exposing the lower intermediate insulating layer 20.

[0102] In this manner, when the first interconnection pattern 23 is patterned so that the first etch stop layer 19 is completely removed, the remaining metal of the first interconnection pattern 23 may reduce leakage current occurring and remaining above the first etch stop layer 19 .

[0103] Figure 8 It can be schematically shown along Figure 1 The section taken from line II' is shown Figure 2A and Figure 2B 2 is a cross-sectional view of a modified example of the conductive path 25 shown in FIG.

[0104] In the modified example, refer to Figure 8 The semiconductor device 1 may further include an intermediate insulating structure ( 8 , 9 , and 10 ) and a second interconnection pattern 12 located below the first interconnection pattern 23 .

[0105] The intermediate insulating structure (8, 9, and 10) may be disposed below the first insulating structure 16, and may further include a second interconnection pattern 12 between the first insulating structure 16 and the intermediate insulating structure (8, 9, and 10) and a second interconnection insulating layer 11 separating the second interconnection pattern 12.

[0106] The layer structure, thickness and material of each layer of the intermediate insulating structure (8, 9 and 10) may be the same as the layer structure, thickness and material of each layer of the first insulating structure 16 described above. Like the first insulating structure 16, the intermediate insulating structure (8, 9 and 10) may have a stacked structure of an intermediate insulating layer 10 and a first etch stop layer 9 located on the intermediate insulating layer 10 and a second etch stop layer 8 located below the intermediate insulating layer 10. For example, the first etch stop layer 9 and the second etch stop layer 8 may have the same thickness, but the inventive concept is not limited thereto, and the intermediate insulating layer 10 may be formed to be thicker than the first etch stop layer 9 and the second etch stop layer 8.

[0107] The material, layer structure and thickness of each layer of the second interconnection pattern 12 and the material, layer structure and thickness of each layer of the second interconnection insulating layer 11 may be respectively the same as the material, layer structure and thickness of each layer of the first interconnection pattern 23 and the material, layer structure and thickness of each layer of the first interconnection insulating layer 21.

[0108] The second interconnection pattern 12 may also include a material having anisotropic resistance characteristics, and the conductive vias ( 26 and 27 ) may each form a contact interface on the inner sidewall of the through-hole in the second interconnection pattern 12 .

[0109] The conductive path 26 may be a structure for electrically connecting the first interconnection pattern 23 and the second interconnection pattern 12 , may include a material different from that of the first interconnection pattern 23 and the second interconnection pattern 12 , and may integrally pass from the upper surface of the second interconnection pattern 12 to the lower surface of the first interconnection pattern 23 .

[0110] The conductive path 26 between the two layers of the interconnection patterns 23 and 12 may not contact the interconnection patterns 23 and 12 in the vertical direction, and the inner sidewalls of the through holes of each first interconnection pattern 23 and the inner sidewalls of the through holes of each second interconnection pattern 12 may contact the conductive path 26 in the lateral direction.

[0111] When the multilayer interconnection pattern is implemented as a fine pattern with a width of about 10 nm or less, in order to prevent a rapid increase in the resistance of each interconnection pattern, a material having anisotropic resistance characteristics may be applied to each interconnection pattern. In this case, the conductive path 26 may have a wedge-shaped structure that passes through the multilayer interconnection pattern to contact the conductive path 26 in a plane, which has a low resistance due to the anisotropic resistance characteristics. In this case, the contact interface is a contact surface between the first interconnection pattern 23 and the conductive path 26 and between the second interconnection pattern 12 and the conductive path 26. The first interconnection pattern 23 and the second interconnection pattern 12 may contact the conductive path 26 in a direction (in-plane) parallel to the XY plane (referred to as a first direction) to have a low contact resistance.

[0112] When passing through the first interconnection pattern 23 and the second interconnection pattern 12, Figure 8 In the embodiment, the length h2 of the conductive path 26 may be longer than the length h3 of the conductive path ( 27 and 35 ) passing through the second interconnection pattern 12 of the single layer or the first interconnection pattern 23 of the single layer.

[0113] exist Figure 8 , although the second interconnection pattern 12 is shown as a lower interconnection structure disposed below the first interconnection pattern 23 based on the first interconnection pattern 23, it can be understood that the second interconnection pattern 12 can be formed on (above) the first interconnection pattern 23 based on the first interconnection pattern 23. For example, the second interconnection pattern 12 can be an upper interconnection structure or a lower interconnection structure having a second interconnection pattern 12 including a material that is the same as that of the first interconnection pattern 23. The second interconnection pattern 12 may include a through-hole aligned with the first through-hole 23o. The conductive path 26 may pass through the first through-hole 23o and the through-hole of the second interconnection pattern 12, and may connect the first interconnection pattern 23 and the second interconnection pattern 12.

[0114] Next, refer to Fig. 9 and Fig.10 , will describe including reference Figures 1 to 8An illustrative example of the semiconductor device 1 of any one of the embodiments is described. Fig. 9 may be a cross-sectional view schematically showing an illustrative example of a semiconductor device 1 according to an embodiment of the inventive concept.

[0115] The semiconductor device 1 may include: a circuit element TR including a transistor and located on a semiconductor substrate; and contact plugs 90 a , 90 b , and 90 c electrically connected to the circuit element TR.

[0116] The circuit element TR may include a channel region CH located on the active region AR, a gate structure G located on the channel region CH, and source / drain regions S / D located on the active region AR and close to the gate structure G.

[0117] In an embodiment of the present inventive concept, the channel region CH may include a plurality of channel layers stacked in a vertical direction (Z) perpendicular to the upper surface of the semiconductor substrate and spaced apart from each other, the gate structure G may be disposed across the plurality of channel layers and surrounding each of the plurality of channel layers, and the plurality of channel layers of the channel region CH may be disposed between the source / drain regions S / D. Thus, the circuit element TR may include a multi-bridge channel field effect transistor (FET) (MBCFET TM ) structured transistor, which may be a full-surround gate field effect transistor. In an embodiment of the inventive concept, the circuit device TR may include a fin field effect transistor (FinFET) device, a metal oxide semiconductor field effect transistor (MOSFET) device with a vertical channel, or a planar MOSFET device.

[0118] The contact plug 90 a may be provided to penetrate into the source / drain region S / D to directly contact the source / drain region S / D, and may function as a source / drain contact.

[0119] The semiconductor device 1 may further include a lower insulating structure ( 110 , 120 , and 121 ) located on the upper surface of the semiconductor substrate.

[0120] The lower insulating structure (110, 120, and 121) may include a first lower insulating layer 110 defining an active region AR, a second lower insulating layer 120 located on the first lower insulating layer 110, and a third lower insulating layer 121 located on the second lower insulating layer 120 and the circuit element TR. At least one of the first lower insulating layer 110, the second lower insulating layer 120, and the third lower insulating layer 121 may include silicon oxide (SiO 2 For example, each of the first lower insulating layer 110, the second lower insulating layer 120, and the third lower insulating layer 121 may be made of silicon oxide (SiO 2 )form.

[0121] The lower insulating structure ( 110 , 120 , and 121 ) may further include a lower etch stop layer 124 on the third lower insulating layer 121 and an intermediate insulating layer 127 on the lower etch stop layer 124 .

[0122] The intermediate insulating layer 127 may be, for example, silicon oxide (SiO 2 ), tetraethyl orthosilicate (TEOS) oxide, carbon-doped silicon oxide (SiOCH), or silicon oxycarbide (SiOC), but the inventive concept is not limited thereto.

[0123] The lower etch stop layer 124 may be an insulating material including, for example, at least one of aluminum nitride (AlN), silicon nitride (SiN), silicon boronitride (SiBN), or silicon carbonitride (SiCN).

[0124] The semiconductor device 1 may further include a first insulating structure ( 148 and 150 ) located on the lower insulating structure ( 110 , 120 , and 121 ).

[0125] The first insulating structure ( 148 and 150 ) may include intermetallic barrier layers 148 and intermetallic insulating layers 150 alternately and repeatedly stacked on the lower insulating structure ( 110 , 120 , and 121 ).

[0126] The first insulating structure ( 148 and 150 ) may have a thickness ranging from about 0.1 μm to about 0.5 μm.

[0127] The lower etch stop layer 124 and the intermetal barrier layer 148 may have the same thickness, but the inventive concept is not limited thereto, and the intermetal insulating layer 150 may be formed thicker than the lower etch stop layer 124 and the intermetal barrier layer 148 .

[0128] Each intermetallic barrier layer 148 may include, for example, at least one of aluminum nitride (AlN), silicon nitride (SiN), silicon boronitride (SiBN), or silicon carbonitride (SiCN). For example, each intermetallic barrier layer 148 may include a first layer and a second layer, at least one of the first layer or the second layer may include aluminum nitride (AlN), and the other one thereof may include silicon carbonitride (SiCN).

[0129] Each intermetallic barrier layer 148 may have a thickness of about 3 nm to about 10 nm.

[0130] The intermetallic insulating layer 150 may include silicon oxide (SiO 2 ) of a first material having a first dielectric constant with a low dielectric constant. The first material may be a low dielectric constant. For example, the dielectric constant of the first material may have a value in the range of about 2.5 to 2.7. Silicon oxide (SiO 2) may have a dielectric constant of about 3.9 to about 4.2, but depending on the formation of silicon oxide (SiO 2 ) method, silicon oxide (SiO 2 ) can have a dielectric constant less than 3.9 or greater than 4.2.

[0131] The semiconductor device 1 may include an interconnect structure.

[0132] The interconnect structure may be disposed in the insulating structure (148 and 150) and may include a plurality of interconnect patterns at different levels. For example, the interconnect structure may include a first metal interconnect pattern M1, a second metal interconnect pattern M2, a third metal interconnect pattern M3, a fourth metal interconnect pattern M4, and a fifth metal interconnect pattern M5 arranged at different levels. Among the first metal interconnect pattern M1, the second metal interconnect pattern M2, the third metal interconnect pattern M3, the fourth metal interconnect pattern M4, and the fifth metal interconnect pattern M5, each of the second metal interconnect pattern M2, the third metal interconnect pattern M3, the fourth metal interconnect pattern M4, and the fifth metal interconnect pattern M5 may include a passage portion V and an interconnect portion L located on and extending from the passage portion V. The first metal interconnect pattern M1 disposed at the lowest level may include a first interconnect portion L1 and a first conductive path V1 passing through the first interconnect portion L1. The third metal interconnect pattern M3 disposed on the second metal interconnect pattern M2 may include a third interconnect portion L3 and a third conductive path (passage portion) V3 connecting the third interconnect portion L3 to the second metal interconnect pattern M2. The first interconnect portion L1 is similar to Figure 2A and Figure 2B The first interconnection pattern 23 shown in FIG. 1 is therefore also referred to as a first interconnection pattern 123 .

[0133] Each of the second metal interconnection pattern M2, the third metal interconnection pattern M3, the fourth metal interconnection pattern M4, and the fifth metal interconnection pattern M5 may include a conductive material pattern 170 and a conductive barrier layer 171 covering the side surface and the bottom surface of the conductive material pattern 170. The conductive material pattern 170 may include a copper (Cu) material. The conductive barrier layer 171 may include, for example, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

[0134] Each of the second metal interconnection pattern M2, the third metal interconnection pattern M3, the fourth metal interconnection pattern M4, and the fifth metal interconnection pattern M5 passes through one intermetallic barrier layer 148 and one intermetallic insulating layer 150, which are sequentially stacked. For example, any one of the second metal interconnection pattern M2, the third metal interconnection pattern M3, the fourth metal interconnection pattern M4, and the fifth metal interconnection pattern M5 may pass through one intermetallic insulating layer 150 and one intermetallic barrier layer 148 contacting a lower surface of the one intermetallic insulating layer 150. In an embodiment of the inventive concept, a lower surface of any one of the second metal interconnection pattern M2, the third metal interconnection pattern M3, the fourth metal interconnection pattern M4, and the fifth metal interconnection pattern M5 may be coplanar with a lower surface of one intermetallic barrier layer 148, but the inventive concept is not limited thereto.

[0135] In this case, the first metal interconnection pattern M1 located on the lower insulating structure ( 110 , 120 , and 121 ) may have a structure different from those of the second to third to fourth to fifth metal interconnection patterns M2 , M3 , M4 , and M5 .

[0136] The first metal interconnection pattern M1 may include a first interconnection portion L1 on the lower etch stop layer 124 and a first conductive via V1 passing through the first interconnection portion L1 up to the lower etch stop layer 124 .

[0137] The first interconnection portion L1 and the first conductive path V1 may include different materials, and the first conductive path V1 may pass through the first interconnection portion L1, may extend in a downward direction while directly contacting the first interconnection portion L1 on the inner sidewall of the through hole, and may contact the upper surface of the second contact plug 90b. For example, the first conductive path V1 may serve as the third contact plug 90c.

[0138] refer to Fig. 9 and / or Fig.10In an embodiment of the present inventive concept, the second contact plug 90b may be referred to as a contact structure, the third contact plug 90c may be referred to as a conductive path, the third lower insulating layer 121 may be referred to as an interlayer insulating layer, the intermediate insulating layer 127 and the intermetallic barrier layer 148 may be referred to as an intermediate insulating structure together, and the first interconnection portion L1 or 123 may be referred to as a first interconnection pattern. The contact structure 90b may be connected to the active region AR and may pass through the interlayer insulating layer 121. The intermediate insulating structure 127 / 148 may have a first hole and may be disposed on the interlayer insulating layer 121. The first interconnection pattern 123 may have a second hole aligned with the first hole, may be disposed on the intermediate insulating structure 127 / 148, and may have an anisotropic resistance characteristic, and the conductive path 90c may pass through the first hole and the second hole to connect to the contact structure 90b, and be connected to the first interconnection pattern 123 through the inner sidewall of the second hole.

[0139] refer to Fig. 9 and / or Fig.10 In an embodiment of the present inventive concept, the intermetallic barrier layer 148 may be referred to as a first etch stop layer. The intermediate insulating structure 127 / 148 may include an intermediate insulating layer 127 and a first etch stop layer 148 disposed between the intermediate insulating layer 127 and the first interconnection pattern 123, wherein the first etch stop layer 148 may include a through hole aligned with the first hole and through which the conductive path 90c passes.

[0140] The pattern of the first interconnection portion L1 may extend in parallel in one direction parallel to the upper surface of the intermediate insulating layer 127 on a plane (XY plane).

[0141] The first metal interconnection pattern M1 may have a smaller line width and interconnection thickness than the above metal interconnection patterns M2 , M3 , M4 , and M5 , and may have a width of, for example, about 10 nm or less.

[0142] The first interconnect L1 may include a material having anisotropic resistance properties. The material having anisotropic resistance properties may be defined as a first resistivity value of the first interconnect L1 in a direction parallel to the XY plane (in-plane) being different from a second resistivity value of the first interconnect L1 in a direction not parallel to the XY plane (out-of-plane). For example, the second resistivity value may be tens to hundreds of times greater than the first resistivity value.

[0143] The first interconnection portion L1 may be a multi-element material having anisotropic resistance characteristics, and may be a material in which a plurality of elements in the material form a hierarchical structure and are combined to have different characteristics between layers.

[0144] like Figures 1 to 8As shown, the first interconnection portion L1 may form the same layered structure in a direction (in-plane) (first direction) parallel to the XY plane which may be the deposition surface of the first interconnection portion L1, and may have a layered structure in the Z direction perpendicular to the XY plane.

[0145] The electron mobility in the same layered structure may be very high to rapidly reduce the resistivity, and the electron mobility between layers may be very low to rapidly increase the resistivity in a direction (out-of-plane) (second direction) different from the XY plane.

[0146] A material having a hierarchical structure may be applied to the first interconnection portion L1 to prevent an increase in resistance of a fine pattern by utilizing a significantly low resistivity in a direction parallel to the XY plane (in-plane). A through hole may be included in the first interconnection portion L1.

[0147] The first conductive path V1 may pass through the through hole and may directly contact the side surface of the first interconnection portion L1 on the inner sidewall of the through hole. The first conductive path V1 may include a material different from that of the first interconnection portion L1 and may include, for example, cobalt (Co), ruthenium (Ru), molybdenum (Mo), copper (Cu), aluminum (Al), or tungsten (W).

[0148] The first conductive path V1 and the first interconnection portion L1 may have a contact interface directly contacting the inner sidewall of the through hole to contact the first conductive path V1 in the first direction where the resistivity of the first interconnection portion L1 is low, thereby significantly reducing the contact resistance. Therefore, the signal RC delay can be reduced.

[0149] An etch stop layer 128 may be further included on the first interconnection portion L1 .

[0150] When the first conductive via V1 is formed by chemical mechanical polishing (CMP), the etch stop layer 128 may be used as a polishing stop layer.

[0151] The etch stop layer 128 may include a through hole through which the first conductive via V1 may pass, and the through hole of the etch stop layer 128 may be aligned with the through hole of the first interconnection portion L1. The upper surface of the etch stop layer 128 may be coplanar with the upper surface of the first conductive via V1.

[0152] The lowermost intermetallic barrier layer 148 may include a first region located below the first interconnection portion L1 and a different region (e.g., a second region disposed below the lowermost intermetallic insulating layer 150), and a portion of the second region may be removed to form a step difference of a predetermined depth. Due to the step difference of the lowermost intermetallic barrier layer 148, the lower surface of the lowermost intermetallic insulating layer 150 may be formed to be lower than the lower surface of the first interconnection portion L1, thereby generating insulation so that there is no residual metal between the first interconnections L1.

[0153] The first conductive path V1 may successively pass through the etch stop layer 128, the first interconnect portion L1, the first intermetallic barrier layer 148, the intermediate insulating layer 127 and the lower etch stop layer 124, may form a contact interface with the first interconnect portion L1 on the inner side wall of the through hole of the first interconnect portion L1, and may be connected to the second contact plug 90b.

[0154] The first interconnection portion L1 may be disposed in the first intermetallic insulating layer 150, and the first conductive via V1 protruding under the first interconnection portion L1 may pass through the intermediate insulating layer 127 to be connected to the second contact plug 90b. In an embodiment of the inventive concept, the intermediate insulating layer 127 may be omitted.

[0155] In this way, in the semiconductor device 1 including the transistor and the multilayer interconnection structure, a material having anisotropic resistance characteristics having very low in-plane resistivity starting from the lower interconnection structure to which a fine pattern having an interconnection width of about 10 nm or less is applied can be applied. In order to maintain the effect of very low resistivity, a wedge-shaped via structure can be applied so that the connection between the first interconnection portion L1 and the first conductive via V1 is made along the side surface thereof.

[0156] Fig.10 It can be shown Fig. 9 sectional view of a modified example of the interconnect structure shown in FIG.

[0157] In the modified example, refer to Fig.10 , the semiconductor device 1 may include a second metal interconnection pattern M2 located on the first metal interconnection pattern M1, the second metal interconnection pattern M2 having a second interconnection portion L2 also applied with a material having anisotropic resistance characteristics.

[0158] An intermediate insulating layer 127 may be further disposed on the first metal interconnection pattern M1, and may include a second interconnection portion L2 on the intermediate insulating layer 127 and a wedge-shaped second conductive path V2 passing therethrough. For example, in addition to the intermediate insulating layer 127 formed on the lower etch stop layer 124 and below the first interconnection portion L1 of the first metal interconnection pattern M1, the intermediate insulating layer 127 may be further formed on one intermetallic barrier layer 148 above the first metal interconnection pattern M1.

[0159] The thickness and material of the intermediate insulating layer 127 may be the same as those described above.

[0160] The material, layer structure and width of each layer of the second interconnection portion L2 may be the same as those of each layer of the first interconnection portion L1. For example, the second interconnection portion L2 may also include a material having anisotropic resistance characteristics, and a contact interface may be formed on the inner sidewalls of the through-holes in the second conductive path V2 and the second interconnection portion L2.

[0161] The second conductive path V2 may be a structure for electrically connecting the first interconnection portion L1 and the second interconnection portion L2, and may integrally pass through from the upper surface of the second interconnection portion L2 to the lower surface of the first interconnection portion L1. The first interconnection portion L1 may include a plurality of through holes so that the first conductive path V1 of the first metal interconnection pattern M1 and the second conductive path V2 of the second metal interconnection pattern M2 pass through while being spaced apart from each other.

[0162] Between the two layers of the interconnections L1 and L2, the contact interface between the second conductive via V2 and the interconnections L1 and L2 may not be formed in the vertical direction but may be disposed on the inner sidewall of the through hole in the lateral direction.

[0163] When the multilayer interconnection pattern is implemented with a fine pattern having a width of about 10nm or less, a material having anisotropic resistance characteristics may be applied to each interconnection pattern to prevent a rapid increase in resistance of each interconnection pattern. In this case, the interconnection structure may have a wedge-shaped structure passing through the multilayer interconnection pattern to contact the conductive paths (V1 and V2) in a plane, wherein the multilayer interconnection pattern has a low resistance due to the anisotropic resistance characteristics. For example, a first conductive path V1 having a wedge-shaped structure may provide a low contact resistance with the first interconnection portion L1 at a contact interface disposed in a first through hole passing through the first interconnection portion L1. A second conductive path V2 having a wedge-shaped structure may provide a low contact resistance with the first interconnection portion L1 at a contact interface disposed in a second through hole passing through the first interconnection portion L1, and may provide a low contact resistance with the second interconnection portion L2 at a contact interface disposed in a third through hole passing through the second interconnection portion L2.

[0164] Next, refer to Figure 1 and FIG. 11A to FIG. 11M , an illustrative example of a method of forming a semiconductor device 1 according to an embodiment of the inventive concept will be described. Figures 11A to 11M It can be schematically shown that the Figure 1 Cross-sectional view of a portion of.

[0165] refer to Figure 1 and Fig.11A , a lower structure LS may be formed. The formation of the lower structure LS may include forming a first lower insulating layer 6 on the substrate 5, forming a lower interconnection structure 13 in the first lower insulating layer 6, and forming a first insulating structure 16 covering the first lower insulating layer 6 and the lower interconnection structure 13. The first lower insulating layer 6 may include silicon oxide (SiO 2 ) or low-κ dielectrics.

[0166] The lower interconnect structure 13 may include an interconnect material layer 13b and a barrier material layer 13a covering the side surface and the bottom surface of the interconnect material layer 13b. The interconnect material layer 13b may include copper (Cu), and the barrier material layer 13a may include, for example, at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). The first insulating structure 16 may sequentially include a second etch stop layer 18 as a layered structure, an intermediate insulating layer 20 located on the second etch stop layer 18, and a first etch stop layer 19 located on the intermediate insulating layer 20.

[0167] The first etch stop layer 19 and the second etch stop layer 18 may be formed of an insulating material including at least one of aluminum nitride (AlN), silicon nitride (SiN), silicon boron nitride (SiBN), or silicon carbonitride (SiCN), but the present inventive concept is not limited thereto. For example, the first etch stop layer 19 and the second etch stop layer 18 may be formed of an insulating material including at least one of aluminum nitride (AlN), silicon nitride (SiN), silicon boron nitride (SiBN), or silicon carbonitride (SiCN). 2 ) are formed by different insulating materials.

[0168] The intermediate insulating layer 20 may be made of silicon oxide (SiO 2 ) or tetraethyl orthosilicate (TEOS) oxide, or may be formed of carbon-doped silicon oxide (SiOCH) or silicon oxycarbide (SiOC).

[0169] The intermediate insulating layer 20 and the first and second etch stop layers 19 and 18 may form a first insulating structure 16 .

[0170] refer to Figure 1 and Fig. 11B , a first interconnection layer 23 ′ may be formed on the first etch stop layer 19 (eg, on the first insulating structure 16 ).

[0171] The first interconnect layer 23' may include a material having anisotropic resistance characteristics. The material having anisotropic resistance characteristics may be defined as a first resistivity value of the first interconnect layer 23' in a direction parallel to the XY plane (in-plane) being different from a second resistivity value of the first interconnect layer 23' in a direction not parallel to the XY plane (out-of-plane). For example, the second resistivity value may be several tens to several hundreds times greater than the first resistivity value.

[0172] The first interconnection layer 23 ′ may be a multi-element material having anisotropic resistance characteristics, and may be a material in which a plurality of elements in the material form a hierarchical structure and are combined to have different characteristics between layers.

[0173] On the first etch stop layer 19 , the first interconnection layer 23 ′ may be formed by depositing a multi-element material forming the first interconnection layer 23 ′.

[0174] In this case, when forming the first interconnection layer 23', in order to form a hierarchical structure, the multi-element material may be deposited to have a predetermined thickness by sputtering and then sintered by heat treatment at a high temperature. In this case, the heat treatment temperature may be in the range of about 700°C to about 800°C.

[0175] Alternatively, after performing atomic layer deposition (ALD) to form a hierarchical structure, energy can be injected by plasma or heat treatment to control the crystal direction to induce crystal growth in a desired direction. In this case, energy injection can be performed alternately with the formation of each layer, but energy injection can be performed once after all first interconnect layers 23' are stacked.

[0176] The first interconnect layer 23' may include a conductive material having at least one of an intermetallic compound, an oxide, a carbide, a nitride, or a boride. For example, the first interconnect layer 23' may be a carbide or a nitride, and may be a material having a MAX phase. For example, the first interconnect layer 23' may be an oxide including a delafossite material. For example, the first interconnect layer 23' may be an intermetallic compound, and may include a topological semimetal material, etc. For example, the first interconnect layer 23' may be a boride material having a hierarchical structure.

[0177] When the first interconnect layer 23' is formed to a predetermined thickness in this manner, as shown in FIG. Figure 1 and Fig. 11C As shown, a preliminary upper etch stop layer 28' and a mask 60 may be formed on the first interconnect layer 23'.

[0178] First, a preliminary upper etch stop layer 28' may be stacked on the first interconnect layer 23', and the preliminary upper etch stop layer 28' may be formed of the same material as the first etch stop layer 19 and the second etch stop layer 18, but the present inventive concept is not limited thereto. The upper etch stop layer 28 may include the same material as the first etch stop layer 19 and the second etch stop layer 18, but the present inventive concept is not limited thereto.

[0179] The mask 60 may be a hard mask for forming a fine pattern when forming the lower through hole.

[0180] refer to Figure 1 and Fig.11D After forming a resist pattern for forming a via hole 61 on the mask 60 and patterning the mask 60 accordingly, the via hole 61 can be formed along the mask 60. The resist pattern can be formed using a photolithography process. The mask 60 can be patterned and the via hole 61 can be formed using a reactive ion etching (RIE) process.

[0181] When forming the via hole 61, the via hole 61 may be formed by continuously exposing from the preliminary upper etch stop layer 28' to the second etch stop layer 18 to expose the upper portion of the lower interconnect structure 13. Therefore, after the first through hole 23o of the first interconnect pattern 23 is also simultaneously formed, the mask 60 may be removed.

[0182] refer to Figure 1 and Fig.11E , a metal layer 25' may be deposited to fill the via hole 61 and cover the preliminary upper etch stop layer 28'. The metal layer 25' may be, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), or tungsten (W), but the inventive concept is not limited thereto. The metal layer 25' may be deposited by, for example, a chemical vapor deposition (CVD) process, but the inventive concept is not limited thereto.

[0183] refer to Fig.11F , the conductive via 25 may be completed by performing a planarization process to expose the preliminary upper etch stop layer 28'. The planarization process may be a chemical mechanical polishing (CMP) process or an etch-back process.

[0184] The conductive via 25 may pass through the first through-hole 23 o and may directly contact the side surface of the first interconnection pattern 23 on the inner sidewall of the first through-hole 23 o .

[0185] The conductive via 25 may include a material different from that of the first interconnection pattern 23 , and may include, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), or tungsten (W).

[0186] refer to Figure 2AThe conductive path 25 and the first interconnection pattern 23 may have a contact interface that directly contacts the inner sidewall of the first through hole 23o to contact the conductive path 25 in the first direction where the resistivity of the first interconnection pattern 23 is low, thereby significantly reducing the contact resistance. Therefore, the signal RC delay can be reduced.

[0187] Depending on the shape of the via hole 61, the conductive via 25 may also have a shape in which the width decreases in the downward direction, but the inventive concept is not limited thereto. Figure 2A The conductive path 25 may include an upper surface 25b, a lower surface 25c, and a side surface 25a connecting the upper surface 25b and the lower surface 25c, and the level of the upper surface 25b may be equal to or higher than the level of the upper surface of the first interconnection pattern 23, while the level of the lower surface 25c may be lower than the level of the lower surface of the first interconnection pattern 23.

[0188] A mask 65 may be formed on the conductive via 25 and the preliminary upper etch stop layer 28'. The mask 65 may be used to pattern the first interconnect layer 23', and its material may be the same as that of the mask 60 previously applied.

[0189] refer to Fig.11G After forming a resist for printing on the mask 65 and patterning the mask 65 accordingly, the mask 65 may be used to pattern and clean the first interconnect layer 23' to form the first interconnect pattern 23. At the same time, the preliminary upper etch stop layer 28' may also be patterned to form the upper etch stop layer 28.

[0190] The etching for forming the separation space 66 by patterning the first interconnection pattern 23 may be performed in multiple stages. For example, etching may be performed first on the upper portion of the first etch stop layer 19, and secondly, additional etching may be performed to over-etch the first etch stop layer 19 to the first depth h1. Due to the additional etching, the first etch stop layer 19 may have a step difference under the first interconnection pattern 23 and the first interconnection insulating layer 21 (see FIG. Fig.11I ), so that the material of the first interconnect layer 23 ′ does not remain under the first interconnect insulating layer 21.

[0191] During the process of removing a portion of the first interconnection layer 23' to form the first interconnection pattern 23, an etching process may be performed to first remove a portion of the first interconnection layer 23' to the upper surface of the first etch stop layer 19, and secondly, additional etching may be performed to completely remove the first etch stop layer 19 to expose the intermediate insulating layer 20. In this case, referring to Figure 7 , the first etch stop layer 19 may be selectively disposed only under the first interconnection pattern 23 .

[0192] refer to Fig.11H After partially or completely removing the mask 65, the separation spaces 66 between the first interconnection patterns 23 may be filled to form an insulating layer 21'. 2 ) is applied to the insulating layer 21 ′. The insulating layer 21 ′ may be over-stacked to cover the upper etch stop layer 28 .

[0193] refer to Fig.11I , a planarization process may be performed, and the insulating layer 21' may be etched until the upper etch stop layer 28 is exposed. Therefore, the planarization may be implemented so that the upper surface of the upper etch stop layer 28, the upper surface of the first interconnect insulating layer 21, and the upper surface of the conductive path 25 are coplanar.

[0194] In this case, if Figure 5 As shown, when the planarization is performed until the upper surface of the first interconnection pattern 23 is exposed, the upper etch stop layer 28 may be completely removed.

[0195] Again, reference Fig.11J , a second insulating structure (29, 30, and 31) may be formed on the first interconnection pattern 23. For example, the second insulating structure (29, 30, and 31) may be formed to cover the upper surfaces of the upper etch stop layer 28, the first interconnection insulating layer 21, and the conductive path 25.

[0196] In the second insulating structure (29, 30 and 31), as with the first insulating structure 16 described above, a second etch stop layer 29, an intermediate insulating layer 30 and a first etch stop layer 31 may be sequentially formed, and their materials and thicknesses may be the same as those previously described.

[0197] A mask 67 may be formed on the first etch stop layer 31 .

[0198] refer to Figure 11K , the upper via hole 68 can be formed by forming a resist on the mask 67 and printing and cleaning the resist.

[0199] The upper via hole 68 may be continuously exposed from the first etch stop layer 31 of the upper second insulation structure (29, 30, and 31) to the lower first etch stop layer 19 disposed under the first interconnection pattern 23. Therefore, the intermediate insulation layer 20 of the first insulation structure 16 may be exposed.

[0200] refer to Fig.11L , an upper conductive via 35 may be further formed by filling the upper via hole 68 .

[0201] In this case, after forming a conductive layer to fill the upper via hole 68 , planarization may be performed to form the upper conductive via 35 .

[0202] When forming the upper via hole 68 , etching may be stopped by the first etch stop layer 19 , and in the upper conductive via 35 filling the upper via hole 68 , planarization may be stopped by the upper first etch stop layer 31 .

[0203] Through the planarization process, an upper conductive path 35 having an upper surface coplanar with the first etch stop layer 31 of the second insulating structure (29, 30, and 31) may be formed. The upper conductive path 35 may extend integrally from the first etch stop layer 19 to the first etch stop layer 31 of the second insulating structure (29, 30, and 31), and a contact interface with the first interconnect pattern 23 may be provided on the inner sidewall of the through hole of the first interconnect pattern 23 to form a wedge-shaped conductive structure. The upper conductive path 35 and the first interconnect pattern 23 may have a contact interface directly contacting the upper conductive path 35 and the first interconnect pattern 23 in a first direction where the resistivity of the first interconnect pattern 23 is low, thereby significantly reducing the contact resistance. Therefore, the signal RC delay may be reduced.

[0204] refer to Fig.11M A conductive material layer may be formed on the second insulating structure ( 29 , 30 , and 31 ), and the conductive material layer may be patterned to form an upper interconnect structure 36 electrically connected to the upper conductive via 35 .

[0205] Next, we will refer to FIG. 12A to FIG. 12I Another example of a method of forming the semiconductor device 1 according to an embodiment of the inventive concept is described. FIG. 12A to FIG. 12I It can be schematically shown that the Figure 1 Cross-sectional view of a portion of.

[0206] exist FIG. 12A to FIG. 12I In the method for forming the semiconductor device 1, a lower structure LS is formed, a first insulating structure 16 is formed, and a first interconnect layer 23', a preliminary upper etching stop layer 28' and a mask 70 are sequentially formed on the first insulating structure 16. FIG. 11A to FIG. 11C The same as in the above description, so the description thereof will be omitted.

[0207] refer to Figure 1 and Fig. 12A After forming a resist layer for printing on the mask 70 and patterning the mask 70 accordingly, the first interconnection layer 23' below can be patterned and cleaned through the mask 70 to form the first interconnection pattern 23. At the same time, the preliminary upper etch stop layer 28' can also be patterned to form the upper etch stop layer 28.

[0208] In this case, in order to pattern the first interconnection pattern 23, etching of the first interconnection layer 23' may be performed in multiple stages. For example, etching may be first performed to form the separation space 71 down to the upper portion of the first etch stop layer 19, and then additional etching may be performed to over-etch to the first depth h1 of the first etch stop layer 19. Due to this additional etching, the first etch stop layer 19 may have a step difference below the first interconnection pattern 23 and the first interconnection insulating layer 21 (see Fig. 12C ), so that the material of the first interconnect layer 23 ′ does not remain under the first interconnect insulating layer 21.

[0209] refer to Figure 1 and Fig. 12B After partially removing the mask 70 by cleaning, the insulating layer 21' may be formed by filling the separation space 71 between the first interconnection patterns 23. The silicon oxide (SiO 2 ) is applied to the insulating layer 21 ′. The insulating layer 21 ′ may be over-stacked to cover the upper etch stop layer 28 .

[0210] refer to Fig. 12C A planarization process may be performed to etch the insulating layer 21' until the upper etch stop layer 28 is exposed. Therefore, the planarization may be implemented such that the upper surface of the upper etch stop layer 28 and the upper surface of the first interconnect insulating layer 21 are coplanar.

[0211] In this case, if Figure 5 As shown, when the planarization is performed until the upper surface of the first interconnection pattern 23 is exposed, the upper etch stop layer 28 may be completely removed.

[0212] refer to Figure 1 and Fig.12D , a via hole 76 for a conductive path may be formed. For example, a mask 75 may be formed on the upper surface of the upper etch stop layer 28 and the upper surface of the first interconnect insulating layer 21. After a resist pattern for forming the via hole 76 is formed on the mask 75 and the mask 75 is patterned accordingly, the via hole 76 may be formed along the mask 75. For example, an etching process may be performed using the mask 75 as an etching mask to form the via hole 76.

[0213] The formation of the via hole 76 may continuously expose from the upper etch stop layer 28 to the second etch stop layer 18 to form the via hole 76 exposing the upper portion of the lower interconnection structure 13 , and the mask 75 may be removed.

[0214] refer to Figure 1 and Fig.12E , a metal layer 25 ′ may be deposited to fill the via hole 76 and cover the upper etch stop layer 28 and the first interconnect insulating layer 21 .

[0215] The metal layer 25 ′ may include a material different from that of the first interconnection pattern 23 and may be formed by depositing a material including at least one of, for example, ruthenium (Ru), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al), or tungsten (W).

[0216] See also Fig.12F The conductive via 25 may be completed by performing a planarization process (eg, chemical mechanical polishing (CMP)) to expose the upper etch stop layer 28 .

[0217] The conductive via 25 may pass through the via hole 76 and may directly contact the side surface of the first interconnection pattern 23 on the inner side wall of the first through hole 23o (see Figure 2A ).

[0218] The conductive via 25 and the first interconnection pattern 23 may have a contact interface directly contacting the inner sidewall of the first through hole 23o to contact the conductive via 25 in the first direction where the resistivity of the first interconnection pattern 23 is low, thereby significantly reducing contact resistance. Therefore, signal RC delay may be reduced.

[0219] Depending on the shape of the via hole, the conductive via 25 may also have a shape in which the width decreases in the downward direction, but the inventive concept is not limited thereto. The conductive via 25 may include an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface, and the level of the upper surface may be equal to or higher than the level of the upper surface of the first interconnection pattern 23, and the level of the lower surface may be lower than the level of the lower surface of the first interconnection pattern 23.

[0220] refer to Figure 12G , a second insulating structure ( 29 , 30 , and 31 ) may be formed again on the first interconnection pattern 23 .

[0221] As described above, in the second insulating structure ( 29 , 30 , and 31 ), the second etch stop layer 29 , the intermediate insulating layer 30 , and the first etch stop layer 31 may be sequentially formed, and the materials and thicknesses thereof may be the same as those previously described.

[0222] A mask 67 may be formed on the first etch stop layer 31 .

[0223] refer to Fig.12H , the upper via hole 68 can be formed by forming a resist on the mask 67 and printing and cleaning the resist.

[0224] The upper via hole 68 may be continuously exposed from the first etch stop layer 31 of the upper second insulation structure (29, 30, and 31) to the lower first etch stop layer 19 disposed under the first interconnection pattern 23. Therefore, the lower intermediate insulation layer 20 may be exposed.

[0225] refer to Fig.12I , an upper conductive via 35 may be further formed by filling the upper via hole 68 .

[0226] In this case, after forming a conductive layer to fill the upper via hole 68 , planarization may be performed to form the upper conductive via 35 .

[0227] When forming the upper via hole 68 , etching may be stopped by the first etch stop layer 19 , and in the upper conductive via 35 filling the upper via hole 68 , planarization may be stopped by the upper first etch stop layer 31 .

[0228] The upper conductive path 35 may extend integrally from the first etch stop layer 19 to the first etch stop layer 31 of the second insulating structure (29, 30, and 31), and a contact interface with the first interconnection pattern 23 may be provided on the inner sidewall of the through hole of the first interconnection pattern 23 to form a wedge-shaped conductive structure. The upper conductive path 35 and the first interconnection pattern 23 may have a contact interface that allows the upper conductive path 35 and the first interconnection pattern 23 to directly contact in a first direction in which the resistivity of the first interconnection pattern 23 is low, thereby significantly reducing contact resistance. Therefore, the signal RC delay may be reduced.

[0229] Through the planarization process, an upper conductive via 35 having an upper surface coplanar with the first etch stop layer 31 of the upper portion of the upper insulating structure (29, 30, and 31) may be formed. A conductive material layer may be formed on the upper insulating structure (29, 30, and 31), and the conductive material layer may be patterned to form an upper interconnect structure 36 electrically connected to the upper conductive via 35.

[0230] According to an embodiment of the inventive concept, a semiconductor device including an interconnect pattern including a material having anisotropic resistance characteristics can be provided. The interconnect pattern can have a very low in-plane resistivity even for a very small line width, thereby reducing RC delay during fine interconnection for miniaturized semiconductor devices.

[0231] In addition, a via hole having a wedge shape can be provided so that the via and the interconnection pattern are in direct contact in a lateral direction within a plane. Therefore, the contact resistance between the via and the interconnection pattern can become very small to prevent RC delay during signal transmission.

[0232] When the interconnect structure is provided in multiple layers, the resistance can be significantly reduced by providing multiple layers of interconnect patterns having anisotropic resistance characteristics and forming vias passing through the multiple layers of the interconnect patterns. Therefore, the performance of the semiconductor device can be improved.

[0233] Various effects of the present inventive concept may not be limited to the above-mentioned contents and may be more easily understood through the description of specific embodiments.

[0234] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Insulation structure; a first interconnection pattern having a first through hole and disposed on an upper surface of the insulating structure; as well as a conductive path passing through the first through-hole of the first interconnection pattern and contacting the first interconnection pattern on an inner sidewall of the first through-hole, wherein the first interconnect pattern includes a material having a first resistivity in a first direction parallel to the upper surface of the insulating structure and having a second resistivity in a second direction different from the first direction and not parallel to the upper surface of the insulating structure, and The first resistivity is lower than the second resistivity.

2. The semiconductor device according to claim 1, wherein The first interconnection pattern and the conductive via include different materials.

3. The semiconductor device according to claim 1, wherein The first interconnection pattern has a width of 10 nm or less.

4. The semiconductor device according to claim 1, wherein: The first interconnect pattern includes a conductive material, wherein the conductive material includes at least one of an intermetallic compound, an oxide, a carbide, a nitride, or a boride, Wherein, the intermetallic compound includes a topological semimetal material, the oxide includes a delafossite material, and the carbide or the nitride includes a material having a MAX phase, wherein M is a transition metal, A is one of elements of Groups 10, 11, 12, 13 and 14, and X is carbon and / or nitrogen.

5. The semiconductor device according to claim 1, wherein The insulating structure comprises: an intermediate insulating layer; and a first etch stop layer, the first etch stop layer being disposed between the intermediate insulating layer and the first interconnect pattern, The first etching stop layer includes a second through hole aligned with the first through hole and through which the conductive path passes.

6. The semiconductor device according to claim 5, wherein: The first etch stop layer includes a first region located below the first interconnect pattern and a second region excluding the first region, The upper surface of the first region has a higher level than the upper surface of the second region.

7. The semiconductor device according to claim 5, wherein: The first etch stop layer is disposed only under the first interconnection pattern.

8. The semiconductor device according to claim 1, wherein The conductive via includes a conductive barrier layer and a via material layer, the conductive barrier layer being formed on a side surface of the via material layer.

9. The semiconductor device according to claim 8, wherein: The conductive barrier layer is disposed between the inner sidewall of the first through hole and the via material layer to directly contact the first interconnection pattern and the via material layer.

10. The semiconductor device according to claim 5, wherein The level of the upper surface of the conductive path is higher than the level of the upper surface of the first interconnection pattern, and The semiconductor device further includes an upper etch stop layer, which is disposed on the upper surface of the first interconnect pattern and includes a third through hole through which the conductive path passes.

11. The semiconductor device according to claim 10, further comprising at least one of an upper interconnect structure disposed on the first interconnect pattern or a lower interconnect structure disposed below the first interconnect pattern, When the conductive via extends in an upward direction to connect to the upper interconnect structure, a lower surface of the conductive via is coplanar with a lower surface of the first etch stop layer, and When the conductive via extends in a downward direction to connect to the lower interconnect structure, an upper surface of the conductive via is coplanar with an upper surface of the upper etch stop layer.

12. The semiconductor device according to claim 11, wherein The upper interconnect structure or the lower interconnect structure includes a second interconnect pattern including a material that is the same as that of the first interconnect pattern, wherein the second interconnection pattern includes a fourth through hole aligned with the first through hole, and The conductive path passes through the first through hole and the fourth through hole, and connects the first interconnection pattern and the second interconnection pattern.

13. The semiconductor device according to claim 1, wherein The conductive path has a side surface inclined at a constant angle.

14. The semiconductor device according to claim 1, wherein The conductive path has a width that decreases in a downward direction.

15. The semiconductor device according to claim 1, wherein The conductive path includes a material having an isotropic resistance characteristic different from a material of the first interconnection pattern.

16. The semiconductor device according to claim 1, wherein The first interconnection pattern comprises: an interconnect material layer, in which the first resistivity in the first direction is lower than the second resistivity in the second direction; and A seed layer is disposed under the interconnect material layer and includes a material different from that of the interconnect material layer.

17. A semiconductor device, comprising: Active area; an interlayer insulating layer, the interlayer insulating layer being disposed on the active region; a contact structure connected to the active region and passing through the interlayer insulating layer; an intermediate insulating structure having a first hole and disposed on the interlayer insulating layer; a first interconnection pattern having a second hole aligned with the first hole, disposed on the intermediate insulating structure and having an anisotropic resistance characteristic; as well as A conductive via passes through the first hole and the second hole to be connected to the contact structure, and is connected to the first interconnection pattern through an inner sidewall of the second hole.

18. The semiconductor device according to claim 17, wherein: The first interconnect pattern includes a material having a first resistivity in a first direction parallel to an upper surface of the intermediate insulating structure and having a second resistivity in a second direction different from the first direction and not parallel to the upper surface of the intermediate insulating structure, The first resistivity is lower than the second resistivity, and The conductive path includes a material having a resistivity in the first direction equal to a resistivity in the second direction.

19. The semiconductor device according to claim 17, wherein: The intermediate insulating structure comprises: an intermediate insulating layer; and a first etch stop layer, the first etch stop layer being disposed between the intermediate insulating layer and the first interconnect pattern, The first etching stop layer includes a through hole aligned with the first hole and through which the conductive path passes.

20. A semiconductor device, comprising: an insulating structure, the insulating structure comprising an intermediate insulating layer, a first etch stop layer located on the intermediate insulating layer, and a second etch stop layer located below the intermediate insulating layer, and comprising a lower through hole exposing the intermediate insulating layer, the first etch stop layer, and the second etch stop layer; a first interconnection pattern having a first through hole aligned with the lower through hole and disposed on an upper surface of the first etch stop layer; an upper etch stop layer having a second through hole aligned with the first through hole and disposed on the first interconnect pattern; as well as a conductive path including a material different from that of the first interconnection pattern, filling the first through-hole, the second through-hole and the lower through-hole, and having an upper surface coplanar with an upper surface of the upper etch stop layer and directly contacting a side surface of the first interconnection pattern through an inner sidewall of the first through-hole.

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