Stack of memory dies with switch selectively connecting memory dies to substrate

Abstract

A memory device includes a stack of memory die packages. Each memory die package includes at least two memory dies. A switch is electrically coupled to at least one of the memory die packages. A bond wire electrically couples the switch to a substrate of the memory device. Each memory die is also electrically coupled to the switch. Based on the received control signal, the switch selects which memory die is electrically coupled and / or communicatively coupled to the substrate using an electrical connection between the memory die and the bond wire that electrically couples the switch to the substrate.

Description

Background Art

[0001] Semiconductor memory and storage devices are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, and non-mobile computing devices. Semiconductor memory may include non-volatile memory or volatile memory. Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory) and electrically erasable programmable read-only memory (EEPROM).

[0002] NAND-type memory packages typically include one or more input / output (I / O) data channels that pass through one or more stacked NAND memory dies (e.g., to achieve greater storage capacity) from a substrate such as a ball grid array (BGA) package. Each of these I / O data channels is typically connected in series from the substrate to each of the memory dies using bonding wires that connect pin caps on the substrate to pin caps on the memory die (e.g., input pins or memory pads), or from a pin cap on one memory die to a pin cap on another memory die. The I / O data channels act as transmission lines that connect portions of all memory dies to the BGA package. However, typical I / O data channels with such conventional bonding wire architectures result in bandwidth limitations on the I / O channels because the I / O data channels support multiple different memory dies in the stack.

[0003] Therefore, it would be beneficial for each memory die in the stack to individually and / or separately access specific I / O data channels. Summary of the invention

[0004] The present application describes a memory device having a stack of memory die packages. In an example, each memory die package includes at least two memory die bonded together. A switch is electrically coupled and / or communicatively coupled to the top surface of one or more memory die packages. The switch enables each memory die in each memory die package to individually connect to an I / O data channel associated with the stack of memory die packages. For example, each memory die in each memory die package is communicatively coupled and / or electrically coupled to a switch (e.g., using bonding wires, through silicon vias (TSVs)). The bonding wire electrically couples the switch to the substrate of the memory device. Based on the control signal received, the switch selects which memory die is electrically coupled and / or communicatively coupled to the substrate. When compared to a conventional bonding wire architecture, this arrangement increases the overall electrical performance of the I / O data channel and the memory device.

[0005] Thus, an example of the present application describes a memory device comprising a first memory die package and a second memory die package. The first memory die package comprises a first memory die bonded to a second memory die. Similarly, the second memory die package comprises a third memory die bonded to a fourth memory die. In addition, the first memory die package and the second memory die package form a stack of memory die packages. The memory device also comprises a switch electrically coupled to a top surface of the first memory die package. A first electrical connection electrically couples the first memory die to the switch, a second electrical connection electrically couples the second memory die to the switch, a third electrical connection electrically couples the third memory die to the switch, and a fourth electrical connection electrically couples the fourth memory die to the switch. The memory device also comprises a bonding wire electrically coupling the switch to a substrate of the memory device.

[0006] The present application also describes a semiconductor package, the semiconductor package including a first semiconductor die and a second semiconductor die bonded together to form a first package. The semiconductor package also includes a third semiconductor die and a fourth semiconductor die bonded together to form a second package. In an example, the second package is stacked with the first package. A switch is electrically coupled to a top surface of the first package, and a plurality of electrical connections electrically couple the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the switch. Bonding wires electrically couple the switch to a substrate of the semiconductor package.

[0007] In yet another example, the present application describes a memory device that includes a controller component, a first semiconductor package having a first semiconductor die bonded to a second semiconductor die, and a second semiconductor package having a third semiconductor die bonded to a fourth semiconductor die. In an example, the second semiconductor package and the first semiconductor package are arranged in a stacked configuration. The memory device also includes a switch component electrically coupled to the first semiconductor package and the second semiconductor package. In an example, the switch component selectively electrically couples each of the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the substrate using bonding wires that electrically couple the switch component to the substrate of the memory device.

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0010] Figure 1AA conventional bond wire architecture of a memory device is shown.

[0011] Figure 1B Various graphs are shown, showing Figure 1A The bandwidth limitations of the bond wire architecture shown in .

[0012] Figure 2 is an example architecture of a memory device including a switch that selectively connects a memory die to a substrate according to an example.

[0013] Figure 3A Another example architecture of a memory device including a switch that selectively connects a memory die to a substrate is shown according to an example.

[0014] Figure 3B Various graphs are shown, showing Figure 3A The bandwidth performance of the memory device shown in .

[0015] Figure 4 Shown are switches and integrated circuits surface mounted to a memory die package according to an example. DETAILED DESCRIPTION

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part of the present invention, and in which specific embodiments or examples are shown by way of diagrammatic illustration. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from the present disclosure. Examples may be practiced as methods, systems, or devices. Therefore, examples may take the form of hardware implementations, complete software implementations, or implementations combining software and hardware aspects. Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the present disclosure is limited by the appended claims and their equivalents.

[0017] In some NAND memory devices, bonding wires are used to form I / O data channels between the substrate of a memory device or memory package (e.g., a BGA package) and multiple memory dies contained in the memory device. Due to the increased storage capacity requirements, multiple memory dies can be stacked in a highly integrated complex packaging system. For example, some memory devices or memory packages may include 2, 4, 8, or 16 memory dies in a single package. These memory dies can be integrated together into one or more I / O data channels using a "single-cap" bonding wire architecture, in which the pin caps of the package substrate are wired to the pin caps on the first memory die by means of bonding wires, and then wired from the pin caps on the first memory die to the pin caps on the second memory die by means of another bonding wire, and so on. However, because each memory die can share the same I / O data channel, the bandwidth on the I / O data channel is usually limited.

[0018] In order to solve the above problems, the present application describes a memory device, which enables each memory die in a memory die stack to individually connect to the I / O data channel of the memory device. In an example, the memory device includes a plurality of memory die packages. Each memory die package includes at least two memory dies bonded together. The switch is electrically coupled and / or communicatively coupled to the top surface of one or more of the memory die packages. The switch enables each memory die in each memory die package to individually connect to the I / O data channel associated with the stack of memory die packages. For example, each memory die in each memory die package is communicatively coupled and / or electrically coupled to the switch. The bonding wire electrically couples the switch to the substrate of the memory device. Based on the received control signal, the switch uses the bonding wire to select which memory die is electrically coupled and / or communicatively coupled to the substrate.

[0019] Thus, a number of technical benefits can be achieved, including, but not limited to: enabling each memory die in a memory device to individually connect to an I / O data channel; reducing or maintaining the height of the memory device by using multiple memory die packages rather than individual memory dies; and increasing the overall electrical performance of the I / O data channels and / or the memory device when compared to a memory device utilizing a conventional bond wire architecture.

[0020] The following will refer to Figure 1A-Figure 4 These various benefits and examples are described in more detail.

[0021] Figure 1A FIG. 1 shows a conventional bonding wire architecture of the memory device 100. Figure 1A As shown in , the memory device 100 includes a substrate 110 and several memory dies mounted on the substrate 110. For example, the memory device 100 includes a first memory die 115, a second memory die 120, a third memory die 125, and a fourth memory die 130. The memory device 100 shows an I / O data channel (or just "channel") 135 through which the substrate 110 and each memory die communicate (e.g., transmit data input / output operations and responses back and forth). Each memory die can be, for example, a NAND flash memory die, which includes internal circuitry (not shown) for providing volatile or non-volatile storage. It should be understood that for illustrative purposes, Figure 1A The separation between the memory dies and between the substrate 110 is presented, and many other circuit details about the memory dies and the memory device 100 that are not particularly relevant to the present disclosure are excluded for ease of discussion.

[0022] In this example, substrate 110 and each memory die include a single pin cap 140A-140E. For example, substrate 110 includes pin cap 104A, and each of the memory dies includes pin caps 140B to 140E, respectively. These pin caps or "I / O pads" are used to connect the internal circuitry of the memory die to the I / O data channel 135.

[0023] Additionally, each pin cap is connected by one or two bond wires to an adjacent memory die or to substrate 110. A bond wire refers to an electrical connection (eg, a wire) that may be soldered or otherwise electrically connected to a pin cap.

[0024] For example, the bond wires are arranged in a cascade pattern where each memory die is connected to each other. Figure 1A In the example shown in , the first bonding wire 145A connects the pin cap 140A on the surface of the substrate 110 and the pin cap 140B of the first memory die 115. Similarly, the second bonding wire 145B connects the pin cap 140B of the first memory die 115 to the pin cap 140C of the second memory die 120, and so on, the bonding wire 145C connects the pin cap 140C to the pin cap 140D, and the bonding wire 145D connects the pin cap 140D to the pin cap 140E. Thus, a series of bonding wires establish a data transmission path, that is, an I / O data channel 135 shared by all memory dies and the substrate 110.

[0025] Because each memory die shares the same I / O data channel 135, the substrate 110 is subject to multiple die loading in the I / O data channel 135, which can negatively impact the electrical performance (e.g., bandwidth / operating speed) of the memory device 100. Figure 1B Further shown in .

[0026] Figure 1B Various graphs are shown, showing Figure 1A . For example, each graph shows the bandwidth of the I / O data channel 135 when each memory die drives the I / O data channel 135. In these examples, each graph includes a graph of frequency (in GHz, X-axis) versus insertion loss (S(2,1), in decibels (dB), Y-axis).

[0027] The first graph 150 shows the bandwidth of the I / O data channel 135 when the first memory die 115 drives the I / O data channel 135. As shown in the first graph 150, the bandwidth of the I / O data channel 135 is about 2.5 GHz. The second graph 155 shows the bandwidth of the I / O data channel 135 when the second memory die 120 drives the I / O data channel 135. As shown in the second graph 155, the bandwidth of the I / O data channel 135 is about 2.8 GHz. The third graph 160 shows the bandwidth of the I / O data channel 135 when the third memory die 125 drives the I / O data channel 135. As shown in the third graph 160, the bandwidth of the I / O data channel 135 is about 3.2 GHz. The fourth graph 165 shows the bandwidth of the I / O data channel 135 when the fourth memory die 130 drives the I / O data channel 135. As shown in the fourth graph 165, the bandwidth of the I / O data channel 135 is about 3.5 GHz.

[0028] Figure 2 2 is an example architecture of a memory device 200 including a switch 210 that selectively connects a memory die to a substrate 220 according to an example. Because the switch 210 allows a single die to be coupled to the substrate 220, when the memory device 200 is connected to the substrate 220, the memory device 200 is connected to the substrate 220. Figure 1A The bandwidth and / or electrical performance of the memory die stack and / or I / O data channels 250 of the memory device 200 is significantly increased when compared to the I / O data channels 135 and / or memory device 100 shown and described.

[0029] In an example, memory device 200 includes a first memory die package 205 and a second memory die package 215. Each of the first memory die package 205 and the second memory die package 215 includes a plurality of memory dies mounted face to face or otherwise bonded together.

[0030] For example, the first memory die package 205 includes a first memory die 225 bonded to a second memory die 230. Similarly, the second memory die package 215 includes a third memory die 235 bonded to a fourth memory die 240. Each memory die in each memory die package can be bonded together as shown and described in U.S. Patent No. 11,004,829, filed on October 7, 2019, entitled “Memory Scaling Semiconductor Device,” which is incorporated herein by reference in its entirety. Although Figure 2 Two memory die packages are shown, but memory device 200 can have any number of memory die packages.

[0031] Each memory die package may be arranged in a stacked configuration or otherwise form a stack of memory die packages. For example, a first memory die package 205 may be stacked on top of a second memory die package 215 .

[0032] Additionally, one or more computing components, semiconductor dies, and / or semiconductor packages may be mounted on the top surface of the first memory die package 205. For example, the switch 210 may be mounted or otherwise coupled to the top surface of the first memory die package 205. The controller 245 (or other ASIC) may also be mounted on the top surface of the first memory die package 205. In an example, the controller 245 provides one or more control signals to the switch 210 that cause the switch 210 to selectively couple each of the various memory dies to the substrate 220.

[0033] Due to the manner in which the memory die of the memory die packages are manufactured and bonded together, the height of each memory die package can be substantially equal to the height of the individual memory die shown and described with respect to Figure 1. Thus, the switch 210 and / or the controller 245 can be mounted on the top surface of the first memory die package 205 without significantly increasing the overall height of the stack of memory die packages and / or the memory device 200 itself.

[0034] In an example, the switch 210 may be a multiplexer die (or multiplexers) that, when activated, enables one memory die of the memory device 200 to be coupled to the substrate 220. For example, each memory die or memory die package may include or otherwise be associated with an I / O data channel 250. The I / O data channel 250 enables the substrate 220 and each memory die to communicate.

[0035] In the illustrated example, the substrate 220 and each memory die stack include one or more pin caps. For example, the substrate 220 includes a first pin cap 255A. The second memory die package 215 includes two pin caps: a second pin cap 255B and a third pin cap 255C. In the example, the second pin cap 255B and the third pin cap 255C are disposed on the top surface of the third memory die 235. However, the second pin cap 255B may be electrically coupled to the third memory die 235, and the third pin cap 255C may be electrically coupled to the fourth memory die 240. For example, although the third pin cap 255C is disposed on the top surface of the third memory die 235, vias (e.g., through silicon vias (TSVs)) and / or one or more transmission lines (or redistribution layers (RDLs)) associated with one or more of the third memory die 235 and / or the fourth memory die 240 may also electrically and / or communicatively couple the fourth memory die 240 to the third pin cap 255C.

[0036] In addition, the first memory die package 205 includes five different pin caps disposed on the top surface of the first memory die 225. For example, the first memory die package 205 includes a fourth pin cap 255D, a fifth pin cap 255E, a sixth pin cap 255F, a seventh pin cap 255G, and an eighth pin cap 255H. In an example, each pin cap on the surface of the first memory die 225 of the first memory die package 205 can also be electrically coupled to the switch 210 via one or more traces 260 or wires.

[0037] In an example, the sixth pin cap 255F can be electrically coupled to the first memory die 225, and the seventh pin cap 255G can be electrically coupled to the second memory die 230. For example, although the seventh pin cap 255G is disposed on the top surface of the first memory die 225, through vias (e.g., TSVs), one or more transmission lines, and / or RDLs (e.g., RDL 265) associated with the second memory die 230 and / or the first memory die 225 can also electrically and / or communicatively couple the second memory die 230 to the seventh pin cap 255G.

[0038] Although a specific number of pin caps have been shown and described on substrate 220 and each memory die package, substrate 220 and each memory die package may include any number of pin caps. In addition, each pin cap may be positioned at any location on substrate 220 and / or each memory die package. For example, TSVs, transmission lines, and / or RDLs may enable various pin caps to be provided at any number of locations on the surface of first memory die 225 and / or third memory die 235.

[0039] like Figure 2 As shown in , various bonding wires electrically couple various pin caps (and various memory dies associated with each pin cap) to the switch 210. For example, the first bonding wire 270A can electrically couple the second pin cap 255B to the fourth pin cap 255D. Similarly, the second bonding wire 270B can electrically couple the third pin cap 255C to the fifth pin cap 255E. The fourth pin cap 255D and the fifth pin cap 255E can also be electrically coupled to the switch 210 using additional bonding wires and / or traces 260. Similarly, each of the sixth pin cap 255F and the seventh pin cap 255G can be electrically coupled to the switch 210 using bonding wires and / or traces 260.

[0040] The switch 210 is also communicatively coupled to the eighth pin pad 255H. For example, bonding wires and / or traces electrically couple the switch 210 to the eighth pin pad 255H. Figure 2As shown in FIG. 2 , the third bonding wire 270C establishes a data transmission path from the eighth pin pad 255H to the first pin pad 255A on the substrate 220 . Based on this configuration, the switch 210 can control which memory dies drive the I / O data channel 250 and couple to the substrate 220 .

[0041] For example and based on a control signal from the controller 245, the switch 210 may establish or otherwise enable a transmission path between the fourth memory die 240 and the substrate 220. Thus, the switch 210 may establish a communication path between the fourth memory die 240, the third pin cap 255C, the second bonding wire 270B, and the fifth pin cap 255E. Next, the switch 210 enables the fourth memory die 240 to be connected to the substrate using the eighth pin cap 255H, the third bonding wire 270C, and the first pin cap 255A.

[0042] In this example, each memory die may share the same I / O data channel 250, however, the switch 210 enables each memory die to individually / separately turn on the I / O data channel 250. As a result, the electrical performance (e.g., bandwidth / operating speed) of the I / O data channel 250 and / or the memory device 200 is improved, especially in conjunction with the related Figure 1A When compared to the electrical performance of the I / O data channel 135 and / or memory device 100 shown and described.

[0043] Figure 3A Another example architecture of a memory device 300 including a switch 310 that selectively connects a memory die to a substrate 320 is shown according to an example. In an example, the memory device 300 may be similar to the memory device 300 described above. Figure 2 A memory device 200 is shown and described.

[0044] For example, the memory device 300 includes a first memory die package 305 and a second memory die package 315. Each of the first memory die package 305 and the second memory die package 315 includes a plurality of memory dies mounted face to face or otherwise bonded together. For example, the first memory die package 305 includes a first memory die 325 bonded to a second memory die 330. Similarly, the second memory die package 315 includes a third memory die 335 bonded to a fourth memory die 340. Although FIG. 3 shows two memory die packages, the memory device 300 may have any number of memory die packages.

[0045] Each memory die package may be arranged in a stacked configuration or otherwise form a stack of memory die packages. For example, a first memory die package 305 may be stacked on top of a second memory die package 315 .

[0046] Additionally, one or more computing components, semiconductor packages, and / or integrated circuits may be mounted on the top surface of the first memory die package 305. For example, a switch 310 may be mounted or otherwise coupled to the top surface of the first memory die package 305. Similarly, a controller 345 or another integrated circuit may also be mounted on the top surface of the first memory die package 305. In an example, the controller 345 provides one or more control signals to the switch 310 that cause the switch 310 to selectively couple each of the various memory dies to the substrate 320.

[0047] exist Figure 3A In the example shown, and similar to Figure 2 In the example shown, substrate 320 and each memory die stack include one or more pin caps. For example, substrate 320 includes a first pin cap 350A. The first pin cap 350A can be electrically coupled to switch 310 via a first bonding wire 355A. For example, switch 310 can include or otherwise be associated with a second pin cap 350B (or another connection pad / point) that enables switch 310 to be electrically coupled to the first pin cap 350A on substrate 305 using the first bonding wire 355A.

[0048] In an example, the second memory die package 315 includes two pin caps: a third pin cap 350C and a fourth pin cap 350D. The third pin cap 350C and the fourth pin cap 350D may be disposed on the top surface of the third memory die 335. In an example, the third pin cap 350C may be electrically coupled to the third memory die 335, and the fourth pin cap 350D may be electrically coupled to the fourth memory die 340.

[0049] For example, although the fourth pin cover 350D is disposed on the top surface of the third memory die 335, vias (e.g., TSVs), one or more transmission lines and / or RDLs 360 associated with the fourth memory die 340 may also electrically and / or communicatively couple the fourth memory die 340 to the fourth pin cover 350D.

[0050] exist Figure 3A In the example shown, a second bond wire 355B electrically couples the third memory die 335 (eg, using a third pin cap 350C) to the switch 310. Similarly, a third bond wire 355C electrically couples the fourth memory die 340 to the switch 310.

[0051] The first memory die package 305 may also include various pin caps. For example, the first memory die package 305 includes two pin caps: a fifth pin cap 350E and a sixth pin cap 350F. The fifth pin cap 350E and the sixth pin cap 350F may be disposed on the top surface of the first memory die 325. In an example, the fifth pin cap 350E may be electrically coupled to the first memory die 325, and the sixth pin cap 350F may be electrically coupled to the second memory die 330.

[0052] For example, although the sixth pin cap 350F is disposed on the top surface of the first memory die 325, a through-via (e.g., TSV) and / or RDL 365 (or another such transmission line) associated with the second memory die 330 may also electrically and / or communicatively couple the second memory die 330 to the sixth pin cap 350F. In an example, each of the fifth pin cap 350E and the sixth pin cap 350F is electrically coupled to the switch 310.

[0053] As about Figure 2 In the example shown and described, the switch 310 establishes data transmission paths from the various pin caps to the substrate 305. For example and based on a control signal from the controller 345, the switch 310 can establish or otherwise enable a transmission path between the fourth memory die 340 and the substrate 305 using the RDL 360, the fourth pin cap 350D, the third bonding wire 355C, and the first bonding wire 355A.

[0054] In an example, each of the memory dies of the memory device 300 may share the same I / O data channel. However, the switch 310 enables each of the memory dies to individually turn on the I / O data channel. As a result, the electrical performance (e.g., bandwidth / operating speed) of the I / O data channel and / or the memory device 300 is improved, especially in conjunction with the related Figure 1A When compared to the electrical performance of the I / O data channel 135 and / or memory device 100 shown and described.

[0055] Figure 3B Various graphs are shown, showing Figure 3A The bandwidth performance of the memory device architecture shown in Figure 2 and Figure 3A The bandwidth performance of various bond wires and / or I / O data channels in Figure 1A When comparing the bandwidth performance of various bond wires and / or I / O data channels 135, Figure 3A The memory device architecture shown in significantly improves the electrical performance of the memory device 300.

[0056] Similar to Figure 1B The curve graph in Figure 3BEach of the graphs in FIG. 1 shows that when each memory die drives an I / O data channel, an I / O data channel (eg, I / O data channel 250 ( Figure 2 In these examples, each graph includes a graph of frequency (in GHz, X-axis) versus insertion loss (S(2,1), in decibels (dB), Y-axis).

[0057] The first graph 360 shows the bandwidth of the I / O data channel when the first memory die 325 drives the I / O data channel. As shown in the first graph 360, the bandwidth of the I / O data channel is about 6.6 GHz. The second graph 370 shows the bandwidth of the I / O data channel when the second memory die 330 drives the I / O data channel. As shown in the second graph 370, the bandwidth of the I / O data channel is about 10.9 GHz. The third graph 380 shows the bandwidth of the I / O data channel when the third memory die 335 drives the I / O data channel. As shown in the third graph 380, the bandwidth of the I / O data channel is about 7.5 GHz. The fourth graph 390 shows the bandwidth of the I / O data channel when the fourth memory die 340 drives the I / O data channel. As shown in the fourth graph 390, the bandwidth of the I / O data channel is about 5.8 GHz.

[0058] Figure 4 4 and 5. The switch 410 and the integrated circuit 420 are shown surface mounted to the memory die package 400 according to an example. In an example, the memory die package 400 can be similar to the memory die package 400 described above. Figure 2 A first memory die package 205 and / or a second memory die package 215 are shown and described.

[0059] In an example, the memory die package 400 includes a first memory die 430 and a second memory die 440. Each of the first memory die 430 and the second memory die 440 can be bonded or otherwise coupled together to form a memory die package 400 such as previously described. Additionally, the switch 410 and / or the integrated circuit 420 can be surface mounted to the top surface of the memory die package 400 using one or more solder balls 450, bonding pads, and / or connection points. For example, the top surface of the memory die package 400 can include one or more bonding pads that receive the solder balls 450 of a flip chip die or package (e.g., the switch 410). Thus, the switch 410 and / or the integrated circuit 420 can be surface mounted to the top surface of the memory die package 400.

[0060] In this example, one or more through vias (e.g., TSVs) and / or associated signal lines (e.g., traces) may connect the first memory die 430 and / or the second memory die 440 directly to the switch 410 and / or the integrated circuit 420. Similarly, one or more memory dies of the second memory die package may also be directly connected to the switch 410 using one or more TSVs and / or associated signal lines. Thus, the switch 410 and / or the integrated circuit may be electrically and / or communicatively coupled to the memory die package 400 using bond wires, solder balls, and / or other connection points.

[0061] Based on the above, an example of the present disclosure describes a memory device, the memory device comprising: a first memory die and a second memory die, which are bonded together to form a first memory die package; a third memory die and a fourth memory die, which are bonded together to form a second memory die package, the second memory die package and the first memory die package forming a stack of memory die packages; a switch, which is electrically coupled to the top surface of the first memory die package; a first electrical connection, which electrically couples the first memory die to the switch; a second electrical connection, which electrically couples the second memory die to the switch; a third electrical connection, which electrically couples the third memory die to the switch; a fourth electrical connection, which electrically couples the fourth memory die to the switch; and a bonding wire, which electrically couples the switch to a substrate of the memory device. In the example, the switch selectively electrically couples one of the first memory die, the second memory die, the third memory die, and the fourth memory die to the substrate using the bonding wire. In an example, the memory device further includes a first pin pad and a second pin pad disposed on a top surface of the first memory package, wherein: a first electrical connection extends from the first pin pad; and a second electrical connection extends from the second pin pad. In an example, the memory device further includes a redistribution layer electrically coupling the second memory die to the second pin pad. In an example, at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bonding wire. In an example, at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bonding pad. In an example, the switch is a multiplexer. In an example, the memory device further includes a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die, and the fourth memory die is electrically coupled to the substrate.

[0062] In other examples, the present disclosure describes a semiconductor package, the semiconductor package comprising: a first semiconductor die and a second semiconductor die, which are bonded together to form a first package; a third semiconductor die and a fourth semiconductor die, which are bonded together to form a second package, the second package being stacked with the first package; a switch, which is electrically coupled to a top surface of the first package; a plurality of electrical connections, which electrically couple the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the switch; and a bonding wire, which electrically couples the switch to a substrate. In an example, the switch selectively electrically couples one of the semiconductor dies to a substrate using a bonding wire. In an example, the semiconductor package also includes a first pin pad and a second pin pad disposed on a top surface of a first memory package, wherein: the first electrical connection extends from the first pin pad; and the second electrical connection extends from the second pin pad. In an example, the semiconductor package includes a redistribution layer that electrically couples the second memory die to the second pin pad. In an example, at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bonding wire. In an example, at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bonding pad. In an example, the switch is a multiplexer. In an example, the semiconductor device also includes a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die, and the fourth memory die is electrically coupled to the substrate.

[0063] Examples of the present disclosure also describe a memory device, the memory device comprising: a controller component; a first semiconductor package having a first semiconductor die bonded to a second semiconductor die; a second semiconductor package having a third semiconductor die bonded to a fourth semiconductor die, the second semiconductor package and the first semiconductor package being arranged in a stacked configuration; and a switch component electrically coupled to the first semiconductor package and the second semiconductor package, the switch component selectively electrically coupling each of the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the substrate using bonding wires that electrically couple the switch component to the substrate of the memory device. In an example, the switch component is electrically coupled to the first semiconductor package using a plurality of bonding wires. In an example, the switch component is electrically coupled to the first semiconductor package using a plurality of bonding pads. In an example, the switch component is a multiplexer.

[0064] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The various aspects, examples and details provided in this disclosure are considered sufficient to convey the property and enable others to make and use the best mode of the claimed disclosure.

[0065] The disclosure claimed for protection should not be construed as being limited to any aspect, example or detail provided in the present disclosure. Whether in combination or individually shown and described, various (structural and methodological) features are intended to be selectively rearranged, included or omitted to produce an embodiment with a specific feature set. After the description and illustration of the present application have been provided, those skilled in the art may envision changes, modifications and alternative aspects within the spirit of the broader aspects of the general inventive concept embodied in the present application, which changes, modifications and alternative aspects do not depart from the broader scope of the disclosure claimed.

[0066] Aspects of the present disclosure have been described above with reference to schematic flow charts and / or schematic block diagrams of methods, devices, systems, and computer program products according to examples of the present disclosure. It should be understood that each frame of the schematic flow chart and / or schematic block diagram, as well as the combination of frames in the schematic flow chart and / or schematic block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device of a computer to generate a machine, so that instructions executed by a processor or other programmable data processing device generate components for implementing the functions and / or actions specified in the frames of one or more schematic flow charts and / or schematic block diagrams.

[0067] Reference to elements using designations such as "first," "second," etc. herein generally does not limit the number or order of those elements. In fact, these designations can be used as a method of distinguishing two or more elements or instances of elements. Thus, reference to a first and a second element does not mean that only two elements can be used, or that the first element precedes the second element. Additionally, unless otherwise stated, a collection of elements may include one or more elements.

[0068] A term of the form "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the specification or the claims means "A or B or C, or any combination of these elements." For example, this term may include A or B or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of: A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member. Similarly, "at least one of: A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member.

[0069] Similarly, as used herein, a phrase referring to a list of items in connection with "and / or" refers to any combination of the items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A memory device, comprising: a first memory die and a second memory die bonded together to form a first memory die package; a third memory die and a fourth memory die bonded together to form a second memory die package, the second memory die package and the first memory die package forming a stack of memory die packages; a switch electrically coupled to a top surface of the first memory die package; a first electrical connection electrically coupling the first memory die to the switch; a second electrical connection electrically coupling the second memory die to the switch; a third electrical connection electrically coupling the third memory die to the switch; a fourth electrical connection electrically coupling the fourth memory die to the switch; as well as A bond wire electrically couples the switch to a substrate of the memory device.

2. The memory device of claim 1, wherein the switch selectively electrically couples one of the first memory die, the second memory die, the third memory die, and the fourth memory die to the substrate using the bond wire.

3. The memory device of claim 1 , further comprising first and second lead pads disposed on the top surface of the first memory package, wherein: The first electrical connection extends from the first lead pad; and The second electrical connection extends from the second lead pad.

4. The memory device of claim 3, further comprising a redistribution layer electrically coupling the second memory die to the second pin pad.

5. The memory device of claim 1, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bond wire.

6. The memory device of claim 1, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bond pad.

7. The memory device of claim 1, wherein the switch is a multiplexer.

8. The memory device of claim 1, further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die, and the fourth memory die is electrically coupled to the substrate.

9. A semiconductor package, comprising: a first semiconductor die and a second semiconductor die bonded together to form a first package; a third semiconductor die and a fourth semiconductor die bonded together to form a second package, the second package being stacked with the first package; a switch electrically coupled to a top surface of the first package; a plurality of electrical connections electrically coupling the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the switch; as well as Bond wires electrically couple the switch to a substrate. 10 . The semiconductor package of claim 9 , wherein the switch selectively electrically couples one of the semiconductor dies to the substrate using the bond wires.

11. The semiconductor package of claim 9, further comprising first and second pin pads disposed on the top surface of the first memory package, wherein: The first electrical connection extends from the first lead pad; and The second electrical connection extends from the second lead pad.

12. The semiconductor package of claim 11, further comprising a redistribution layer electrically coupling the second memory die to the second pin pad. 13 . The semiconductor package of claim 9 , wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bond wire.

14. The semiconductor package of claim 9, wherein at least one of the first electrical connection, the second electrical connection, the third electrical connection, and the fourth electrical connection is a bonding pad.

15. The semiconductor package of claim 9, wherein the switch is a multiplexer.

16. The semiconductor package of claim 9, further comprising a controller that provides a control signal to the switch, the control signal indicating which of the first memory die, the second memory die, the third memory die, and the fourth memory die is electrically coupled to the substrate.

17. A memory device comprising: Controller component; a first semiconductor package having a first semiconductor die bonded to a second semiconductor die; a second semiconductor package having a third semiconductor die bonded to a fourth semiconductor die, the second semiconductor package and the first semiconductor package being arranged in a stacked configuration; as well as A switch component is electrically coupled to the first semiconductor package and the second semiconductor package, the switch component selectively electrically coupling each of the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the substrate of the memory device using bonding wires that electrically couple the switch component to the substrate.

18. The memory device of claim 17, wherein the switch component is electrically coupled to the first semiconductor package using a plurality of bond wires.

19. The memory device of claim 17, wherein the switch component is electrically coupled to the first semiconductor package using a plurality of bonding pads.

20. The memory device of claim 17, wherein the switching means is a multiplexer.

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