Semiconductor structure and packaging structure

Abstract

The invention provides a semiconductor structure and a packaging structure, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate which is provided with a first surface and a second surface which are opposite to each other and comprises a first area and a second area; the first interconnection layer covers the second surface of the substrate; the first through hole is located in the first area of the substrate, and the first through hole penetrates through the substrate; the first insulating layer is located in the first through hole, and the first insulating layer covers the side wall of the first through hole and the first interconnection layer; the first capacitor structure comprises a first lower electrode layer, a first dielectric layer and a first upper electrode layer which are stacked in sequence, and the first lower electrode layer covers the first insulating layer; the first bonding pad and the second bonding pad are located on the side, away from the substrate, of the first interconnection layer; wherein the first bonding pad is electrically connected with the first lower electrode layer, and the second bonding pad is electrically connected with the first upper electrode layer. According to the embodiment of the invention, the semiconductor structure can improve the suppression effect of high-frequency power supply noise in the packaging substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a packaging structure. Background Art

[0002] With the rapid development of high-performance computing, such as artificial intelligence (AI), advanced packaging technologies such as COWOS technology are becoming increasingly important. In advanced packaging technology, the packaging substrate plays a vital role, not only to meet the basic electrical connection and physical support functions, but also to meet a series of more stringent requirements to adapt to the needs of modern electronic systems with high performance, high density and low power consumption.

[0003] Common package substrate capacitors usually adopt a planar structure, which occupies more package substrate space. At the same time, the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the package substrate capacitor are relatively high, which limits its performance in high-frequency applications and cannot effectively meet the challenges of current and future high-performance computing chips.

[0004] Therefore, a technical solution is urgently needed to effectively suppress high-frequency power noise in the packaging substrate to meet the needs of high-performance computing for low latency, high bandwidth and stable power management.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The present disclosure provides a semiconductor structure and a packaging structure, wherein the semiconductor structure can improve the suppression effect of high-frequency power supply noise in a packaging substrate.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a semiconductor structure is provided.

[0009] include:

[0010] A substrate having a first surface and a second surface opposite to each other, the substrate comprising a first region and a second region;

[0011] a first interconnect layer, the first interconnect layer covering the second surface of the substrate;

[0012] A first through hole, the first through hole is located in the first region of the substrate, and the first through hole passes through the substrate;

[0013] a first insulating layer, the first insulating layer being located in the first through hole and covering a side wall of the first through hole and the first interconnection layer;

[0014] A first capacitor structure, the first capacitor structure comprising a first lower electrode layer, a first dielectric layer and a first upper electrode layer stacked in sequence, the first lower electrode layer covering the first insulating layer;

[0015] A first pad and a second pad, wherein the first pad and the second pad are located on a side of the first interconnect layer facing away from the substrate;

[0016] The first pad is electrically connected to the first lower electrode layer, and the second pad is electrically connected to the first upper electrode layer.

[0017] In one embodiment, the first interconnection layer has a protrusion, which penetrates the first insulating layer and is electrically connected to the first lower electrode layer.

[0018] In one embodiment, the first lower electrode layer includes a first tantalum nitride layer and a first titanium nitride layer stacked in sequence, wherein the first tantalum nitride layer is electrically connected to the protrusion.

[0019] In one embodiment, the conductive material in the first interconnect layer is metal copper or metal aluminum.

[0020] In one embodiment, the semiconductor structure also includes a first contact plug, at least a portion of the first contact plug is located above the first surface and electrically connected to the first upper electrode layer; a second interconnect layer, the second interconnect layer is above the first contact plug; and a first conductive column, the first conductive column penetrates the substrate, one end of the first conductive column is electrically connected to the first contact plug through the second interconnect layer, and the other end is electrically connected to the second pad through the first interconnect layer.

[0021] In one embodiment, an orthographic projection of the first contact plug on the substrate overlaps with an orthographic projection of the first through-hole on the substrate.

[0022] In one embodiment, an orthographic projection area of ​​the first conductive pillar on the substrate is smaller than an orthographic projection area of ​​the first through hole on the substrate.

[0023] In one embodiment, at least a portion of the first contact plug is located in the first through hole and contacts the first upper electrode layer.

[0024] In one embodiment, the first upper electrode layer includes a second titanium nitride layer and a second tantalum nitride layer stacked in sequence, wherein the titanium nitride layer covers the first dielectric layer.

[0025] In one embodiment, the semiconductor structure further includes a second through hole, the second through hole is located in the second region of the substrate, and the second through hole penetrates the substrate;

[0026] a second insulating layer, the second insulating layer covering the sidewall of the second through hole, the first interconnection layer and the first surface of the second region;

[0027] A second capacitor structure, the second capacitor structure comprises a second lower electrode layer, a second dielectric layer and a second upper electrode layer stacked in sequence, the second lower electrode layer covers the second insulating layer;

[0028] a third pad and a fourth pad, wherein the third pad and the fourth pad are located on a side of the second interconnect layer facing away from the substrate;

[0029] The third pad is electrically connected to the second lower electrode layer, and the fourth pad is electrically connected to the second upper electrode layer.

[0030] In one embodiment, the semiconductor structure also includes a second contact plug and a third contact plug, which are located above the first surface, and the second contact plug is electrically connected to the second lower electrode layer, and the third contact plug is electrically connected to the second upper electrode layer; the third pad is electrically connected to the second lower electrode layer through the second contact plug and the second interconnect layer; and the fourth pad is electrically connected to the second upper electrode layer through the third contact plug and the second interconnect layer.

[0031] In one embodiment, an orthographic projection area of ​​the first capacitor structure on the substrate is larger than an orthographic projection area of ​​the second capacitor structure on the substrate.

[0032] In one embodiment, the number of the first capacitor structures is greater than the number of the second capacitor structures.

[0033] According to another aspect of the present disclosure, there is provided a packaging structure, comprising:

[0034] Package substrate;

[0035] The semiconductor structure mentioned above, the semiconductor structure is located on a packaging substrate;

[0036] Semiconductor device, the semiconductor device is located on the semiconductor structure.

[0037] In one embodiment, the first pad and the second pad in the semiconductor structure are electrically connected to the package substrate, and the third pad and the fourth pad in the semiconductor structure are electrically connected to the semiconductor device.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0040] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown; Figure 2 A top view of a substrate provided for an embodiment of the present disclosure; Figure 3-16 A schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown; Fig.17 A schematic diagram of a packaging structure provided by an embodiment of the present disclosure is shown; DETAILED DESCRIPTION

[0041] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0042] In advanced packaging technologies such as COWOS technology, the packaging structure consists of multiple key components, including system-on-chip, high-bandwidth memory, silicon interposer and packaging substrate. This packaging method tightly integrates different chips and memory components to improve the performance and efficiency of the overall system while reducing signal delay and power consumption.

[0043] Common package substrate capacitors usually adopt a planar structure, which occupies more package substrate space. Under the trend of high-density packaging and miniaturization, this has become a bottleneck in the design. At the same time, the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the package substrate capacitor are relatively high. Among them, the equivalent series resistance refers to the resistance inside the capacitor, which includes the resistance of the conductor inside the capacitor, the loss of the capacitor dielectric, and the resistance of the capacitor lead. The size of ESR directly affects the performance of the capacitor at high frequencies. High ESR will cause the effective capacitance value of the capacitor to decrease at high frequencies, increasing signal distortion and noise. Equivalent series inductance refers to the inductance inside the capacitor, which is mainly composed of the inductance effect of the capacitor lead and internal structure. At high frequencies, ESL resonates with the capacitance value of the capacitor, resulting in a decrease in the effective capacitance value of the capacitor. The size of ESL also affects the performance of the capacitor at high frequencies. High ESL will limit the filtering and decoupling capabilities of the capacitor at high frequencies. In other words, the capacitance value of the package substrate capacitor is usually low and performs poorly at high frequencies, which limits its performance in high-frequency applications and cannot effectively cope with the challenges of current and future high-performance computing chips.

[0044] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a packaging structure. By setting a capacitor for a packaging substrate in the semiconductor structure, that is, integrating the packaging substrate with the capacitor in the semiconductor structure with high density, the required physical space can be reduced, making the design more compact. At the same time, the power decoupling and signal integrity performance are improved in high-frequency applications, and the semiconductor structure is used to improve the suppression effect of high-frequency power supply noise in the packaging substrate.

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Figure 1 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure is shown; Figure 2 A top view of a substrate provided for an embodiment of the present disclosure;

[0047] Reference Figure 1 As shown, in one embodiment, a semiconductor structure 100,

[0048] include:

[0049] A substrate 110, wherein the substrate 110 has a first surface and a second surface opposite to each other, and includes a first region I and a second region II;

[0050] A first interconnect layer 120, the first interconnect layer 120 covers the second surface of the substrate 110;

[0051] A first through hole 130 , wherein the first through hole 130 is located in the first region I of the substrate, and the first through hole 130 passes through the substrate 110 ;

[0052] A first insulating layer 140 , wherein the first insulating layer 140 is located in the first through hole 130 , and the first insulating layer 140 covers the sidewall of the first through hole 130 and the first interconnection layer 120 ;

[0053] A first capacitor structure 150, the first capacitor structure 150 includes a first lower electrode layer 151, a first dielectric layer 152 and a first upper electrode layer 153 stacked in sequence, and the first lower electrode layer 151 covers the first insulating layer 140;

[0054] A first pad 161 and a second pad 162, wherein the first pad 161 and the second pad 162 are located at a side of the first interconnect layer 120 facing away from the substrate 110;

[0055] The first pad 161 is electrically connected to the first lower electrode layer 151 , and the second pad 162 is electrically connected to the first upper electrode layer 153 .

[0056] Reference Figure 1-Figure 2 , the semiconductor structure 100 is described in detail.

[0057] The material of the substrate 110 can be silicon, germanium, silicon germanium, silicon carbide and other materials. In some embodiments, the substrate 110 can be a silicon interposer, which is usually made of silicon material and has a high-density wiring layer, which can achieve high-speed, low-latency interconnection between chips and provide efficient distribution of power and signals. At the same time, the silicon interposer can integrate various functions, including power management circuits, capacitors, resistors, etc., to optimize the power network, reduce power noise, and improve signal integrity and overall system performance.

[0058] The substrate 110 includes a first region I and a second region II. Figure 2 As shown, the first region I can be located in the middle region of the substrate 110 for setting the capacitor structure for the package substrate, and the second region II can be located in the corner region of the substrate 110 for setting the capacitor structure for the substrate. By setting different types of capacitor structures in the first region I and the second region II, respectively, more sophisticated power management can be achieved, electromagnetic interference (EMI) can be reduced, and the signal path can be optimized, thereby improving the performance and efficiency of the entire system.

[0059] The first interconnect layer 120, also known as the first redistribution layer, has the main function of realizing electrical connection between the semiconductor structure 100 and the external packaging substrate. This layer is usually made of a highly conductive metal material, which has good conductivity and low resistivity to ensure efficient transmission of signals and currents. The first interconnect layer 120 covers the second surface of the substrate 110, that is, the first interconnect layer 120 is below the substrate 110 and in contact with each other.

[0060] The first insulating layer 140 is located inside the first through hole 130, covers the sidewalls of the first through hole 130, and also covers the surface of the first interconnection layer 120, that is, the first insulating layer 140 also covers the surface of the first interconnection layer 120 at the bottom of the first through hole 130. The first insulating layer 140 is made of a dielectric material, such as silicon dioxide, silicon nitride or other low-k materials. The first insulating layer 140 mainly plays a role in electrical isolation.

[0061] The first capacitor structure 150 is composed of a first lower electrode layer 151, a first dielectric layer 152 and a first upper electrode layer 153 stacked in sequence. The first dielectric layer 152 is located between the first lower electrode layer 151 and the first upper electrode layer 153, and is a key part of the capacitor structure. It is composed of materials with high dielectric constants, such as hafnium dioxide, titanium dioxide or silicon nitride. Compared with planar capacitors, the first capacitor structure 150 has a larger capacitance value, as well as lower equivalent series resistance (ESR) and equivalent series inductance (ESL).

[0062] The first pad 161 and the second pad 162 are located on the side of the first interconnect layer 120 away from the substrate 110, that is, the bottom of the first interconnect layer 120. The first pad 161 and the second pad 162 are connected to the corresponding pads on the package substrate through solder balls or conductive glue to form an electrical path.

[0063] Among them, the electrical connection between the first pad 161 and the second pad 162 and the first capacitor structure 150 is the key to realize power decoupling and signal filtering, that is, the first pad 161 and the second pad 162 are electrically connected to the package substrate, and at the same time, the first pad 161 is electrically connected to the first lower electrode layer 151, and the first pad 161 can be used as a connection point for power or grounding, and the second pad 162 is electrically connected to the first upper electrode layer 153, as the other end of the first capacitor structure 150, and the second pad 162 can be used as a power / ground connection point at the other end, so that the power or ground signal of the package substrate is directly introduced into the first capacitor structure 150. This direct connection helps to reduce the voltage drop and signal interference on the power line, and ensure the stable operation of the package substrate circuit.

[0064] In one embodiment, the first interconnection layer 120 has a convex portion 121, which penetrates the first insulating layer 140 and is electrically connected to the first lower electrode layer 151. The convex portion 121 is a part of the first interconnection layer 120, protruding from the plane of the first interconnection layer 120 to form a protruding and extending structure. The convex portion 121 penetrates the first insulating layer 140 and directly contacts the first lower electrode layer 151, thereby establishing an electrical path between the first interconnection layer 120 and the first capacitor structure 150. This direct connection method reduces the length of the signal transmission path, helps to reduce signal delay and voltage drop on the power line, and improves signal integrity and power stability.

[0065] In one embodiment, the first lower electrode layer 151 includes a first tantalum nitride layer 154 and a first titanium nitride layer 155 stacked in sequence, wherein the first tantalum nitride layer 154 is electrically connected to the protrusion 121. The first tantalum nitride layer 154, as the outer layer of the first lower electrode layer 151, is directly electrically connected to the protrusion 121 of the first interconnection layer 120. Tantalum nitride is a material with high conductivity and good chemical stability, which can ensure reliable electrical contact with the first interconnection layer 120 and provide chemical protection for subsequent process steps. The first titanium nitride layer 155 is located on the first tantalum nitride layer 154. Titanium nitride also has good conductivity and mechanical strength, which can enhance the overall structural stability of the first lower electrode layer 151 and provide a flat and stable interface for the first dielectric layer 152. In the prior art, the interconnection structure is directly in contact with the titanium nitride layer. Due to the difference in material properties between the two, a weak bond may be formed at the interface, resulting in the so-called "peeling" phenomenon, that is, peeling between material layers. This peeling reduces the reliability of the electrical connection, increases the contact resistance, and even causes circuit failure in extreme cases. In this embodiment, the above technical problems can be effectively solved, so that the protrusion 121 of the first interconnection layer 120 is reliably electrically connected to the first lower electrode layer 151 .

[0066] In one embodiment, the conductive material in the first interconnect layer 120 is copper or aluminum. Both metals have excellent conductivity, can effectively transmit current and signals, and have good cost-effectiveness and process compatibility.

[0067] In one embodiment, the semiconductor structure 100 further includes: a first contact plug 171, at least a portion of the first contact plug 171 is located above the first surface and is electrically connected to the first upper electrode layer 153; a second interconnection layer 180, the second interconnection layer 180 is above the first contact plug 171; and a first conductive pillar 190, the first conductive pillar 190 penetrates the substrate, one end of the first conductive pillar 190 is electrically connected to the first contact plug 171 through the second interconnection layer 180, and the other end of the first conductive pillar 190 is electrically connected to the second pad 162 through the first interconnection layer 120. The first contact plug 171 serves as a vertical connection between the first upper electrode layer 153 and the second interconnection layer 180, and the first contact plug 171 ensures that the first upper electrode layer 153 can establish an electrical path with the second interconnection layer 180. The second interconnection layer 180 is located above the first contact plug 171, and the second interconnection layer 180 transmits the signal from the first contact plug 171 to the top of the first conductive pillar 190 through horizontal wiring to achieve electrical connection between different layers. The first conductive column 190 is a conductive structure that vertically penetrates the substrate 110, one end of which is electrically connected to the second interconnect layer 180, and the other end is electrically connected to the first interconnect layer 120, so as to transmit the signal from the second interconnect layer 180 to the first interconnect layer 120. Finally, the signal reaches the second pad 162 through the first interconnect layer 120. The second pad 162 serves as a connection point for the external packaging substrate, realizing the electrical connection between the internal circuit of the chip and the outside world. In other words, the first upper electrode layer 153 is electrically connected to the second pad 162 through the first contact plug 171, the second interconnect layer 180, and the first conductive column 190 in sequence. In this way, the signal transmission path between the first upper electrode layer 153 and the second pad 162 is established, ensuring the realization of the functions of the first capacitor structure 150, such as power decoupling, signal filtering, etc., while meeting the requirements of modern integrated circuits for high-density wiring and high-performance electrical connections.

[0068] In one embodiment, the orthographic projection of the first contact plug 171 on the substrate 110 overlaps with the orthographic projection of the first through hole 130 on the substrate 110. That is, the first contact plug 171 is directly above the first through hole 130, which can achieve the shortest electrical path, reduce signal delay, improve signal integrity and power stability, and at the same time, by vertically stacking the electrical connection structure, a more complex circuit layout can be achieved within a limited chip area while maintaining high quality of signal transmission and reliability of the power network.

[0069] In one embodiment, the orthographic projection area of ​​the first conductive pillar 190 on the substrate 110 is smaller than the orthographic projection area of ​​the first through hole 130 on the substrate 110. As a conductive structure that vertically penetrates the substrate 110, the first conductive pillar 190 mainly functions to establish a direct electrical path from the second interconnection layer 180 to the first interconnection layer 120, while the first through hole 130 mainly provides sufficient space for the first capacitor structure 150, that is, the size of the first through hole 130 determines the performance of the first capacitor structure 150, such as the capacitance value. In this way, the size of the first through hole 130 is larger than the size of the first conductive pillar 190. The smaller size of the first conductive pillar 190 allows a more complex circuit layout to be implemented within a limited chip area while maintaining high quality of signal transmission and reliability of the power supply network. The larger size of the first through hole 130 contributes to power supply decoupling of the package substrate.

[0070] In one embodiment, at least a portion of the first contact plug 171 is located in the first through hole 130 and contacts the first upper electrode layer 153. At least a portion of the first contact plug 171 is located in the first through hole 130, which can increase the contact area between the first contact plug 171 and the first upper electrode layer 153, thereby reducing the contact resistance, thereby reducing the energy loss during signal transmission, and improving power efficiency and signal integrity.

[0071] In one embodiment, the first upper electrode layer 153 includes a second titanium nitride layer 156 and a second tantalum nitride layer 157 stacked in sequence, wherein the second titanium nitride layer 156 covers the first dielectric layer 152. That is, the second tantalum nitride layer 157 is in contact with the first contact plug 171, and the second tantalum nitride layer 157 has better adhesion and compatibility with the material (usually copper or aluminum) of the first contact plug 171, and can form a more stable interface, reducing the occurrence of peeling. The second tantalum nitride layer 157 can provide a layer of chemical protection to prevent the material of the first contact plug 171 from directly contacting the second titanium nitride layer 156, avoid chemical reactions or diffusion that may occur in subsequent process steps, and maintain the chemical stability and structural integrity of each layer of material. The second tantalum nitride layer 157, as a transition layer between the first contact plug 171 and the second titanium nitride layer 156, can reduce contact resistance, improve the efficiency and quality of signal transmission, and maintain good electrical connection performance. By introducing the second tantalum nitride layer 157 between the first contact plug 171 and the second titanium nitride layer 156, effective isolation between material layers can be achieved, avoiding interlayer peeling caused by material incompatibility or stress during the process, and improving the long-term stability and reliability of the entire capacitor structure.

[0072] In one embodiment, the semiconductor structure 100 further includes a second through hole 230 , the second through hole 230 is located in the second region II of the substrate 110 , and the second through hole 230 penetrates the substrate 110 ;

[0073] A second insulating layer 240, the second insulating layer 240 covers the sidewalls of the second through hole 230, the first interconnection layer 120 and the first surface of the second region II;

[0074] A second capacitor structure 250, the second capacitor structure 250 comprises a second lower electrode layer 251, a second dielectric layer 252 and a second upper electrode layer 253 stacked in sequence, and the second lower electrode layer 251 covers the second insulating layer 240;

[0075] A third pad 261 and a fourth pad 262 , wherein the third pad 261 and the fourth pad 262 are located on a side of the second interconnect layer 180 facing away from the substrate 110 ;

[0076] The third pad 261 is electrically connected to the second lower electrode layer 251 , and the fourth pad 262 is electrically connected to the second upper electrode layer 253 .

[0077] That is to say, the third pad 261 and the fourth pad 262 are electrically connected to the semiconductor device. At the same time, the third pad 261 is electrically connected to the second lower electrode layer 251. The third pad 261 can be used as a connection point for the signal line of the semiconductor device. The fourth pad 262 is electrically connected to the second upper electrode layer 253. As the other end of the second capacitor structure 250, the fourth pad 262 can be used as the signal line of the semiconductor device at the other end. In this way, through the electrical connection between the third pad 261 and the fourth pad 262 and the second capacitor structure 250, an efficient electrical path can be established between the signal line inside the semiconductor device and the second capacitor structure 250, thereby reducing the voltage drop and signal interference on the signal line and ensuring high-quality signal transmission.

[0078] In one embodiment, the semiconductor structure 100 further includes a second contact plug 271 and a third contact plug 272, which are located above the first surface, and the second contact plug 271 is electrically connected to the second lower electrode layer 251, and the third contact plug 272 is electrically connected to the second upper electrode layer 253; the third pad 261 is electrically connected to the second lower electrode layer 253 and the second interconnect layer 180 through the second contact plug 271; and the fourth pad 262 is electrically connected to the second upper electrode layer 251 through the third contact plug 272 and the second interconnect layer 180. In other words, the function of the second contact plug 271 is to establish an electrical path between the second lower electrode layer 251 and the second interconnect layer 180, thereby realizing the connection between the second capacitor structure 250 and the external circuit. The third contact plug 272 is used to connect the second upper electrode layer 253 and the second interconnect layer 180, ensuring that the other end of the second capacitor structure 250 can establish an electrical path with the external circuit. The third pad 261 can be used as a connection point for the signal line to directly introduce the signal into the second capacitor structure 250. The fourth pad 262 is used as a connection point for the other end signal line to connect the other end of the second capacitor structure 250 to achieve a complete signal transmission path, while providing power decoupling and signal filtering functions. The orthographic projections of the second contact plug 271 and the third contact plug 272 on the substrate 110 do not overlap with the orthographic projections of the second through hole 230 on the substrate 110, that is, the second contact plug 271 and the third contact plug 272 are not directly above the second through hole 230.

[0079] In one embodiment, the orthographic projection area of ​​the first capacitor structure 150 on the substrate 110 is greater than the orthographic projection area of ​​the second capacitor structure 250 on the substrate 110. The first capacitor structure 150 has a larger orthographic projection area, and the first capacitor structure 150 can provide a larger capacitance value. The power supply decoupling on the package substrate needs to handle larger current fluctuations and a wider frequency range to ensure the stability and signal integrity of the power supply in high-speed, high-power applications. The larger size of the first capacitor structure 150 allows it to store and release more charge, effectively reducing the voltage fluctuations on the power line and improving the stability of the power supply network. In contrast, the orthographic projection area of ​​the second capacitor structure 250 is smaller because it is mainly used for decoupling of semiconductor devices, and the current fluctuations and frequency ranges handled are relatively small. The power supply decoupling requirements inside semiconductor devices are usually concentrated on specific signal paths and local power supply networks, so the design of the second capacitor structure 250 focuses more on providing a fast response and low-latency decoupling effect to reduce transient voltage fluctuations on signal lines and improve signal integrity and system performance.

[0080] In one embodiment, the number of the first capacitor structure 150 is greater than the number of the second capacitor structure 250. Due to the power decoupling effect of the first capacitor structure 150 on the package substrate, a larger number is required to ensure the stability of the power network of the entire system. The power decoupling capacitor on the package substrate needs to handle larger current fluctuations, especially in high-speed, high-power applications, to reduce voltage drops and signal interference on the power line. Therefore, increasing the number of first capacitor structures 150 can provide a denser decoupling network to ensure the stability of the power supply and the integrity of the signal. In contrast, the second capacitor structure 250 is mainly used for decoupling inside semiconductor devices, and the current fluctuations and frequency ranges handled are relatively small. The power decoupling requirements inside semiconductor devices are usually concentrated on specific signal paths and local power networks, so a smaller number is required, but more precise layout and optimization are required to achieve fast response and low-latency decoupling effects.

[0081] The embodiments of the present disclosure can reduce the required physical space and make the design more compact by providing capacitors for the packaging substrate in the semiconductor structure, i.e., integrating the packaging substrate with the capacitors in the semiconductor structure at a high density. At the same time, the power decoupling and signal integrity performance can be improved in high-frequency applications, thereby achieving the semiconductor structure to improve the suppression effect of high-frequency power supply noise in the packaging substrate.

[0082] On the basis of the above-mentioned embodiment, the present disclosure also provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure is described in detail below.

[0083] Figure 3-16 A schematic diagram of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown;

[0084] In one embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0085] See also Figure 3 As shown, a substrate 110 is provided, the substrate 110 has a first surface, and the substrate 110 includes a first region I and a second region II;

[0086] See also Figure 4 As shown, a first groove 131 is formed in the first region I of the substrate 110, and a second groove 231 is formed in the second region II of the substrate 110;

[0087] See also Figure 5 As shown, an insulating material layer 340 is deposited, and the insulating material layer 340 covers the sidewalls and bottom surfaces of the first groove 131 and the second groove 231 , and covers the first surface.

[0088] See also Figure 6-10As shown, a lower electrode material layer 351 , a dielectric material layer 352 , and an upper electrode material layer 253 are deposited in sequence, and the lower electrode material layer 351 covers the insulating material layer 340 .

[0089] See also Fig.13 As shown, the lower electrode material layer 351, the dielectric material layer 352, and the upper electrode material layer 253 covering the first surface of the first region I are etched to expose the first surface. The insulating material layer 340, the lower electrode material layer 351, the dielectric material layer 352, and the upper electrode material layer 253 retained in the first region I become the first insulating layer 140, the first lower electrode layer 151, the first dielectric layer 152, and the first upper electrode layer 153 respectively; the insulating material layer 340, the lower electrode material layer 351, the dielectric material layer 352, and the upper electrode material layer 253 retained in the second region II become the second insulating layer 240, the second lower electrode layer 251, the second dielectric layer 252, and the second upper electrode layer 253 respectively.

[0090] See also Fig.16 As shown, the side of the substrate 110 away from the first surface is thinned to expose the first insulating layer 140. At this time, the first groove 131 and the second groove 231 become the first through hole 130 and the second through hole 230 respectively, and the surface of the substrate 110 away from the first surface is the second surface. The first lower electrode layer 151, the first dielectric layer 152, and the first upper electrode layer 153 in the first through hole 130 form a first capacitor structure 150, and the second lower electrode layer 251, the second dielectric layer 252, and the second upper electrode layer 253 retained in the second region II form a second capacitor structure 250.

[0091] See also Figure 1 As shown, the first insulating layer 140 is etched from the side of the substrate 110 away from the first surface to expose the first lower electrode layer 151; a first interconnection layer 120 is formed to cover the second surface of the substrate, and a protrusion 121 is formed at the same time, the protrusion 121 penetrates the first insulating layer 140 and is electrically connected to the first lower electrode layer 151; a first pad 161 and a second pad 162 are formed on the side of the first interconnection layer 120 away from the substrate 110, wherein the first pad 161 is electrically connected to the first lower electrode layer 151, and the second pad 162 is electrically connected to the first upper electrode layer 153.

[0092] In one embodiment, see Figure 11-12 After depositing the lower electrode material layer 351 , the dielectric material layer 352 , and the upper electrode material layer 253 , the preparation method further includes depositing a filling material layer 358 , the filling material layer 358 filling the first groove 131 and the second groove 231 , and covering the upper electrode material layer 253 ; and planarizing the filling material layer 358 to expose the upper electrode material layer 253 .

[0093] In one embodiment, see Fig.13 , etching the lower electrode material layer 351, the dielectric material layer 352, and the upper electrode material layer 253 covering the first surface of the first region I to expose the first surface, and also including etching away the filling material layer 358 in the first region I, and the filling material layer 358 retained in the second region II becomes the first filling layer 258.

[0094] In one embodiment, see Figure 14-15 After etching the lower electrode material layer 351, the dielectric material layer 352, and the upper electrode material layer 253 covering the first surface of the first region I to expose the first surface, the preparation method further includes forming a covering dielectric layer 170, the covering dielectric layer 170 covering the first surface of the first region I and the second upper electrode layer 253 of the second region II; forming a first contact plug 171, a second contact plug 271, and a third contact plug 272 in the covering dielectric layer 170, wherein the first contact plug 171 is at least partially located in the first region I and the second upper electrode layer 253 of the second region II; A through hole 130 is formed and electrically connected to the first upper electrode layer 153, a second contact plug 271 is electrically connected to the second lower electrode layer 251, and a third contact plug 272 is electrically connected to the second upper electrode layer 253; a second interconnect layer 180 is formed on the covering dielectric layer 170, and a third pad 261 and a fourth pad 262 are formed on the side of the second interconnect layer 180 facing away from the substrate 110, wherein the third pad 261 is electrically connected to the second contact plug 271, and the fourth pad 262 is electrically connected to the third contact plug 272.

[0095] In one embodiment, see Figure 1 Before etching the first insulating layer 140 from the side of the substrate 110 away from the first surface, the preparation method also includes forming a first conductive column 190, the first conductive column 190 penetrates the covering dielectric layer 170 and the substrate 110, and the first interconnection layer 120 is electrically connected to the second interconnection layer 180 through the first conductive column 190.

[0096] In one embodiment, see Figure 6-10 As shown, a lower electrode material layer 351, a dielectric material layer 352, and an upper electrode material layer 253 are deposited in sequence, including depositing a first tantalum nitride material layer 354, a first titanium nitride material layer 355, a dielectric material layer 352, a second titanium nitride material layer 356, and a second tantalum nitride material layer 357 in sequence.

[0097] Based on the above embodiments, the present disclosure also provides a packaging structure, which is described in detail below.

[0098] Fig.17 A schematic diagram of a packaging structure provided by an embodiment of the present disclosure is shown;

[0099] In one embodiment, a packaging structure 200 is provided, comprising:

[0100] Packaging substrate 201;

[0101] The semiconductor structure 100 mentioned above is located on a packaging substrate 201;

[0102] The semiconductor device 202 is located on the semiconductor structure 100 .

[0103] In one embodiment, the first pad 161 and the second pad 162 in the semiconductor structure 100 are electrically connected to the package substrate 201, and the third pad 261 and the fourth pad 262 in the semiconductor structure 100 are electrically connected to the semiconductor device 202. The first pad 161 and the second pad 162 are electrically connected to the package substrate, and at the same time, the first pad 161 is electrically connected to the first lower electrode layer 151, and the first pad 161 can be used as a connection point for power or grounding. The second pad 162 is electrically connected to the first upper electrode layer 153 as the other end of the first capacitor structure 150, and the second pad 162 can be used as a power / ground connection point at the other end. In this way, the power or ground signal of the package substrate is directly introduced into the first capacitor structure 150. This direct connection helps to reduce the voltage drop and signal interference on the power line, and ensure the stable operation of the package substrate circuit. In addition, through the electrical connection between the third pad 261 and the fourth pad 262 and the semiconductor device, an efficient electrical path can be established between the signal line inside the semiconductor device and the second capacitor structure 250, reducing the voltage drop and signal interference on the signal line, and ensuring high-quality signal transmission.

[0104] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0105] In the description of the present disclosure, it should be understood that the terms "including" and "having" and any variations thereof used herein are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0106] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and it can make the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate having a first surface and a second surface opposite to each other, the substrate comprising a first region and a second region; a first interconnect layer, the first interconnect layer covering the second surface of the substrate; a first through hole, wherein the first through hole is located in the first region of the substrate and passes through the substrate; a first insulating layer, wherein the first insulating layer is located in the first through hole, and the first insulating layer covers a side wall of the first through hole and the first interconnection layer; A first capacitor structure, the first capacitor structure comprising a first lower electrode layer, a first dielectric layer and a first upper electrode layer stacked in sequence, the first lower electrode layer covering the first insulating layer; A first pad and a second pad, wherein the first pad and the second pad are located on a side of the first interconnect layer facing away from the substrate; The first pad is electrically connected to the first lower electrode layer, and the second pad is electrically connected to the first upper electrode layer.

2. The semiconductor structure according to claim 1, characterized in that: The first interconnection layer has a convex portion, and the convex portion penetrates the first insulating layer and is electrically connected to the first lower electrode layer.

3. The semiconductor structure according to claim 2, characterized in that: The first lower electrode layer includes a first tantalum nitride layer and a first titanium nitride layer stacked in sequence, wherein the first tantalum nitride layer is electrically connected to the protrusion.

4. The semiconductor structure according to claim 2, characterized in that: The conductive material in the first interconnection layer is metal copper or metal aluminum.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a first contact plug, at least a portion of which is located above the first surface and electrically connected to the first upper electrode layer; a second interconnect layer, which is above the first contact plug; A first conductive column, wherein the first conductive column penetrates the substrate, one end of the first conductive column is electrically connected to the first contact plug through the second interconnect layer, and the other end of the first conductive column is electrically connected to the second pad through the first interconnect layer.

6. The semiconductor structure according to claim 5, characterized in that: An orthographic projection of the first contact plug on the substrate overlaps with an orthographic projection of the first through hole on the substrate.

7. The semiconductor structure according to claim 5, characterized in that: An orthographic projection area of ​​the first conductive pillar on the substrate is smaller than an orthographic projection area of ​​the first through hole on the substrate.

8. The semiconductor structure according to claim 5, characterized in that: At least a portion of the first contact plug is located in the first through hole and contacts the first upper electrode layer.

9. The semiconductor structure according to claim 1, characterized in that: The first upper electrode layer includes a second titanium nitride layer and a second tantalum nitride layer stacked in sequence, wherein the second titanium nitride layer covers the first dielectric layer.

10. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a second through hole, wherein the second through hole is located in the second region of the substrate and passes through the substrate; a second insulating layer, the second insulating layer covering the sidewall of the second through hole, the first interconnection layer and the first surface of the second region; a second capacitor structure, the second capacitor structure comprising a second lower electrode layer, a second dielectric layer, and a second upper electrode layer stacked in sequence, the second lower electrode layer covering the second insulating layer; a third pad and a fourth pad, wherein the third pad and the fourth pad are located on a side of the second interconnect layer facing away from the substrate; Wherein, the third pad is electrically connected to the second lower electrode layer, and the fourth pad is electrically connected to the second upper electrode layer.

11. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes a second contact plug and a third contact plug, which are located above the first surface, and the second contact plug is electrically connected to the second lower electrode layer, and the third contact plug is electrically connected to the second upper electrode layer; the third pad is electrically connected to the second lower electrode layer through the second contact plug and the second interconnection layer; the fourth pad is electrically connected to the second upper electrode layer through the third contact plug and the second interconnection layer.

12. The semiconductor structure according to claim 10, characterized in that An orthographic projection area of ​​the first capacitor structure on the substrate is larger than an orthographic projection area of ​​the second capacitor structure on the substrate.

13. The semiconductor structure according to claim 10, characterized in that: The number of the first capacitor structures is greater than the number of the second capacitor structures.

14. A packaging structure, characterized in that: include: Package substrate; The semiconductor structure according to any one of claims 1 to 13, wherein the semiconductor structure is located on the packaging substrate; A semiconductor device is located on the semiconductor structure.

15. The packaging structure according to claim 14, characterized in that: The first pad and the second pad in the semiconductor structure are electrically connected to the packaging substrate, and the third pad and the fourth pad in the semiconductor structure are electrically connected to the semiconductor device.

Images