Control method and circuit for electronic equipment

Abstract

The invention relates to a control method and circuit for electronic equipment. A control circuit provides a drive signal to an electronic switch of an electronic converter. The first drive circuit has a first enable node receiving a first enable signal and a PWM signal generator circuit configured to provide a PWM drive signal in response to the first enable signal. The second drive circuit has a second enable node configured to receive a second enable signal and a PFM signal generator circuit configured to provide a PFM drive signal in response to the second enable signal. Logic circuitry coupled to the first drive circuit and the second drive circuit is configured to assert at least one of the first enable signal and the second enable signal in response to the mode select signal.

Description

[0001] Priority claim

[0002] This application claims the benefit of Italian Patent Application No. 102023000018543 filed on September 11, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to methods and circuits for (eg, DC-DC) electronic converter circuits, such as power management or regulation methods and circuits.

[0004] One or more embodiments may be used in various application scenarios, such as the automotive field. Background Art

[0005] Power supply circuits such as AC / DC or DC / DC switched mode power supplies are well known in the art. There are many types of electronic converters, mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. Isolated converters are, for example, "flyback", "forward", "half-bridge" and "full-bridge" type converters. These types of converters are well known to those skilled in the art, as demonstrated, for example, by application note AN513 / 0393 "Topologies for Switched Mode Power Supplies", L. Wuidart, 1999, STMicroelectronics (incorporated herein by reference).

[0006] Figure 1 FIG. 2 is a schematic diagram of a DC / DC electronic converter 20. In particular, the universal electronic converter 20 includes two circuits for receiving a DC voltage V IN The input terminals 200a and 200b and two for supplying a DC voltage V out For example, the input voltage V IN It may be supplied by a DC voltage source 10 such as a battery, or may be obtained from an AC voltage with the aid of a rectification circuit such as a bridge rectifier (and possibly a filtering circuit). Alternatively, the output voltage V out Can be used to supply (eg, current) to an electrical load 30 .

[0007] As is well known, an electronic converter includes one or more reactive components (such as inductors and / or capacitors) and one or more electronic switches configured to control current flow from input terminals 200a and 200b to the one or more reactive components and / or current flow from the one or more reactive components to output terminals 202a and 202b.

[0008] Due to the different operating modes of the electronic converter, the current intensity in the electrical load 30 can vary within a wide range of values.

[0009] As those skilled in the art will appreciate, electronic (e.g., DC-DC) converter circuits can operate in at least two operating modes: a continuous current mode (CCM) mode, which can be applied to any load value, but whose efficiency is greatly reduced at "light" load (e.g., near zero) values ​​due to switching losses; and a discontinuous current mode (DCM) mode, which is suitable for light load values ​​but at the expense of regulation and electromagnetic interference emissions (EMI).

[0010] Switching between the two operating modes (CCM to DCM and vice versa) can be complex and result in discontinuities, burst behavior and offsets in the regulated voltage. Also, reducing internal power consumption can be challenging, for example due to the presence of enabling circuitry for driving on and off.

[0011] A conventional system for controlling the operation of a DC-DC converter is known as Peak Current Mode (PCM).

[0012] In a DC-DC converter device equipped with a PCM control loop, the transition from CCM to DCM and from DCM to CCM occurs by means of an internally generated signal called a SKIP signal.

[0013] In another conventional system, such as a pulse frequency modulation (PFM) control loop, the internally generated transient control signal is referred to as a pulse skipping regulation.

[0014] (Pulse Regulation) The SKIP signal is generated by comparing the output voltage V out The reference voltage for PCM regulation is generated. For example, when the output voltage V out When is greater than a reference voltage, the internally generated SKIP signal is asserted to a first logic value (eg, “high” or “1”).

[0015] In response to the assertion, the switching activity of the DC-DC converter is interrupted and the output node V out enters a high impedance condition.

[0016] On the contrary, when the output voltage V outBelow the reference voltage, the internally generated SKIP signal is de-asserted to have a second logic value (eg, “low” or “0”).

[0017] In response to de-assertion, switching activity (re)starts pumping the output load.

[0018] Such conventional arrangements may exhibit one or more of the following disadvantages: the output voltage V out Large ripple on the output, output voltage offset, complexity of burst regulation, small bandwidth PCM loop (especially at low power), poor quality response to transient current loads cause V out undervoltage on the , and electromagnetic interference.

[0019] Contributions are needed in technology to overcome the shortcomings mentioned above. Summary of the invention

[0020] One or more embodiments may relate to control circuitry.

[0021] One or more embodiments may be directed to corresponding electronic devices, such as, for example, a buck converter.

[0022] One or more embodiments facilitate providing a way to smoothly control operating mode transitions in an electronic converter device.

[0023] One or more embodiments utilize a protocol to manage low / high power transitions in a single DC-DC converter.

[0024] For example, a transition of an electronic converter from a CCM to a DCM operating mode can be performed while consuming very low quiescent current, especially at light loads.

[0025] One or more embodiments facilitate very fast switching between control loops in various operating modes in a manner that avoids discontinuities in the output regulation voltage provided.

[0026] One or more embodiments provide a way to handle internal enabling circuitry in order to reduce quiescent current consumption during idle phases.

[0027] One or more embodiments involve relatively simple analog circuitry, thereby providing a simplified design for a controller of a DC-DC converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments will now be described by way of non-limiting examples with reference to the accompanying drawings, in which:

[0029] Figure 1 is an example diagram of an electronic device;

[0030] Figure 2is an example diagram of an electronic device according to the present disclosure;

[0031] Figure 3 yes Figure 2 An example diagram of a portion of an electronic device illustrated in;

[0032] Figure 4 yes Figure 2 An example diagram of another portion of the electronic device illustrated in;

[0033] Figure 5 is a diagram of a control method according to the present disclosure;

[0034] Figure 6 is a diagram of an electronic device according to the present disclosure;

[0035] Fig. 7A and Figure 7B is a graph showing the evolution of a signal over time in one or more embodiments;

[0036] Figure 8 is a diagram of a portion of a control circuit according to the present disclosure;

[0037] Figures 9 to 14 is a graph showing the evolution of a signal over time in one or more embodiments. DETAILED DESCRIPTION

[0038] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0039] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0040] The edges of a feature drawn in a figure do not necessarily indicate the end of the extent of the feature.

[0041] In the following description, one or more specific details are explained to provide a deeper understanding of examples of embodiments of the present description. Embodiments can be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0042] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this description do not necessarily refer to the same embodiment.

[0043] Furthermore, particular configurations, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0045] For simplicity, in the following detailed description, the same reference symbols may be used to represent nodes / lines in a circuit and signals that may appear on the nodes or lines.

[0046] Figure 2 FIG. 1 is a schematic diagram showing an embodiment of a buck converter 20a having an improved control circuit 100. Specifically, the buck converter 20a includes a circuit for receiving a DC input voltage V IN The two input terminals 200a and 200b are used to supply the output voltage V out The two output terminals 202a and 202b, where the output voltage V out Equal to or lower than the input voltage V IN .

[0047] In the considered example, the buck converter 20a comprises two electronic switches Q1 and Q2 (and their current paths) coupled in series (eg directly) between input terminals 200a and 200b, wherein an intermediate node between the electronic switches Q1 and Q2 represents a switching node Lx.

[0048] Specifically, the electronic switch Q1 is a high-side switch coupled (e.g., directly coupled) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch coupled (e.g., directly coupled) between the switching node Lx and the (negative) terminal 200b, which terminal 200b often represents the ground GND. Therefore, the (high-side) switch Q1 and the (low-side) switch Q2 represent a switch configured to connect the switching node Lx to the terminal 200a (voltage V IN ) or half bridge of terminal 200b (ground GND).

[0049] In various embodiments, switches Q1 and / or Q2 are transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs), for example n-channel FETs, such as NMOS. Typically, the second electronic switch Q2 is also implemented with only a diode, with the anode connected to terminal 200b and the cathode connected to the switch node Lx.

[0050] In the embodiment considered, the low pass filter LPF is located intermediate the switching node Lx and the output terminal 202a.

[0051] For example, the low pass filter LPF includes an inductive element L (such as an inductor) coupled (eg, directly coupled) between the switching node Lx and the (positive) output terminal 202a and a capacitor C coupled (eg, directly coupled) between the output terminals 202a and 202b.

[0052] like Figure 2 As illustrated in , the (negative) output terminal 202b is coupled (eg, directly coupled) to the (negative) input terminal 200b.

[0053] like Figure 2 As illustrated in FIG. 1 , output terminals 202 a and 202 b are coupled via a feedback network (eg, voltage divider R_up, R_down) configured to provide a feedback voltage V FB As the output voltage V out A scaled copy of .

[0054] like Figure 2 As illustrated in FIG. 1 , the electronic switches Q1, Q2 are configured to be driven by respective control signals DRV1, DRV2 generated via the controller circuit 10. For example, the second control signal DRV2 for the second electronic switch Q2 may be obtained by inverting (eg, via the NOT gate 201) the first control signal DRV1.

[0055] like Figure 2 As illustrated in the figure, the controller circuit 100 includes: a first control circuit 30, such as a pulse width modulation (PWM) peak current mode (PCM) control circuit, suitable for a first operation mode or mode of the converter 20a, such as a continuous current mode (CCM) or a discontinuous current mode (DCM) operation mode; a second control circuit 40, such as a pulse frequency modulation (PFM) constant ON time (COT) control circuit, suitable for a second operation mode or mode of the converter 20a, such as a light load mode; and a mode selection circuit 50, such as a comparator circuit 500, configured to provide a trigger signal JUMP2COT to trigger the control unit MCU to assert or de-assert the enable signal EN_PCM, EN_COT to enable the first or second control circuit 30, 40 to drive the switching circuit Q1, Q2, as discussed below.

[0056] like Figure 2 As illustrated in the figure, a logic unit MCU (such as a microcontroller) is coupled to the controller circuit 100 to provide one or more activation signals thereto, such as a first enable signal EN_PCM configured to activate / deactivate the first control circuit 30 and / or a second enable signal EN_COT configured to activate / deactivate the second control circuit 40.

[0057] like Figure 2As illustrated in FIG. 1 , the first control circuit 30 includes: a first error amplifier circuit 300, including a first error amplifier circuit 300 coupled to a reference voltage level V REF The first input node 300a is coupled to the feedback network R_up, R_down to receive the feedback voltage V FB The first error amplifier circuit 300 is configured to provide a difference signal Vc as a feedback voltage V at an output node 300c. FB With reference voltage level V REF the difference between the first comparison signal Vc and the second comparison signal Vc; a PCM circuit 302, coupled to the first comparator circuit 300 to receive the first comparator signal Vc and coupled to the control unit MCU to receive the enable signal EN_PCM, the PCM circuit 302 being configured to generate a PWM control signal PWM1 for the switch circuits Q1 and Q2 when the first enable signal EN_PCM is asserted; preferably, a clamp circuit (CC) 304 is inserted between the first comparator circuit 300 and the PCM circuit 302, the clamp circuit 304 being configured to apply a voltage clamp to the first comparison signal Vc to limit the voltage value of the comparison signal Vc, for example, so as to maintain the same voltage level as the second control circuit 40, as discussed below.

[0058] like Figure 2 As illustrated in FIG. 1 , the second control circuit 40 includes: a second comparator or error amplifier circuit 400, including a circuit coupled to a reference voltage level V REF The first input node 400a is coupled to the feedback network R_up, R_down to receive the feedback voltage V FB The second error amplifier circuit 400 is configured to provide a comparison or difference signal V2 at an output node 400c as a feedback voltage V FB With reference voltage level V REF and a timing circuit 402, coupled to the second comparator circuit 400 to receive the comparison signal V2 and coupled to the control unit MCU to receive the second enable signal EN_COT, the timing circuit 402 is configured to generate a timing signal for the switching circuits Q1, Q2 when the second enable signal EN_COT is asserted.

[0059] like Figure 2 As illustrated in FIG. 1 , the mode selection circuit 50 includes a third comparator circuit 500 having a voltage level V coupled to a reference voltage level V REF The first input node 500a is coupled to the feedback network R_up, R_down to receive the feedback voltage V FB The third comparator circuit 500 is configured to perform a feedback voltage V FB With reference voltage level VREF , thereby providing a trigger signal JUMP2COT at the output node 500c as a result of the comparison.

[0060] It is noted that the functionality discussed with respect to separate and distinct circuits 300 , 400 , 500 may actually involve the same circuitry performing error amplifier / comparator operations shared between the various control circuits 30 , 40 , 50 in one or more embodiments.

[0061] Figure 3 and Figure 4 is an example of a portion of the second control circuit 40 .

[0062] like Figure 3 As illustrated in , the method according to the present disclosure includes calibrating at least one of the second comparator 400 and the timing circuit 402 of the second circuit 40 when the first control circuit 30 is enabled, for example in response to the control unit MCU asserting the first enable signal EN_PCM.

[0063] Performing a calibration operation of the second control circuit 40 at the beginning of the operation phase of the first circuit 30 driving the switching circuits Q1, Q2 facilitates its continued operation in providing an output signal to the load.

[0064] like Figure 3 As illustrated in , calibrating the comparator circuit 400 of the second control circuit 40 includes compensating for an offset of the comparator circuit 400 .

[0065] like Figure 3 As illustrated in , the offset non-ideality of the comparator 400 is modeled as a voltage generator Voff coupled to the second input node 400b of the comparator.

[0066] To compensate for such offset, comparator 400 may include dedicated offset compensation circuitry, or it may be coupled to a control logic MCU that includes internal circuitry configured to perform calibration.

[0067] like Figure 3 As illustrated in FIG. 1 , the offset calibration circuit system includes: a first switch S1 inserted between a first input node 400a and a second input node 400b of the comparator 400, the first switch S1 being configured to be driven between a first “ON” or “closed” state in response to an enable signal EN_PCM being asserted and a second “OFF” or “open” state in response to an enable signal EN_PCM being deasserted; a second switch S2 inserted between the second input node 400b of the comparator 400 and a feedback node V FBan edge detector circuit 410 coupled to an output node 400 c of the comparator circuit 400, the edge detector circuit 410 being configured to detect when a comparison signal V2 output by the comparator switches from a first (e.g., “low” or “0”) logic level to a second (e.g., “high” or “1”) logic level; a counter 420 coupled to the edge detector circuit 410 and configured to increase the digital calibration signal CAL1 before the edge detector detects a change in the comparison signal V2; and a digital-to-analog converter DAC circuit 430 coupled to the counter 420 to receive the digital calibration signal CAL1 therefrom and to a first input node 400 a of the comparator circuit 400 to provide a signal (e.g., voltage) based on the digital calibration signal CAL1 thereto.

[0068] like Figure 3 As illustrated in , the offset calibration method includes: in response to the enable signal EN_PCM being asserted, coupling the first input node 400a and the second input node 400b therebetween; and increasing the digital calibration signal CAL1 through the counter 420 until the comparison signal V2 jumps to the second logic value, thereby indicating that the input offset voltage Voff has been compensated.

[0069] like Figure 3 As illustrated in FIG. 4 , once the counter 420 has reached the value of the digital calibration signal CAL1 that triggers the edge detector 410, the counter 420 becomes a working register to store such value. For example, in the next operation cycle of the second control circuit 40 driving the switch circuits Q1 and Q2, the digital calibration signal value is retrieved from the counter to compare the feedback voltage V FB With reference voltage V REF When the comparator 400 is maintained at an offset Voff, the offset Voff of the comparator 400 is compensated. For example, when the control unit MCU subsequently asserts the enable signal EN_PCM, the stored value of CAL1 may be reset, thereby facilitating fine-tuning of the offset calibration.

[0070] In alternative scenarios, the MCU may include different offset calibration circuitry to perform the offset calibration methods discussed herein. For example, a method called successive approximation (SAR) may be applicable to one or more alternative scenarios. For example, the article "How does successive approximation sar adc work and where is it best used" accessible from Circuit Digest (circuitdigest.com) and incorporated herein by reference discusses an exemplary circuit for performing SAR.

[0071] like Figure 4 As illustrated in FIG. 1 , the timing circuit calibration includes configuring the timing circuit 402 to generate a drive signal TON whose duration (specifically, ON time duration T ON ) matches the duration of the drive signal PWM1 (ON time duration) generated by the first control circuit 30 at the beginning of its enabled operation. This facilitates providing the same amount of energy to the output load 30 when switching from one control circuit 30 to another control circuit 40 (due to timing alignment), optionally with the output voltage V out together with the same ripple of (due to the offset compensation of comparator 400, such as Figure 3 as exemplified in ). like Figure 3 and / or Figure 4 The arrangement illustrated in promotes improved continuity of operation when the alternating control circuits 30, 40 drive the switching circuits Q1, Q2.

[0072] like Figure 4 As illustrated in FIG. 1 , the timing circuit 402 is coupled to a control unit (eg, a microcontroller MCU) to receive therefrom a signal T based on the signal T output by the timing circuit 400. ON and a second calibration signal CAL2 (eg, an n-bit signal) of the driving signal PWM1 output by the first control unit 30 .

[0073] For example, the control unit MCU can be similar to Figure 3 The way the offset voltage Voff is discussed in Figure 4 In other words, in order to make the TON signal consistent with the PWM1 signal, it is possible to use a counter (for example, equipped on the control unit MCU) to generate a second digital word CAL2 to adjust the timing circuit 402 to change the duration of the ON time of the timing signal TON. For example, Figure 4 The calibration illustrated in can also utilize the SAR method discussed previously.

[0074] like Figure 5 and Figure 6 As illustrated in the figure, the control unit MCU can be configured to drive the first or second control circuit 30, 40 so as to provide the corresponding first or second control signal PWM1, TON to the switching circuit Q1, Q2 according to a method encoded as a finite state machine FSM equipped on the control unit MCU (for example, in its data storage part).

[0075] Figure 5 This is an example diagram of the FSM equipped on the control unit MCU.

[0076] like Figure 5 As illustrated in FIG. 1 , the finite state machine FSM includes four states: a first state CCM and a second state DCM, in which the switch circuits Q1 and Q2 are driven by the first control circuit 30 ; and a third state COT and a fourth state ULP, in which the switch circuits Q1 and Q2 are driven by the second control circuit 40 .

[0077] The following especially refers to Figures 6 to 14 The manner in which the first and second circuits 30 , 40 operate in each state of the FSM, CCM, DCM, COT, and ULP, is discussed.

[0078] Figure 6 is an example simplified block diagram of a device 60 suitable for use in one or more embodiments of the electronic converter circuit 20a.

[0079] like Figure 6 As illustrated in , the device 60 comprises a control unit MCU, which is coupled to the electronic converter 20a and to service circuitry (such as a clock generator circuit CLK and other user circuits A).

[0080] like Figure 6 As illustrated in FIG. 1 , the control unit MCU comprises a data storage unit FSM configured to store transition rules of a finite state machine and a processing unit CU configured to process signals involved in a control method for the electronic converter 20 a.

[0081] For example, the logic unit MCU includes a microcontroller or an ASIC / FPGA circuit.

[0082] like Figure 6As illustrated in the figure, in addition to 30, 40, 50 and Q1, Q2 already discussed, the electronic converter hardware 20a may also include other circuits, such as: a zero-crossing detector circuit ZCD, configured to sense the current at the switching node Lx of the switching circuit Q1, Q2 when activated via the ZCD enable signal EN_ZCD, and assert a corresponding detection signal when a current polarity reversal at the switching node Lx is detected; other peripheral circuits OTHP, such as, for example, an alarm generating circuit system, which can be activated or deactivated based on a control signal from the control unit MCU; and a clock generator circuit CLK, which is coupled to the control unit MCU to provide a synchronous clock signal CLK, for example for controlling the loop circuits 30, 40 and / or other user circuits A.

[0083] like Fig. 7A As illustrated in FIG. 1 , the method of changing the operation mode of the circuit 20a from the first (e.g., “high” power) operation mode CCM to the fourth (e.g., “low” power) operation mode ULP includes: during a first time interval T0-T1, detecting a current I flowing in the filter circuit LPF COIL and the current signal I is detected in a manner known per se (for example, using a ZCD detector circuit ZCD provided on the control unit MCU) COIL An integer number N (for example, Fig. 7A The method further comprises the steps of: counting zero-crossing events (N=7) of the first state CCM and the second state DCM in response to the assertion of the overflow signal max_cntZCD; when the first time interval T0-T1 elapses, asserting the overflow signal max_cntZCD to a first logic value (e.g., "1" or "true"), and switching from the first state CCM to the second state DCM in response to the assertion of the overflow signal max_cntZCD; for example, if the ZCD events are not consecutive, resetting the detector circuit ZCD after two missed zero-crossing detection events; at time T2, in response to the assertion of the JUM2COT signal by the mode selection circuit 50, switching the operation from DCM to COT by deactivating (EN_PCM="0" or "false") the first control circuit 30 and activating (EN_COT="1" or "true") the second control circuit 40; during the time interval T2-T3, asserting the timing signal T ON The switching frequency or period Tsw is compared with the frequency / period of the internal clock signal CLK (for example, provided on the device 60 including the control unit MCU); for a predefined integer number of clock cycles M (for example, Fig. 7A M=8 in it), monitors the frequency or period of the timing signal TON and compares the monitored frequency / period with the internal clock frequency / period; and when the time interval T2-T3 has passed, in response to detecting that the frequency or period Tsw of the timing signal TON is lower than the frequency / period of the internal clock signal CLK over the entire length of a predefined integer M clock cycles, switches the operation from the third state COT to the fourth state ULP.

[0084] like Fig. 7A As exemplified in Figure 4 (and optionally Figure 3 ) in the calibration operation (one or more) illustrated in the first CCM state, the current signal I COIL The on-time fraction TSW of the switching cycle of is equal to the on-time fraction TSW of the signal in the fourth state ULP, thereby providing smooth operation of the electronic device 20a.

[0085] As illustrated herein, in the fourth state ULP, the Figure 6 Some of the circuits of the device 60 illustrated in FIG. 6 are modified to reduce energy consumption.

[0086] For example, circuit OTHP and CLK are turned off, leaving a residual consumption of 900 nA to pre-bias the node to be fast enough during the turn-on phase.

[0087] like Figure 6 and Figure 7B As illustrated in the example: for example, after a delay of one clock cycle from the transition to ULP, the low power signal LP is sampled by the digital circuit DIGITAL of the MCU; in response to reaching the ULP state at time T3, the control unit MCU interrupts the internal clock CLK and the startup circuit A and the pre-regulated voltage OTHP, with minimal participation consumption (e.g., about 7.4 microamperes); at the same time, the MCU maintains the assertion of the second enable signal EN_COT (e.g., the total consumption is 800nA); the zero crossing detector circuit ZCD can be periodically disabled and only when the coil current I COIL specifically, the enable signal EN_ZCD is asserted for a time equal to Ton + Toff, and the timing circuit 402 is turned on and off every Ton; and the signals HP and LP represent the high power mode and low power mode of the operating switching transistors Q1, Q2.

[0088] For example, in this ULP "idle" mode, the total consumption of the control logic MCU is 9.6 microamps, in addition, the consumption of the switching circuit 20a is about 500 nanoamps from the power stages Q1, Q2.

[0089] like Figures 5 to 9As illustrated in the figure, the method of changing the operating mode of the circuit 20a from the second (e.g., "low" power LP) operating mode 40 to the second (e.g., "high" power HP) operating mode 30 includes: in response to failing to detect three consecutive ZCD events, asserting the full transition signal TR_HL - which indicates that the output load is high enough to resume CCM mode operation, changing from the fourth state ULP in the FSM to the first state CCM; otherwise, during low power constant on-time operation (third state COT of the FSM), in response to detecting (e.g., in time interval T4) that the switching frequency is higher than the frequency of the internal clock signal CLK, the system jumps to the second state DCM.

[0090] like Figure 5 This latter transition is indicated by the arrow TR_HF, as illustrated in FIG.

[0091] As discussed previously and in Fig. 9 As illustrated in FIG. 1 , during operation in the fourth mode ULP, the internal clock signal CLK is turned off. Therefore, due to the time window generated at each Ton and calibrated in the CCM or DCM mode state, for example, the transition TR_HF may be equal to one clock cycle of the internal clock CLK.

[0092] Figure 8 is a diagram of an example of a logic circuit 80 dedicated to managing the signals during the TR_HF transition.

[0093] For example: or high switching frequency causes a shift from the third COT state to the second DCM state, such as Fig. 9 - this is the case when the second comparator 400 is calibrated to switch at the internal clock frequency; or if the current load is high enough for the system to operate in the CCM region, there is a high load transition from the third state COT to the first state CCM, such as Fig.10 exemplified in .

[0094] like Figure 8As illustrated in FIG. 1 , the logic circuit 80 configured to perform a transition from the second operation mode to the first operation mode includes: a first signal processing chain 801, 803, 805, 807, including a first NAND circuit 801 coupled to a group of memory elements (e.g., triggers) 803, 805, 807, the first processing chain 801, 803, 805, 807 being configured to provide a trigger signal TR_HF for a transition from a fourth state ULP or a third state COT to a first state CCM; a second signal processing chain 802, 804, 806, 808, including a second NAND circuit coupled to another group of memory elements (e.g., triggers) 804, 806, 808 Circuit 802, the second processing chain 802, 804, 806, 808 is configured to provide a trigger signal TR_HL for transition from the fourth state ULP or the third state COT to the first state CCM; a combinational logic gate 810 (such as an AND gate), which is coupled to the first processing chain 801, 803, 805, 807 and to the second processing chain 802, 804, 806, 808 to combine the trigger signals TR_HF, TR_HL and determine the transition to be performed; and another memory circuit 812 (for example, a flip-flop), which is configured to sample the result of the combinational logic gate 810, thereby generating a universal trigger signal TR that can be provided to the control unit MCU.

[0095] like Figures 5 to 10 As illustrated in , once the TR_HL signal is asserted, the transition from low power to high power mode begins. For example, the first control circuit 30 is enabled via the corresponding enable signal EN_PCM. At the same time, the general trigger signal TR can reset the sleep signal of the oscillator in the main logic, startup bias and pre-regulator provided to the MCU. For example, during this interval, the second control circuit 40 is active even if the general trigger signal TR is received. When the first clock cycle arrives, for the synchronous state machine, the PCM loop 30 takes over the control of the regulation. Due to the execution of Figure 3 and Figure 4 , the boundary between DCM and CCM is the same for the second control circuit 40 and the first control circuit 30. Therefore, if the trigger signal TR_HL enables the corresponding state transition, this is the result of the load reaching a threshold, for example to keep the system in CCM and thus in the PCM loop. In this way, the bounce between the control loops can be offset. If a fast load transition occurs, such as from a "low" to a "high" load, the second circuit 40 can be active to recover the Vout undervoltage. For example, even if the first PCM circuit 30 remains operational for some time after the TR HL event, the second COT circuit may be able to respond to such a load change.

[0096] In one or more embodiments, transitions triggered by the TR_HF signal or by the TR_HL signal may consume substantially similar amounts of power.

[0097] like Figures 2 to 10 As illustrated in , the first control circuit 30 and the second control circuit 40 can be activated alternately by corresponding activation signals. For example, in response to the additional comparator 500 asserting the additional comparison signal JUMP2COT having a first (e.g., "1" or "true") logic value, the first circuit 30 is turned off; optionally, the first comparison signal Vc is clamped to the bottom voltage range allowed at the output of the error amplifier; at the same time, the second control circuit 40 operates until a transition event occurs (e.g., the TR_HL or TR_HF signal is asserted). However, in response to the TR event, the first control circuit 30 is turned on, but the PCM circuit 302 does not take over control until the first clock cycle arrives; in response to the first clock cycle, the PCM loop starts driving the switch circuits Q1, Q2, and the second control circuit 40 performs calibration.

[0098] like Figure 2 and Figure 3 As illustrated in , the first comparator 300 and the second comparator 400 share the same feedback VFb and voltage reference VREF, and they are enabled and disabled by a synchronous state machine encoded in the control circuit system MCU 500.

[0099] Fig.10 Comprising parts a) to h), a time diagram of the transition from high power to low power and back is shown, for example when the system is operated in a further low noise mode.

[0100] like Fig.10 As illustrated in part b) of , the error signal %E indicates that the amount of error in the output regulation voltage remains low, for example, below 0.5%, for transitions between CCM and DCM (ie, alternating from the first control circuit 30 to the second control circuit 40).

[0101] like Fig.10 As illustrated in parts e) and f), in response to a certain number of ZCD events represented by the ZCD signal and in response to the assertion of the further comparison signal JUMP2COT, the control circuit MCU drives the transition from the CCM operation mode to the COT operation time by activating the second control circuit 40 and deactivating the first control circuit 30.

[0102] like Fig.10 As illustrated in parts d) and g) of FIG. 4 , in response to the transition signal TR being asserted, the control circuit MCU drives the transition from the COT operation mode to the CCM operation time by activating the first control circuit 30 and calibrating the second control circuit 40.

[0103] like Fig.10 As illustrated in part h), during the time interval T2-T4, i.e., during operation in the first "low power" mode, the internal clock signal CLK is de-asserted or turned off along with other circuits to have an overall reduced power consumption (e.g., approximately 9.6 microamperes) during this "idle" phase.

[0104] For example, during operation of the first control circuit 30, the on-time duration TON may have a first value (eg, approximately 300 ns, where 1 ns=10 -9 s=1 nanosecond), and the second control circuit may set the on-time duration TON equal to a second value (eg, 343 ns) slightly higher than the first value to confirm the transition from one cycle to another.

[0105] like Fig.11 As illustrated in FIG. 1 , in a first exemplary scenario, the high power to low power operation mode transition includes: at a first moment K0, asserting the enable zero crossing detection signal EN_ZCD with a first (e.g., “1” or “high”) logic value, which triggers a counter (e.g., mounted on the control unit MCU) to count the coil current (at Fig.11 The number of zero crossings (as represented in part b of ) is counted; at the second moment K2, in response to the ZCD counter assembled on the MCU reaching a given number (for example, seven) at K1 as a prerequisite and in response to asserting another comparison signal JUMP2COT with a first logic value, the switching circuits Q1 and Q2 are driven by the second control circuit 40 instead of the first control circuit 30; at the third moment K3, in response to the switching frequency during operation of the second control circuit 40 being lower than the internal clock frequency, the system enters the low power mode ULP, thereby shutting down the internal clock generator and most of the internal circuits.

[0106] like Fig.12 As illustrated in the second exemplary scenario, the transition from high power to low power (for example, when the load current COIL changes from 3A to 100mA while the system operates in low current mode) includes: at a first moment K1, in response to the load current COIL reaching the boundary value at K0, the zero-crossing detection counter starts counting the number of times the coil current crosses zero; at a second moment K2, when at least a given number (for example, 7) of ZCD events occur consecutively, the system enters the DCM operation mode from CCM; in response to asserting another comparison signal JUMP2COT with a first logic value, the operation of the switching circuit D1 is transferred from the first control circuit 30 to the second control circuit 40; at a fourth moment K3, in response to the COT switching frequency being lower than the internal frequency of the clock, the system enters the ultra-low power mode ULP, thereby shutting down the oscillator CLK and most of the internal circuits.

[0107] For example, during the on-time phase of the driving signal TON generated by the second control circuit 40, the ton generator is turned on and the ZCD is turned on for a time equal to Ton+Toff.

[0108] like Fig.13 As illustrated in , when switching from "low power" mode to "high power" mode: Fig.14 As illustrated in part b) of the embodiment, when the load current increases continuously, the system operation moves from DCM to CCM; in response to reaching the boundary between the two operation modes, the ZCD comparator becomes zero, and in response to missing a certain number (e.g., three) of ZCD detections when the system is in the ULP state of the FSM, the control unit MCU asserts the TR HL signal to be high (e.g., at time P1); in response to the de-assertion of the transition signal TR, for example, at time P2, as shown in FIG. Fig.13 As illustrated in , the COT loop 40 performs calibration and enables the PCM loop 30 to start driving the switching circuits Q1 , Q2 .

[0109] like Fig.13 As illustrated in part b) of , since Ton during operation of the second control circuit 40 is almost equal to Ton in the PCM (due to the calibration operation), the discontinuity of the coil current is negligible.

[0110] like Fig.13 As illustrated in part a), during the transition from the fourth ULP state to the second DCM state, the output voltage V out There are small disturbances.

[0111] like Fig.14 As illustrated in the figure, when the load current suddenly increases (for example, from 100 mA to 4 A, as illustrated in part b) of the figure), the FSM driving operation is to quickly switch from ULP to CCM in response to the following situations: at time P1', when the device 60 is in the ULP state, the ZCD detection is missed within a certain number (for example, three) of Ton time intervals, so that the transition signal TR HL is asserted high by the control unit MCU; in response to the lapse of time to restart the circuit that was disabled during the idle ULP stage, the clock signal CLK is restarted; at time P2', when the rising edge of the clock signal CLK is detected, the second control circuit 40 enters the calibration state, and the first control circuit 30 is enabled and the PCM loop takes over the control of the switching circuits Q1 and Q2.

[0112] like Fig.14 As illustrated in part a), although the load value suddenly changes, the variation of the output voltage Vout is still controlled (eg, about 2%).

[0113] As illustrated herein, a control circuit 100 for an electronic converter device 20a includes at least one electronic switch Q1, Q2 having a current flow path therethrough, the electronic switch being configured to conduct in response to a drive signal DRV1, DRV2 received at a control node having a first value, and not conduct in response to the drive signal having a second value, wherein the at least one electronic switch is coupled to an inductive circuit element LPF, the output current I COIL flows through the inductive circuit element, and wherein the electronic converter device is configured to provide an output voltage V via two output nodes 202a, 202b based on an input voltage Vin supplied to at least one switching transistor out .

[0114] In a first exemplary scenario, the control circuit 100 comprises: an output node configured to be coupled to the control node of the at least one electronic switch to provide the drive signal thereto; an input node configured to receive a feedback signal V indicating the output voltage FB ; two additional input nodes configured to be coupled to the two output nodes of the electronic converter device; and a first drive circuit 30 coupled to the input node of the control circuit to receive a feedback signal. The first drive circuit includes: a first enable node configured to receive a first enable signal EN_PCM; and a pulse width modulated PWM signal generator circuit (02) configured to provide a PWM drive signal PWM1 to the output node of the control circuit in response to the first enable signal being asserted, the PWM drive signal being a function of the difference between the feedback voltage and the first reference voltage level. The second drive circuit 40 is coupled to the input node of the control circuit to receive a feedback signal. The second drive circuit includes: a second enable node configured to receive a second enable signal EN_COT; and a pulse frequency modulated PFM signal generator circuit 402 configured to provide a PFM drive signal TON to the output node of the control circuit in response to the second enable signal being asserted, the PFM drive signal being a function of the difference between the feedback voltage and the second reference voltage level V REF The logic circuit system MCU 60 is coupled to the first driving circuit and to the second driving circuit, and the logic circuit system (MCU, 60) is configured to assert at least one of the first enable signal (EN_PCM) and the second enable signal (EN_COT). The comparator 500 has a first comparator input node 500a coupled to the third reference voltage level and a second comparator input node 500b coupled to the output node of the control circuit to receive the feedback voltage, wherein the comparator is configured to perform a comparison of the feedback voltage with the third reference voltage level and provide a mode selection signal at a comparator output node 500c as a result of the comparison.

[0115] For example, the logic circuitry is configured to de-assert the first enable signal and assert the second enable signal in response to the mode selection signal JUMP2COT being asserted.

[0116] In a second exemplary scenario, the control circuit further comprises: a zero-crossing detection circuit system ZCD coupled to two further input nodes of the control circuit and configured to assert a zero-crossing detection signal in response to detecting a zero value of an output current flowing through the inductive circuit element of the electronic converter device; and a timing circuit system CLK configured to provide an internal clock signal having an internal clock period.

[0117] In the second example considered, the logic circuit system MCU 60 is configured to assert the first enable signal EN_PCM in response to the following situations: the zero-crossing detection circuit system fails to assert the zero-crossing detection signal EN_ZCD for a time interval equal to an integer (preferably equal to three) cycles of the internal clock signal; or the period of the PFM drive signal is lower than the period of the internal clock signal.

[0118] Still in the second exemplary scenario, for example when the second enable signal is asserted and in response to the period of the PFM drive signal being lower than the period of the internal clock signal for a monitoring time interval equal to an integer number (preferably eight) of clock cycles, the logic circuit system is configured to disable EN_ZCD, putting the zero-crossing detection circuit system and the timing circuit system CLK into a sleep state.

[0119] In a third exemplary scenario, the control circuit includes: a zero-crossing detection circuit system coupled to two further input nodes of the control circuit and configured to assert a zero-crossing detection signal EN_ZCD in response to detecting a zero value of an output current flowing through an inductive circuit element of the electronic converter device, wherein the logic circuit system is configured to assert a second enable signal in response to the zero-crossing detection circuit asserting the ZCD signal a consecutive integer number of times (preferably equal to seven times).

[0120] As illustrated herein, the first control circuit (30) includes: an error amplifier 400 having a first amplifier input node 400a coupled to a first reference voltage level and another amplifier input node 400b coupled to the second node of the control circuit, the error amplifier circuit 50 being configured to provide a first error amplifier signal Vc based on a difference between a feedback voltage and the first reference voltage level; and a clamping circuit 304 being configured to limit the voltage level of the first error amplifier signal.

[0121] As illustrated herein, the logic circuitry is configured to calibrate the PFM signal generator circuit 402 to set the duty cycle Tsw of the PFM drive signal TON equal to the duty cycle of the PWM drive signal PWM1 in response to asserting the first enable signal EN_PCM.

[0122] As illustrated herein, the second control circuit 40 includes a comparator circuit 400, which includes a first comparator input node 400a coupled to a second reference voltage level, a second comparator input node 400b coupled to an input node of the control circuit to receive a feedback voltage, and the comparator circuit is configured to provide a comparison signal V2 at an output node 400c based on a comparison of the feedback voltage with the reference voltage level.

[0123] For example: the comparator circuit of the second control circuit further includes a reset node RST configured to reset the comparison signal; and the logic circuit system is configured to provide the comparator circuit with an offset calibration signal CAL1, CAL2m according to the comparison signal in response to asserting the first enable signal.

[0124] As illustrated herein, the first reference voltage, the second reference voltage, and the third reference voltage are equal to the same reference voltage.

[0125] For example, as illustrated herein, the electronic device 20a includes: at least one electronic switch Q1, Q2 having a current flow path therethrough, configured to be turned on in response to a drive signal DRV1, DRV2 received at a control node having a first value, and not turned on in response to the drive signal having a second value; an inductive circuit element LPF coupled to the at least one electronic switch, outputting a current I COIL flows through an inductive circuit element LPF; an input voltage Vin is supplied to at least one switching transistor; two output nodes 202a, 202b are coupled to the inductive circuit element; and a control circuit 100 according to the present disclosure is coupled to the inductive circuit element, the two output nodes and at least one electronic switch, the control circuit being configured to drive an electronic converter device to provide an output voltage to an electrical load 30 based on the input voltage supplied to the at least one switching transistor.

[0126] Otherwise, it will be understood that the various individual implementation options illustrated throughout the drawings accompanying this description are not necessarily intended to be employed in the same combination illustrated in the drawings. Thus, one or more embodiments may employ these (otherwise non-mandatory) options alone and / or in different combinations relative to the combinations illustrated in the drawings.

[0127] The claims are an integral part of the technical teaching provided herein with reference to the exemplary embodiments.

[0128] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection, which is defined by the appended claims.

Claims

1. A control circuit for an electronic converter device, the electronic converter device comprising at least one electronic switch having a current flow path therethrough, the electronic switch being configured to conduct in response to a drive signal received at a control node having a first value and to not conduct in response to the drive signal having a second value, wherein the at least one electronic switch is coupled to an inductive circuit element through which an output current flows, wherein the electronic converter device is configured to provide an output voltage via two output nodes based on an input voltage supplied to the at least one switching transistor, the control circuit comprising: an output node configured to be coupled to the control node of the at least one electronic switch to provide the drive signal thereto; an input node configured to receive a feedback signal indicative of the output voltage; two further input nodes configured to be coupled to the two output nodes of the electronic converter device; A first driving circuit is coupled to an input node of the control circuit to receive a feedback signal, the first driving circuit comprising: A first enabling node configured to receive a first enabling signal; and a pulse width modulation (PWM) signal generator circuit configured to provide a PWM drive signal to the output node of the control circuit in response to the first enable signal being asserted, wherein the PWM drive signal is a function of a difference between a feedback voltage and a first reference voltage level; A second driving circuit, coupled to an input node of the control circuit to receive a feedback signal, the second driving circuit comprising: A second enable node configured to receive a second enable signal; and a pulse frequency modulation (PFM) signal generator circuit configured to provide a PFM drive signal to the output node of the control circuit in response to the second enable signal being asserted, wherein the PFM drive signal is a function of a difference between a feedback voltage and a second reference voltage level; logic circuitry coupled to the first driver circuit and to the second driver circuit, wherein the logic circuitry is configured to assert at least one of the first enable signal and the second enable signal; and a comparator having a first comparator input node coupled to a third reference voltage level and a second comparator input node coupled to said output node of the control circuit to receive the feedback voltage, the comparator being configured to perform a comparison of the feedback voltage with the third reference voltage level and to provide a mode selection signal at a comparator output node as a result of the comparison; Wherein the logic circuitry is configured to de-assert the first enable signal and assert the second enable signal in response to the mode select signal being asserted.

2. The control circuit according to claim 1, further comprising: zero-crossing detection circuitry coupled to two further input nodes of the control circuit and configured to assert a zero-crossing detection signal in response to detecting a zero value of an output current flowing through the inductive circuit element of the electronic converter device when enabled by the enable signal; and a timing circuit system configured to provide an internal clock signal having an internal clock period; wherein the logic circuitry is configured to assert the first enable signal in response to: the zero-crossing detection circuitry fails to assert the zero-crossing detection signal for a time interval equal to a first integer number of cycles of the internal clock signal; or The period of the PFM driving signal is lower than the period of the internal clock signal.

3. The control circuit of claim 2 , wherein the logic circuit system is configured to disable the zero-crossing detection circuit system and the timing circuit system when the second enable signal is asserted and in response to a period of the PFM drive signal being higher than a period of the internal clock signal for a monitoring time interval equal to a second integer number of periods of the internal clock signal.

4. The control circuit according to claim 1, comprising: zero-crossing detection circuitry coupled to two other input nodes of the control circuit and configured to assert a zero-crossing detection signal in response to detecting a zero value of an output current flowing through the inductive circuit element of the electronic converter device; The logic circuit system is configured to assert the second enable signal in response to the zero-crossing detection circuit asserting the zero-crossing detection signal consecutively an integer number of times.

5. The control circuit of claim 1 , wherein the first control circuit comprises: an error amplifier having a first amplifier input node coupled to a first reference voltage level and having a further amplifier input node coupled to said second node of the control circuit, the error amplifier circuit being configured to provide a first error amplifier signal based on a difference between a feedback voltage and the first reference voltage level; as well as The clamp circuit is configured to limit the voltage level of the first error amplifier signal.

6. The control circuit of claim 1 , wherein the logic circuitry is configured to calibrate the PFM signal generator circuit to set a duty cycle of the PFM drive signal equal to a duty cycle of the PWM drive signal in response to asserting the first enable signal.

7. The control circuit of claim 1 , wherein the second control circuit comprises a comparator circuit comprising a first comparator input node coupled to a second reference voltage level, a second comparator input node coupled to an input node of the control circuit to receive a feedback voltage, the comparator circuit being configured to provide a comparison signal at an output node based on a comparison of the feedback voltage with the reference voltage level.

8. The control circuit of claim 7, wherein: The comparator circuit of the second control circuit further includes a reset node configured to reset the comparison signal; and The logic circuitry is configured to provide an offset calibration signal according to the comparison signal to the comparator circuit in response to asserting the first enable signal.

9. The control circuit of claim 1, wherein the first reference voltage, the second reference voltage, and the third reference voltage are equal to the same reference voltage.

10. An electronic device, comprising: at least one electronic switch having a current flow path therethrough configured to conduct in response to a drive signal having a first value received at a control node and to not conduct in response to the drive signal having a second value; an inductive circuit element coupled to the at least one electronic switch, the output current flowing through the inductive circuit element; an input voltage supplied to the at least one switching transistor; two output nodes coupled to the inductive circuit elements; as well as The control circuit of claim 1, configured to drive the electronic converter device to provide an output voltage to an electrical load based on an input voltage supplied to the at least one switching transistor.

11. A control circuit for an electronic converter device, comprising: an output node generating a drive signal for application to a control node of an electronic switch of an electronic converter device; an input node configured to receive a feedback signal indicative of an output voltage of the electronic converter device; a first driver circuit comprising a pulse width modulation (PWM) signal generator circuit configured to provide a PWM drive signal to the output node when enabled by a first enable signal, wherein the PWM drive signal is a function of a difference between a feedback voltage and a first reference voltage level; a second driver circuit comprising a pulse frequency modulation (PFM) signal generator circuit configured to provide a PFM drive signal to the output node when enabled by a second enable signal, wherein the PFM drive signal is a function of a difference between a feedback voltage and a second reference voltage level; a comparator circuit system configured to compare the feedback voltage with a third reference voltage level and provide a mode selection signal; Logic circuitry is configured to control assertion and de-assertion of a first enable signal and a second enable signal, wherein the logic circuitry de-asserts the first enable signal and asserts the second enable signal in response to assertion of the mode select signal.

12. The control circuit according to claim 11, further comprising: zero-crossing detection circuitry configured to assert a zero-crossing detection signal in response to detecting a zero value for an output current of the electronic converter device; as well as a timing circuit system configured to provide an internal clock signal having an internal clock period; Wherein the logic circuitry asserts the first enable signal in response to the zero-crossing detection circuitry failing to assert the zero-crossing detection signal for a time interval equal to a first integer number of cycles of the internal clock signal.

13. The control circuit of claim 12 , wherein the logic circuitry is configured to disable the zero-crossing detection circuitry and the timing circuitry when the second enable signal is asserted and in response to a period of the PFM drive signal being lower than a period of the internal clock signal for a duration longer than the monitoring time interval.

14. The control circuit according to claim 11, further comprising: zero-crossing detection circuitry configured to assert a zero-crossing detection signal in response to detecting a zero value for an output current of the electronic converter device; as well as a timing circuit system configured to provide an internal clock signal having an internal clock period; The logic circuit system asserts the first enable signal in response to a period of the PFM drive signal being lower than a period of the internal clock signal.

15. The control circuit of claim 14, wherein the logic circuit system is configured to disable the zero-crossing detection circuit system and the timing circuit system when the second enable signal is asserted and in response to a period of the PFM drive signal being lower than a period of the internal clock signal for a duration longer than the monitoring time interval.

16. The control circuit according to claim 11, comprising: zero-crossing detection circuitry configured to assert a zero-crossing detection signal in response to detecting a zero value for an output current of the electronic converter device; The logic circuit system asserts a second enable signal in response to the zero-crossing detection signal.

17. The control circuit of claim 11, wherein the first control circuit comprises: an error amplifier configured to provide a first error amplifier signal based on a difference between a feedback voltage and a first reference voltage level; as well as The clamp circuit is configured to limit the voltage level of the first error amplifier signal.

18. The control circuit of claim 11, wherein the logic circuitry is configured to calibrate the PFM signal generator circuit to set a duty cycle of the PFM drive signal equal to a duty cycle of the PWM drive signal in response to asserting the first enable signal.

19. The control circuit of claim 11, wherein the second control circuit comprises a comparator circuit configured to provide a comparison signal at the output node based on a comparison of the feedback voltage with a reference voltage level.

20. The control circuit of claim 19, wherein: The comparator circuit of the second control circuit further includes a reset node configured to reset the comparison signal; and Logic circuitry is configured to provide an offset calibration signal based on the comparison signal to the comparator circuit in response to asserting the first enable signal.

21. The control circuit of claim 11, wherein the first reference voltage, the second reference voltage, and the third reference voltage are equal to the same reference voltage.

22. An electronic device, comprising: an electronic converter device having an electronic switch and an inductive circuit element coupled to the electronic switch; as well as The control circuit according to claim 11.

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