Internal power supply circuit applied to integrated circuit chip

Abstract

The invention discloses an internal power supply circuit applied to an integrated circuit chip, which comprises a power supply generation module and a noise protection module, and is characterized in that the noise protection module is arranged at an output stage transistor end of the power supply generation module and is used for detecting input voltage in the chip; and when negative ground bounce noise occurs in the internal input voltage, a current path between the power supply generation module and the internal power supply voltage output end is cut off, so that the influence of the ground bounce noise on the internal power supply voltage can be effectively shielded. Besides, the internal power supply circuit does not need to be connected with a resistor in series on a current path of an output stage transistor, so that ground bounce noise in the circuit is effectively shielded, and the load capacity of the output stage of the power supply circuit is not reduced, so that the power supply can stably work under a higher load condition, and the service life of the power supply is prolonged. And an application scene with a higher power requirement is met.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and in particular to an internal power circuit applied to an integrated circuit chip. Background Art

[0002] With the demand for power electronic products and the development of semiconductor technology, power management chips are widely used in the fields of communications, consumption, computing, etc. DC-DC converters are the most common type of power management chips and are widely used due to their high efficiency. Figure 1 The circuit diagram of a conventional synchronous step-down DC-DC converter is shown, including a switching power supply integrated circuit (IC) chip, an inductor L0, an output capacitor C0, and a load RL. The switching power supply chip includes a controller, a driver, and power switches S1 and S2.

[0003] The controller uses a certain control method (for example, PWM or PFM) to generate a pulse control signal with a certain duty cycle, and drives the power switches S1 and S2 through the driver, so that the common node SW of the power switches S1 and S2 generates a pulse signal with a peak value from the power supply to the ground, and generates a stable output voltage on the load RL after filtering by the inductor L0 and the capacitor C0.

[0004] However, there are some non-ideal factors that must be considered in practical applications. For example, the parasitic inductance and resistance of the wire bonding after IC chip packaging, such as Figure 2 The parasitic inductance Lpara1 and Lpara2 and the parasitic resistance Rpara1 and Rpara2 are shown in FIG. In general packages, the parasitic resistance is in the order of tens of milliohms, and the parasitic inductance is in the order of several nanohenries. Due to the alternating switching of the power switches S1 and S2, a sudden change in current will be generated on the parasitic inductance of the wire, and then a large voltage change will be generated at both ends of the parasitic inductance due to the corresponding change in magnetic flux. In other words, there will be a certain voltage difference between the ground potential PGND inside the IC chip and the ideal ground potential GND outside the chip, and the ground potential PGND of the chip will be in a high-frequency "bounce" state when the power switch is turned on and off. This is the ground bounce phenomenon (Ground Bounce). When a thinner package wire is used in the chip for cost considerations, or when the circuit load is heavy, the jump amplitude of the ground potential of the IC chip will increase, which will affect some key performances of the IC chip, such as causing internal power supply voltage instability, reference voltage drift, and feedback loop failure.

[0005] Figure 3 A circuit diagram showing an internal power supply circuit of the prior art is shown. Figure 4 FIG. 1 shows a schematic diagram of the output of an internal power supply circuit in the prior art when a ground bounce phenomenon occurs. Figure 3As shown in FIG. 1 , in a DC-DC converter 100 , in order to deal with problems such as excessive input voltage, the IC chip usually needs to convert the input voltage PVIN into an internal power supply voltage VCC suitable for the operation of the on-chip circuit through an internal power supply circuit 110 . Figure 4 As shown, when the ground bounce phenomenon occurs, the power supply voltage PVIN and the ground potential PGND at the chip end will be affected by the ground bounce noise to produce transient voltage changes, which will then cause the difference between the internal power supply voltage VCC and the chip ground potential PGND to be discharged, resulting in instability of the power supply voltage VCC inside the IC chip.

[0006] Currently, if Figure 3 As shown, the existing ground bounce noise resistance design solution usually adds a series resistor (e.g. Figure 3 The resistor R2 in the circuit is used to limit the energy transfer of ground bounce noise. Although this resistor can effectively reduce the impact of noise, it also significantly weakens the load capacity of the output stage of the power supply circuit, which is a key performance indicator of the power supply circuit.

[0007] Therefore, finding a new solution that can effectively resist ground bounce noise without significantly affecting load capacity has become an important issue in improving chip performance. Summary of the invention

[0008] In view of the above problems, an object of the present invention is to provide an internal power supply circuit applied to an integrated circuit chip, which can effectively shield the ground bounce noise in the circuit without significantly reducing the load capacity of the output stage of the power supply circuit.

[0009] According to one aspect of the present invention, there is provided an internal power supply circuit for an integrated circuit chip, comprising: a power supply generating module for generating an internal power supply voltage according to an internal input voltage of the chip, the power supply generating module comprising an output-stage transistor, a first end of the output-stage transistor being connected to the internal input voltage of the chip, and a second end of the output-stage transistor being connected to an output end of the power supply generating module; and a noise protection module, arranged between the second end of the output-stage transistor and the output end of the power supply generating module, for detecting the internal input voltage and disconnecting a current path between the output-stage transistor and the output end of the power supply generating module when negative ground bounce noise occurs in the internal input voltage.

[0010] Optionally, the noise protection module includes: a first transistor arranged between the second end of the output stage transistor and the output end of the power supply generating module, and a detection control unit connected to the control end of the first transistor and the internal input voltage, for controlling the conduction and cutoff of the first transistor according to the internal input voltage, wherein the detection control unit is used to turn off the first transistor when the negative ground bounce noise appears in the internal input voltage.

[0011] Optionally, the detection control unit includes: a second transistor arranged between the control end of the first transistor and the output end of the power generation module; and a first capacitor and a first resistor connected in series between the internal input voltage and the output end of the power generation module, and the intermediate node of the first capacitor and the first resistor is connected to the control end of the second transistor.

[0012] Optionally, the detection control unit further includes: a second resistor, a first end of the second resistor is connected to the control end of the first transistor, and a second end of the second resistor is connected to an internal reference ground of the chip.

[0013] Optionally, the first transistor and the second transistor are P-type field effect transistors.

[0014] Optionally, the power generation module further includes: a control unit arranged between the internal input voltage and the internal reference ground of the chip, the control unit being used to generate a control signal, and the control signal adjusts the internal power supply voltage by controlling the conduction degree of the output transistor.

[0015] Optionally, the control unit includes: a third resistor and a first reverse diode connected in series between the internal input voltage and the internal reference ground, the intermediate node of the third resistor and the first reverse diode being connected to the control end of the output stage transistor to provide the control signal; and a second capacitor arranged between the control end of the output stage transistor and the internal reference ground.

[0016] Optionally, the control unit includes: a source follower unit arranged between the internal input voltage and the internal reference ground of the chip, the source follower unit being used to generate a first voltage based on the internal input voltage; a charge pump unit being used to pump up the first voltage in response to a timing control signal to generate a charge pump output signal; a filtering unit being used to filter the charge pump output signal and generate the control signal; and a feedback adjustment unit being used to adjust the control signal based on the feedback signal of the internal power supply voltage and the reference voltage signal.

[0017] Optionally, the source follower unit includes: a fourth resistor and a second reverse diode connected in series between the internal input voltage and the internal reference ground; a third transistor and a third capacitor connected in series between the internal input voltage and the internal reference ground, the control end of the third transistor is connected to the middle node of the fourth resistor and the second reverse diode, and the middle node of the third transistor and the third capacitor is used to output the first voltage; and a fourth capacitor arranged between the control end of the third transistor and the internal reference ground, wherein the charge pump unit includes: at least one transistor and at least one flying capacitor forming a differential cross-coupling architecture, wherein the filter unit includes: a filter resistor, a first end connected to the output of the charge pump unit, and a second end connected to the control end of the output stage transistor; and a filter capacitor, a first end connected to the control end of the output stage transistor, and a second end connected to the internal reference ground, wherein the feedback adjustment unit includes: a first error amplifier, used to compare the feedback signal with the reference voltage signal; and a fourth transistor arranged between the control end of the output stage transistor and the internal reference ground, and the control end of the fourth transistor is connected to the output of the error amplifier.

[0018] Optionally, the control unit includes: a second error amplifier, used to compare the feedback signal of the internal power supply voltage with a reference voltage signal; a fifth transistor, the second end of the fifth transistor is connected to the internal reference ground of the chip, and the control end of the fifth transistor is connected to the output end of the second error amplifier; a sixth transistor, the first end of the sixth transistor is connected to the internal input voltage, and the control end and the second end of the sixth transistor are connected to the first end of the fifth transistor, wherein the control end of the sixth transistor is also connected to the control end of the output stage transistor to generate the control signal.

[0019] In summary, an embodiment of the present invention provides an internal power supply circuit applied to an integrated circuit chip, including a power supply generating module and a noise protection module, wherein the noise protection module is arranged at the output-stage transistor terminal of the power supply generating module, and is used to detect the input voltage inside the chip, and disconnect the current path between the power supply generating module and the internal power supply voltage output terminal when negative ground bounce noise occurs in the internal input voltage, thereby effectively shielding the influence of the ground bounce noise on the internal power supply voltage. In addition, since the internal power supply circuit of the present invention does not need to connect a resistor in series on the current path of the output-stage transistor, the technical solution of the present invention will not reduce the load capacity of the output stage of the power supply circuit while effectively shielding the ground bounce noise in the circuit, thereby enabling the power supply to work stably under higher load conditions and meet application scenarios with greater power requirements. Therefore, the internal power supply circuit of the embodiment of the present invention can not only enhance the reliability and stability of the circuit, but also improve the performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A circuit diagram of a conventional synchronous step-down DC-DC converter is shown.

[0022] Figure 2 A schematic diagram showing parasitic inductance and parasitic resistance of wire bonding after IC chip packaging of a conventional DC-DC converter is shown.

[0023] Figure 3 A circuit diagram of an internal power supply circuit in the prior art is shown.

[0024] Figure 4 The output schematic diagram of the internal power supply circuit in the prior art when the ground bounce phenomenon occurs is shown.

[0025] Figure 5 A circuit diagram of a power converter control circuit according to an embodiment of the present invention is shown.

[0026] Figure 6 A circuit diagram showing an internal power supply circuit according to a first embodiment of the present invention is shown.

[0027] Figure 7 A circuit diagram showing an internal power supply circuit according to a second embodiment of the present invention is shown.

[0028] Figure 8 A circuit diagram showing an internal power supply circuit according to a third embodiment of the present invention is shown.

[0029] Fig. 9 The output waveform diagram of the internal power supply circuit of the embodiment of the present invention when the ground bounce phenomenon occurs is shown.

[0030] Fig.10 Schematic diagrams of waveforms of the internal power supply voltage of the embodiment of the present invention and the internal power supply voltage of the prior art are respectively shown. DETAILED DESCRIPTION

[0031] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0032] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0033] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuit, a programmable circuit, a state machine circuit and / or an element that can store instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0034] In the present application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, the second terminal and the control terminal of a P-type field effect transistor are the source, the drain and the gate, respectively, and the first terminal, the second terminal and the control terminal of an N-type field effect transistor are the drain, the source and the gate, respectively.

[0035] The embodiment of the present invention first provides a power converter control circuit with an internal power supply circuit, which is used for PWM control or PFM control of a DC-DC converter. Various exemplary examples are illustrated and described below in conjunction with a buck converter type system, but the present invention is not limited to this, and any type of DC-DC converter architecture can be associated to use the various concepts disclosed in the present invention, such as the topological classification of the power circuit, including a buck converter, a boost converter, a flyback converter, and a buck-boost converter, etc. In addition, although complementary PWM control of a high-side switching device and a low-side switching device is used in the illustrations of the embodiments of the present invention, the concepts described in the present invention can be implemented in a power converter using only a single switching device, and / or in a power converter applying more than two pulse width modulations.

[0036] like Figure 5 A circuit diagram of a power converter control circuit 200 according to an embodiment of the present invention is shown, which can be implemented as an integrated circuit (IC) chip having various terminals or pins, as shown in the figure, for interconnecting with other components of a DC-DC converter system. Figure 5 In the example of , the integrated circuit 200 includes power switches S1 and S2 and corresponding drivers 201, but in other possible examples, one or all of these components may be external to the integrated circuit 200. Similarly, Figure 4 The control circuit 200 in the embodiment also provides a terminal 212 for connecting to an output inductor L0 of an external buck converter, the other end of the output inductor L0 being connected to an output capacitor C0 and a load RL, but other examples are possible, and one or more of these components may be provided in the integrated circuit 200.

[0037] Figure 5 The system shown implements a buck converter operated by an integrated circuit 200, wherein the integrated circuit 200 is controlled according to a closed-loop feedback of an output voltage VOUT, and the output voltage VOUT is provided to a load RL in parallel with an output capacitor C0. In addition, in this embodiment, the control circuit 200 adjusts the output voltage VOUT according to a reference voltage signal, but other embodiments are also possible, wherein the control circuit 200 may provide an external pin or terminal (not shown in the figure) for adjusting the output according to an externally supplied set point signal. Further, the integrated circuit 200 also includes a power input terminal 211, through the connection of an external power supply voltage VIN to the power input terminal 211, to input power to the integrated circuit 200, and the integrated circuit 200 also includes a power ground connection terminal 213 to connect to an external reference ground GND.

[0038] Furthermore, the high-side power switch S1 and the low-side power switch S2 are connected in series between the input voltage terminal 211 and the power ground terminal 213. The power switches S1 and S2 are as follows: Figure 5 , but the present invention is not limited thereto, and other embodiments using different types of switches are also possible, and / or the power switches S1 and S2 can be integrated outside the integrated circuit 200. Pulse width modulated gate control signals are provided by the driver 201 to the power switches S1 and S2, respectively, to control the on and off of the power switches S1 and S2. The inductor output terminal 212 (SW) is used for the connection of the external inductor L0 between the integrated circuit 200 and the load RL, wherein the output terminal 212 is connected to the common node of the high-side power switch S1 and the low-side power switch S2 as shown.

[0039] Furthermore, if Figure 5As shown, the integrated circuit 200 also includes an internal power supply circuit 300, which is arranged between the power input terminal 211 and the power ground connection terminal 213, and is used to generate an internal power supply voltage VCC according to the internal input voltage PVIN at the power input terminal 211 to supply power to the remaining modules in the integrated circuit 200. For example, the internal power supply circuit 300 can be implemented by a source follower, a charge pump or a low voltage drop linear regulator. It can be understood that the external input voltage VIN and the reference ground GND are generally considered to be an ideal power supply and an ideal ground, respectively, while the input voltage PVIN and the reference ground PGND inside the integrated circuit 200 will be affected by ground bounce noise. Therefore, in order to avoid the problem of instability of the internal power supply voltage VCC of the chip caused by ground bounce noise, the internal power supply circuit 300 of the embodiment of the present invention further includes a ground bounce noise protection design to reduce the impact of ground bounce noise on the internal power supply voltage VCC.

[0040] Figure 6 FIG. 3 shows a schematic circuit diagram of an internal power supply circuit 301 according to a first embodiment of the present invention. Figure 6 As shown, the internal power supply circuit 301 includes a power generation module 311 and a noise protection module 312 .

[0041] The power generation module 311 is used to generate an internal power supply voltage VCC according to the internal input voltage PVIN of the chip to supply power to the load ILOAD inside the chip. Further, the power generation module 311 of this embodiment can be implemented by a source follower, which includes an output stage transistor MN1 and a control unit that provides a control signal GATE to the output stage transistor MN1, and the control signal GATE adjusts the internal power supply voltage VCC by controlling the conduction degree of the output stage transistor MN1.

[0042] Furthermore, the output stage transistor MN1 is, for example, an N-type field effect transistor, whose drain is connected to the internal input voltage PVIN of the chip, whose source is used to be connected to the output end of the internal power supply voltage VCC, and whose gate is connected to the control signal GATE.

[0043] Further, the control unit includes a resistor R1, a reverse diode D1 and a capacitor C1. The first end of the resistor R1 is connected to the internal input voltage PVIN, the second end of the resistor R1 is connected to the cathode of the reverse diode D1, the anode of the reverse diode D1 is connected to the internal reference ground PGND, and the intermediate node between the resistor R1 and the reverse diode D1 is used to output the control signal GATE. The capacitor C1 is a voltage stabilizing capacitor, which is arranged between the gate of the output stage transistor MN1 and the internal reference ground PGND. Further, the reverse diode D1 is a Zener diode.

[0044] Furthermore, the noise protection module 312 is arranged between the source of the output stage transistor MN1 and the output end of the internal power supply voltage VCC. The noise protection module 312 is used to detect the internal input voltage PVIN and disconnect the current path between the output stage transistor MN1 and the output end of the internal power supply voltage VCC when negative ground bounce noise appears in the internal input voltage PVIN, so as to avoid the influence of ground bounce noise on the internal power supply voltage VCC and improve the stability of the internal power supply voltage VCC.

[0045] Further, the noise protection module 312 includes a transistor MP1 arranged between the source of the output stage transistor MN1 and the output end of the internal power supply voltage VCC, and a detection control unit composed of a capacitor C3, a resistor R2 and a transistor MP2. Wherein, transistors MP1 and MP2 are, for example, P-type field effect transistors, the drain of transistor MP1 is connected to the source of the output stage transistor MN1, and the source of transistor MP1 is connected to the output end of the internal power supply voltage VCC. The first end of capacitor C3 is connected to the internal input voltage PVIN, the second end of capacitor C3 is connected to the first end of resistor R2, and the second end of resistor R2 is connected to the output end of the internal power supply voltage VCC. The drain of transistor MP2 is connected to the gate of transistor MP1, the source of transistor MP2 is connected to the output end of the internal power supply voltage VCC, and the gate of transistor MP2 is connected to the intermediate node of capacitor C3 and resistor R2. Wherein, the detection control unit is used to control the conduction and shutdown of transistor MP1 according to the internal input voltage PVIN. As an example, the detection control unit is used to turn off the transistor MP1 when negative ground bounce noise occurs in the internal input voltage PVIN.

[0046] Furthermore, the detection control unit further includes a resistor R3 disposed between the gate of the transistor MP1 and the internal reference ground PGND, and the resistor R3 is used to bias the gate voltage of the transistor MP1 when the internal input voltage PVIN does not have ground bounce noise.

[0047] Furthermore, the internal power supply circuit 301 of this embodiment further includes a capacitor C2 disposed between the output end of the internal power supply voltage VCC and the internal reference ground PGND. The capacitor C2 is used as a voltage stabilizing capacitor to maintain the stability of the internal power supply voltage VCC.

[0048] Fig. 9 FIG. 2 shows an output waveform diagram of the internal power supply circuit of an embodiment of the present invention when a ground bounce phenomenon occurs. Fig. 9, PVIN_PGND represents the waveform of the difference between the input voltage inside the chip and the reference ground, VCC_PGND (proposed) represents the waveform of the internal power supply voltage output by the internal power supply circuit of the embodiment of the present invention, VCC_PGND (original) represents the waveform of the internal power supply voltage output by the traditional internal power supply circuit, PG1_PGND represents the waveform of the gate voltage of the transistor MP1, and PG2_PGND represents the waveform of the gate voltage of the transistor MP2. Figure 6 and Fig. 9 The principle of the noise protection module according to the embodiment of the present invention is described.

[0049] In this embodiment, when there is no ground bounce noise between the internal input voltage PVIN and the internal reference ground PGND, the gate voltage PG2 of the transistor MP2 is made equal to the internal power supply voltage VCC through the resistor R2, so the transistor MP2 is turned off, and then the gate voltage PG1 of the transistor MP1 is pulled down to the internal reference ground PGND through the resistor R3, so the transistor MP1 is turned on, so that the current path between the output stage transistor MN1 and the output end of the internal power supply voltage VCC is turned on.

[0050] When ground bounce noise is triggered in the circuit, transient voltage changes will occur in the internal input voltage PVIN and the internal reference ground PGND. At this time, there is positive noise in the circuit that makes the internal input voltage PVIN and the internal reference ground PGND far away from each other, and negative noise in the circuit that makes the internal input voltage PVIN and the internal reference ground PGND close to each other. Since a voltage-stabilizing capacitor C1 is provided between the gate of the output-stage transistor MN1 and the internal reference ground PGND, it can be ensured that the potential of the control signal GATE in the power generation module 311 is basically stable relative to the internal reference ground PGND. The output-stage transistor MN1 is turned on by the control signal GATE. At this time, the positive noise in the circuit that makes the internal input voltage PVIN and the internal reference ground PGND far away from each other will basically not affect the internal power supply voltage VCC.

[0051] When the negative noise of the internal input voltage PVIN and the internal reference ground PGND close to each other is triggered, the gate voltage PG2 of the transistor MP2 can be pulled down through the coupling effect of the capacitor C3, thereby turning on the transistor MP2, and then the transistor MP2 will pull up the gate voltage PG1 of the transistor MP1 to the internal power supply voltage VCC. At this time, since the gate potential and the source potential of the transistor MP1 are both the internal power supply voltage VCC, and the drain potential of the transistor MP1 is pulled down by the negative noise of the internal input voltage PVIN, the transistor MP1 is turned off, thereby shielding the discharge of the negative ground bounce noise to the internal power supply voltage VCC, thereby ensuring the stability of the internal power supply voltage VCC.

[0052] In addition, compared with the prior art solutions, since the internal power supply circuit of the present invention does not need to connect a resistor in series on the current path of the output stage transistor, the technical solution of the present invention can effectively shield the ground bounce noise in the circuit without reducing the load capacity of the output stage of the power supply circuit.

[0053] Figure 7 FIG. 3 shows a circuit diagram of an internal power supply circuit 302 according to a second embodiment of the present invention. Figure 7 As shown, the internal power circuit 302 of this embodiment includes a power generation module 313 and a noise protection module 312. The circuit and principle of the noise protection module 312 of this embodiment are the same as those of the noise protection module 312 of the first embodiment, and will not be repeated here.

[0054] Among them, the power generation module 313 of this embodiment is implemented by a charge pump circuit, which includes an output stage transistor MN1 and a control unit that provides a control signal GATE to the output stage transistor MN1. The control signal GATE adjusts the output of the internal power supply voltage VCC by controlling the conduction degree of the output stage transistor MN1.

[0055] Similar to the first embodiment, the output stage transistor MN1 is, for example, an N-type field effect transistor, whose drain is connected to the internal input voltage PVIN of the chip, whose source is used to be connected to the output end of the internal power supply voltage VCC, and whose gate is connected to the control signal GATE.

[0056] Furthermore, the control unit includes: a source follower unit 321, a charge pump unit 322, a filter unit 323 and a feedback adjustment unit 324. The source follower unit 321 is arranged between the internal input voltage PVIN and the internal reference ground PGND, and is used to generate a first voltage V1 according to the internal input voltage PVIN. The charge pump unit 322 is used to pump up the first voltage V1 in response to the timing control signals PHA and PHB to generate a charge pump output signal VP. The filter unit 323 is used to filter the charge pump output signal to generate the control signal GATE. The feedback adjustment unit 324 is used to adjust the control signal GATE according to the feedback signal VFB of the internal power supply voltage VCC and the reference voltage signal VREF.

[0057] Further, the source follower unit 321 includes a resistor R4, a reverse diode D2, a transistor MN2, and capacitors C4 and C5. The first end of the resistor R4 is connected to the internal input voltage PVIN, the second end of the resistor R4 is connected to the cathode of the reverse diode D2 and the gate of the transistor MN2, and the anode of the reverse diode D2 is connected to the internal reference ground PGND. Transistor MN2 serves as a source follower transistor, for example, an N-type field effect transistor, whose drain is connected to the internal input voltage PVIN, and whose source is used to output the first voltage V1. Capacitor C4 and capacitor C5 serve as voltage stabilizing capacitors, capacitor C4 is arranged between the source of transistor MN2 and the internal reference ground PGND, and capacitor C5 is arranged between the gate of transistor MN2 and the internal reference ground PGND. Further, the reverse diode D2 is a Zener diode.

[0058] Further, the charge pump unit 322 includes transistors T1 to T4 and flying capacitors CF1 and CF2. One end of the flying capacitor CF1 is connected to the timing control signal PHA, and the other end is connected to the boost node A inside the charge pump unit 322. One end of the flying capacitor CF2 is connected to the timing control signal PHB, and the other end is connected to the boost node B inside the charge pump unit 322. Transistors T1 to T4 adopt a differential cross-coupling architecture, transistors T1 and T2 are N-type field effect transistors, transistors T3 and T4 are P-type field effect transistors, sources of transistors T1 and T2 are connected to the first voltage V1, drains of transistors T1 and T3 and gates of transistors T2 and T4 are connected to the boost node A, drains of transistors T2 and T4 and gates of transistors T1 and T3 are connected to the boost node B, and sources of transistors T3 and T4 are connected to the output end of the charge pump output signal VP. Furthermore, the timing control signals PHA and PHB are differential signals. The charge pump unit 322 utilizes the characteristic that the voltages across the flying capacitors CF1 and CF2 cannot change suddenly, and continuously superimposes the voltage difference between the high and low levels of the timing control signals PHA and PHB on the first voltage V1, thereby obtaining a charge pump output signal VP higher than the first voltage V1 at the output end.

[0059] Furthermore, the filter unit 323 includes a filter resistor Rs and a filter capacitor Cs. The first end of the filter resistor Rs is connected to the output end of the charge pump unit 322, and the second end is connected to the gate of the output stage transistor MN1. The filter capacitor Cs is arranged between the gate of the output stage transistor MN1 and the internal reference ground PGND.

[0060] Further, the feedback adjustment unit 324 includes: an operational amplifier OP1 and a transistor MN3. The non-inverting input terminal of the operational amplifier OP1 is used to receive the feedback signal VFB, the inverting input terminal of the operational amplifier OP1 is used to receive the reference voltage signal VREF, and the operational amplifier OP1 is used to compare the feedback signal VFB with the reference voltage signal VREF. The transistor MN3 is, for example, an N-type field effect transistor, the drain of the transistor MN3 is connected to the gate of the output stage transistor MN1, the gate of the transistor MN3 is connected to the output terminal of the operational amplifier OP1, and the source of the transistor MN3 is connected to the internal reference ground PGND.

[0061] Furthermore, when the circuit is in a steady state, the output stage transistor MN1 is turned on by the control signal GATE, and the output stage transistor MN1 provides current to the load ILOAD, so that the internal power supply voltage VCC rises. When the feedback signal VFB is greater than the reference voltage signal VREF, the operational amplifier OP1 turns on the transistor MN3, and the control signal GATE is pulled down through the transistor MN3 to reduce the conduction degree of the output stage transistor MN1, so that the internal power supply voltage VCC can be stabilized within a set voltage range.

[0062] Furthermore, the internal power supply circuit 302 of this embodiment may also include a feedback network arranged at the output end of the internal power supply voltage VCC. Figure 7 As shown, the feedback network includes feedback resistors Rf1 and Rf2 connected in series between the output end of the internal power voltage VCC and the internal reference ground PGND, and the middle node of the feedback resistors Rf1 and Rf2 is used to output the feedback signal VFB of the internal power voltage VCC.

[0063] Figure 8 FIG. 3 shows a circuit diagram of the internal power supply circuit 303 of the third embodiment of the present invention. Figure 8 As shown, the internal power circuit 303 of this embodiment includes a power generation module 314 and a noise protection module 312. The circuit and principle of the noise protection module 312 of this embodiment are the same as those of the noise protection module 312 of the first embodiment, and will not be repeated here.

[0064] The power generation module 314 of this embodiment is implemented by a low voltage difference linear regulator, which includes an output stage transistor MP2 and a control unit that provides a control signal GATE to the output stage transistor MP2. The control signal GATE adjusts the internal power supply voltage VCC by controlling the conduction degree of the output stage transistor MP2.

[0065] Furthermore, the output stage transistor MP2 is, for example, a P-type field effect transistor, whose source is connected to the internal input voltage PVIN of the chip, whose drain is used to be connected to the output end of the internal power supply voltage VCC, and whose gate is connected to the control signal GATE.

[0066] Further, the control unit includes: a transistor MP3, a transistor MN4 and an error amplifier OP2. Among them, the transistor MP3 is, for example, a P-type field effect transistor, whose source is connected to the internal input voltage PVIN, and whose gate and drain are connected to the gate of the output stage transistor MP2, so the transistor MP3 and the output stage transistor MP2 of this embodiment form a current mirror structure. The non-phase input terminal of the operational amplifier OP2 is used to receive the reference voltage signal VREF, the inverting input terminal of the operational amplifier OP2 is used to receive the feedback signal VFB of the internal power supply voltage VCC, and the operational amplifier OP2 is used to compare the feedback signal VFB with the reference voltage signal VREF. The transistor MN4 is, for example, an N-type field effect transistor, the drain of the transistor MN4 is connected to the drain of the transistor MP3, the gate of the transistor MN4 is connected to the output terminal of the operational amplifier OP2, and the source of the transistor MN4 is connected to the internal reference ground PGND.

[0067] Similarly, the internal power supply circuit 303 of this embodiment may also include a feedback network arranged at the output end of the internal power supply voltage VCC. Figure 8 As shown, the feedback network includes feedback resistors Rf1 and Rf2 connected in series between the output end of the internal power voltage VCC and the internal reference ground PGND, and the middle node of the feedback resistors Rf1 and Rf2 is used to output the feedback signal VFB of the internal power voltage VCC.

[0068] Furthermore, when the circuit is in a steady state, since the feedback signal VFB is less than the reference voltage signal VREF, the operational amplifier OP2 turns on the output stage transistor MN4, and pulls the control signal GATE down to the internal reference ground PGND through the output stage transistor MN4, so that the output stage transistor MP2 is turned on, and current is provided to the load ILOAD through the output stage transistor MP2, so that the internal power supply voltage VCC rises. When the feedback signal VFB is greater than the reference voltage signal VREF, the operational amplifier OP2 turns off the transistor MN4, and then pulls the control signal GATE up to the internal input voltage PVIN through the transistor MP3, reducing the conduction degree of the output stage transistor MP2, thereby stabilizing the internal power supply voltage VCC within a set voltage range.

[0069] Fig.10 Schematic diagrams of waveforms of the internal power supply voltage of the embodiment of the present invention and the internal power supply voltage of the prior art are shown respectively. Fig.10In the figure, the horizontal axis represents the load current of the chip internal power circuit, the vertical axis represents the output voltage of the chip internal power circuit, curve 1 represents the output voltage waveform of the internal power circuit of the prior art, and curve 2 represents the output voltage waveform of the internal power circuit of the embodiment of the present invention. Fig.10 As shown, the output voltage of the internal power supply circuit in the prior art decreases as the on-chip load current increases, while the output voltage of the internal power supply circuit in the embodiment of the present invention can remain stable as the on-chip load current increases. Therefore, the technical solution of the present invention will not reduce the load capacity of the output stage of the power supply circuit while effectively shielding the ground bounce noise in the circuit.

[0070] In summary, an embodiment of the present invention provides an internal power supply circuit applied to an integrated circuit chip, including a power supply generating module and a noise protection module, wherein the noise protection module is arranged at the output-stage transistor terminal of the power supply generating module, and is used to detect the input voltage inside the chip, and disconnect the current path between the power supply generating module and the internal power supply voltage output terminal when negative ground bounce noise occurs in the internal input voltage, thereby effectively shielding the influence of the ground bounce noise on the internal power supply voltage. In addition, since the internal power supply circuit of the present invention does not need to connect a resistor in series on the current path of the output-stage transistor, the technical solution of the present invention will not reduce the load capacity of the output stage of the power supply circuit while effectively shielding the ground bounce noise in the circuit, thereby enabling the power supply to work stably under higher load conditions and meet application scenarios with greater power requirements. Therefore, the internal power supply circuit of the embodiment of the present invention can not only enhance the reliability and stability of the circuit, but also improve the performance of the system.

[0071] It should be noted that although in this article, the device is described as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it can be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It can be understood by those skilled in the art that the conductivity type refers to the mechanism by which the conduction occurs, such as conduction by holes or electrons, so the conductivity type does not involve the doping concentration but the doping type, such as P-type or N-type. It can be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating the action that occurs immediately when the start-up action begins, but there may be some small but reasonable one or more delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It is well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the desired goal of exactness as described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

[0072] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0073] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An internal power supply circuit applied to an integrated circuit chip, comprising: A power generation module, used to generate an internal power supply voltage according to an internal input voltage of the chip, the power generation module comprising an output-stage transistor, a first end of the output-stage transistor being connected to the internal input voltage of the chip, and a second end of the output-stage transistor being connected to an output end of the power generation module; as well as The noise protection module is arranged between the second end of the output stage transistor and the output end of the power generation module, and is used to detect the internal input voltage and disconnect the current path between the output stage transistor and the output end of the power generation module when negative ground bounce noise occurs in the internal input voltage.

2. The internal power supply circuit according to claim 1, wherein: The noise protection module comprises: a first transistor disposed between the second end of the output stage transistor and the output end of the power generation module, and a detection control unit connected to the control terminal of the first transistor and the internal input voltage, and configured to control the on and off of the first transistor according to the internal input voltage, The detection control unit is used to turn off the first transistor when the negative ground bounce noise appears in the internal input voltage.

3. The internal power supply circuit according to claim 2, wherein: The detection control unit comprises: A second transistor disposed between the control terminal of the first transistor and the output terminal of the power generation module; and A first capacitor and a first resistor are connected in series between the internal input voltage and the output end of the power generation module, and an intermediate node between the first capacitor and the first resistor is connected to the control end of the second transistor.

4. The internal power supply circuit according to claim 3, wherein: The detection control unit also includes: A second resistor, wherein a first end of the second resistor is connected to the control end of the first transistor, and a second end of the second resistor is connected to an internal reference ground of the chip.

5. The internal power supply circuit according to claim 3, wherein: The first transistor and the second transistor are P-type field effect transistors.

6. The internal power supply circuit according to claim 1, wherein: The power generation module also includes: A control unit is arranged between the internal input voltage and the internal reference ground of the chip, and the control unit is used to generate a control signal, and the control signal adjusts the internal power supply voltage by controlling the conduction degree of the output transistor.

7. The internal power supply circuit according to claim 6, wherein: The control unit comprises: a third resistor and a first reverse diode connected in series between the internal input voltage and the internal reference ground, wherein an intermediate node between the third resistor and the first reverse diode is connected to a control terminal of the output stage transistor to provide the control signal; and A second capacitor is disposed between the control terminal of the output stage transistor and the internal reference ground.

8. The internal power supply circuit according to claim 6, wherein: The control unit comprises: A source follower unit disposed between an internal input voltage and an internal reference ground of the chip, the source follower unit being used to generate a first voltage according to the internal input voltage; A charge pump unit, configured to perform a pump-up operation on the first voltage in response to a timing control signal to generate a charge pump output signal; a filtering unit, configured to filter the charge pump output signal and generate the control signal; and A feedback adjustment unit is used to adjust the control signal according to the feedback signal of the internal power supply voltage and the reference voltage signal.

9. The internal power supply circuit according to claim 8, wherein: The source following unit comprises: a fourth resistor and a second reverse diode connected in series between the internal input voltage and the internal reference ground; a third transistor and a third capacitor connected in series between the internal input voltage and the internal reference ground, the control terminal of the third transistor being connected to an intermediate node between the fourth resistor and the second reverse diode, and the intermediate node between the third transistor and the third capacitor being used to output the first voltage; and a fourth capacitor disposed between the control terminal of the third transistor and the internal reference ground, The charge pump unit comprises: at least one transistor and at least one flying capacitor forming a differential cross-coupling architecture. Wherein, the filtering unit comprises: a filter resistor, a first end of which is connected to the output of the charge pump unit, and a second end of which is connected to the control end of the output stage transistor; and A filter capacitor, a first end of which is connected to the control end of the output stage transistor, and a second end of which is connected to the internal reference ground, Wherein, the feedback adjustment unit comprises: a first error amplifier, configured to compare the feedback signal with the reference voltage signal; and A fourth transistor is disposed between the control terminal of the output stage transistor and the internal reference ground, wherein the control terminal of the fourth transistor is connected to the output of the error amplifier.

10. The internal power supply circuit according to claim 6, wherein: The control unit comprises: a second error amplifier, used to compare the feedback signal of the internal power supply voltage with a reference voltage signal; a fifth transistor, wherein a second terminal of the fifth transistor is connected to an internal reference ground of the chip, and a control terminal of the fifth transistor is connected to an output terminal of the second error amplifier; a sixth transistor, wherein a first terminal of the sixth transistor is connected to the internal input voltage, a control terminal and a second terminal of the sixth transistor are connected to the first terminal of the fifth transistor, Wherein, the control end of the sixth transistor is also connected to the control end of the output-stage transistor to generate the control signal.

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