RF tandem switching device with switching time acceleration

Abstract

The invention relates to an RF series switching device with switching time acceleration. An RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

Description

Technical Field

[0001] The present invention generally relates to RF series switch arrangements with switching time acceleration, and in a specific embodiment to corresponding methods for switching time acceleration. Background Art

[0002] Antenna tuning switches are used in mobile phones to adjust the characteristics of the antenna. The switch is implemented as MOS transistors stacked in series. The series connection is required to achieve high voltage handling at the RF frequencies generated at the antenna. The switch is connected between the feed of the antenna and the planar front-end electronics or coupled between the integrated antenna and the system ground plane. An important parameter of a switchable element is the switching time, which defines the time it takes for the switch to be fully opened or fully closed. This time defines when the RF signal can be applied to the antenna. The development of cellular standards shows that the switching time needs to be reduced. This demand is particularly due to the increase in the number of frequency bands and the need for fine-tuning capabilities.

[0003] The limitation to reducing the switching time comes from the RC network that must be charged to open or close the switch. This RC network consists of a resistor in series with the gate terminal of each switch and the gate-source / gate-drain capacitance. The RC time constant cannot be made smaller for two reasons. The gate-source / gate-drain capacitance must be high to keep the drain / source well defined when the RF signal is applied and the switch is opened (i.e., operating in the off state). A resistor in series with the gate terminal is required to define the DC voltage at the gate terminal. This resistor must be high to maintain a high impedance of the gate. When the RF signal is present and the switch is open, a high impedance is required to minimize the effect of the DC bias voltage on the gate voltage at high frequencies. The power loss in the switch is inversely proportional to the bias resistor of the circuit.

[0004] Therefore, there is a trade-off between the switching speed of the switch and the RF performance. One challenge for improving switch performance is to quickly recharge the gate of the switch in the high-ohmic state of the switch without reducing the RC time constant. This trade-off is particularly important in high-stack antenna tuning switches, where the RC time constant cannot be easily reduced without severely degrading the power loss and drastically distorting the voltage distribution within the MOSFET stack. Summary of the invention

[0005] According to one embodiment, an RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

[0006] According to one embodiment, an RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, a main control output, an acceleration control input, and an acceleration control output; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a shunt series switch coupled between the main control output of the shunt switch and the main control input of the series switch, and coupled between the acceleration control output of the shunt switch and the acceleration control input of the series switch.

[0007] According to one embodiment, a method for operating an RF switching device, wherein the RF switching device includes a series switch, a shunt switch, and a shunt series switch, the series switch including a first switching time acceleration circuit, the shunt switch including a second switching time acceleration circuit, and the shunt series switch is used to selectively couple the series switch to the shunt switch, wherein the method includes: establishing a conductive path during a switching transient and off-state operating mode of the series switch; and interrupting the conductive path during an on-state operating mode of the series switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1A is a schematic diagram of a shunt RF switch using conventional resistive biasing;

[0010] Figure 1B is a schematic diagram of an exemplary shunt RF switch with switching time acceleration;

[0011] Figure 1C Included for control Figure 1B A timing diagram of time domain waveforms of the main branch and the acceleration branch of the exemplary shunt RF switch shown in;

[0012] Figure 1D Shows Figure 1B A symbolic representation of an exemplary shunt RF switch shown in;

[0013] Figure 2A , Figure 2B , Figure 2C ,and Figure 2D is an example of an applied RF switch for antenna tuning, which includes a shunt switch combined with a series switch;

[0014] Figure 3 It is used in the following Figure 4A and Figure 4B A general signal diagram of an RF series switching device with switching time acceleration shown in;

[0015] Figure 4A is a schematic diagram of an RF series switch device with switching time acceleration according to one embodiment;

[0016] Figure 4B is a schematic diagram of an RF series switch device with switching time acceleration according to another embodiment;

[0017] Figure 5 is used for Figure 4A and Figure 4B Schematic diagram of an additional switching time acceleration circuit for the series switch shown in;

[0018] Figure 6 is used for Figure 5 A timing diagram with control voltage levels of the switching time acceleration circuit shown in ;

[0019] Figure 7 is coupled to Figure 1B The shunt switch shown in Figure 5 Schematic diagram of the switching time acceleration circuit;

[0020] Figure 8 is with Figure 5 A schematic diagram of an example blocking diode implementation associated with a switching time acceleration circuit;

[0021] Fig. 9A is a schematic diagram of an RF series switch device including a shunt series switch and the shunt switch and the series switch with switching time acceleration according to one embodiment;

[0022] Fig. 9B is a schematic diagram of an RF series switch device including a shunt series switch and the shunt switch and the series switch with switching time acceleration according to another embodiment;

[0023] Fig. 9C is with Fig. 9A and Fig. 9B A timing diagram associated with an RF series switching device;

[0024] Fig.10 Yes Operation Fig. 9A and Fig. 9B A flow chart of a method for an RF series switching device;

[0025] Fig.11A , Fig. 11B ,and Fig. 11C yes Fig. 9A and Fig. 9B The example embodiment of the shunt series switch shown in ; and

[0026] Fig.12is a schematic diagram of an RF series switch device according to one embodiment, the RF series switch device including a shunt switch and a series switch with switching time acceleration, the shunt series switch, and a plurality of RF clamps. DETAILED DESCRIPTION

[0027] The making and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in various specific contexts. The specific embodiments discussed only illustrate the specific ways to make and use the present invention, and do not limit the scope of the present invention.

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and in which specific embodiments in which the present invention can be practiced are shown in a graphical manner. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, the features illustrated or described for one embodiment may be used in other embodiments or used in combination with other embodiments to produce another embodiment. The present invention is intended to include such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustration purposes only. For clarity, unless otherwise stated, in different drawings, the same or similar elements have been indicated by corresponding reference numerals.

[0029] Switching time acceleration implementations for shunt high voltage RF switches are shown and described in co-pending patent application Ser. No. 17 / 648,849, entitled “RF Switch with Switching Time Acceleration,” which is incorporated herein by reference in its entirety. While the implementation in the '849 patent application demonstrates excellent results for shunt switching, it is not directly applicable to series switching, as discussed in further detail below. Figure 1A , Figure 1B , Figure 1C and Figure 1D The switching time acceleration of the '849 patent application is briefly shown and described.

[0030] Figure 1A Schematic diagram of a shunt RF switch 100A using conventional resistive biasing. The shunt RF switch 100A is a shunt switch coupled between an RF source 102 and ground, and includes a plurality of stacked NMOS transistors S1, S2, ..., and SN. Figure 1AOnly three such transistors are shown in FIG, but those skilled in the art will recognize that any number of such transistors may be used based on the semiconductor technology used and the high voltage requirements required for a particular application. The shunt RF switch 100A includes a plurality of drain-to-source resistors RDS1, RDS2, ..., and RDSN, wherein a single drain-to-source resistor is coupled to the drain-to-source of a corresponding NMOS transistor. The shunt RF switch 100A also includes a plurality of gate resistors RG1, RG2, ..., and RGN, which are coupled to the gate of each corresponding NMOS transistor. Resistor RG1 receives a control signal at a control input node 104 for operating the shunt RF switch 100A. When the control signal at the control input node 104 is low, the shunt RF switch 100A is turned off. Conversely, when the control signal at the control input node 104 is high, the shunt RF switch 100A is turned on.

[0031] Figure 1B is a schematic diagram of an exemplary shunt RF switch 100B with switching time acceleration. The shunt RF switch 100B includes all components of the shunt RF switch 100A, but the resistor and transistor labels are omitted. In addition, the shunt RF switch 100B includes: an acceleration branch 106, which includes a plurality of PMOS transistors for selectively shorting a gate resistor; an acceleration branch 108, which includes a plurality of NMOS transistors for selectively shorting a drain-to-source resistor; and an acceleration branch control network 110, which is used to provide control signals to the acceleration branch 106 and the acceleration branch 108. In the shunt RF switch 100B, the gate resistor is coupled between the main control input node 104 and the main control output node 105. The drain-to-source resistor is coupled between the RF source 102 and ground.

[0032] Figure 1C Included for control Figure 1B 100B. The timing diagram of the time domain waveforms of the main branch and the acceleration branch of the exemplary shunt RF switch 100B shown in . The control waveform 104' for the main control input node 104 is used to switch the main branch of the shunt RF switch 100B (RF switch 100A) from the off state to the on state, and then from the on state back to the original off state. The acceleration control input waveform 112' of the acceleration control input node 112 for the acceleration branch 106 and the acceleration branch 108 is operable during a first switching transient acceleration 116 associated with the rising edge of the control waveform, and during a second switching transient acceleration 118 associated with the falling edge of the control waveform signal 112' coupled to the node 112.

[0033] Figure 1D Shows Figure 1B, which is coupled to an RF source 102, a main control input node 104, a speed-up control input node 112, and a ground node.

[0034] Thus, embodiments of the present invention are based in part on the switching time acceleration implementations shown and described in the '849 patent application. Figure 1B The '849 application shows a conceptual circuit diagram of an improved circuit by adding acceleration branches 106 and 108 based on switches (eg, PMOS and NMOS transistors) that short-circuit the gate and drain-source bias network resistors during switching transients. Figure 1A The switching times of conventional shunt switches with series resistive bias in FIG. 100A are compared to those of conventional shunt switches with series resistive bias in FIG. 100A. The control of the speed-up branches 106 and 108 is performed by a high-ohmic resistor-based speed-up branch control network 110, which follows the stacked configuration of the shunt RF switch 100A and is fed from the cold side (i.e., ground side) of the switch. At the beginning of a "change state" command for the shunt RF switch 100A, the speed-up switch is enabled for a short time and disabled after the switching transient is completed. Figure 1C The time domain waveforms used to control the main branch and the acceleration branch are shown in . Figure 1B The circuit shown in is not directly applicable to series switches because it does not solve the problem of feeding the control signal (denoted as "main control input" at control input node 104 and as "acceleration control input" at acceleration control input node 112) if one of the two poles of the switch is not shorted to ground, but is coupled between two RF sources.

[0035] The configuration of the shunt RF switch 100B means that the control nodes 104 and 112 are directly coupled to the low voltage, low ohmic control circuit. If the ground input of the switch is exposed to a high RF voltage (which is the typical operating mode of a series switch), a high RF voltage drop will appear on the bottom-most device of the acceleration branch control network (i.e., the lowest resistor and the lowest PMOS connected to the control node 104). In turn, this will lead to high power losses and even reliability risks. In order to enable the ground input of the shunt RF switch 100B to be exposed to a high RF voltage, the control signal must be applied via a high ohmic impedance path to allow nodes 104 and 112 to be exposed to a high voltage level similar to the switch input itself.

[0036] Figure 2A , Figure 2B , Figure 2C ,and Figure 2D is an example of an applied RF switch for antenna tuning, which includes a shunt switch combined with a series switch. Figure 2A , Figure 2B , Figure 2C ,and Figure 2DThe antenna includes a shunt switch S1 coupled between a first RF source RF1 and ground, and a series switch S2 coupled between the first RF source RF1 and a second RF source RF2. The second RF source RF2 is directly or indirectly coupled to the antenna and the antenna feed 202 at a node 204. Figure 2A In , the inductor L1 is coupled between the second RF source RF2 and the node 204. Figure 2B In , the inductor L1 is coupled between the first RF source RF1 and the ground. Figure 2C In FIG. 2 , capacitor C1 is coupled between the second RF source RF2 and node 204. Figure 2D In the embodiment, capacitor C1 is coupled between the first RF source RF1 and ground.

[0037] According to an embodiment, the switch branches in the RF series switch device include at least one series switch branch and may include a shunt branch that remains in an off state during RF operation in a default configuration. The shunt switch can be used for the purpose of ESD protection of the series branch, as known in the art. In some embodiments, the shunt switch is used as a path for transmitting a control signal from a controller to the series switch, as will be described in further detail below.

[0038] The use of a series switch with switching time acceleration according to an embodiment is not limited to any particular application. However, the series switch including switching time acceleration has particular advantages in the primary target application of RF antenna tuning. Figure 2A , Figure 2B , Figure 2C ,and Figure 2D Several examples of antenna tuning applications are depicted in Figure 1. In all cases, a reactive component (capacitor or inductor) is coupled to the antenna aperture tuning point via a series switch. In some cases (where the inductor is coupled directly to ground, such as Figure 2B In the example of FIG. 1 , when the series switch is in the off state, the shunt switch can be closed to short the inductor to ground. This will prevent the inductor and the capacitance of the off-state series switch from forming an unwanted series resonance at high frequencies.

[0039] In a first set of embodiments, both the shunt switch S1 and the series switch S2 include RF switches with accelerated switching times, such as Figure 1B However, in order to remedy the problem set forth above by directly replacing the circuit with the series switch S2, an additional switch time acceleration circuit is used. The additional switch time acceleration circuit includes two additional switches and a diode circuit. The diode circuit limits the function of each additional switch to only charging the main control input 104 or only discharging the main control input 104. According to one embodiment, the additional switch time acceleration block can be partially merged with the shunt switch S1. The operation and advantages of the partially merged embodiment will be discussed below, especially with respect to Figure 7Description of the invention. The additional switching time acceleration block solves the direct replacement problem by providing a low ohmic impedance path between the controller and the main control input 104 of the series switch S2 via the additional switching time acceleration circuit. The low ohmic impedance path is provided during the switching phase of the switching device (i.e., S2=off) and is interrupted during RF operation (i.e., S2=on). Additionally, the stacked structure of the two additional switches allows the additional switching time acceleration circuit to withstand the (potentially) high RF voltage applied to either of the two RF terminals of the main switch.

[0040] In a second set of embodiments, both the shunt switch S1 and the series switch S2 include RF switches with accelerated switching times, such as Figure 1B As shown in . However, in order to remedy the problem set forth above by directly replacing the circuit with the series switch S2, a "shunt series" switch is also implemented for selectively transmitting a control signal between the shunt switch S1 and the series switch S2. Conceptually, the "shunt series" switch extends the acceleration branch of the shunt switch toward the series switch during the switching phase of the switching device, treats the combined branch as a single branch, and switches both the series switch and the shunt switch to the target state of the series switch, and then interrupts the path between the shunt switch and the acceleration branch of the series switch during the RF operation phase.

[0041] Figure 3 According to the embodiment Figure 4A and Figure 4B 300. The general signal diagram 300 shows a main control input waveform 302, an acceleration control input waveform 304, a series switch main bias waveform 306, a positive acceleration path input waveform 308, and a negative acceleration path input waveform 310. The main control input waveform 302 and the acceleration control input waveform 304 are similar to Figure 1B The corresponding waveforms for the shunt RF switch 100B shown in FIG. 3 are substantially the same. The positive acceleration path input waveform 308 and the negative acceleration path input waveform 310 are used to selectively enable the PMOS and NMOS switches in the additional switching time acceleration circuit, as described below with respect to FIG. Figure 4A and Figure 4B The additional switching time acceleration circuit is further shown and described in detail.

[0042] Figure 4A , Figure 4B , Fig. 9A ,and Fig. 9B The RF series switch devices discussed in the drawings all include a series switch coupled between an RF source RF1 and an RF source RF2. In these figures, the series switch is shown in symbolic form, and the actual RF1 and RF2 nodes are not shown at the circuit level. Figure 4A , Figure 4B , Fig. 9A ,and Fig. 9B The RF series switch arrangement discussed in the Figure 1B The shunt RF switch 100B shown in FIG. In the shunt switch, the "RF" node corresponds to the "RF2" node, and the ground node corresponds to the "RF1" node.

[0043] Figure 4A Schematic diagram of an RF series switch device 400A with switching time acceleration according to one embodiment. The RF series switch device 400A includes a series switch 404 (S2), a shunt switch 402 (S1), and an additional switching time acceleration circuit 406. Both the series switch 404 (S2) and the shunt switch 402 (S1) include the switching time acceleration circuit device as described above. The additional switching time acceleration circuit 406 includes a PMOS switch S3 and an NMOS switch S4. Figure 5 It is further described in detail. The shunt switch S1 is coupled between the RF source RF1 and the ground, and includes a main control input node 408A and an acceleration control input node 410A. The series switch S2 is coupled between the RF source RF1 and the RF source RF2, and includes a main control input node 408B and an acceleration control input node 410B. The RF series switch device 400A also includes a first bias resistor R1 coupled between the series switch acceleration bias node 418 and the acceleration control input node 410B, and a second bias resistor R2 coupled between the series switch main bias node 420 and the main control input node 408B. The additional switching time acceleration circuit 406 includes a positive acceleration path input node 412 coupled to one end of the switch S3 and a negative acceleration path input node 414 coupled to one end of the switch S4. The following will be about Figure 5 and Figure 6 4B depicts the control node voltages for switch S3 and switch S4. The other end of switch S3 and the other end of switch S4 are both coupled to the main control input node 408B. Figure 4A , the additional switching time acceleration circuit 406 is shown as a separate component from the shunt switch S1 and the series switch S2.

[0044] Figure 4B FIG. 4 is a schematic diagram of an RF series switch device 400B with switching time acceleration according to another embodiment, wherein an additional switching time acceleration circuit 406 is coupled to the shunt switch S1 and is combined with the shunt switch S1 for increasing high voltage performance, as will be referred to below. Figure 74. As explained above. Thus, shunt switch 402 (S1) includes a positive acceleration path input node 412, a negative acceleration path input node 414, a main control input node 408A, and an acceleration control input node 410A. In addition, the output of switch S3 (merged into shunt switch 402) is coupled to the anode of diode D3 of diode circuit 416, and the output of switch S4 (merged into shunt switch 402) is coupled to the cathode of diode D4 of diode circuit 416. The cathode of diode D3 and the anode of diode D4 are both coupled to main control input node 408B. Diode circuit 416 can optionally be coupled to RF source RF1 at input 417 to provide for Figure 8 The bias voltage of certain diode embodiments is best shown in FIG.

[0045] In one embodiment, diode D3 and diode D4 of diode circuit 416 are used to overcome implementation challenges related to electrical limitations of practical devices used in the circuit implementation of RF series switch device 400B. In particular, the diodes prevent electrical overstress and block current from flowing into another additional switch when another additional switch is activated (i.e., switched on to charge or discharge the main switch).

[0046] Figure 5 is used for Figure 4A and Figure 4B Schematic diagram of an additional switching time acceleration circuit 406 for the series switch 404 shown in FIG. Figure 5 The additional switching time acceleration circuit 406 is replicated at the top, where switches S3 and S4 are shown. Switches S3 and S4 and diode circuit 416 are Figure 5506N. The drain of transistor PN is coupled to the anode of diode D1. The cathode of diode D1 (node ​​510) is coupled to the main control input node of series switch 404, as previously discussed. The source of transistor P1 is coupled to the positive acceleration path input node 412. Resistor 506A is coupled to the first gate bias node 502. Switch S4 in turn includes a plurality of stacked NMOS transistors N1, N2, ..., to NN, which are coupled to corresponding plurality of gate resistors 508A, 508B, 508C, ..., to 508N. The drain of transistor NN is coupled to the cathode of diode D2. The anode of diode D2 (node ​​512) is also coupled to the main control input node of series switch 404, as previously discussed. The source of transistor N1 is coupled to the negative acceleration path input node 414. Resistor 508A is coupled to the second gate bias node 504. Diode circuit 416 can optionally be coupled to RF source RF1 at input 417 to provide a bias voltage as previously described.

[0047] Figure 6 is used for Figure 5 A timing diagram 600 with control voltage levels of an additional switch time acceleration circuit shown in FIG. Representative waveforms during an initial off-state 610 of the series switch 404, during an on-state 612 of the series switch 404, and during a subsequent off-state 614 of the series switch 404 are shown. The representative waveforms are a first gate bias waveform 602, a second gate bias waveform 604, a positive acceleration path input waveform 606, and a negative acceleration path input waveform 608. The first gate bias waveform 602 is set to ground, the second gate bias waveform 604 includes a single positive pulse during the subsequent off-state 614, the positive acceleration path input waveform 606 includes a single positive pulse during the on-state 612, and the negative acceleration path input waveform 608 includes a single negative pulse during the subsequent off-state 614.

[0048] The voltage levels used in timing diagram 600 are:

[0049] 1) GND = ground potential, relative to which all other voltages are defined;

[0050] 2) -Vctrl = negative voltage relative to GND, corresponding to the control voltage for the off-state switch (-Vctrl is typically in the range of -2V to -4V); and

[0051] 3) +Vctrl = positive voltage relative to GND, corresponding to the control voltage for the on-state switch (+Vctrl is typically in the range of +2V to +4V).

[0052] Notice, Figure 6 The timing diagram and Figure 1C There are differences between the functional (or logical) timing diagrams of Figure 6 In , the negative acceleration path is enabled by applying a negative voltage. Figure 1C In the example, the corresponding signal becomes a logic "high" level to enable the negative acceleration path. Figure 1C The speed-up control at logic "high" level shorts all bias resistors of the main switch to enable fast charging / discharging of the stack. To this end, after switching to the on state, the speed-up control is kept "high" for a short period of time to allow all transistors in the stack to change their states correctly, after which the speed-up control signal becomes "low" to disable the short-circuiting of the bias resistors.

[0053] In summary, without the functional advantages of the switching time acceleration circuit 406 described above, the only charging / discharging path for the series switch is resistor R2. Resistor R2 is a high ohmic resistor, which therefore cannot provide a low ohmic path for fast switching. Since the power loss across the resistor is too large, it is impractical to make resistor R2 low ohmic. The additional switching time acceleration circuit provides a low ohmic impedance path between the positive acceleration path input node 412 and the negative acceleration path input 414 and the main control input of the series switch. The additional switching time acceleration circuit 406 provides a low ohmic impedance path during the switching phase of the switching device and interrupts the low ohmic impedance path during RF operation (or in other words, provides a high ohmic impedance path). Additionally, the stacking structure of the two additional switches allows the additional switching time acceleration circuit to withstand the (potential) high RF voltage applied to any of the two RF terminals of the main switch. The series switch can be coupled between RF1 and RF2 and can be biased via R2 without the acceleration circuit 406, but in this hypothetical configuration, the series switch will switch slowly. An important purpose of the speed up circuit 406 is to speed up the switching and maintain low RF losses by keeping the value of the resistor R2 high.

[0054] Figure 7 is coupled to Figure 1B The shunt RF switch 100B shown in FIG. Figure 5 Schematic diagram of switches S3 and S4 of the switching time acceleration circuit for Figure 4B, . In particular, switches S3 and S4 are physically coupled to the shunt RF switch 100B because the relative positions of the gates of transistors P1, P2, ..., PN and the gates of transistors N1, N2, ..., NN are arranged to be in the same relative vertical position as the gates of the transistors stacked in the shunt RF switch 100B in the integrated circuit implementation. This arrangement ensures that the switching performance is enhanced because the problems associated with large voltage gradients are avoided. The arrangement is mainly related to the physical implementation of the circuit. For efficient and reliable operation of the circuit (i.e., the RF voltage distribution in the transistor P1, P2, ..., PN and N1, N2, ..., NN device stacks is equal), the physical implementation means that P1, P2, ..., PN and N1, N2, ..., NN stacks are run next to the main stack in the same grid as the main stack (the number of stacked devices is the same, and each device corresponds to a corresponding transistor in the main stack).

[0055] Figure 8 is with Figure 5 Schematic diagrams of example blocking diode implementations associated with a switching time acceleration circuit of FIG. 802. A first implementation 802 includes a diode D1 having an anode coupled to node 1 and a cathode coupled to node 5; a diode D2 having an anode coupled to node 4 and a cathode coupled to node 2; and an optional bias voltage input coupled to node 3. A second implementation 804 includes only diodes D1 and D2, without the optional bias voltage input at node 3. A third implementation 806 includes a transistor P1 having a drain coupled to node 1; and a diode D1 having an anode coupled to the source of transistor P1 and a cathode coupled to node 5. Implementation 806 also includes a transistor N1 having a drain coupled to node 2; and a diode D2 having a cathode coupled to the source of transistor N1 and an anode coupled to node 4. In implementation 806, the gates of transistors P1 and N1 are coupled to node 3. A fourth implementation 808 includes transistors P1 and N1 in a diode-connected transistor configuration, and the connection to node 3 is omitted. In addition to transistors P1 and N1, fifth embodiment 810 includes series-connected transistors P2 and N2 coupled between node 3 and node 5, and transistors P3 and N3 coupled between node 3 and node 4. Sixth embodiment 812 includes all elements of embodiment 810, but additionally includes transistor N4 having a source coupled to the source of transistor P1, a drain coupled to node 5, and a gate coupled to the junction between transistors P2 and N2. Embodiment 812 also includes transistor P4 having a source coupled to the source of transistor N1, a drain coupled to node 4, and a gate coupled to the junction between transistors P3 and N3.

[0056] Fig. 9A and Fig. 9B is a schematic diagram of an RF series switch device including a shunt series switch and a shunt switch and a series switch with switching time acceleration according to a second set of embodiments. The shunt switch and the series switch are similar to those discussed previously. Figure 1B Same as shown in .

[0057] Fig. 9A is a schematic diagram of an RF switch device 900A according to one embodiment, which includes a shunt switch 902 coupled between an RF source RF1 and ground, a series switch 904 coupled between the RF source RF1 and the RF source RF2, and a "shunt series" switch 906. The shunt switch 902 and the series switch 904 each also include a main control input node (908A, 908B, respectively) and an acceleration control input node (910A, 910B, respectively), which are used to control the switch state and for accelerating the switching transient. The shunt switch 902 also includes a main control output node 914 and an acceleration control output node 912. The shunt series switch 906 is coupled between the main control output node 914 of the shunt switch 902 and the main control input node 908B of the series switch 904, and is coupled between the acceleration control output node 912 of the shunt switch 902 and the acceleration control input node 910B of the series switch 904. The shunt series switch 906 has an input for receiving a shunt series control signal at the shunt series control node 916. In one embodiment, the shunt series switch 906 is configured to establish a conductive path during the switching transient and off-state operation of the series switch 904, and to interrupt the conductive path during the on-state operation of the series switch 904. Fig. 9C The timing diagram and Fig.10 The flowchart further describes the operation of the RF switching device 900A in detail.

[0058] Fig. 9B is a schematic diagram of an RF switch device 900B, which includes Fig. 9A However, except for Fig. 9A In addition to the components shown in , the RF switch device 900B also includes optional resistors 922 , 924 , and 926 .

[0059] The RF switch device 900B may additionally include a high ohmic resistive bias network (resistors 924 and 926) coupled to the main control input node 908B and the acceleration control input node 910B of the series switch 904, such as Fig. 9B. Resistor 924 is coupled between the acceleration control input node 910B and the series switch acceleration bias node 918. Resistor 926 is coupled between the main control input node 908B and the series switch main bias node 920. When the shunt series switch 906 is operated in the off state and the bias voltage cannot be delivered from the main control input terminal and the acceleration control input terminal, the high ohmic resistive bias network is used to maintain the desired bias voltage at the gate of the main switch and at the control terminal of the acceleration network during RF operation. The control voltages at the series switch main bias node and the acceleration bias node (920, 918) are synchronized with the main control signal and the acceleration control signal, as shown in FIG. Fig. 9C 0044] As shown in the timing diagram in and described in further detail below. In some embodiments, the values ​​of high ohmic resistors 924 and 926 may be in the range of 10k to 1M Ohm.

[0060] The RF switch arrangement may further include an additional high ohmic resistor 922 coupled between the shunt series control node 916 and the shunt series switch 906, as shown in FIG. Fig. 9B As shown in . Resistor 922 can be used to decouple the shunt series control voltage source at the RF frequency from the shunt series control node 916 of the shunt series switch 906, thereby preventing unnecessary power loss or a low impedance ground path for the RF signal path (i.e., RF1-RF2) of the switch device. In some embodiments, the value of high ohmic resistor 922 can be in the range of 10k to 1M Ohm.

[0061] Fig. 9C is with Fig. 9A and Fig. 9B The timing diagram 900C associated with the RF series switch device of FIG. 900C. The main control input waveform 934 places the RF series switch device in an initial off-state, an on-state, and a subsequent off-state. The acceleration control input waveform 936 includes a first switch transient acceleration 930 associated with the rising edge of the acceleration control input waveform and a second switch transient acceleration 932 associated with the falling edge of the acceleration control input waveform. The acceleration control input waveform 936 is high when the main control input waveform 934 is high and during the second switch transient acceleration 932 time period. The shunt series control waveform 938 is high except for the time period between the first switch transient acceleration 930 and the second switch transient acceleration 932 time periods. Therefore, the control voltages at the series switch main bias node and the acceleration bias node (920, 918) are synchronized with the main control signal and the acceleration control signal, such as Fig. 9C As shown in the timing diagram.

[0062] In operation, it is assumed that the shunt switch is always kept in the off state during operation. In order to apply different bias voltages to the series switch in the on state (i.e., positive bias voltage) and the shunt switch in the off state (negative bias voltage), the shunt series switch interrupts the DC path between the bias networks of the two switches, thereby allowing voltages with different levels and polarities to be applied to the series switch and the shunt switch simultaneously during RF operation.

[0063] Fig.10 Yes Operation Fig. 9A and Fig. 9B Flowchart 1000 of a method for an RF series switch device of the present invention. The method starts at step 1002. At step 1004, the method determines whether the series switch and the shunt switch are in the same state. If the answer is yes, the method continues by causing the shunt series switch to enter the on state at step 1006. Then, the shunt switch and the series switch are switched to a new state at step 1008. Subsequently, the shunt series switch is caused to enter the off state at step 1010. Thereafter, the shunt switch is caused to enter the initial state at step 1012. The method then ends at step 1014. If the answer to the inquiry of step 1004 is no, the shunt switch is caused to enter the same state as the series switch at step 1016. The method continues by causing the shunt series switch to enter the on state at step 1018. Then, the shunt switch and the series switch are switched to a new state at step 1020. Subsequently, the shunt series switch is caused to enter the off state at step 1022. The method then ends at step 1024.

[0064] Fig.11A , Fig. 11B ,and Fig. 11C yes Fig. 9A and Fig. 9B 11 , the two separate switches are identified as switch SS1 and switch SS2. Various implementations of switches SS1 and SS2 (and connections to RF source RF1) are described in detail in the following examples. Fig.11A , Fig. 11B ,and Fig. 11C is shown in and described below.

[0065] The shunt series switch 906 can be implemented in the form of a T-junction, such as Fig.11A1100A is shown in the switch device 1100A shown in . Switch SS1 is implemented using separate switches S1, S3, and S5 coupled together at node 1102. Switch SS2 is implemented using separate switches S2, S4, and S6 coupled together at node 1104. The shunt elements (switch S3, switch S4) of the T-junction can be directly coupled to the RF1 node of the switch device. The purpose of the T-junction is to protect the switch from exceeding the maximum DC voltage difference when the path between the shunt switch and the series switch is not established. In other words, the junction realizes a stacked switch structure under DC voltage. Note that the voltage level at the control node may swing between a negative DC voltage and a positive DC voltage, with the DC component at the RF1 pin being close to zero.

[0066] Fig.11A The T-junction switch device 1100A shown in FIG. 1 can be used as shown in FIG. Fig. 11B 1100B shown in FIG. 1100B is implemented using MOS transistors operating in switch mode. Switch SS1 is implemented using transistor switches N1, P1, and N3 coupled together at node 1102. Switch SS2 is implemented using transistor switches N2, P2, and N4 coupled together at node 1104. PMOS and NMOS devices provide reverse switching functions. If the voltage drop across the terminals exceeds the maximum rated voltage of a single transistor device, then Fig. 11B Each transistor shown in can be implemented as a series connection of multiple transistor devices.

[0067] Fig. 11B Each switching MOSFET shown in 1100C may additionally include a complementary device in parallel with the single switching MOSFET to form a so-called transmission gate, as shown in switch device 1100C. Such a device may be more suitable for providing a low-ohmic on-state path for each of the two signal branches, thereby further accelerating the switching acceleration. In particular, switch SS1 includes transmission gates T1, T3, and T5 coupled together at node 1102. Switch SS2 includes transmission gates T2, T4, and T6 coupled together at node 1104.

[0068] Fig.12 FIG. 1 is a schematic diagram of an RF series switch device 1200 according to an embodiment, which includes a shunt switch and a series switch with switching time acceleration, a shunt series switch, and a plurality of RF clamps. In addition to the plurality of RF clamps described in detail below, the RF series switch device 1200 and Fig. 9B The RF switch device 900B shown in and described previously is substantially the same.

[0069] In one embodiment, the plurality of RF clamps 940 include a plurality of capacitors C1, C2, C3, C4, and C5. Fig.12 , but additional or fewer such clamps may be used. In one embodiment, capacitor C1 is coupled between RF1 (RF source RF1) and the acceleration control output node 912, capacitor C2 is coupled between RF1 and the main control output node 914, capacitor C3 is coupled between RF1 and node 928, capacitor C4 is coupled between RF1 and node 910, and capacitor C5 is coupled between RF1 and node 908.

[0070] The RF clamp provides a low impedance path between the RF node RF1 and the control node of the shunt series switch, such as Fig.12 The purpose of each clamp is to keep the AC voltage at the control terminal equal to or close to the AC voltage at the RF1 node to protect the switch device 1200 from damage when it is driven by a high power RF signal. The RF clamp can be implemented in the form of a linear capacitor, with a value typically between 10fF and 100fF.

[0071] Example embodiments of the invention are summarized here. Other embodiments may also be understood from the overall description and claims submitted herein.

[0072] Example 1. According to one embodiment, an RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and an acceleration control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a switching time acceleration circuit having a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

[0073] Example 2. The RF switch device of Example 1, wherein the switching time acceleration circuit includes a third switch coupled between the positive acceleration path input and the first output.

[0074] Example 3. The RF switch device according to any of the above examples, wherein the third switch comprises a plurality of stacked PMOS transistors.

[0075] Example 4. An RF switching device according to any of the above examples, wherein the switching time acceleration circuit includes a second output, which is coupled to the main control input of the series switch, and wherein the switching time acceleration circuit includes a fourth switch coupled between the negative acceleration path input and the second output.

[0076] Example 5. The RF switch device according to any of the above examples, wherein the fourth switch comprises a plurality of stacked NMOS transistors.

[0077] Example 6. The RF switch device according to any of the above examples, further comprising a diode circuit coupled to the third switch and the fourth switch.

[0078] Example 7. According to one embodiment, an RF switching device includes: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, a main control output, an acceleration control input, and an acceleration control output; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and an acceleration control input; and a shunt series switch coupled between the main control output of the shunt switch and the main control input of the series switch, and coupled between the acceleration control output of the shunt switch and the acceleration control input of the series switch.

[0079] Example 8. The RF switch device of Example 7, wherein the shunt series switch is configured to establish a conductive path during a switching transient and an off-state operating mode of the series switch, and is configured to interrupt the conductive path during an on-state operating mode of the series switch.

[0080] Example 9. The RF switch device according to any of the above examples, wherein the shunt series switch further includes a shunt series control node.

[0081] Example 10. The RF switch device according to any of the above examples, wherein the shunt series switch includes a first T-junction switch device and a second T-junction switch device.

[0082] Example 11. The RF switch device according to any of the above examples, wherein the first T-junction switch device and the second T-junction switch device each include a first NMOS transistor and a second NMOS transistor coupled to a PMOS transistor.

[0083] Example 12. The RF switch device according to any of the above examples, wherein the first T-junction switch device and the second T-junction switch device each include a first NMOS transmission gate and a second NMOS transmission gate coupled to a PMOS transmission gate.

[0084] Example 13. According to one embodiment, a method for operating an RF switching device, wherein the RF switching device includes a series switch, a shunt switch, and a shunt series switch, the series switch including a first switching time acceleration circuit, the shunt switch including a second switching time acceleration circuit, the shunt series switch being used to selectively couple the series switch to the shunt switch, wherein the method includes establishing a conductive path during a switching transient and off-state operating mode of the series switch; and interrupting the conductive path during an on-state operating mode of the series switch.

[0085] Example 14. The method of Example 13 further includes querying the RF switching device to determine whether the series switch and the shunt switch are in the same state.

[0086] Example 15. A method according to any of the above examples, wherein if the series switch and the shunt switch are in the same state, the method further includes: placing the shunt series switch in an on state; switching the shunt switch and the series switch to a new state; placing the shunt series switch in an off state; and placing the shunt switch in an initial state.

[0087] Example 16. A method according to any of the above examples, wherein if the series switch and the shunt switch are not in the same state, the method further comprises placing the shunt switch in the same state as the series switch.

[0088] Example 17. A method according to any of the above examples, wherein the method further includes placing the shunt series switch in an on state; switching the shunt switch and the series switch to a new state; and placing the shunt series switch in an off state.

[0089] Example 18. The method of any of the above examples further comprises clamping at least one circuit node of the RF switching device to the first RF source.

[0090] Example 19. The method of any of the above examples further includes coupling a shunt switch between the first RF source and ground.

[0091] Example 20. The method of any of the above examples further comprises coupling a series switch between the first RF source and the second RF source.

[0092] Example 21. An RF switching device according to Example 1, wherein the shunt switch includes a first plurality of stacked transistors, wherein the switching time acceleration circuit includes a second plurality of stacked transistors and a third plurality of stacked transistors, and wherein the second plurality of stacked transistors are physically close to the first plurality of stacked transistors and have the same grid configuration.

[0093] Example 22. An RF switch device according to any of the above examples, wherein the third plurality of stacked transistors are physically close to the first plurality of stacked transistors and have the same grid configuration.

[0094] Example 23. The RF switch device according to any of the above examples further includes a diode circuit coupled between the shunt switch and the series switch.

[0095] Example 24. An RF switching device according to any of the above examples, wherein the diode circuit includes a pair of anti-parallel diodes.

[0096] Example 25. An RF switching device according to any of the above examples, wherein the diode circuit further includes a bias voltage input.

[0097] Example 26. An RF switching device according to any of the above examples, wherein the diode circuit includes a PMOS transistor having a source coupled to the first diode and a gate coupled to the bias voltage input, and wherein the diode circuit includes an NMOS transistor having a source coupled to the second diode and a gate coupled to the bias voltage input.

[0098] Example 27. An RF switching device according to any of the above examples, wherein the diode circuit includes a pair of diode-connected transistors.

[0099] Example 28. An RF switching device according to any of the above examples, wherein the diode circuit includes: a first PMOS transistor; a first NMOS transistor; a second PMOS transistor and a second NMOS transistor coupled between the drain of the first PMOS transistor and a bias voltage input; and a third PMOS transistor and a third NMOS transistor coupled between the drain of the first NMOS transistor and the bias voltage input.

[0100] Example 29. An RF switching device according to any of the above examples, wherein the diode circuit includes: a first PMOS transistor coupled to a fourth NMOS transistor; a first NMOS transistor coupled to the fourth PMOS transistor; a second PMOS transistor and a second NMOS transistor coupled between the drain of the fourth NMOS transistor and a bias voltage input; a third PMOS transistor and a third NMOS transistor coupled between the drain of the fourth PMOS transistor and the bias voltage input.

[0101] Example 30. An RF switch device according to any of the above examples, wherein the first plurality of transistors includes a plurality of NMOS transistors, wherein the second plurality of transistors includes a plurality of PMOS transistors, and wherein the third plurality of transistors includes a plurality of NMOS transistors.

[0102] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art after reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An RF switch device, comprising: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, and a speed-up control input; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and a speed up control input; and A switch time acceleration circuit has a positive acceleration path input, a negative acceleration path input, and a first output coupled to the main control input of the series switch.

2. The RF switching device of claim 1, wherein the switching time acceleration circuit comprises a third switch coupled between the positive acceleration path input and the first output. 3 . The RF switch device of claim 2 , wherein the third switch comprises a plurality of stacked PMOS transistors.

4. The RF switching device of claim 2, wherein the switching time acceleration circuit includes a second output, the second output being coupled to the main control input of the series switch, and wherein the switching time acceleration circuit includes a fourth switch coupled between the negative acceleration path input and the second output. The RF switch device of claim 4 , wherein the fourth switch comprises a plurality of stacked NMOS transistors. 6 . The RF switch device of claim 4 , further comprising a diode circuit coupled to the third switch and the fourth switch.

7. An RF switch device, comprising: a shunt switch having a first RF terminal, a second RF terminal coupled to ground, a main control input, a main control output, a speed-up control input, and a speed-up control output; a series switch having a first RF terminal coupled to the first RF terminal of the shunt switch, a second RF terminal, a main control input, and a speed up control input; as well as A shunt series switch is coupled between the main control output of the shunt switch and the main control input of the series switch, and is coupled between the speed-up control output of the shunt switch and the speed-up control input of the series switch.

8. The RF switching device of claim 7, wherein the shunt series switch is configured to establish a conductive path during a switching transient and an off-state operating mode of the series switch, and is configured to interrupt the conductive path during an on-state operating mode of the series switch.

9. The RF switch device of claim 7, wherein the shunt series switch further comprises a shunt series control node.

10. The RF switch device of claim 7, wherein the shunt series switch comprises a first T-junction switch device and a second T-junction switch device. 11 . The RF switch device of claim 10 , wherein the first and second T-junction switch devices each include a first NMOS transistor and a second NMOS transistor coupled to a PMOS transistor. 12 . The RF switch device of claim 10 , wherein the first and second T-junction switch devices each include a first NMOS transmission gate and a second NMOS transmission gate coupled to a PMOS transmission gate.

13. A method of operating an RF switch device, wherein the RF switch device comprises a series switch, a shunt switch, and a shunt series switch, the series switch comprising a first switching time acceleration circuit, the shunt switch comprising a second switching time acceleration circuit, the shunt series switch being used to selectively couple the series switch to the shunt switch, the method comprising: establishing a conductive path during a switching transient and an off-state operating mode of the series switch; as well as The conductive path is interrupted during an on-state operating mode of the series switch.

14. The method of claim 13, further comprising interrogating the RF switching device to determine whether the series switch and the shunt switch are in the same state.

15. The method of claim 14, wherein if the series switch and the shunt switch are in the same state, the method further comprises: placing the shunt series switch in an on state; Switching the shunt switch and the series switch to a new state; placing the shunt series switch in an off state; as well as The shunt switch is placed in an initial state.

16. The method of claim 14, wherein if the series switch and the shunt switch are not in the same state, the method further comprises placing the shunt switch in the same state as the series switch.

17. The method according to claim 16, wherein the method further comprises: placing the shunt series switch in an on state; Switching the shunt switch and the series switch to a new state; as well as The shunt series switch is placed in an off state.

18. The method of claim 13, further comprising clamping at least one circuit node of the RF switching device to a first RF source.

19. The method of claim 13, further comprising coupling the shunt switch between a first RF source and ground.

20. The method of claim 13, further comprising coupling the series switch between a first RF source and a second RF source.

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