A broadband vector signal generator

Abstract

This application discloses a broadband vector signal generator, including a multi-channel phase-locked loop (PLL) module, a baseband processing module, and a radio frequency (RF) processing module. The generator performs PLL on a synchronization reference signal to obtain five clock signals; acquires waveform data; performs digital-to-analog conversion on the waveform data based on a first clock signal to obtain two baseband signals; divides a third clock signal to obtain a frequency-divided signal; uses a second clock signal or the frequency-divided signal as a quadrature modulation local oscillator signal to orthogonally modulate the two baseband signals to obtain a quadrature modulation signal; performs power control on the quadrature modulation signal to obtain a first RF signal, a first control signal, and a second control signal; uses a fourth clock signal as an up-converted local oscillator signal to up-convert the first control signal to obtain a second RF signal; and uses a fifth clock signal as a down-converted local oscillator signal to down-convert the second control signal to obtain a third RF signal. This broadband vector signal generator can achieve wide bandwidth and high linearity.

Description

Technical Field

[0001] This application belongs to the field of radio frequency circuit technology, and specifically relates to a broadband vector signal generator. Background Technology

[0002] Radio frequency vector signal generators are widely used test instruments that can generate any desired signal within a specified bandwidth and frequency range to provide specified excitation to the device under test. Therefore, they are widely used in the field of wireless communication testing and are important instruments and equipment used in the research and development and production of various wireless communication products, as well as in aerospace, broadband digital pre-distortion (DPD) verification, 6G prediction, and high-end scientific experiments.

[0003] Currently, some of the most common vector signal generators (such as the N5182B vector signal generator) are not suitable for the latest communication testing requirements. For example, 2-carrier or 3-carrier tests used in 5G NR co-construction and sharing require a bandwidth of 200MHz or 300MHz, which exceeds the 160MHz range of the N5182B. The 6GHz-7.125GHz frequency range planned for dedicated 5G also exceeds the maximum frequency range of the N5182B. The 320MHz bandwidth and 6GHz-7.125GHz frequency range specified by WiFi 7 exceed both the bandwidth and frequency range of the N5182.

[0004] Although some high-end products can cover the bandwidth required for multi-carrier output, the linearity drops sharply when multi-carrier output, some performance characteristics are close to or lower than 5G testing standards, and the frequency range of dedicated 5G planning exceeds its highest frequency range, making it difficult to meet actual testing needs. Summary of the Invention

[0005] The technical objective of this application is to provide a broadband vector signal generator that addresses the technical problems of limited frequency bandwidth and poor linearity of current radio frequency vector signal generators, which cannot meet the latest practical communication testing requirements.

[0006] To achieve the above technical objectives, this application provides a broadband vector signal generator, including: a phase-locked loop module for locking a synchronization reference signal to obtain a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal;

[0007] The baseband processing module is used to acquire waveform data and perform digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals.

[0008] The radio frequency processing module includes a quadrature modulation unit, a power control unit, a frequency divider, an up-conversion unit, and a down-conversion unit;

[0009] The frequency divider is used to divide the third clock signal to obtain a frequency-divided signal;

[0010] The quadrature modulation unit is used to use the second clock signal or the frequency division signal as the local oscillator signal for quadrature modulation to perform quadrature modulation on the two baseband signals to obtain a quadrature modulation signal;

[0011] The power control unit is used to perform power control on the quadrature modulation signal to obtain a first radio frequency signal, a first control signal, and a second control signal.

[0012] The upconversion unit is used to use the fourth clock signal as the local oscillator signal for upconversion, and to upconvert the first control signal to obtain the second radio frequency signal.

[0013] The downconversion unit is used to use the fifth clock signal as the local oscillator signal for downconversion, and to downconvert the second control signal to obtain the third radio frequency signal.

[0014] Furthermore, the multi-channel phase-locked module includes a first phase-locked unit, a second phase-locked unit, a fourth phase-locked unit, and a fifth phase-locked unit;

[0015] The first phase-locked unit is used to lock the synchronization reference signal into phase before power distribution, and outputs a first phase-locked signal, a second phase-locked signal and a third phase-locked signal;

[0016] The second phase-locked unit is used to perform phase-locking based on the first phase-locked signal to obtain the first clock signal;

[0017] The fourth phase-locked unit is used to perform phase-locking based on the second phase-locked signal to obtain the second clock signal, the third clock signal and the fourth clock signal;

[0018] The fifth phase-locked unit is used to perform phase-locking based on the third phase-locked signal to obtain the fifth clock signal.

[0019] In some possible implementations, the multi-channel phase-locked module further includes a third phase-locked unit;

[0020] The third phase-locked unit is used to phase-lock the second phase-locked signal to generate a point frequency signal, and send the point frequency signal to the fourth phase-locked unit;

[0021] The fourth phase-locked unit is also used to lock the frequency of the point frequency signal and output the second clock signal, the third clock signal and the fourth clock signal.

[0022] Furthermore, the fourth phase-locked unit includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch, and a second one-to-many switch connected in sequence. Multiple radio frequency channels are formed between the first one-to-many switch and the many-to-one switch, and each radio frequency channel is provided with a filter.

[0023] The output terminals of the fourth integrated phase-locked loop and the third phase-locked unit are connected;

[0024] The one or more switches are respectively connected to the quadrature modulation unit, the frequency divider and the upconversion unit, and are used to output the second clock signal, the third clock signal and the fourth clock signal.

[0025] Furthermore, the first clock signal includes a first clock sub-signal and a second clock sub-signal;

[0026] The baseband processing module includes a processor and a digital-to-analog converter, and the processor and the digital-to-analog converter are connected by a low-voltage differential signal bus;

[0027] The first clock sub-signal serves as the clock reference signal for the processor;

[0028] The second clock sub-signal serves as the clock reference signal for the digital-to-analog converter;

[0029] The processor is used to transmit the waveform data to the digital-to-analog converter;

[0030] The digital-to-analog converter is used to perform digital-to-analog conversion on the waveform data and output two baseband signals.

[0031] Furthermore, the baseband processing module also includes a USB interface and / or a network port, which are used to receive control commands issued by the host computer and transmit the control commands to the processor so that the processor can perform corresponding operations to obtain operation results and return the operation results to the host computer.

[0032] Furthermore, the second phase-locked unit includes a second integrated phase-locked loop and a clock distributor;

[0033] The second integrated phase-locked loop is used to lock the first phase-locked signal and generate a synchronization signal;

[0034] The clock distributor is used to generate the first clock sub-signal by dividing the frequency based on the synchronization signal, and to generate the second clock sub-signal based on the synchronization signal.

[0035] Furthermore, the multi-channel phase-locked module also includes:

[0036] Synchronization reference signal generation unit;

[0037] The synchronization reference signal generation unit includes a crystal oscillator, an external input channel, and a switch. The crystal oscillator and the external input channel are connected to one end of the switch. The crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs a selected synchronization reference signal.

[0038] Furthermore, the baseband processing module also includes:

[0039] Trigger unit;

[0040] When the trigger function is set to output mode, a trigger signal is output through the trigger unit whenever the looped waveform file moves from the end to the beginning; when the trigger function is set to input mode, the waveform file is played back once every time a trigger signal transmitted by the trigger unit is detected, wherein the waveform file stores the waveform data.

[0041] Furthermore, the triggering mode of the triggering function is either single triggering or continuous triggering.

[0042] Compared with the prior art, the broadband vector signal generator provided in this application has the following beneficial technical effects: by using a multi-channel phase-locked loop module to lock the synchronization reference signal into phase, multiple clock signals are obtained, which can be used for synchronization and frequency conversion processing, and can support flexible frequency conversion, thus generating wide-bandwidth radio frequency signals; the quadrature modulation unit, up-conversion unit and down-conversion unit use different clock signal sources, which helps to improve the stability and accuracy of the signal generated by each unit, and can achieve high linearity signal generation to a certain extent. Attached Figure Description

[0043] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings:

[0044] Figure 1 This is a schematic diagram of the structure of a broadband vector signal generator provided in an embodiment of this application;

[0045] Figure 2 This is a partial structural diagram of the baseband processing module in the broadband vector signal generator provided in the embodiments of this application;

[0046] Figure 3 This is a schematic diagram of the data flow of the external communication interface in the broadband vector signal generator provided in the embodiments of this application;

[0047] Figure 4 This is a schematic diagram of the USB interface circuit in a broadband vector signal generator provided in an embodiment of this application.

[0048] Figure 5 This is a schematic diagram of the LAN interface circuit in a broadband vector signal generator provided in an embodiment of this application.

[0049] Figure 6 A schematic diagram of the data stream for high-speed playback in the baseband processing module of the broadband vector signal generator provided in this embodiment of the application;

[0050] Figure 7 A schematic diagram of the digital-to-analog converter circuit in the broadband vector signal generator provided in this application embodiment;

[0051] Figure 8 This is a schematic diagram of the memory circuit in a broadband vector signal generator provided in an embodiment of this application;

[0052] Figure 9 A schematic diagram of the synchronization reference signal generation unit in a broadband vector signal generator provided in this application embodiment;

[0053] Figure 10 A schematic diagram of the first phase-locked unit in the broadband vector signal generator provided in the embodiments of this application;

[0054] Figure 11 A schematic diagram of the second phase-locked unit in a broadband vector signal generator provided in this application embodiment;

[0055] Figure 12 A schematic diagram of the fourth phase-locked unit in the broadband vector signal generator provided in the embodiments of this application;

[0056] Figure 13 This is a schematic diagram of the power control unit in a broadband vector signal generator provided in an embodiment of this application;

[0057] Figure label:

[0058] 10-Multi-channel phase-locked loop module, 20-Baseband processing module, 30-RF processing module, 101-First phase-locked loop unit, 102-Second phase-locked loop unit, 103-Third phase-locked loop unit, 104-Fourth phase-locked loop unit, 105-Fifth phase-locked loop unit, 106-Synchronization reference signal generation unit, 201-FPGA, 202-Digital-to-analog converter, 203-USB interface, 204-Memory, 205-Non-volatile memory unit, 206-Processing unit, 207-Ethernet port, 208-Trigger unit, 301-Quadrature modulation unit, 302-Power control unit, 303-Frequency divider, 304-Up-conversion unit, 305-Down-conversion unit, 306-First filter unit, 307-Second filter unit. Detailed Implementation

[0059] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0060] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0061] like Figure 1 As shown in the figure, this application provides a broadband vector signal generator, including a multi-channel phase-locked module 10, a baseband processing module 20, and a radio frequency processing module 30.

[0062] In specific implementation, the multi-channel phase-locked loop module 10 is used to phase-lock the synchronization reference signal to obtain a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal. The baseband processing module 20 is used to acquire waveform data and perform digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals. The radio frequency processing module 30 includes a quadrature modulation unit 301, a power control unit 302, a frequency divider 303, an up-conversion unit 304, and a down-conversion unit 305. Frequency divider 303 is used to divide the third clock signal to obtain a divided signal; quadrature modulation unit 301 is used to use the second clock signal or the divided signal as the local oscillator signal for quadrature modulation, and to perform quadrature modulation on the two baseband signals to obtain a quadrature modulation signal; power control unit 302 is used to perform power control on the quadrature modulation signal to obtain a first radio frequency signal, a first control signal, and a second control signal; upconversion unit 304 is used to use the fourth clock signal as the local oscillator signal for upconversion, and to perform upconversion on the first control signal to obtain a second radio frequency signal; downconversion unit 305 is used to use the fifth clock signal as the local oscillator signal for downconversion, and to perform downconversion on the second control signal to obtain a third radio frequency signal.

[0063] The broadband vector signal generator provided in this application has a processor at its core in the high-speed digital section. The processor can be a Field-Programmable Gate Array (FPGA201), such as... Figure 1 and Figure 2As shown, the high-speed digital section can also include external communication interfaces such as USB interface 203 and network port 207, non-volatile memory unit 205, memory 204, digital-to-analog converter 202, etc.; while the radio frequency section includes multiple phase-locked loop, quadrature modulation, secondary frequency conversion, power control and filtering units, etc.; the system block diagram of the broadband vector signal generator in the embodiment is as follows. Figure 1 As shown.

[0064] like Figure 1 As shown, in this embodiment, memory 204 can be used to store waveform data that needs to be played back because memory 204 has a high speed and large bandwidth; it can be used for temporary storage required during waveform playback; the data in memory 204 will be lost after power failure.

[0065] In this embodiment, the most commonly used USB interface 203 and network port 207 can be used as external control interfaces to receive waveform data and control commands issued by the host computer and return the device status; this is the main way for the broadband vector signal generator to communicate with the host computer, and it is also an interface necessary for automatic testing.

[0066] In practical implementation, non-volatile storage unit 205 can be used to store waveform data sent by the user for repeated use. The data in non-volatile storage unit 205 will not be lost after power failure. The waveform data sent by the user is stored in the memory in the form of a file (waveform file) according to the specified format, with the file name and basic information added. When needed later, it is not necessary to send waveform data from the host computer again, but it can be directly retrieved from non-volatile storage unit 205. At the same time, the configuration information of the broadband vector signal generator (hereinafter referred to as the device) can also be stored in non-volatile storage unit 205. The non-volatile storage unit 205 can be in the form of an SD / TF card or a hard drive.

[0067] In this embodiment, Secure Digital Input and Output (SDIO) can be used to read and write SD / TF cards, its main feature being high read and write speeds. Through the high-speed port of the FPGA201 and related IP, SATA bus read and write to SSD hard drives can be implemented. SSD hard drives have larger capacities and faster read and write speeds, but they are more expensive, consume more power, and are larger in size.

[0068] The FPGA 201 is used to support the communication protocol with the USB interface 203 and the network port 207 to facilitate communication with the host computer; it enables reading and writing of the non-volatile memory unit 205 to store waveform files and configuration information; it operates the memory 204 to read and write to store waveform file data in the memory 204, and reads it at high speed during playback and transmits it to the digital-to-analog converter 202; it implements the trigger function; and it interacts with the processing unit 206 to transmit various commands and execute corresponding operations.

[0069] The baseband processing module 20 may also include a processing unit 206, which is mainly responsible for parsing the control commands sent by the host computer, executing the corresponding operations according to the commands, and returning the results. The processing unit 206 can be an MCU; its main task is to parse various instructions sent by the host computer, execute them, and return the status results. The FPGA 201 and the processing unit 206 can generally interact through a set of I / O. The control and configuration of other controlled devices such as phase-locked loops and switches are also controlled by the processing unit 206 through SPI, I2C, I / O, etc.

[0070] The digital-to-analog converter 202 converts waveform data into analog signals, which serve as the baseband input for quadrature modulation. To achieve quadrature modulation, the digital-to-analog converter 202 has two independent output channels.

[0071] In some embodiments, the baseband processing module 20 further includes a trigger unit 208, which can be set to an input mode or an output mode. When the trigger function is set to the output mode, a trigger signal is output by the trigger unit 208 whenever the looped waveform file moves from the end to the beginning, so that other test instruments (such as a spectrum analyzer) can track it. When the trigger function is set to the input mode, the waveform file is played back once every time a trigger signal transmitted by the trigger unit 208 is detected.

[0072] In this embodiment, the triggering function is implemented by the logic of FPGA201. When set to output mode, FPGA201 pulls up a narrow pulse on the trigger I / O pin whenever the waveform is played back to the end and starts again from the beginning; when set to input mode, FPGA201 plays back the waveform file from the beginning every time it receives a narrow pulse. In a specific embodiment, the triggering mode of the triggering function is either single triggering or continuous triggering. This application implements different triggering functions through FPGA201 logic programming.

[0073] The embodiment realizes the interaction between FPGA201 and external interfaces, the interaction with processing unit 206, the triggering function, the reading and writing of non-volatile memory unit 205 and high-speed playback, and the interaction with host computer.

[0074] The data sent from the host computer can be either waveform files or control commands; the data links for the two differ, such as... Figure 3As shown, waveform data sent from the host computer can be permanently stored in the SD / TF non-volatile storage unit 205, or directly written to the memory 204 for later playback. In some embodiments, control commands sent from the host computer are forwarded by the FPGA 201 to the processing unit 206 for command parsing, execution of corresponding operations, and return of status results. For waveform files already stored in the non-volatile storage unit 205, the FPGA 201 can also read the required data from the non-volatile storage unit 205 and write it to the memory 204 for later playback by issuing commands.

[0075] The USB interface 203 can be implemented using a USB interface 203 chip, which converts the USB interface 203 into local I / O before interacting with the FPGA 201. In some embodiments, the USB uses a USB 3.0 interface chip, model FT601, which is compatible with USB 2.0; it converts the USB interface 203 into local I / O before data interaction with the FPGA 201. Related circuitry is as follows... Figure 4 As shown.

[0076] To achieve gigabit LAN port 207 and improve data read / write speeds, some implementations use MicroChip's KSZ9031RNX chip for port 207, converting gigabit Ethernet into local high-speed I / O for easy data interaction with FPGA201. For compatibility with Visa32 and IEEE488.2 protocols, port 207 can be configured as a TCP server, allowing users to control vector signal generators via virtual instrument programming for automated testing. The LAN interface circuit is as follows... Figure 5 As shown.

[0077] In this embodiment, the broadband vector signal generator also includes a power management unit (not shown in the figure), which is a series of power supply systems that provide the necessary power to each device.

[0078] Please continue reading Figure 1 In some embodiments, the multiplex phase-locked module 10 includes a first phase-locked unit 101, a second phase-locked unit 102, a fourth phase-locked unit 104, and a fifth phase-locked unit 105.

[0079] The first phase-locked unit 101 is used to phase-lock the synchronization reference signal before power distribution, and outputs a first phase-locked signal, a second phase-locked signal, and a third phase-locked signal. The second phase-locked unit 102 is used to phase-lock based on the first phase-locked signal to obtain a first clock signal. The fourth phase-locked unit 104 is used to phase-lock based on the second phase-locked signal to obtain a second clock signal, a third clock signal, and a fourth clock signal. The fifth phase-locked unit 105 is used to phase-lock based on the third phase-locked signal to obtain a fifth clock signal.

[0080] The fourth phase-locked unit 104 typically employs a fractional-order frequency division method, which can introduce integer boundary spurious signals. To achieve optimal EVM (Error Vector Magnitude), ACP (Adjacent Channel Power), and spurious performance, the output of the fourth phase-locked unit 104 must effectively suppress boundary spurious signals. Therefore, in some embodiments, the multiplexed phase-locked module 10 further includes a third phase-locked unit 103. The third phase-locked unit 103 is used to phase-lock the second phase-locked signal to generate a point-frequency signal, and then sends the point-frequency signal to the fourth phase-locked unit 104. The fourth phase-locked unit 104 is also used to lock the point-frequency signal, outputting a second clock signal, a third clock signal, and a fourth clock signal.

[0081] A frequency signal is dynamically generated by the third phase-locked unit 103 to provide input to the fourth phase-locked unit 104. As an example, the third phase-locked unit 103 is an integrated phase-locked loop (third phase-locked loop, not shown in the figure). It uses one signal from the first phase-locked unit 101 as input and locks it, dynamically outputting a point-frequency signal as input to the fourth phase-locked unit 104. By employing a variable reference frequency operating mode, the output frequency of the third phase-locked unit 103 is dynamically adjusted so that the boundary spurious frequencies generated by the fourth phase-locked unit 104 during fractional frequency division are further away from integer multiples of the phase detection frequency. This allows them to be effectively suppressed by the phase-locked loop filter, thereby effectively suppressing spurious signals.

[0082] In this embodiment, the first phase-locked unit 101 is used to lock the frequency of the synchronization reference signal to generate an ultra-low phase noise reference signal, which is divided into three paths to provide input for the subsequent second phase-locked unit 102, third phase-locked unit 103 and fifth phase-locked unit 105.

[0083] A synchronization reference signal can be used to synchronize the frequencies of different electronic devices to avoid frequency discrepancies. This application achieves frequency synchronization through phase-locked loop (PLL) technology. It can use either an externally input synchronization reference signal or an internal synchronization reference signal, with the choice between the two controlled by a single-pole double-throw (SPDT) switch, whose state can be controlled by commands from a host computer. The internal 10MHz signal can be equipped with either a temperature-compensated crystal oscillator (TCC) or a oven-controlled crystal oscillator (OCC) to obtain a stable, low-phase-noise output. Using an OCC offers higher frequency stability and lower phase noise, but it occupies a larger size and consumes more power. A TCC provides better frequency stability and lower phase noise, while being smaller and consuming less power. Through the switch selection, users can flexibly switch the source of the synchronization reference signal to adapt to different application scenarios and requirements.

[0084] The switching structure of the synchronization signal in the embodiment is as follows: Figure 9As shown, the multi-channel phase-locked module 10 also includes a synchronization reference signal generation unit 106; the synchronization reference signal generation unit 106 includes a crystal oscillator, an external input channel and a switch, the output terminal of the crystal oscillator and the output terminal of the external input channel are connected to one end of the switch, the crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs the selected synchronization reference signal.

[0085] In some embodiments, the first phase-locked unit 101 may consist of a phase-locked loop and a power divider. The phase-locked loop uses a voltage-controlled crystal oscillator to ensure phase noise levels and locks the synchronization signal through the phase-locked loop chip to eliminate frequency differences. The power divider further splits the phase-locked output into three paths for use by subsequent circuits. The output frequency of the first phase-locked unit 101 can be fixed. In a specific implementation, a 100MHz low-phase-noise voltage-controlled crystal oscillator can be used, with 10MHz as the synchronization reference signal. After being locked by the first integrated phase-locked loop (not shown in the figure), power distribution is performed for output. The functional block diagram is as follows: Figure 10 As shown.

[0086] In some embodiments, the second phase-locked unit 102 locks the signal frequency of the first phase-locked unit 101 and outputs two frequency signals, one of which is provided to the digital-to-analog converter 202 as a clock input, and the other is provided to the processor (such as FPGA 201) as a reference frequency.

[0087] As an example, such as Figure 11 As shown, the second phase-locked unit 102 can consist of an integrated phase-locked loop (second integrated phase-locked loop, not shown in the figure) and a clock distributor. Using one signal (first phase-locked signal) from the first phase-locked unit 101 as input, a low-phase-noise signal output with a maximum frequency of 1.25 GHz is generated after locking. The clock distributor has two outputs: one transmits the highest 1.25 GHz signal (second clock sub-signal) to the digital-to-analog converter 202 as a clock, and the other signal, after frequency division (generating the first clock sub-signal), is provided to the FPGA 201.

[0088] High-speed playback refers to outputting waveform data stored in memory 204 as an analog signal via digital-to-analog converter 202. This output signal is also called the baseband signal. To obtain optimal bandwidth, in some embodiments, a low-voltage differential signal bus is used to connect the processor (FPGA 201) and the digital-to-analog converter 202 (high-speed digital-to-analog converter 202). The first clock sub-signal and the second clock sub-signal enable the low-voltage differential signal (LVDS) frequency between the FPGA 201 and the digital-to-analog converter 202 to be synchronized with the clock frequency of the digital-to-analog converter 202, ensuring stable output from the digital-to-analog converter 202 and avoiding anomalies caused by data discontinuity. The output frequency of the second phase-locked loop unit 102 varies according to the sample rate set for the actual high-speed playback.

[0089] In this embodiment, Texas Instruments' DAC3482 can be used as a high-speed digital-to-analog converter 202. It is a dual-channel 16-bit converter using LVDS bus and DDR transmission. The LVDS bus switching frequency of a typical FPGA201 is approximately 1.25 GHz; the LVDS interface-based digital-to-analog converter 202 is usually a parallel data interface, therefore its maximum data transfer rate is 1.25 GSPS. Using DDR transmission, data from both converters is transmitted via the same LVDS bus, allowing the system to provide a maximum data rate of 1.25G / 2 = 625 MSPS, corresponding to a maximum modulation bandwidth of 625M × 0.8 = 500MHz. Common 5G NR multi-carrier tests typically use two or three carriers. Taking three carriers as an example, the actual bandwidth used is 100MHz × 3 = 300MHz; the maximum bandwidth specified for WiFi 7 is 320MHz, so a modulation bandwidth of 500MHz is sufficient.

[0090] To achieve high-speed playback, the FPGA201 needs to stably supply 1.25G × 16 = 20Gbit / s of data to the digital-to-analog converter 202. This exceeds the speed achievable by typical external interfaces such as the USB interface 203 and the Ethernet port 207. Therefore, the design uses DDR memory 204 to store the waveforms to be played back. Relying on the ultra-high read capability of memory 204, the FPGA201 reads the data from memory 204 into its buffer, and then the buffer is passed to the digital-to-analog converter 202 to achieve high-speed playback and obtain a 500MHz bandwidth and high linearity baseband signal. Figure 6 This process is shown.

[0091] The DAC3482 digital-to-analog converter 202 features a digital quadrature modulator correction function, which allows direct adjustment of the difference between the two converters by writing to registers to correct quadrature modulation and achieve optimal sideband suppression and local oscillator suppression.

[0092] The relevant circuitry of the digital-to-analog converter 202 used in this embodiment is as follows: Figure 7 As shown; the circuit diagram for memory 204 is as follows. Figure 8 As shown.

[0093] In this embodiment, the fourth phase-locked unit 104 locks the signal frequency of the third phase-locked unit 103 and generates signals of corresponding frequencies (second clock signal, third clock signal and fourth clock signal) according to user settings. These signals can be used as the local oscillator of the quadrature modulation unit 301, the input of the frequency divider 303 or the local oscillator signal of the up-conversion unit 304.

[0094] As an example, the fourth phase-locked unit 104 consists of an integrated phase-locked loop (fourth integrated phase-locked loop, not shown in the figure), a series of filter banks, and RF switches. The fourth integrated phase-locked loop takes the output signal of the third phase-locked unit 103 as its input and locks onto it; the output of the fourth phase-locked unit 104 can be used as the local oscillator input of the quadrature modulation unit 301, the input of the frequency divider 303, or the local oscillator input of the up-conversion unit 304.

[0095] The fourth phase-locked unit 104 generally has a wide frequency coverage. Some embodiments use a set of filters after the phase-locked output to effectively suppress harmonics and achieve multiplexed output through an RF switch. Its block diagram is shown below. Figure 12 As shown.

[0096] like Figure 12As shown, the fourth phase-locked unit 104 includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch, and a second one-to-many switch connected in sequence. Multiple radio frequency (RF) channels are formed between the first one-to-many switch and the many-to-one switch, and each RF channel is equipped with a filter. The output terminals of the fourth integrated phase-locked loop and the third phase-locked unit 103 are connected. The one-to-many switch is respectively connected to the quadrature modulation unit 301, the up-conversion unit 304, and the down-conversion unit 305, for outputting a second clock signal, a third clock signal, and a fourth clock signal. Through the integrated phase-locked loop (PLL) and subsequent switch design, the fourth phase-locked unit 104 can simultaneously generate and distribute multiple clock signals. This design improves the flexibility and availability of clock signals, allowing different modules (such as the quadrature modulation unit 301, the frequency divider 303, and the up-conversion unit 304) to select and use appropriate clock signals as needed. Furthermore, the filters on the multiple RF channels help filter the clock signals passing through these channels to remove unwanted frequency components or noise, maintaining the purity and stability of the RF signal, thereby improving the performance of the entire vector signal generator.

[0097] In some embodiments, the fifth phase-locked unit 105 locks the frequency of the third phase-locked signal output by the first phase-locked unit 101 to generate a fixed-frequency local oscillator signal (the fifth clock signal), which serves as the local oscillator input of the down-conversion unit 305. As an example, the fifth phase-locked unit 105 is an integrated phase-locked loop (the fifth integrated phase-locked loop, not shown in the figure), which uses one signal (the third phase-locked signal) from the first phase-locked unit 101 as its input and locks it; it outputs a fixed-frequency signal (the fifth clock signal) as the local oscillator input of the down-conversion unit 305.

[0098] The quadrature modulation unit 301 modulates the baseband signal onto the radio frequency. The baseband signal of the quadrature modulation unit 301 comes from the digital-to-analog converter 202, and the local oscillator signal of the quadrature modulation unit 301 can come from the fourth phase-locked loop unit 104 or the frequency divider 303.

[0099] In specific implementation, the quadrature modulation unit 301 is a quadrature modulator, which can specifically adopt zero-IF modulation. Fine-tuning is performed by adjusting the amplitude, phase difference, and DC bias difference between the outputs of the two digital-to-analog converters 202 to obtain optimal sideband suppression and local oscillator suppression performance. When the output of the fourth phase-locked loop unit 104 is used as the local oscillator, the frequency coverage within the frequency range of the fourth phase-locked loop unit 104 can be achieved. A suitable combination of phase-locked loop devices and quadrature modulators must be selected to obtain optimal characteristics. In some embodiments, the 0.4-6 GHz frequency band is selected as the frequency band for the quadrature modulation output, thus achieving a frequency coverage up to 6 GHz.

[0100] In this embodiment, the power control unit 302 is used to adjust the power of the quadrature modulation signal. As an example, the power control unit 302 includes two cascaded amplifiers and two variable attenuators. The amplifiers typically have a gain of 20dB; the attenuators are voltage-controlled attenuators, each with a power adjustment range of 25dB, resulting in a total range of 50dB for the two cascaded attenuators. By using the output voltage of a 14-bit digital-to-analog converter 202 and adjusting the voltage-controlled attenuators, extremely fine power steps can be achieved, such as... Figure 13 As shown.

[0101] For signals in the higher frequency range (e.g., 6GHz-8GHz), this application employs up-conversion. The signal obtained through quadrature modulation and power control (the first control signal) serves as the input to the up-conversion unit 304, and the output signal of the fourth phase-locked loop unit 104 (the fourth clock signal) serves as the local oscillator for up-conversion. The output signal can be filtered by the first filter unit 306 to output the second radio frequency signal. In the embodiments, when using up-conversion, interference signals such as local oscillator leakage, image, and harmonics may be generated. In specific implementations, the up-conversion unit 304 is connected to the first filter unit 306, which is used to suppress these interference signals. The first filter unit 306 can be a set of bandpass filters, whose passband covers the frequency range of 6-8GHz.

[0102] In some embodiments, up-conversion is used when the practical frequency range is higher than that of the fourth phase-locked unit 104 and the quadrature modulation frequency range. In one embodiment, an up-conversion mixer is used to implement the up-conversion unit 304. The output signal (first control signal) of the power control unit 302 is used as the input of the up-conversion unit 304, and one output signal (fourth clock signal) of the fourth phase-locked unit 104 is used as the local oscillator for up-conversion. In another embodiment, the frequency divider 303 can use a two-way divider to take the 4-5.33GHz frequency band of the fourth phase-locked unit 104, and after division, obtain a 2-2.66GHz signal as the local oscillator for quadrature modulation. This 2-2.66GHz quadrature modulation signal is then used as the input of the up-conversion mixer. The direct output of the fourth phase-locked unit 104 is used as the local oscillator of the up-conversion mixer, thus covering a frequency range of 6-8GHz.

[0103] For signals with lower frequencies (frequency range less than 0.4 GHz), this application employs down-conversion. The signal obtained through quadrature modulation and power control (the second control signal) serves as the input to the down-conversion unit 305, and the output signal of the fifth phase-locked loop unit 105 (the fifth clock signal) serves as the local oscillator for down-conversion; the output signal can be filtered by the second filter unit 307 to output the third radio frequency signal.

[0104] In a specific embodiment, when the practical frequency range is lower than the frequency range of the fourth phase-locked unit 104 and the quadrature modulation, down-conversion is required. The down-conversion unit 305 can be implemented using a down-conversion mixer, with the output signal (second control signal) of the power control unit 302 as the input to the down-conversion unit 305, and the fifth phase-locked unit 105 as the local oscillator for down-conversion. Using a high local oscillator mode, the frequency range below 0.4 GHz is covered after conversion, and then a low-pass filter (second filter unit 307) is used to filter out noise. When using down-conversion, its output generally contains local oscillator leakage, harmonics, and other signals; to obtain a cleaner output, the second filter unit 307 can be used to improve local oscillator leakage and harmonic performance. The second filter unit 307 can be a fixed low-pass filter.

[0105] The broadband vector signal generator provided in this application embodiment can achieve excellent performance in key indicators, and is especially suitable for demanding testing needs such as multi-carrier 5G testing and WiFi 7 testing. For dedicated 5G in the 6.0-7.125GHz range, it can also provide an ACP characteristic of 60dBc (the higher the frequency, the lower the ACP).

[0106] The measured performance indicators of the broadband vector signal generator provided in the embodiment are as follows:

[0107] Frequency: Up to 8GHz

[0108] Bandwidth: Maximum 500MHz

[0109] Power step: 0.02dB

[0110] N78 band single-carrier 5G NRTM31a EVM: 0.50%

[0111] N78 band 3-carrier 5G NR TM31a EVM: 0.65%

[0112] N78 band single-carrier 5G NR TM31a ACP (ACPR / ACLR): 62dBc / 64dBc

[0113] N78 band 3-carrier 5G NR TM31a ACP (ACPR / ACLR): 53dBc / 55dBc

[0114] 7.1GHz band single-carrier 5G NR TM31a ACP (ACPR / ACLR): 60dBc / 62dBc

[0115] Stray noise: -80dBc

[0116] Local oscillator leakage: -70dBc

[0117] Image suppression: -70dBc

[0118] Harmonics: Better than -35dBc;

[0119] Among them, ACPR (Adjacent Channel Power Ratio) is the power ratio of adjacent channels; ACLR (Adjacent Channel Leakage Ratio) is the leakage ratio of adjacent channels.

[0120] This broadband vector signal generator offers excellent performance at a competitive price and features high broadband linearity.

[0121] The broadband vector signal generator provided in this application has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this application. The description of the above embodiments is only for the purpose of helping to understand the concept of this application and should not be construed as a limitation on the scope of protection of this application.

Claims

1. A broadband vector signal generator, characterized in that, include: The multi-channel phase-locked loop module is used to lock the synchronization reference signal into a phase to obtain a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal; The baseband processing module is used to acquire waveform data and perform digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals. The radio frequency processing module includes a quadrature modulation unit, a power control unit, a frequency divider, an up-conversion unit, and a down-conversion unit; The frequency divider is used to divide the third clock signal to obtain a frequency-divided signal; The quadrature modulation unit is used to use the second clock signal or the frequency division signal as the local oscillator signal for quadrature modulation to perform quadrature modulation on the two baseband signals to obtain a quadrature modulation signal; The power control unit is used to perform power control on the quadrature modulation signal to obtain a first radio frequency signal, a first control signal, and a second control signal. The upconversion unit is used to use the fourth clock signal as the local oscillator signal for upconversion, and to upconvert the first control signal to obtain the second radio frequency signal. The downconversion unit is used to use the fifth clock signal as the local oscillator signal for downconversion, and to downconvert the second control signal to obtain the third radio frequency signal.

2. The broadband vector signal generator according to claim 1, characterized in that, The multi-channel phase-locked module includes a first phase-locked unit, a second phase-locked unit, a fourth phase-locked unit, and a fifth phase-locked unit; The first phase-locked unit is used to lock the synchronization reference signal into phase before power distribution, and outputs a first phase-locked signal, a second phase-locked signal and a third phase-locked signal; The second phase-locked unit is used to perform phase-locking based on the first phase-locked signal to obtain the first clock signal; The fourth phase-locked unit is used to perform phase-locking based on the second phase-locked signal to obtain the second clock signal, the third clock signal and the fourth clock signal; The fifth phase-locked unit is used to perform phase-locking based on the third phase-locked signal to obtain the fifth clock signal.

3. The broadband vector signal generator according to claim 2, characterized in that, The multi-channel phase-locked module also includes a third phase-locked unit; The third phase-locked unit is used to phase-lock the second phase-locked signal to generate a point frequency signal, and send the point frequency signal to the fourth phase-locked unit; The fourth phase-locked unit is also used to lock the frequency of the point frequency signal and output the second clock signal, the third clock signal and the fourth clock signal.

4. The broadband vector signal generator according to claim 3, characterized in that, The fourth phase-locked unit includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch, and a second one-to-many switch connected in sequence. Multiple radio frequency channels are formed between the first one-to-many switch and the many-to-one switch, and each radio frequency channel is provided with a filter. The output terminals of the fourth integrated phase-locked loop and the third phase-locked unit are connected; The one or more switches are respectively connected to the quadrature modulation unit, the frequency divider and the upconversion unit, and are used to output the second clock signal, the third clock signal and the fourth clock signal.

5. The broadband vector signal generator according to claim 2, characterized in that, The first clock signal includes a first clock sub-signal and a second clock sub-signal; The baseband processing module includes a processor and a digital-to-analog converter, and the processor and the digital-to-analog converter are connected by a low-voltage differential signal bus; The first clock sub-signal serves as the clock reference signal for the processor; The second clock sub-signal serves as the clock reference signal for the digital-to-analog converter; The processor is used to transmit the waveform data to the digital-to-analog converter; The digital-to-analog converter is used to perform digital-to-analog conversion on the waveform data and output two baseband signals.

6. The broadband vector signal generator according to claim 5, characterized in that, The baseband processing module further includes a USB interface and / or a network port, which are used to receive control commands issued by the host computer and transmit the control commands to the processor so that the processor can perform corresponding operations to obtain operation results and return the operation results to the host computer.

7. The broadband vector signal generator according to claim 5, characterized in that, The second phase-locked unit includes a second integrated phase-locked loop and a clock distributor; The second integrated phase-locked loop is used to lock the first phase-locked signal and generate a synchronization signal; The clock distributor is used to generate the first clock sub-signal by dividing the frequency based on the synchronization signal, and to generate the second clock sub-signal based on the synchronization signal.

8. The broadband vector signal generator according to claim 1, characterized in that, The multi-channel phase-locked module also includes: Synchronization reference signal generation unit; The synchronization reference signal generation unit includes a crystal oscillator, an external input channel, and a switch. The crystal oscillator and the external input channel are connected to one end of the switch. The crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs a selected synchronization reference signal.

9. The broadband vector signal generator according to claim 1, characterized in that, The baseband processing module further includes: Trigger unit; When the trigger function is set to output mode, a trigger signal is output through the trigger unit whenever the looped waveform file moves from the end to the beginning; when the trigger function is set to input mode, the waveform file is played back once every time a trigger signal transmitted by the trigger unit is detected, wherein the waveform file stores the waveform data.

10. The broadband vector signal generator according to claim 9, characterized in that, The triggering mode of the triggering function is either single triggering or continuous triggering.

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