A system, method, storage medium, and electronic device for data transmission

Abstract

This specification discloses a system, method, storage medium, and electronic device for data transmission, comprising: an interconnect endpoint determining a data packet to be transmitted; determining a virtual MAC address corresponding to the target interconnect endpoint based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and using this virtual MAC address as the target MAC address; and sending the data packet to be transmitted and the target MAC address to an interconnect switching node. The interconnect switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnect endpoint based on the target MAC address. This reduces network configuration complexity and transmission latency, saves cache space, reduces storage and hardware costs, and reduces network overhead. Furthermore, the above data transmission process is simple and standardized, does not require any dedicated drivers or operating system support, and is easy for various network devices to implement data transmission, improving the compatibility and interoperability of network devices.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a system, method, storage medium, and electronic device for data transmission. Background Technology

[0002] With the continuous development of technology, large-scale models are being used more and more widely.

[0003] Since tasks such as training large models and performing computational tasks related to large models typically involve a large amount of computation and data processing, the servers performing these tasks have high requirements. However, traditional servers that rely solely on the Central Processing Unit (CPU) to execute tasks are no longer sufficient. Instead, Graphics Processing Units (GPUs) can provide parallel computing capabilities, thus enabling the use of GPU servers—servers equipped with high-performance GPUs—to perform these tasks.

[0004] To fully utilize the computing efficiency of GPUs, multiple GPU servers can be interconnected, transferring data between them to collaboratively execute tasks. Therefore, how to perform data transfer between interconnected GPU servers is a crucial issue.

[0005] Based on this, this specification provides a data transmission system. Summary of the Invention

[0006] This specification provides a system, method, storage medium, and electronic device for data transmission to partially solve the aforementioned problems existing in the prior art.

[0007] The following technical solution is adopted in this specification:

[0008] This specification provides a data transmission system comprising interconnect switching nodes and a plurality of interconnect endpoints. Each interconnect endpoint is pre-configured with a virtual Media Access Control (MAC) address, which is configured based on a shared video memory space constructed from the video memory of the interconnect endpoints. The interconnect switching nodes are nodes that only provide Layer 2 Ethernet switching functionality, and the interconnect endpoints are GPU servers; wherein:

[0009] The interconnect endpoint is used to determine the data packet to be transmitted; based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, the virtual MAC address corresponding to the target interconnect endpoint is determined and used as the target MAC address; the data packet to be transmitted and the target MAC address are sent to the interconnect switching node;

[0010] The interconnection switching node is used to receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0011] Optionally, the interconnect endpoint is specifically used to determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted; calculate the virtual MAC address corresponding to the video memory address using a pre-set calculation rule, and use it as the target MAC address of the target interconnect endpoint.

[0012] Optionally, the data packet to be transmitted is a data packet generated by the transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet (TLP).

[0013] Specifically, the interconnection endpoint is used to encapsulate the data packet to be transmitted and the target MAC address using tunneling technology, determine the target data packet of a specified type, and send the target data packet to the interconnection switching node.

[0014] Optionally, before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, the interconnection endpoint is further configured to determine a first credit value corresponding to the target interconnection endpoint at the current time; when the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

[0015] This specification provides a method for data transmission applied to interconnect endpoints in a data transmission system. The data transmission system includes interconnect switching nodes and several interconnect endpoints. Each interconnect endpoint is pre-configured with a virtual Media Access Control (MAC) address, which is configured based on a shared video memory space constructed from the video memory of each interconnect endpoint. The switching node is a node that only provides Layer 2 Ethernet switching functionality, and the interconnect endpoints are GPU servers. The method includes:

[0016] Identify the data packet to be transmitted;

[0017] Based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to the target interconnect endpoint, and use it as the target MAC address;

[0018] The data packet to be transmitted and the target MAC address are sent to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0019] Optionally, based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, the virtual MAC address corresponding to the target interconnect endpoint is determined and used as the target MAC address, specifically including:

[0020] Determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted;

[0021] Using pre-set calculation rules, the virtual MAC address corresponding to the video memory address is calculated and used as the target MAC address of the target interconnect endpoint.

[0022] Optionally, the data packet to be transmitted is a data packet generated by the transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet (TLP).

[0023] Sending the data packet to be transmitted and the target MAC address to the interconnection switching node specifically includes:

[0024] Using tunneling technology, the data packet to be transmitted and the target MAC address are encapsulated to determine the target data packet of a specified type;

[0025] The target data packet is sent to the interconnection switching node.

[0026] Optionally, the method further includes:

[0027] Before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, determine the first credit value corresponding to the target interconnection endpoint at the current moment;

[0028] When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

[0029] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned method for data transmission.

[0030] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the aforementioned method for data transmission.

[0031] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects:

[0032] The data transmission system provided in this specification allows an interconnect endpoint to determine a data packet to be transmitted. Based on the video memory address corresponding to the target interconnect endpoint contained in the data packet, the endpoint determines the virtual MAC address corresponding to the target interconnect endpoint and uses this virtual MAC address as the target MAC address. The data packet and the target MAC address are then sent to the interconnect switching node. The interconnect switching node can then receive the data packet and the target MAC address and, based on the target MAC address, send the data packet to the target interconnect endpoint.

[0033] As can be seen from the above method, when transmitting data in this application, the interconnect endpoint can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnect endpoint based on the video memory address of the target interconnect endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The data packet to be transmitted and the target MAC address are then sent to the interconnect switching node. The interconnect switching node can then receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnect endpoint based on the target MAC address. By first determining the data packet to be transmitted, then determining the target MAC address of the target interconnect endpoint based on the video memory address of the target interconnect endpoint in the shared video memory space, and then sending the data packet to be transmitted and the target MAC address to the interconnect switching node, the interconnect endpoint eliminates the steps of establishing a connection with the CPU and asynchronous communication, avoiding the impact of the CPU on the performance of data transmission, simplifying the data transmission process, improving data transmission performance, and reducing the complexity of network configuration and transmission latency. Furthermore, the interconnect endpoint directly sends the data packet to be transmitted and the target MAC address to the interconnect switching node, saving cache space and reducing storage costs. Afterwards, the interconnect switching node sends the data packet to be transmitted and the target MAC address to the target interconnect endpoint. This interconnecting switching node only provides Layer 2 Ethernet switching functionality, lacking network and transport layers. It also eliminates Layer 3 resolution, Layer 3 table lookup, and forwarding, thereby reducing forwarding latency and hardware costs, and minimizing network overhead. Furthermore, the data transmission process is simple and standardized, requiring no dedicated drivers or operating system primitives, making it easy for various network devices to implement data transmission and improving network device compatibility and interoperability. Additionally, the data transmission process does not require software or applications to be on the critical path; data transmission is entirely handled by high-performance hardware, resulting in high bandwidth. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and are used to explain this specification, but do not constitute an undue limitation thereof. In the drawings:

[0035] Figure 1This is a schematic diagram of a data transmission system provided in this specification;

[0036] Figure 2 This is a schematic diagram illustrating a data transmission process provided in this specification;

[0037] Figure 3 This is a schematic diagram of a data transmission system provided in this specification;

[0038] Figure 4 This is a flowchart illustrating a data transmission method provided in this specification;

[0039] Figure 5 This is a flowchart illustrating another data transmission method provided in this specification;

[0040] Figure 6 This specification provides a corresponding Figure 4 or Figure 5 A schematic diagram of the structure of an electronic device. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0042] Currently, GPU servers in intelligent computing centers providing computing services are generally interconnected, and the interconnection between these GPU servers typically employs Remote Direct Memory Access (RDMA) technology. RDMA is a technology that allows computing nodes in a network to directly read or write data from memory to the memory of other computers without significant involvement from the operating system kernel and CPU. Later, with the development of Artificial Intelligence (AI) and intelligent computing technologies, GPU Direct RDMA technology emerged. GPU Direct RDMA allows direct data transfer between GPUs or between a GPU and a remote host, without going through the host's CPU or system memory. In other words, this technology allows devices in the network to directly access the GPU's memory without the intervention of the CPU and system memory.

[0043] Furthermore, the main methods for implementing RDMA technology currently are Remote Direct Memory Access over Converged Ethernet (RDMA over Converged Ethernet version 2, or RoCE V2) and InfiniBand (IB) technologies. RoCE v2 is the second-generation version of RoCE (RDMA over Converged Ethernet). Because IB implementation requires dedicated switches and proprietary hardware, it is costly and complex to manage. RoCE, on the other hand, can utilize the mature Ethernet infrastructure, making it easier to deploy and manage. In the construction of intelligent computing centers, RoCE V2 technology has become the mainstream technology for interconnecting GPU servers.

[0044] However, firstly, RoCE technology requires switches to support and configure Priority Flow Control (PFC) to support effective congestion control strategies and avoid performance degradation or packet loss under high load conditions, making RoCE network configuration complex. Secondly, performance may be affected by other types of traffic in the network or by unoptimized network device configurations, meaning RoCE performance is dependent on network conditions. Thirdly, RoCE supports Layer 3 network communication, introducing additional processing overhead, especially increased processing latency, leading to high network overhead. Furthermore, subtle differences in RoCE v2 implementations by different vendors result in poor interoperability. Additionally, despite the emergence of GPU Direct RDMA technology, RDMA management and connection establishment still require GPU processing, and the CPU may affect the overall performance of RDMA, thus RoCE performance is affected by CPU usage. Moreover, since RoCE and the GPU communicate asynchronously, semantic synchronization requires methods such as interrupts (or doorbells) and polling. This not only complicates the RoCE processing flow but also makes the RoCE network card logic complex and costly. Furthermore, RoCE requires driver and operating system support, and application optimization is necessary to fully leverage its performance advantages. Moreover, in pursuit of ultimate performance, RoCE-supporting drivers and corresponding operating system features are constantly being iterated and updated. When using RoCE, it's essential to keep drivers and operating systems up-to-date with the latest updates and patches, which can lead to software compatibility issues.

[0045] Based on this, this specification provides a system, method, storage medium, and electronic device for data transmission. The technical solutions provided by various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0046] Figure 1This is a schematic diagram of a data transmission system provided in this specification. Figure 1 The system shown includes an interconnect switching node 100 and several interconnect endpoints 101. Each interconnect endpoint 101 is pre-configured with a virtual media access control (MAC) address. The virtual MAC address is configured based on a shared video memory space constructed from the video memory of each interconnect endpoint 101. The interconnect switching node 100 is a node that only provides Layer 2 Ethernet switching functionality, and the interconnect endpoints 101 are GPU servers.

[0047] First, interconnect endpoint 101 can determine the data packet to be transmitted. This interconnect endpoint 101 can be a GPU server, which has at least one GPU; the specific number of GPUs is not specified in this specification. The data packet to be transmitted can be sent to interconnect endpoint 101 by other devices, programs, or networks; the specific device, program, or network sending it is not specified in this specification. The data packet to be transmitted contains the video memory address corresponding to the target interconnect endpoint. Of course, the data packet to be transmitted may also include data to be transmitted; this is not specified in this specification. The data to be transmitted can be business data related to a large model, such as sample data, gradients, or parameters of a large model used for training, or task results obtained when using a large model to perform a task, where the model parameters are in the hundreds of billions or tens of billions. This business is related to a large model; this business can be training a large model or using a large model to perform a task. This specification does not limit the specific business scenario or the purpose of the large model. The target interconnect endpoint is the destination of the data to be transmitted, and this target interconnect endpoint can be any one of the interconnect endpoints 101 in the aforementioned data transmission system. The aforementioned memory address is the memory address of the target interconnect endpoint within the shared memory space, and this memory address can be preset. The shared memory space is pre-constructed from the memory of each interconnect endpoint 101, meaning the memory of each interconnect endpoint 101 is pre-mapped to the same space, i.e., the shared memory space. Furthermore, each interconnect endpoint 101 has a corresponding preset memory address within the shared memory space; that is, each interconnect endpoint 101 has a preset memory address within the shared memory space.

[0048] Then, the interconnect endpoint 101 can determine the virtual MAC address corresponding to the target interconnect endpoint based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The virtual MAC address is pre-configured based on the shared video memory space. Each interconnect endpoint 101 is pre-configured with a virtual MAC address, meaning that static MAC address allocation is performed on the interconnected GPU servers, i.e., interconnect endpoints 101, based on the shared video memory space. This virtual MAC address is a virtual MAC address corresponding to the interconnect endpoint 101, used to represent the interconnect endpoint 101. Furthermore, this virtual MAC address has a corresponding relationship with the aforementioned video memory address. Therefore, the interconnect endpoint 101 can first determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to that video memory address, and use it as the target MAC address corresponding to the target interconnect endpoint. Specifically, the interconnect endpoint 101 can first determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to that video memory address according to a pre-built translation table, and use it as the target MAC address corresponding to the target interconnect endpoint. The aforementioned translation table is pre-built and contains the correspondence between virtual MAC addresses and video memory addresses.

[0049] In addition, the interconnect endpoint 101 can determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and then calculate the virtual MAC address corresponding to the video memory address using a pre-set calculation rule, and use it as the target MAC address of the target interconnect endpoint. This calculation rule is pre-set and is used to calculate the virtual MAC address corresponding to the video memory address, that is, to convert the video memory address into a virtual MAC address.

[0050] Subsequently, interconnect endpoint 101 can send the data packet to be transmitted and the destination MAC address to interconnect switching node 100. Interconnect switching node 100 is a node that only provides Layer 2 Ethernet switching functionality, that is, a node that only provides data link layer functionality; this interconnect switching node can be a switch. Furthermore, interconnect switching node 100 does not have topology self-learning capabilities. The aforementioned interconnect endpoint 101 can directly send the data packet to be transmitted and the destination MAC address to interconnect switching node 100.

[0051] Then, the interconnection switching node 100 can receive the data packet to be transmitted and the destination MAC address, and send the data packet to the target interconnection endpoint according to the destination MAC address. Specifically, the interconnection switching node 100 can receive the data packet to be transmitted and the destination MAC address, and send the data packet to the target interconnection endpoint according to the destination MAC address using a pre-configured forwarding table. This forwarding table is pre-configured.

[0052] As can be seen from the above data transmission system, the interconnect endpoint can determine the data packet to be transmitted, and based on the video memory address corresponding to the target interconnect endpoint contained in the data packet, determine the virtual MAC address corresponding to the target interconnect endpoint, and use it as the target MAC address. The data packet to be transmitted and the target MAC address are then sent to the interconnect switching node. The interconnect switching node can then receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnect endpoint based on the target MAC address. By first determining the data packet to be transmitted, then determining the target MAC address of the target interconnect endpoint based on the video memory address of the target interconnect endpoint in the shared video memory space, and then sending the data packet to be transmitted and the target MAC address to the interconnect switching node, the interconnect endpoint eliminates the steps of establishing a connection with the CPU and asynchronous communication, avoiding the impact of the CPU on data transmission performance, simplifying the data transmission process, improving data transmission performance, and reducing network configuration complexity and transmission latency. Furthermore, this interconnect endpoint directly sends the data packet to be transmitted and the target MAC address to the interconnect switching node, saving cache space and reducing storage costs.

[0053] Subsequently, the interconnecting switch node sends the data packet to be transmitted and the destination MAC address to the target interconnecting endpoint. This interconnecting switch node only provides Layer 2 Ethernet switching functionality, lacking network and transport layers, and eliminating Layer 3 resolution, Layer 3 table lookup, and forwarding steps, thereby reducing forwarding latency and hardware costs, and minimizing network overhead. Furthermore, the above data transmission process is simple and standardized, requiring no dedicated drivers or operating system primitives, making it easy for various network devices to implement data transmission, improving network device compatibility and interoperability. Additionally, the above data transmission process does not require software or applications to be on the critical path; data transmission is entirely performed by high-performance hardware, resulting in high bandwidth.

[0054] In this specification, it should be noted that the aforementioned data transmission system is used in a scenario where GPU servers of a pre-defined type of intelligent computing center are interconnected. Firstly, the GPU servers of this pre-defined type of intelligent computing center are distributed across a single data center or several data centers and belong to a single organization, unlike the completely open nature of the Internet. Therefore, the interconnection area corresponding to the GPU servers of this pre-defined type of intelligent computing center is closed. That is, the aforementioned interconnection endpoints 101 can be distributed across a single data center or several data centers and belong to the same organization; therefore, the interconnection area corresponding to each of the aforementioned interconnection endpoints 101 is closed.

[0055] Secondly, although intelligent computing data centers undergo continuous upgrades and construction, the GPU servers and switches in operational intelligent computing centers generally have a fixed topology. Except for reasons of failure, the topology will not change arbitrarily, unlike the unpredictable and frequently changing topology of the Internet. Therefore, the interconnection topology of the GPU servers in this type of intelligent computing center is quasi-static. That is, the interconnection topology between the aforementioned interconnection endpoints 101 and interconnection switching nodes 100 is quasi-static.

[0056] Then, the GPU servers of this type of intelligent computing center are interconnected using fiber optic or coaxial cables, with strict standards for physical media selection and transmission noise suppression, ensuring a physical link transmission error rate of less than 10%. -12 The following characteristics ensure that network packet loss due to transmission errors is extremely rare. Therefore, the physical characteristics of the interconnection links between the GPU servers in this type of intelligent computing center are excellent. Specifically, the interconnection endpoints 101 and the interconnection switching node 100 are connected using fiber optic cables or coaxial cables.

[0057] In this specification, the data packet to be transmitted can be a data packet generated by the transaction layer in a specified bus standard, which can be the Peripheral Component Interconnect Express (PCIe) standard. Furthermore, the data packet format is a Transaction Layer Packet (TLP). PCIe (Peripheral Component Interconnect Express), commonly abbreviated as PCI Express, is a high-speed serial computer expansion bus standard used to connect internal computer components. The TLP (Transaction Layer Packet) is a data packet format defined in the PCIe specification for transmitting data and commands between PCIe devices. The TLP is a core component of PCIe communication; it is a data packet generated by the transaction layer in PCIe.

[0058] Therefore, to ensure better transmission of the data packets to be transmitted on the interconnection switching node 100, when sending the data packets and target MAC addresses to the interconnection switching node 100, the interconnection endpoint 101 can employ tunneling technology to encapsulate the data packets and target MAC addresses, determine the specified type of target data packet, and then send the target data packet to the interconnection switching node. Tunneling refers to the technique of encapsulating data packets of one protocol within data packets of another protocol in network communication. This technique allows data of one protocol to be transmitted over a network of another protocol, thereby achieving cross-network or cross-protocol data transmission. This tunneling technology is a pre-configured technique. It is used to encapsulate the data packets and target MAC addresses to be transmitted. The specified type refers to the type of data that can be transmitted on the interconnection switching node 100; that is, data packets of the specified type can be transmitted on the interconnection switching node 100, and this specified type of data packet can be an Ethernet frame.

[0059] Based on this, such as Figure 2 As shown, Figure 2 This is a schematic diagram illustrating a data transmission process provided in this specification. Figure 2 Interconnect endpoint 101 can determine the data packet to be transmitted. Based on the video memory address corresponding to the target interconnect endpoint contained in the data packet, it determines the virtual MAC address corresponding to the target interconnect endpoint and uses it as the target MAC address. Using tunneling technology, the data packet to be transmitted and the target MAC address are encapsulated to determine a target data packet of a specified type. The target data packet is then sent to interconnect switching node 100. Interconnect switching node 100 can receive the target data packet sent by interconnect endpoint 101 and, based on the target MAC address in the target data packet, send the target data packet to the target interconnect endpoint 101. It should be noted that since the target interconnect endpoint is one of the aforementioned interconnect endpoints 101, ... Figure 2 The target interconnect endpoint is also labeled as 101.

[0060] In this specification, the GPU server interconnection in the aforementioned data transmission system can be viewed as a Layer 2 network, integrating the advantages of both Layer 2 Ethernet switching and PCIe, and employing tunneling technology. This allows the data transmission process to fully utilize the transmission, switching, and flexibility features of Ethernet. The interconnection transmission semantics of the GPU servers are PCIe semantics, avoiding the problems of asynchronous network communication. Furthermore, since the PCIe semantics of GPU servers are generally asynchronous Direct Memory Access (DMA) operations, from an end-to-end perspective, there is a memory-to-memory communication model. Therefore, the reliability and end-to-end flow control issues of the Layer 2 network can be shared with the corresponding PCIe mechanisms.

[0061] In this specification, during data transmission, insufficient storage space at the target interconnect endpoints may lead to excessive network load and congestion. Therefore, a Global Credit-Based Flow Control Mechanism can be employed to prevent network congestion through precise pre-emptive load control. This mechanism is a method for managing and controlling data flow in a network. It uses information to control data transmission and reception, ensuring that each node in the network can effectively manage and schedule data flow to avoid congestion and improve overall network performance.

[0062] Specifically, before sending the data packet to be transmitted and the target MAC address to the interconnection switching node 100, the interconnection endpoint 101 can also determine the first credit value corresponding to the target interconnection endpoint at the current moment. When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node 100. The first credit value is the credit value at the current moment. This first credit value can be the one sent by the target interconnection endpoint to the interconnection endpoint 101, or it can be calculated based on the credit value sent by the target interconnection endpoint to the interconnection endpoint 101. This first credit value represents the remaining storage space corresponding to the interconnection endpoint 101 in the target interconnection endpoint; that is, the remaining storage space refers to the remaining space in the target interconnection endpoint used to store the data sent by the interconnection endpoint 101. The preset threshold is a pre-set value. When the first credit value is greater than the preset threshold, it indicates that there is sufficient remaining space in the target interconnection endpoint used to store the data sent by the interconnection endpoint 101. The interconnection endpoint 101 can then send the data packet to be transmitted and the target MAC address to the interconnection switching node 100, so that the interconnection switching node 100 can send the data packet to be transmitted and the target MAC address to the target interconnection endpoint. When the first credit value is not greater than a preset threshold, it indicates that the remaining space in the target interconnect endpoint for storing data sent by interconnect endpoint 101 is insufficient. Interconnect endpoint 101 needs to wait until the remaining space is sufficient, that is, the interconnect endpoint 101 needs to execute a wait instruction until the remaining space is sufficient before sending the data packet to be transmitted and the target MAC address to the interconnect switching node 100. This allows the interconnect switching node 100 to send the data packet to be transmitted and the target MAC address to the target interconnect endpoint, thus avoiding network congestion and long waiting times. This wait instruction is preset and is used to enable interconnect endpoint 101 to process the waiting state.

[0063] When determining the first credit value corresponding to the target interconnect endpoint at the current moment, if the current moment is the first time interconnect endpoint 101 transmits data to the target interconnect endpoint, then interconnect endpoint 101 can receive the credit value sent by the target interconnect endpoint through interconnect switching node 100 and use it as the first credit value corresponding to the target interconnect endpoint at the current moment. This first credit value is the credit value sent by the target interconnect endpoint. However, if the current moment is not the first time interconnect endpoint 101 transmits data to the target interconnect endpoint, then interconnect endpoint 101 can determine the credit value sent by the target interconnect endpoint through interconnect switching node and use it as the initial credit value. The number of data transmissions to the target interconnect endpoint before the current moment is determined, and the first credit value corresponding to the target interconnect endpoint at the current moment is determined based on the number of transmissions and the initial credit value. This first credit value is calculated based on the initial credit value and the number of transmissions. The more transmissions, the less remaining storage space the target interconnect endpoint has, and the smaller the first credit value. Conversely, the fewer transmissions, the more remaining storage space the target interconnect endpoint has, and the larger the first credit value.

[0064] When determining the first credit value corresponding to the target interconnect endpoint at the current time based on the number of transmissions and the initial credit value, the interconnect endpoint 101 can determine the transmission credit value based on the number of transmissions and the unit credit value, and then determine the difference between the initial credit value and the transmission credit value, which is used as the first credit value corresponding to the target interconnect endpoint at the current time. The unit credit value is preset and can be preset by the target interconnect endpoint and sent to the interconnect endpoint 101.

[0065] In addition, the target interconnect endpoint can also send the current remaining storage space, i.e. the current credit value, to the interconnect endpoint 101 in real time. Therefore, when determining the first credit value corresponding to the target interconnect endpoint at the current time, the interconnect endpoint 101 can receive the credit value sent by the target interconnect endpoint through the interconnect exchange node 100 and use it as the first credit value corresponding to the target interconnect endpoint at the current time.

[0066] In this specification, the aforementioned data transmission system is implemented based on GPU server interconnection, meaning that all interconnection endpoints in this data transmission system are interconnected through interconnection switching nodes. Furthermore, this data transmission system is designed for GPU server interconnection scenarios in a pre-defined type of intelligent computing center, thus adopting a "simple network" design concept. This data transmission system is implemented based on a Layer 2 Ethernet-switched GPU server interconnection structure with shared GPU memory space. This GPU server interconnection structure is also the structure of the data transmission system, consisting of interconnection switching nodes and several interconnection endpoints. The interconnection switching nodes only have Layer 2 Ethernet switching functionality and lack topology self-learning capabilities. The interconnection switching nodes include a MAC forwarding table established through manual configuration, and the interconnection endpoints can employ tunneling technology to carry standard PCIe TLPs within Ethernet MAC packets. Additionally, the congestion control mechanism during data transmission can employ a network-wide credit mechanism. Network reliability can be achieved through an end-to-end retransmission mechanism, shared with the PCIe data link layer retransmission mechanism.

[0067] In this specification, due to the enclosed nature and quasi-static nature of the interconnect topology of the GPU server (i.e., interconnect endpoints), all GPU memory in the entire GPU server interconnect area can be statically mapped to the same memory space, i.e., a shared memory space. Static MAC addresses are then allocated to each interconnect endpoint based on this shared memory space. Therefore, the aforementioned data transmission system may further include a management node 102, specifically as follows... Figure 3 As shown, Figure 3 This diagram illustrates a data transmission system provided in this specification. The management node can be a pre-configured program that constructs a shared video memory space based on the video memory of each interconnected endpoint. Then, based on this shared video memory space, a virtual media access control (MAC) address is configured for each interconnected endpoint and sent to each endpoint. This virtual MAC address can be randomly configured by the management node or configured according to preset rules; this specification does not impose specific limitations on it.

[0068] In this specification, the data transmission system described above adopts a "simple network" design concept, treating the entire GPU server interconnect area as a simple network. It only needs "simple" transmission and switching functions, eliminating the need for complex network and transport layers. The network layer typically enables interconnection between different subnets, while the transport layer enables end-to-end communication between peer business entities. In open internet scenarios, network and transport layers are necessary. However, due to the closed nature of the GPU server interconnect, it is unnecessary to artificially divide the closed interconnect endpoints into multiple subnets; there is no subnet communication issue, and a unified Layer 2 network can be constructed. Since the interconnect endpoints use TLP over MAC tunneling technology, PCIe has its own end-side switching mechanism within the CPU or GPU, thus eliminating the need for a transport layer. TLP over MAC refers to encapsulating PCIe TLP packets into packets that can be transmitted at the Ethernet MAC layer.

[0069] Furthermore, Ethernet switching is used to leverage the mature Ethernet ecosystem. However, Layer 2 Ethernet suffers from broadcast storms. Considering the quasi-static nature of GPU server interconnect topologies, the aforementioned data transmission system abandons the Layer 2 topology self-learning function of Ethernet and adopts a static configuration approach to fundamentally avoid the broadcast storm problem.

[0070] In this specification, the GPU server interconnect structure in the aforementioned data transmission system only has a two-layer protocol structure, which is completely transparent to upper-layer applications. Therefore, no special drivers or operating system primitives are required. Upper-layer applications use the GPU server interconnect simply by using PCIe endpoints.

[0071] In this specification, the aforementioned data transmission system may include a plurality of interconnection switching nodes 100. Each interconnection switching node 100 stores a pre-set forwarding table and has a connected interconnection endpoint 101. The interconnection switching nodes 100 may also be interconnected with each other. The specific connection methods between the interconnection switching nodes 100 and between each interconnection switching node 100 and each interconnection endpoint 101 can be determined based on the actual connection situation of the preset type of intelligent computing center.

[0072] In this specification, firstly, in the above data transmission system, the interconnection endpoint 101, i.e., the network card side, eliminates the steps of establishing a connection with the CPU and asynchronous communication. Secondly, in the interconnection switching node 100, i.e., the switching side, the steps of Layer 3 resolution, Layer 3 table lookup, and forwarding are eliminated, thereby simplifying the processing and resulting in lower latency. Simultaneously, the above data transmission system uses a network-wide credit flow control mechanism to reduce the probability of network congestion and lower the average network latency.

[0073] Secondly, because the PCIe interface bandwidth is greater than the network interface bandwidth, the PCIe interface can fully utilize the network interface bandwidth. This allows the aforementioned data transmission system to achieve high bandwidth by reusing PCIe semantics, thereby better executing services related to large models. No software is on the critical path in this data transmission system; data transmission is entirely performed by high-performance hardware. In other words, this data transmission system achieves high bandwidth through end-to-end hardware-based data transmission. Furthermore, the aforementioned data transmission system uses a network-wide credit-based flow control mechanism to reduce the probability of network congestion, resulting in high bandwidth utilization.

[0074] Then, in the aforementioned data transmission system, the interconnect endpoint 101, i.e., the network interface card (NIC) side, avoids expensive on-chip caching and only requires streaming processing. Furthermore, the interconnect switching node 100, i.e., the switching side, avoids expensive Layer 3 forwarding and switching logic and topology discovery logic, thereby reducing the hardware cost of data transmission. Additionally, the GPU server interconnect structure of the aforementioned data transmission system only has a Layer 2 protocol structure, lacking network and transport layer structures, and possesses PCIe semantics, requiring no dedicated drivers or operating system primitives, thus reducing the software and maintenance costs of data transmission. Moreover, the interconnect switching node 100 in the aforementioned data transmission system employs Layer 2 Ethernet switching functionality, which fully utilizes the transmission, switching, and flexibility features of Ethernet, and facilitates the use of the mature Ethernet ecosystem, offering numerous cost-effective solutions.

[0075] Furthermore, the aforementioned data transmission system is implemented based on Layer 2 Ethernet switching functionality of "simple networking," which is simple and standardized, and offers good compatibility with equipment from various vendors. Moreover, this data transmission system is transparent to upper-layer applications, eliminating software-level compatibility issues.

[0076] Based on the above-described data transmission system, this specification also provides a data transmission method, such as... Figure 4 As shown, Figure 4 This is a flowchart illustrating a data transmission method provided in this specification. Figure 4 The method shown is applied to the interconnect endpoint 101 in the above data transmission system. The data transmission system includes interconnect switching nodes and several interconnect endpoints. Each interconnect endpoint is pre-configured with a virtual media access control (MAC) address. The virtual MAC address is configured based on a shared video memory space constructed from the video memory of each interconnect endpoint. The switching node is a node that only provides Layer 2 Ethernet switching functionality, and the interconnect endpoint is a GPU server. The method includes the following steps:

[0077] S100: Determine the data packet to be transmitted.

[0078] The interconnect endpoint can determine the data packet to be transmitted. This data packet contains the video memory address corresponding to the target interconnect endpoint. Of course, the data packet may also include data to be transmitted; this specification does not specify a particular limitation. The data packet to be transmitted and... Figure 1 The data packets to be transmitted in the system shown are the same, so they will not be described again here.

[0079] S102: Determine the virtual MAC address corresponding to the target interconnect endpoint based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and use it as the target MAC address.

[0080] The interconnect endpoint can determine the virtual MAC address corresponding to the target interconnect endpoint based on the video memory address of the target interconnect endpoint contained in the data packet to be transmitted, and use this virtual MAC address as the target MAC address. The virtual MAC address is pre-configured based on the shared video memory space and is a virtual MAC address corresponding to the interconnect endpoint, used to characterize the interconnect endpoint. Furthermore, this virtual MAC address has a corresponding relationship with the video memory address. Therefore, the interconnect endpoint can first determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to that video memory address, and use this virtual MAC address as the target MAC address of the target interconnect endpoint.

[0081] Specifically, the interconnect endpoint can first determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted. Based on a pre-built translation table, it determines the virtual MAC address corresponding to this video memory address and uses it as the target MAC address of the target interconnect endpoint. This translation table is pre-built and contains the correspondence between virtual MAC addresses and video memory addresses.

[0082] In addition, the interconnect endpoint can determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and then calculate the virtual MAC address corresponding to the video memory address using a pre-set calculation rule, which is then used as the target MAC address of the target interconnect endpoint. This calculation rule is pre-set and is used to calculate the virtual MAC address corresponding to the video memory address, that is, to convert the video memory address into a virtual MAC address.

[0083] S104: Send the data packet to be transmitted and the target MAC address to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0084] The interconnect endpoint can send the data packet to be transmitted and the target MAC address to the interconnect switching node, so that the interconnect switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnect endpoint according to the target MAC address.

[0085] In this specification, the interconnection switching nodes and interconnection endpoints mentioned above are all switches and GPU servers of a preset type of intelligent computing center. This preset type of intelligent computing center is similar to the one described above. Figure 1 The data transmission system shown is consistent with the preset type of intelligent computing center, so it will not be described again here.

[0086] In this specification, the data packet to be transmitted can be a data packet generated by the transaction layer in a specified bus standard, such as PCIe (Peripheral Component Interconnection High-Speed ​​Standard), and the data packet format is a Transaction Layer Packet (TLP). Therefore, to ensure better transmission of the data packet on the interconnect switching node, when sending the data packet and destination MAC address to the interconnect switching node, the interconnect endpoint can employ tunneling technology to encapsulate the data packet and destination MAC address, determine the specified type of target data packet, and then send the target data packet to the interconnect switching node. The specified type refers to the type of data that can be transmitted on the interconnect switching node; that is, the specified type of data packet can be transmitted on the interconnect switching node, and this specified type of data packet can be an Ethernet frame.

[0087] Based on this, the interconnect endpoint can determine the data packet to be transmitted, and based on the memory address corresponding to the target interconnect endpoint contained in the data packet, determine the virtual MAC address corresponding to the target interconnect endpoint, and use it as the target MAC address. Using tunneling technology, the data packet to be transmitted and the target MAC address are encapsulated, a target data packet of a specified type is determined, and the target data packet is sent to the interconnect switching node so that the interconnect switching node can receive the target data packet sent by the interconnect endpoint. Then, based on the target MAC address in the target data packet, the target data packet is sent to the target interconnect endpoint.

[0088] In this specification, before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, the aforementioned interconnection endpoint can also determine the first credit value corresponding to the target interconnection endpoint at the current moment. When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node. The first credit value is the credit value at the current moment. This first credit value can be the one sent by the target interconnection endpoint to the interconnection endpoint, or it can be calculated based on the credit value sent by the target interconnection endpoint to interconnection endpoint 101. This first credit value represents the remaining storage space of the target interconnection endpoint, which refers to the remaining space in the target interconnection endpoint storing the data sent by the interconnection endpoint. The preset threshold is a pre-set value. The process of determining the first credit value corresponding to the target interconnection endpoint at the current moment is similar to the process described above. Figure 1 The process by which interconnect endpoint 101 determines the first credit value corresponding to the target interconnect endpoint at the current moment in the data transmission system shown is the same, and will not be repeated here.

[0089] In addition, based on the above-mentioned data transmission system, this specification also provides a data transmission method, such as... Figure 5 As shown, Figure 5 This is a flowchart illustrating another data transmission method provided in this specification. Figure 5 The method shown is applied to the interconnect switching node 100 in the above data transmission system. The data transmission system includes the interconnect switching node and several interconnect endpoints. Each interconnect endpoint is pre-configured with a virtual media access control (MAC) address. The virtual MAC address is configured based on a shared video memory space constructed from the video memory of each interconnect endpoint. The switching node is a node that only provides Layer 2 Ethernet switching functionality, and the interconnect endpoints are GPU servers. The method includes the following steps:

[0090] S200: Receive a data packet to be transmitted and a target MAC address; wherein the data packet to be transmitted is determined by the interconnect endpoint, the target MAC address is determined by the interconnect endpoint based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and the target MAC address is the virtual MAC address corresponding to the target interconnect endpoint.

[0091] S202: Send the data packet to be transmitted to the target interconnection terminal according to the target MAC address.

[0092] An interconnect switching node can receive data packets to be transmitted and a destination MAC address, and then send the data packets to the target interconnect endpoint based on the destination MAC address. This interconnect switching node is a node that only provides Layer 2 Ethernet switching functionality, that is, a node that only provides data link layer functionality; this interconnect switching node can be a switch. Furthermore, this interconnect switching node does not have topology self-learning capabilities. The data packets to be transmitted are determined by the interconnect endpoint, and the destination MAC address is determined by the interconnect endpoint based on the memory address corresponding to the target interconnect endpoint contained in the data packets to be transmitted; the destination MAC address is the virtual MAC address corresponding to the target interconnect endpoint.

[0093] Specifically, the interconnection switching node 100 can receive the data packet to be transmitted and the destination MAC address, and send the data packet to the target interconnection endpoint according to the destination MAC address using a pre-configured forwarding table. This forwarding table is pre-configured.

[0094] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 4 or Figure 5 This provides a method for data transmission.

[0095] This instruction manual also provides Figure 6 The one shown corresponds to Figure 4 or Figure 5 A schematic diagram of the structure of an electronic device. (e.g.) Figure 6 As shown, at the hardware level, this electronic device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above. Figure 4 or Figure 5 This provides a method for data transmission.

[0096] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0097] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0098] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0099] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0100] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware components.

[0101] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0102] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0103] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0104] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0105] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0106] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0107] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0108] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0109] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0111] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0112] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A data transmission system, characterized in that, The system includes interconnect switching nodes and several interconnect endpoints. Each interconnect endpoint is pre-configured with a virtual media access control (MAC) address, which is configured based on a shared video memory space constructed from the video memory of each interconnect endpoint. The interconnect switching nodes are nodes that only provide Layer 2 Ethernet switching functionality, and the interconnect endpoints are GPU servers; wherein: The interconnect endpoint is used to determine the data packet to be transmitted; based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, the virtual MAC address corresponding to the target interconnect endpoint is determined and used as the target MAC address; the data packet to be transmitted and the target MAC address are sent to the interconnect switching node; The interconnection switching node is used to receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

2. The system as described in claim 1, characterized in that, The interconnect endpoint is specifically used to determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted; and to calculate the virtual MAC address corresponding to the video memory address using a pre-set calculation rule, and use it as the target MAC address of the target interconnect endpoint.

3. The system as described in claim 1, characterized in that, The data packet to be transmitted is a data packet generated by the transaction layer in the specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet (TLP). Specifically, the interconnection endpoint is used to encapsulate the data packet to be transmitted and the target MAC address using tunneling technology, determine the target data packet of a specified type, and send the target data packet to the interconnection switching node.

4. The system as described in claim 1, characterized in that, Before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, the interconnection endpoint is also used to determine the first credit value corresponding to the target interconnection endpoint at the current time; when the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

5. A method for data transmission, characterized in that, The method is applied to interconnect endpoints in a data transmission system, the data transmission system including interconnect switching nodes and several interconnect endpoints, each interconnect endpoint being pre-configured with a virtual media access control (MAC) address, the virtual MAC address being configured based on a shared video memory space constructed from the video memory of each interconnect endpoint, the switching node being a node that only provides Layer 2 Ethernet switching functionality, and the interconnect endpoints being GPU servers, the method comprising: Identify the data packet to be transmitted; Based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to the target interconnect endpoint, and use it as the target MAC address; The data packet to be transmitted and the target MAC address are sent to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

6. The method as described in claim 5, characterized in that, Based on the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to the target interconnect endpoint, and use it as the target MAC address, specifically including: Determine the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted; Using pre-set calculation rules, the virtual MAC address corresponding to the video memory address is calculated and used as the target MAC address of the target interconnect endpoint.

7. The method as described in claim 5, characterized in that, The data packet to be transmitted is a data packet generated by the transaction layer in the specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet (TLP). Sending the data packet to be transmitted and the target MAC address to the interconnection switching node specifically includes: Using tunneling technology, the data packet to be transmitted and the target MAC address are encapsulated to determine the target data packet of a specified type; The target data packet is sent to the interconnection switching node.

8. The method as described in claim 5, characterized in that, The method further includes: Before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, determine the first credit value corresponding to the target interconnection endpoint at the current moment; When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 5 to 8.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method described in any one of claims 5 to 8.

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