Ramp generating circuit, image sensing apparatus, and method of operating image sensing apparatus

Abstract

The invention relates to a ramp generation circuit, an image sensing apparatus, and a method of operating the image sensing apparatus. A ramp generation circuit includes: a ramp voltage generator configured to generate a ramp voltage that varies according to a first slope or a second slope; a blocking capacitor configured to transfer a ramp voltage to the transfer node; a signal output unit configured to amplify a voltage of the transfer node to output a ramp output signal to an output node; and a ramp switch configured to selectively connect the transfer node to the output node.

Description

Technical Field

[0001] Techniques and embodiments of the present disclosure generally relate to a ramp generation circuit capable of generating a high dynamic range (HDR) image, an image sensing device including the ramp generation circuit, and a method of operating the image sensing device. Background Art

[0002] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, the demand for high-performance image sensing devices is increasing in various fields such as smartphones, wearable smart devices, digital cameras, game consoles, IoT (Internet of Things), robots, surveillance cameras, and medical micro cameras.

[0003] Recently, in order to provide high-quality images, interest in HDR images is rapidly increasing, and various technologies capable of acquiring HDR images are being developed. Among these technologies, a technology for varying an analog gain for converting an electrical signal indicating the intensity of incident light into digital data can help obtain an HDR image, but there is a problem that hardware implementation for acquiring these HDR images consumes much more resources. Summary of the invention

[0004] According to an embodiment of the present disclosure, a ramp generating circuit may include: a ramp voltage generator configured to generate a ramp voltage that varies according to a first slope or a second slope; a blocking capacitor configured to transmit the ramp voltage to a transfer node; a signal output unit configured to amplify the voltage of the transfer node to output a ramp output signal to an output node; and a ramp switch configured to selectively connect the transfer node to the output node.

[0005] According to another embodiment of the present disclosure, an image sensing device may include: a ramp generating circuit, which includes a ramp source follower transistor and a ramp switch, the ramp source follower transistor is configured to output a ramp output signal to an output node by amplifying the voltage of a transfer node to which a ramp voltage that varies according to a first slope or a second slope is applied, and the ramp switch is configured to selectively connect the transfer node to the output node; and an analog-to-digital converter (ADC) configured to generate image data by comparing the ramp output signal with a pixel signal output from a pixel configured to sense incident light.

[0006] According to another embodiment of the present disclosure, a method for operating an image sensing device may include the following steps: generating first image data by comparing a ramp output signal that varies according to a first slope with a pixel signal output from a pixel configured to sense incident light; electrically connecting an output node that outputs the ramp output signal to a gate of a ramp source follower transistor configured to generate the ramp output signal; and generating second image data by comparing the ramp output signal that varies according to a second slope different from the first slope with the pixel signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0008] Figure 1 is a block diagram illustrating an imaging device according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of the present disclosure are shown Figure 1 A circuit diagram of pixels included in a pixel array.

[0010] Figure 3 is a graph showing the relationship between illumination and each of a response generated at a high analog gain and a response generated at a low analog gain according to some embodiments of the present disclosure.

[0011] Figure 4 Some embodiments of the present disclosure are shown Figure 1 The circuit diagram of the analog-to-digital converter (ADC) is shown.

[0012] Figure 5 The following are some examples based on the present disclosure. Figure 4 The circuit diagram of the ramp generator is shown.

[0013] Figure 6 It is a diagram showing some embodiments of the present disclosure. Figure 2 A timing diagram showing the operation of the ADC to convert a pixel signal into image data. DETAILED DESCRIPTION

[0014] The present disclosure provides embodiments and examples of a ramp generating circuit capable of generating a high dynamic range (HDR) image, an image sensing device including the ramp generating circuit, and a method of operating the image sensing device, which can be used in a configuration that substantially solves one or more technical or engineering problems and alleviates limitations or disadvantages encountered in some other image sensing devices. Some embodiments of the present disclosure relate to a ramp generating circuit capable of generating a high dynamic range (HDR) image with relatively simplified hardware, an image sensing device including the ramp generating circuit, and a method of operating the image sensing device. Recognizing the above problems, a ramp generating circuit based on some embodiments of the present disclosure, an image sensing device including the ramp generating circuit, and a method of operating the image sensing device can reduce the circuit area and power consumption required to implement a ramp generator configured to use multiple analog gains.

[0015] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated as examples in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0016] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the present disclosure can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0017] Various embodiments of the present disclosure are directed to a ramp generation circuit capable of generating a high dynamic range (HDR) image with relatively simplified hardware, an image sensing device including the ramp generation circuit, and a method of operating the image sensing device.

[0018] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and descriptive and are intended to provide further description of embodiments of the disclosure as claimed.

[0019] Figure 1 is a block diagram showing an imaging device 10 according to some embodiments of the present disclosure.

[0020] Reference Figure 1 The imaging device 10 may refer to a device such as a digital still camera for photographing still images or a digital video camera for photographing moving images. For example, the imaging device 10 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smart phone, etc. The imaging device 10 may include a device having both a lens and an image pickup element, so that the device can capture (or photograph) a target object, and thus can create an image of the target object.

[0021] The imaging device 10 may include an image sensing device 100 and an image signal processor (ISP) 200 .

[0022] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 100 may include a pixel array 110, a row driver 120, a ramp generator 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. Figure 1 The components of image sensing device 100 shown are discussed merely as examples, and embodiments of the present disclosure may encompass numerous other variations, permutations, changes, modifications, and alterations.

[0023] The pixel array 110 may include a plurality of imaging pixels arranged in rows and columns. In one example, the plurality of imaging pixels may be arranged in a two-dimensional (2D) pixel array including rows and columns. In another example, the plurality of imaging pixels may be arranged in a three-dimensional (3D) pixel array. The plurality of imaging pixels may convert optical signals into electrical signals based on unit pixels or pixel groups, wherein the pixels in the pixel group share at least a specific internal circuit. The pixel array 110 may receive a drive signal including a row selection signal, a pixel reset signal, and a transfer signal from the row driver 120. Upon receiving the drive signal, the corresponding imaging pixel in the pixel array 110 may be enabled to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0024] The row driver 120 may enable the pixel array 110 to perform specific operations on the imaging pixels in the corresponding row based on the command and control signal provided by the controller circuit (e.g., the timing controller 170). In some embodiments, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row selection signal to select one or more rows among the multiple rows. The row driver 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to the selected at least one row and a transfer signal for the pixels corresponding to the selected at least one row. Therefore, the reference signal and the image signal, which are analog signals generated by the respective imaging pixels of the selected row, may be sequentially transmitted to the ADC 140. The reference signal may be an electrical signal provided to the ADC 140 in a state where the sensing node (e.g., the floating diffusion node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the ADC 140 in a state where the photocharge generated by the imaging pixel is accumulated in the sensing node. The reference signal indicating the reset noise of each pixel and the image signal indicating the intensity of incident light (hereinafter, simply referred to as “incident intensity”) may be collectively referred to as a pixel signal as necessary.

[0025] CMOS sensors may use correlated double sampling (CDS) to remove undesired offset values ​​(called fixed pattern noise) of pixels by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) may remove undesired offset values ​​of pixels by comparing the pixel output voltages obtained before and after the photocharges generated by the incident light are accumulated in the sensing node so that only the pixel output voltage based on the incident light may be measured. In some embodiments of the present disclosure, ADC 140 may sequentially sample and hold the voltage levels of the image signal and the reference signal provided to each of the plurality of column lines from the pixel array 110. That is, ADC 140 may sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0026] The ramp generator 130 may generate a ramp signal required for an analog-to-digital conversion (ADC) operation of the ADC 140 under the control of the timing controller 170, and may supply the generated ramp signal to the ADC 140. The ramp generator 130 may also be referred to as a ramp generating circuit.

[0027] ADC 140 may sample and hold the pixel signal of each column when receiving the pixel signal from each column line of pixel array 110, may convert the resulting signal into a digital signal, and may output the digital signal. In some embodiments, ADC 140 may be implemented as a ramp comparison type ADC configured to use the ramp output signal of ramp generator 130. The ramp comparison type ADC may include a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down according to time, and a timer (or counter) for performing counting until the voltage of the ramp signal matches the analog pixel signal.

[0028] The image data (IDATA) generated by ADC 140 may correspond to at least two different sensitivities. Here, sensitivity may mean an increase in the amount of image data IDATA (or an increase in response) relative to an increase in the amount of incident intensity. That is, as the sensitivity increases, the increase in the image data IDATA increases in response to an increase in incident intensity. As the sensitivity decreases, the increase in the image data IDATA decreases in response to an increase in incident intensity. In some embodiments, the sensitivity may be determined by an analog gain. The analog gain may refer to a ratio of a voltage level of an analog pixel signal that varies according to the incident intensity to the size of the image data (IDATA).

[0029] The output buffer 150 may temporarily hold the column-based image data (i.e., data (IDATA) obtained by analog-to-digital conversion of the pixel signal) provided from the ADC 140 to output the image data. In one embodiment, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0030] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and may sequentially output the image data (IDATA) temporarily stored in the selected column of the output buffer 150. In some embodiments, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal, and may select a column of the output buffer 150, thereby outputting the image data (IDATA) from the selected column of the output buffer 150 as an output signal.

[0031] The timing controller 170 may control operations of the row driver 120 , the ramp generator 130 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0032] The timing controller 170 may provide clock signals required for the operation of the respective components of the image sensing device 100, control signals for timing control, and address signals for selecting a row or column to the row driver 120, the ramp generator 130, the ADC 140, the output buffer 150, and the column driver 160. In an embodiment, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0033] The image signal processor (ISP) 200 may perform image processing of image data received from the image sensing device 100. The image signal processor (ISP) 200 may reduce noise of the image data, and may perform various types of image signal processing (e.g., interpolation, synthesis, gamma correction, color filter array interpolation, color matrix, color correction, color enhancement, lens distortion correction, etc.) for image quality improvement of the image data. In addition, the image signal processor (ISP) 200 may compress image data created by performing image signal processing for image quality improvement, so that the image signal processor (ISP) 200 may create an image file using the compressed image data. Alternatively, the image signal processor (ISP) 200 may restore the image data from the image file. In this case, the scheme for compressing such image data may be a reversible format or an irreversible format. As a representative example of such a compression format, in the case of using a still image, a Joint Photographic Experts Group (JPEG) format, a JPEG 2000 format, etc. may be used. In addition, in the case of using a moving image, a plurality of frames may be compressed according to the Moving Picture Experts Group (MPEG) standard, so that a moving image file may be created. For example, the image file may be created according to the Exchangeable Image File Format (Exif) standard.

[0034] The image signal processor (ISP) 200 may generate an HDR image by synthesizing at least two images having different sensitivities. For example, the image sensing device 100 may output a low sensitivity image generated by a low analog gain having a relatively lower sensitivity and a high sensitivity image generated by a high analog gain having a relatively higher sensitivity. The image signal processor (ISP) 200 may combine the low sensitivity image and the high sensitivity image, resulting in an HDR image. Here, low sensitivity and high sensitivity may correspond to relative concepts, the image sensing device 100 may generate image data (IDATA) having at least N different sensitivities (where N is an integer of 2 or more), and the image sensing processor 200 may use the resulting image data (IDATA) to generate an HDR image.

[0035] The image signal processor (ISP) 200 may transmit the ISP image data to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) for processing the ISP image data received from the image signal processor (ISP) 200, a memory (e.g., a nonvolatile memory) for storing the ISP image data, or a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data.

[0036] In addition, the image signal processor (ISP) 200 may transmit a control signal for controlling the operation of the image sensing device 100 (eg, whether to operate, operation timing, operation mode, etc.) to the image sensing device 100 .

[0037] Figure 2 Some embodiments of the present disclosure are shown Figure 1 1 is a circuit diagram of a pixel (PX) included in the pixel array 110.

[0038] Reference Figure 2 , the pixel (PX) may be one of a plurality of pixels included in the pixel array 110. Although for convenience of description, Figure 2 Only one pixel (PX) is shown, but other embodiments are possible, and it should be noted that other pixels may also have substantially the same structure and operation as the pixel (PX) without departing from the scope or spirit of the present disclosure.

[0039] The pixel (PX) may include a photoelectric conversion element (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a pixel capacitor (C p ), source follower transistor (SF) and select transistor (SX). Figure 4 The pixel (PX) is shown to include only one photoelectric conversion element (PD), but other embodiments are possible. It should be noted that the pixel (PX) can also be a shared pixel including multiple photoelectric conversion elements. In this case, multiple transfer transistors can be provided to correspond to the multiple photoelectric conversion elements respectively.

[0040] Each photoelectric conversion element (PD) may generate and accumulate photocharges corresponding to the incident intensity. For example, each photoelectric conversion element (PD) may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0041] If the photoelectric conversion element (PD) is implemented as a photodiode, the photoelectric conversion element (PD) may be a region in which a second conductive impurity (eg, N-type impurity) is doped in a substrate including a first conductive impurity (eg, P-type impurity).

[0042] The transfer transistor (TX) may be connected between the photoelectric conversion element (PD) and the floating diffusion region (FD). The transfer transistor (TX) may be turned on or off in response to a transfer signal (TG). If the transfer transistor (TX) is turned on by a transfer signal (TG) of a logic high level, the photocharge accumulated in the corresponding photoelectric conversion element (PD) may be transferred to the floating diffusion region (FD).

[0043] The reset transistor (RX) may be disposed between the floating diffusion region (FD) and the power supply voltage (VDD), and the voltage of the floating diffusion region (FD) may be reset to the power supply voltage (VDD) in response to a reset control signal (RG).

[0044] The floating diffusion region (FD) may accumulate photocharges received from the transfer transistor (TX). The floating diffusion region (FD) may be coupled to a pixel capacitor (C p ). For example, the floating diffusion region (FD) may be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate (e.g., a P-type substrate) including a first conductive impurity. In this case, the substrate and the doped region may be modeled as a pixel capacitor (C p ). The floating diffusion region (FD) may be referred to as a sensing node.

[0045] In some embodiments, a logic high level may refer to a voltage level for enabling (eg, turning on) a corresponding element (eg, a transistor), and a logic low level may refer to a voltage level for disabling (eg, turning off) a corresponding element (eg, a transistor).

[0046] Although for the sake of convenience, Figure 2 The case of using a floating diffusion region (FD) having only one capacitor is shown, but other embodiments are possible, and the floating diffusion region (FD) may also have two or more capacitors. For example, the floating diffusion region (FD) may selectively receive additional capacitance by connecting to a dual conversion gain (DCG) transistor so that the floating diffusion region (FD) may have two capacitors.

[0047] The source follower transistor (SF) can be connected between the selection transistor (SX) and the power supply voltage (VDD), can amplify the change in the potential of the floating diffusion region (FD) that has received the photocharge accumulated in the photoelectric conversion element (PD), and can send the amplified result to the selection transistor (SX).

[0048] The selection transistor (SX) may be connected between the source follower transistor (SF) and the output signal line and may be turned on by a selection control signal (SEL) so that the selection transistor (SX) may output an electrical signal received from the source follower transistor (SF) as a pixel signal (PS).

[0049] Figure 3 is a graph showing the relationship between illumination and each of a response generated at a high analog gain and a response generated at a low analog gain according to some embodiments of the present disclosure.

[0050] Reference Figure 3, image data generated by the ADC 140 having a high analog gain may be defined as a high analog gain (HAG) response, and image data generated by the ADC 140 having a low analog gain may be defined as a low analog gain (LAG) response. Figure 3 A high analog gain (HAG) response having a relatively larger response increase according to an increase in incident intensity and a low analog gain (LAG) response having a relatively smaller response increase according to an increase in incident intensity are shown. Figure 3 It can be seen that each of the HAG response and the LAG response is a function of the incident intensity ("intensity of incident light") applied to the corresponding pixel. Here, the response may refer to the image data (IDATA) of the corresponding pixel.

[0051] In this case, the response may have a signal-to-noise ratio (SNR) limit (ie, an SNR threshold level) and a saturation level.

[0052] The signal-to-noise ratio (SNR) threshold level may refer to a threshold value that may satisfy a predetermined reference SNR. A response less than the SNR threshold level may be regarded as an invalid response that does not satisfy the reference SNR, and a response greater than the SNR threshold level may be regarded as a valid response that satisfies the reference SNR. The reference SNR may be determined experimentally in consideration of the characteristics of the image sensing device 100.

[0053] The saturation level may represent a maximum level indicating the incident intensity. The saturation level may be determined by the ability of the pixel to convert the incident intensity into a photocharge (e.g., the capacitance of the photoelectric conversion element), the ability of the photocharge to be converted into an analog signal (e.g., the capacitance of the floating diffusion region (FD)), and the ability of the analog signal to be converted into a digital signal (e.g., the input range of the ADC). As the incident intensity increases, the response may increase in proportion to the incident intensity until the response reaches the saturation level. After the response reaches the saturation level, the response does not increase despite the increase in the incident intensity. For example, after the response reaches the saturation level, the response may have the same value as the saturation value and does not increase above the saturation level.

[0054] The effective response of each pixel may refer to a response that may indicate an incident intensity when a reference SNR is satisfied. The range of incident intensities corresponding to the effective response of a pixel may be referred to as a dynamic range of the pixel. That is, the dynamic range of a pixel may refer to a range of incident light intensities to which each pixel has an effective response.

[0055] The HAG response may provide a response having a relatively large increase in response to an increase in incident intensity. Thus, in response to an increase in incident intensity, the HAG response may have a relatively larger slope until the response reaches a saturation level, and after the response reaches the saturation level, has a fixed level corresponding to the saturation level regardless of an increase in incident intensity.

[0056] The LAG response may provide a response having a relatively small increase in response to an increase in incident intensity. Thus, the LAG response may increase with a relatively smaller slope in response to an increase in incident intensity until the response reaches a saturation level, and after the response reaches the saturation level, has a fixed level corresponding to the saturation level regardless of an increase in incident intensity.

[0057] like Figure 3 As shown, the minimum value of the HAG response dynamic range (DR_H) (or the first dynamic range) may be smaller than the minimum value of the LAG response dynamic range (DR_L) (or the second dynamic range), and the maximum value of the HAG response dynamic range (DR_H) may be smaller than the maximum value of the LAG response dynamic range (DR_L). Therefore, in a low illumination range where the incident intensity is relatively small, the HAG response may be more suitable for indicating the incident intensity. In a high illumination range where the incident intensity is relatively large, the LAG response may be more suitable for indicating the incident intensity.

[0058] A high dynamic range (HDR) image can be implemented using both a HAG response suitable for a low illumination range and a LAG response suitable for a high illumination range. To this end, at least a portion of the HAG response dynamic range and at least a portion of the LAG response dynamic range can overlap each other.

[0059] The method for forming a high dynamic range (HDR) image may be implemented as a method for synthesizing an HDR image by calculating (e.g., summing) a HAG response and a LAG response and / or a method for forming a final image based on the HAG response at a low illumination level and forming a final image based on the LAG response at a high illumination level, but is not limited thereto.

[0060] Figure 4 is a circuit diagram illustrating an analog-to-digital converter (ADC) 140 according to some embodiments of the present disclosure.

[0061] Reference Figure 4 ADC 140 may receive a ramp output signal (V ramp_out ), can receive a pixel signal (PS) from a pixel (PX), and can output a signal (V ramp_out ) and pixel signal (PS) generate and output ADC data (ADC_OUT).

[0062] ADC 140 may include a first correlated double sampling (CDS) capacitor (C CDS1 ), the second CDS capacitor (C CDS2 ), comparator 142, a first switch (SW1), a second switch (SW2) and a counter 144.

[0063] The first CDS capacitor (C CDS1) can receive a ramp output signal (V ramp_out ), and the ramp output signal (V ramp_out ) is transmitted to the comparator 142. The second CDS capacitor (C CDS2 ) may receive a pixel signal (PS) from a pixel (PX) and may transmit the pixel signal (PS) to the comparator 142. The first CDS capacitor (C CDS1 ) may be referred to as the first input capacitor of ADC 140, and the second CDS capacitor (C CDS2 ) may be referred to as the second input capacitor of ADC 140.

[0064] The comparator 142 can compare the ramp output signal (V ramp_out ) and the pixel signal (PS), a comparison data (CMP_OUT) may be generated according to the result of the comparison, and the comparison data (CMP_OUT) may be transmitted to the counter 144. In some embodiments, when the ramp output signal (V ramp_out ) is greater than the pixel signal (PS), the comparator 142 may generate the comparison data (CMP_OUT) having a logic high level. In addition, when the ramp output signal (V ramp_out ) is less than the pixel signal (PS), the comparator 142 may generate the comparison data (CMP_OUT) having a logic low level. That is, the comparison data (CMP_OUT) may indicate that the ramp output signal (V ramp_out ) and the pixel signal (PS).

[0065] The first switch (SW1) can be configured to automatically reset to zero according to the first CDS signal (AZ CDS1 ) is opened or closed, the second switch (SW2) can be automatically reset to zero according to the second CDS signal (AZ CDS1 ) is opened or closed. A first CDS auto-zero signal (AZ) having a logic high level is received. CDS1 ) can connect the non-inverting input terminal of the comparator 142 to the inverting output terminal of the comparator 142. In addition, the second CDS auto-zero signal (AZ CDS2 ) can connect the inverting input terminal of the comparator 142 to the non-inverting output terminal of the comparator 142. At the same timing point, the first CDS auto-zero signal and the second CDS auto-zero signal (AZ CDS1 AZ CDS2 ) may have a logic high level and a logic low level. The first CDS auto-zero signal and the second CDS auto-zero signal (AZ CDS1 AZ CDS2 ) may be generated and supplied by the timing controller 170.

[0066] As the first switch (SW1) and the second switch (SW2) are closed, the comparator 142 may perform an auto-zero operation. Here, the auto-zero operation may refer to adjusting the input with a ramp output signal (V ramp_out ) and the voltage level of the inverting input terminal to which the pixel signal (PS) is input for comparison of the ramp output signal (V ramp_out ) and pixel signal (PS).

[0067] The counter 144 may be enabled in response to the counter enable signal (CNT_EN), the enabled counter 144 may perform counting in response to the logic high level comparison data (CMP_OUT), and may output the counting result as ADC data (ADC_OUT). Here, the ADC data (ADC_OUT) may correspond to Figure 1 The image data (IDATA) described in .

[0068] Figure 5 Some embodiments of the present disclosure are shown Figure 4 A circuit diagram of the ramp generator 130 is shown.

[0069] Reference Figure 5 , the ramp generator 130 may correspond to Figure 4 The ramp generator 130 shown in FIG. 1 may include a ramp voltage generator 132, a blocking capacitor (C b ), ramp switch (SW r ) and signal output unit 134.

[0070] The slope voltage generator 132 may generate a slope voltage (V ramp Here, the magnitude (or absolute value) of the first slope may be greater than the magnitude (or absolute value) of the second slope. The ramp voltage generator 132 may include a plurality of current transistors (CX1 to CXm) (wherein "m" is an integer of 2 or more) and a variable load resistor (R gain ).

[0071] Multiple current transistors (CX1 to CXm) can be connected in parallel between the power supply voltage terminal (VDD) and the variable load resistor (R gain ). The plurality of current transistors (CX1-CXm) may be turned on or off in sequence in response to the corresponding current control signals (CG1-CGm). The plurality of turned-on current transistors (CX1-CXm) may respectively generate currents having the same magnitude. Therefore, each of the plurality of current transistors (CX1-CXm) may generate a current having the same magnitude according to the current control signal (C) of the variable load resistor (R gain ) The slope of the ramp voltage (Vramp ). Current control signals (CG1-CGm) for respectively controlling the plurality of current transistors (CX1-CXm) may be provided from the timing controller 170. Each current control signal (CG1-CGm) may have a logic high level or a logic low level, and a current transistor to which a current control signal of a logic high level is applied may be turned on, and a current transistor to which a current control signal of a logic low level is applied may be turned off.

[0072] exist Figure 5 In the embodiment, although each of the plurality of current transistors (CX1-CXm) is shown as an NMOS transistor, other implementations are possible, and each of the plurality of current transistors (CX1-CXm) may also be implemented as a PMOS transistor.

[0073] Variable load resistor (R gain ) can generate a ramp voltage (V ramp In some embodiments, the variable load resistor (R gain ) can have a first resistance value in the low analog gain (LAG) mode and a second resistance value in the high analog gain (HAG) mode. For example, the first resistance value can be greater than the second resistance value so that the ramp voltage (V ramp ) can have a slope greater than the ramp voltage (V ramp ). In some embodiments, the variable load resistor (V gain ) can be controlled by the timing controller 170.

[0074] Blocking capacitor (C b ) can be connected to generate a ramp voltage (V ramp )'s generation node (N g ) and the transfer node (N) corresponding to the input node of the signal output unit 134 t ). The blocking capacitor (C b ) can be transferred to the node (N t ) only transmits the ramp voltage (V ramp ) of the DC component other than the ramp voltage (V ramp ) of the alternating current (AC) component. Here, the AC component may indicate the ramp voltage (V ramp ) component of the change. The blocking capacitor (C b ) can be used to ramp the voltage (V ramp ) is transmitted to the transfer node (N t ) instead of the ramp voltage (V ramp ) is transmitted to the transfer node (N t Here, the ramp voltage (Vramp ) can be represented as a ramp input signal (V ramp_in ).

[0075] Ramp switch (SW r ) can be connected to the transfer node (N t ) and the output ramp output signal (V ramp_out ) output node (N o ). Since the transfer node (N t ) corresponds to the ramp source follower transistor (SF r ) gate and the output node (N o ) corresponds to the ramp source follower transistor (SF r ) source, so the ramp switch (SW r ) can be connected to a ramp source follower transistor (SW r ) between the gate and source. The ramp switch (SW r ) can respond to the ramp auto-zero signal (AZ r ) and opens and / or closes. The ramp switch (SW) receives the auto-zero signal (AZr) at a logic high level. r ) can transfer nodes (N t ) is electrically connected to the output node (N o ). Receives a logic low ramp auto-zero signal (AZ r ) of the ramp switch (SW r ) can transfer nodes (N t ) and output nodes (N o ) are electrically separated from each other. The ramp auto-zero signal (AZ r ) may be generated and supplied by the timing controller 170.

[0076] In the ramp voltage (V ramp ) or ramp output signal (V ramp_out ) changes from a specific slope (eg, a first slope) to another slope (eg, a second slope) different from the specific slope, the ramp auto-zero signal (AZ r ) may have a logic high level. That is, when the ramp voltage (V ramp ) or ramp output signal (V ramp_out ) before the slope changes, the ramp auto-zero signal (AZ r ) may have a logic high level.

[0077] The signal output unit 134 may include a ramp source follower transistor (SF r ) and the source follower current source (CS sf ).

[0078] Slope source follower transistor (SFr ) can be connected to a source follower current source (CS sf ) and the ground terminal, and can be transferred by placing the indicated transfer node (N t ) voltage ramp input signal (V ramp_in ) changes to generate a ramp output signal (V ramp_out That is, the ramp source follower transistor (SF r ) can be connected to the transfer node (N t ), the ramp source follower transistor (SF r ) can be connected to the output node (N o ), the ramp source follower transistor (SF r ) can be connected to the ground terminal. Figure 5 As shown, the ramp source follower transistor (SF r ) may be implemented as a P-channel MOSFET (PMOS) transistor, but the scope of the present disclosure is not limited thereto, and may also be implemented as an N-channel MOSFET (NMOS) transistor according to another embodiment. However, in this case, the source follower current source (CS sf ) can be connected to the ground terminal instead of the power supply voltage terminal (VDD).

[0079] Source follower current source (CS sf ) can be connected between the power supply voltage terminal (VDD) and the ramp source follower transistor (SF r )(or output node N o ). The source follower current source (CS sf ) can control the current flowing through the ramp source follower transistor (SF r ) current, making the ramp output signal (V ramp_out ) relative to the ramp input signal (V ramp_in ) is linear.

[0080] Figure 6 It is a diagram showing some embodiments of the present disclosure. Figure 2 A timing diagram showing the operation of ADC 140 to convert pixel signals into image data is shown.

[0081] Reference Figure 6, the operation of converting the pixel signal into the image data may be performed while being divided into a first reset period (RST1), a second reset period (RST2), a second signal period (SIG2), and a first signal period (SIG1). The first reset period (RST1) may refer to a period during which the reference signal of the pixel (PX) is AD (analog-to-digital) converted in the LAG mode, and the second reset period (RST12) may refer to a period during which the reference signal of the pixel (PX) is AD converted in the LAG mode. The second signal period (SIG2) may refer to a period during which the image signal of the pixel (PX) is AD converted in the HAG mode, and the first signal period (SIG1) may refer to a period during which the image signal of the pixel (PX) is AD converted in the LAG mode.

[0082] LAG mode may refer to using a ramp output signal with a large slope (V ramp_out ) so that the response (or image data) increase proportional to the increased incident intensity can be relatively reduced. The HAG mode may refer to a mode using a ramp output signal (V ramp_out ) so that the amount of response (or image data) increase proportional to the increased incident intensity can be relatively increased.

[0083] In the first reset period ( RST1 ), as the pixel reset signal (RG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage for resetting the floating diffusion area (FD) may be output from the pixel (PX).

[0084] In the first CDS auto-zero signal and the second CDS auto-zero signal (AZ CDS1 AZ CDS2 ) has a logic high level, the comparator 142 can output a ramp signal (V ramp_out ) and the pixel signal (PS).

[0085] In the ramp auto-zero signal (AZ r ) has a logic high level, the ramp generator 130 can output the ramp signal (V ramp_out ) performs an auto-zero operation. In more detail, the ramp generator 130 may perform an auto-zero operation, wherein the ramp switch (SW r ) by a ramp auto-zero signal (AZ) with a logic high level r ) is closed, and then the output node (N o ) is regulated to the voltage level of the transfer node (N t ) voltage level.

[0086] After a predetermined time has elapsed, under the control of the timing controller 170, the ramp generator 130 may output a ramp output signal (V ramp_out Here, the ramp offset may be related to the characteristics of the ramp generator 130 and may be a change in the voltage level relative to the auto-zero completion level.

[0087] The comparison data (CMP_OUT) can be output on the ramp output signal (V ramp_out ) is greater than the pixel signal (PS) and has a logic high level during the period in which the ramp output signal (V ramp_out ) has a logic low level during the period when the pixel signal (PS) is less than the pixel signal (PS).

[0088] The counter enable signal (CNT_EN) can be used to ramp the output signal (V ramp_out ) has a logic high level in a period in which the comparison data (CMP_OUT) has a first negative (-) slope. The counter 144 may be enabled in response to the counter enable signal (CNT_EN) having a logic high level, and the enabled counter 144 may perform counting in a period in which the comparison data (CMP_OUT) has a logic high level, and may output a first reference value indicating a counting result as the ADC data (ADC_OUT).

[0089] The first reference value may be a digital value obtained when a pixel signal (PS) corresponding to a reference signal is AD converted in a LAG mode.

[0090] In the second reset period (RST2), the ramp auto-zero signal (AZ r ) has a logic high level, the ramp generator 130 can output the ramp signal (V ramp_out ) performs an auto-zero operation. Specifically, the ramp generator 130 may perform an auto-zero operation, wherein the ramp switch (SWr) is switched to an auto-zero state by a ramp auto-zero signal (AZ) having a logic high level. r ) is closed, and then the output node (N o ) is regulated to the voltage level of the transfer node (N t ) voltage level.

[0091] In the first reset period (RST1), as a ramp voltage (V ramp ), a ramp output signal with a first slope (V ramp_out ), only the ramp voltage (V ramp ) through the blocking capacitor (C b ) is selectively transmitted to the transfer node (N t ), and transfer node (N t) is amplified. That is, the voltage change of the transfer node (V t ) can be independent of the ramp voltage (V ramp ) of the DC voltage (or DC component) (eg, higher than the ramp voltage V ramp The DC voltage of the voltage), and the output node (N o ) can be adjusted to a transfer node (V t ) voltage level. Here, after the first reset period (RST1) ends, the transfer node (N t ) may be preset to be higher than the pixel signal (PS) corresponding to the reference signal.

[0092] When the ramp voltage (V ramp ) is directly supplied to ADC 140, the voltage supplied to ADC 140 in the second reset period (RST2) becomes lower than the pixel signal (PS) corresponding to the reference signal, so that ADC 140 cannot generate image data indicating the pixel signal (PS) corresponding to the reference signal. Therefore, a method of using a plurality of ramp voltage generators may be considered, but the size of the circuit area and power consumption required for the ramp voltage generator may increase. In addition, the ramp voltages are generated by different ramp voltage generators and then transmitted to the destination through different paths. As a result, unexpected deviations may occur, thereby possibly introducing noise into the image data.

[0093] However, the ramp generator 130 according to some embodiments of the present disclosure may provide a ramp output signal (V R ) capable of generating image data representing a pixel signal (PS) in each of the LAG mode and the HAG mode by using only one ramp voltage generator 132. ramp_out ), resulting in a reduction in the required circuit area and power consumption. In addition, a path can be used based on a ramp voltage (V ramp ) to generate a ramp output signal (V ramp_out ), and the resulting ramp output signal (V ramp_out ) can be provided to the input capacitor of the ADC 140 through one path, thereby preventing deviation and noise caused by differences between the paths.

[0094] After a predetermined time has elapsed, under the control of the timing controller 170, the ramp generator 130 may output a ramp output signal (V ramp_out Here, in the second reset period (RST2), the ramp output signal (V ramp_out ) may be smaller than the ramp output signal (Vramp_out )’s first slope.

[0095] The comparison data (CMP_OUT) can be output on the ramp output signal (V ramp_out ) is greater than the pixel signal (PS) and has a logic high level during the period in which the ramp output signal (V ramp_out ) has a logic low level during the period when the pixel signal (PS) is less than the pixel signal (PS).

[0096] The counter enable signal (CNT_EN) can be used to ramp the output signal (V ramp_out ) has a logic high level in a period in which the comparison data (CMP_OUT) has a second slope. The counter 144 may be enabled in response to the counter enable signal (CNT_EN) having a logic high level, and the enabled counter 144 may perform counting in a period in which the comparison data (CMP_OUT) has a logic high level, and may output a second reference value indicating a counting result as the ADC data (ADC_OUT).

[0097] The second reference value may be a digital value obtained when a pixel signal (PS) corresponding to the reference signal is AD converted in the HAG mode.

[0098] In the second signal period (SIG2), as the transfer signal (TG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage of a floating diffusion region (FD) accumulating photocharges generated by the pixel (PX) may be output from the pixel (PX). The voltage level of the pixel signal (PS) may decrease in response to the amount of photocharges accumulated in the floating diffusion region (FD).

[0099] As the second signal period (SIG2) begins, the ramp voltage generator 132 is initialized so that the ramp output signal (V ramp_out ) returns to the voltage at which the auto-zero operation is performed in the second reset period (RST2), and after a predetermined time has elapsed, the ramp generator 130 may output a ramp output signal (V ramp_out In this case, the ramp output signal (V ramp_out ) may be equal to the ramp output signal (V ramp_out )’s second slope.

[0100] According to the ramp output signal (V ramp_out ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0101] The counter 144 enabled in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) has a logic high level, and may output a second signal value indicating the counting result as ADC data (ADC_OUT).

[0102] The second signal value may be a digital value obtained when a pixel signal PS (ie, an image signal) corresponding to a voltage of a floating diffusion region (FD) accumulating photocharges generated by a pixel (PX) is AD converted in a HAG mode.

[0103] In the HAG mode, a value corresponding to a voltage difference between an image signal and a reference signal (ie, a signal component from which reset noise has been removed) may be obtained by subtracting a second reference value from a second signal value.

[0104] In the first signal period (SIG1), the ramp auto-zero signal (AZ r ) has a logic high level, the ramp generator 130 can output the ramp signal (V ramp_out ) performs an automatic zeroing operation. In detail, the ramp generator 130 may perform an automatic zeroing operation, wherein the ramp switch (SW r ) by a ramp auto-zero signal (AZ) with a logic high level r ) is closed, and the output node (N o ) is regulated to the voltage level of the transfer node (N t ) voltage level. In addition, as the ramp voltage generator 132 is initialized, the ramp output signal (V ramp_out ) can return to the voltage at the time point when the ramp output signal (Vramp_out) starts to fall (or decrease) in the first reset period (RST1).

[0105] After a predetermined time has elapsed, the ramp generator 130 may output a ramp output signal (V ramp_out Here, in the first signal period (SIG1), the ramp output signal (V ramp_out ) may be equal to the first slope of the ramp output signal (V ramp_out )’s first slope.

[0106] According to the ramp output signal (V ramp_out ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0107] The counter 144 enabled in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) has a logic high level, and may output a first signal value indicating a counting result as ADC data (ADC_OUT).

[0108] The first signal value may be a digital value obtained when a pixel signal (PS) corresponding to a voltage of a floating diffusion region (FD) accumulating photocharges generated by a pixel (PX) is AD-converted in a LAG mode.

[0109] In the LAG mode, a value corresponding to a voltage difference between an image signal and a reference signal (ie, a signal component from which reset noise has been removed) may be obtained by subtracting a first reference value from a first signal value.

[0110] Figure 6 The operating method of the image sensing device 100 described in the embodiment may include: outputting a ramp output signal (V ramp_out ) is compared with a pixel signal (PS) output from a pixel (PX) sensing incident light to generate first image data; an output ramp output signal (V ramp_out ) output node (N o ) is electrically connected to generate a ramp output signal (V ramp_out ) of the ramp source follower transistor (SF r ) of the gate; and by outputting a ramp signal (V ramp_out ) is compared with the pixel signal (PS) to generate second image data.

[0111] In some embodiments, the above method may be applied to each of the first reset period (RST1) and the second reset period (RST2). In this case, the pixel signal (PS) may correspond to a reference signal, the first image data may be a first reference value, and the second image data may be a second reference value.

[0112] In some other embodiments, the above method may be applied to each of the second signal period (SIG2) and the first signal period (SIG1). In this case, the pixel signal (PS) may correspond to an image signal, the first image data may be the second signal value, and the second image data may be the first signal value.

[0113] Although for ease of description, the embodiments of the present disclosure disclose an example of an ADC 140 configured to generate image data with two analog gains, other embodiments are possible, and the technical concepts of the disclosed technology may also be applied to other situations in which image data is generated using three or more analog gains without departing from the scope or spirit of the present disclosure.

[0114] As is apparent from the above description, the ramp generating circuit, the image sensing device including the ramp generating circuit, and the method of operating the image sensing device according to some embodiments of the present disclosure can reduce the circuit area and power consumption required to implement a ramp generator configured to use multiple analog gains.

[0115] The embodiments of the present disclosure can provide various effects that can be recognized directly or indirectly.

[0116] Although a number of exemplary embodiments have been described, it will be appreciated that modifications and enhancements to the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this disclosure.

[0117] CROSS-REFERENCE TO RELATED APPLICATIONS

[0118] This patent application claims priority to and the benefit of Korean Patent Application No. 10-2023-0119512, filed on September 8, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A ramp generating circuit, the ramp generating circuit comprising: a slope voltage generator that generates a slope voltage that varies according to a first slope or a second slope; a blocking capacitor that transmits the ramp voltage to a transfer node; a signal output unit, the signal output unit amplifying the voltage of the transfer node to output a ramp output signal to an output node; as well as A ramp switch selectively connects the transfer node to the output node.

2. The ramp generating circuit according to claim 1, wherein: The first slope is greater than the second slope.

3. The ramp generating circuit according to claim 1, wherein: The ramp voltage generator comprises: a plurality of current transistors connected in parallel between a power supply terminal and a generation node at which the ramp voltage generator generates the ramp voltage; and A variable load resistor is connected between the generating node and a ground terminal and has a variable resistance value.

4. The ramp generating circuit according to claim 3, wherein: The blocking capacitor is connected to the generating node and the transferring node.

5. The ramp generating circuit according to claim 1, wherein: The blocking capacitor selectively transmits an alternating current (AC) component of the ramp voltage to the transfer node.

6. The ramp generating circuit according to claim 1, wherein: The blocking capacitor transmits the ramp voltage to the transfer node such that the voltage of the transfer node is independent of a direct current (DC) component of the ramp voltage.

7. The ramp generating circuit according to claim 1, wherein: The signal output unit includes a source follower transistor having a gate connected to the transfer node and a source connected to the output node.

8. The ramp generating circuit according to claim 7, wherein: The drain of the source follower transistor is connected to the ground terminal.

9. The ramp generating circuit according to claim 1, wherein: The ramp switch selectively connects the transfer node to the output node in response to a ramp auto-zero signal having a logic high level before the slope of the ramp output signal changes between the first slope and the second slope.

10. The ramp generating circuit according to claim 1, wherein: The signal output unit further generates the ramp output signal that changes according to one of the first slope and the second slope based on the ramp voltage, and The signal output unit outputs the ramp output signal through a single path.

11. An image sensing device, comprising: A ramp generating circuit, the ramp generating circuit comprising: a slope source follower transistor that outputs a slope output signal to an output node by amplifying a voltage of a transfer node to which a slope voltage varying according to a first slope or a second slope is applied; and a ramp switch that selectively connects the transfer node to the output node; and An analog-to-digital converter ADC generates image data by comparing the ramp output signal with a pixel signal output from a pixel sensing incident light.

12. The image sensing device according to claim 11, wherein: The ADC comprises: a comparator that generates comparison data by comparing the ramp output signal with the pixel signal; a first switch selectively connecting a non-inverting input terminal of the comparator to an inverting output terminal of the comparator; a second switch selectively connecting an inverting input terminal of the comparator to a non-inverting output terminal of the comparator; and A counter generates the image data by counting the comparison data.

13. The image sensing device according to claim 12, wherein: The first switch and the second switch further adjust voltage levels of the non-inverting input terminal and the inverting input terminal, respectively, for the comparator to compare the ramp output signal with the pixel signal.

14. The image sensing device according to claim 12, wherein: The ADC further comprises: a first input capacitor connected between the output node and the non-inverting input terminal; and A second input capacitor is connected between the output node and the inverting input terminal.

15. The image sensing device according to claim 11, wherein: The ramp switch selectively connects the transfer node to the output node in response to a ramp auto-zero signal having a logic high level before the slope of the ramp output signal changes between the first slope and the second slope.

16. The image sensing device according to claim 11, wherein: The ramp source follower transistor further generates the ramp output signal that varies according to one of the first slope and the second slope based on the ramp voltage, and The ramp source follower transistor outputs the ramp output signal through a single path.

17. A method of operating an image sensing device, the method comprising the steps of: generating first image data by comparing a ramp output signal that varies according to a first slope with a pixel signal output from a pixel that senses incident light; electrically connecting an output node outputting the ramp output signal to a gate of a ramp source follower transistor generating the ramp output signal; as well as Second image data is generated by comparing the ramp output signal, which varies according to a second slope different from the first slope, with the pixel signal.

18. The method according to claim 17, wherein: When the pixel signal is a reference signal generated in a state where a sensing node of the pixel is reset, the first slope is greater than the second slope.

19. The method according to claim 17, wherein: When the pixel signal is an image signal generated in a state in which photocharges generated by the pixel are accumulated in a sensing node of the pixel, the first slope is smaller than the second slope.

20. The method according to claim 17, further comprising the steps of: After the output node is electrically connected to the gate of the ramp source follower transistor, the voltage level of the ramp output signal is set higher than the voltage level of the pixel signal.

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