Manufacturing method of 1.5T SONOS memory

Abstract

The present invention discloses a method for manufacturing a 1.5T SONOS memory, comprising: depositing a select gate material layer on an underlying structure; forming a hard mask layer; performing self-aligned etching to form a select gate on the side of a control gate structure, comprising the following steps: performing a first non-selective BT etch to remove the hard mask layer on the surface and form a sidewall protection structure; performing a first SL etch to selectively etch the select gate material layer, thereby lowering the top surface of the exposed select gate material layer and increasing the flatness of the top surface of the select gate material layer; performing a second non-selective BT etch to push down the flat top surface of the select gate material layer and remove the sidewall protection structure; performing a second SL etch to selectively etch the select gate material layer to form a select gate and adjust the height and morphology of the select gate. The present invention can improve the side verticality and dimensional uniformity of the select gate formed by the sidewall process, thereby increasing the process window and reducing the size of the device.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a 1.5T SONOS memory. Background Art

[0002] like Figure 1A to Figure 1B , which is a schematic diagram of the device structure in each step of the manufacturing method of the existing 1.5T SONOS memory;

[0003] like Figure 1A As shown, a selection gate material layer 107a is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer 107a covers the top surface, side surfaces and the top surface of the semiconductor substrate 101 outside the control gate structure of the control gate structure; a first sidewall 105 is provided between the selection gate material layer 107a and the side surfaces of the control gate structure, and a gate dielectric layer 106 is provided between the selection gate material layer 107a and the top surface of the semiconductor substrate 101.

[0004] Typically, the material of the select gate material layer 107 a includes polysilicon.

[0005] The semiconductor substrate 101 includes a silicon substrate.

[0006] The gate dielectric layer 106 includes a gate oxide layer formed by oxidizing the semiconductor substrate 101 .

[0007] The control gate structure includes a first ONO layer 102 and a control gate conductive material layer 103 stacked in sequence.

[0008] The first ONO layer 102 includes a silicon oxide tunneling layer, a silicon nitride storage layer, and a silicon oxide control layer stacked in sequence.

[0009] The control gate conductive material layer 103 is made of polysilicon.

[0010] A capping layer 104 is further formed on the top surface of the control gate conductive material layer 103 . The material of the capping layer 104 includes silicon oxide or silicon nitride.

[0011] Two adjacent control gate structures form a gate combination structure. Figure 1A A gate assembly structure is shown.

[0012] In the gate assembly structure, the first side surfaces of the two control gate structures are adjacent to each other.

[0013] The space between the first side surfaces of the two control gate structures is completely filled with the select gate material layer 107 a .

[0014] like Figure 1BAs shown, the select gate material layer 107a is self-alignedly etched to form the select gate 107 on the side of the control gate structure. Therefore, the select gate 107 is formed by a spacer process, so that the morphology of the select gate 107 is affected by the spacer etching process. For example, the side of the select gate 107 is tilted, and the top width of the select gate 107 is reduced. The overall width of the select gate 107, i.e., the critical dimension (CD), cannot be precisely controlled due to the influence of the etching process. This results in poor dimensional uniformity of the select gate 107, including the dimensional uniformity at different positions above and below the same select gate 107, as well as the dimensional uniformity between different select gates 107. This has an adverse impact on device performance and the process manufacturing window. To ensure the process manufacturing window, the device size cannot be further reduced, which is not conducive to reducing the area of ​​the memory. Summary of the Invention

[0015] The technical problem to be solved by the present invention is to provide a manufacturing method for a 1.5T SONOS memory, which can form a select gate using a sidewall process while improving the side verticality and dimensional uniformity of the select gate, thereby increasing the process window and further reducing the size of the device and the chip area.

[0016] To solve the above technical problems, the present invention provides a method for manufacturing a 1.5T SONOS memory, comprising the following steps:

[0017] A selection gate material layer is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer covers the top surface, side surfaces of the control gate structure and the top surface of the semiconductor substrate outside the control gate structure; a first sidewall is spaced between the selection gate material layer and the side surfaces of the control gate structure, and a gate dielectric layer is isolated between the selection gate material layer and the top surface of the semiconductor substrate.

[0018] A hard mask layer (HM) is formed on a top surface of the select gate material layer.

[0019] Performing self-aligned etching to form a select gate on the side of the control gate structure, the self-aligned etching comprising the following steps:

[0020] A first break through (BT) etch is performed, wherein the first BT etch is non-selective and removes the hard mask layer above the top surface of the control gate structure. The hard mask layer on the side of the control gate structure is retained to form a sidewall protection structure, and the hard mask layer outside the control gate structure outside the sidewall protection structure is removed.

[0021] A first soft landing (SL) etch is performed, wherein the first SL etch is for selectively etching the select gate material layer, and the etching thickness of the select gate material layer by the first SL etch is less than or equal to the thickness of the select gate material layer on the top surface of the control gate structure, so as to partially or completely remove the select gate material layer on the top surface of the control gate structure, so as to lower the top surface of the exposed select gate material layer and increase the flatness of the top surface of the select gate material layer.

[0022] A second BT etching is performed, which is non-selective etching and pushes down the top surface of the select gate material layer on a flat basis to ensure the vertical morphology of the side of the select gate. After the second BT etching is completed, the sidewall protection structure is removed.

[0023] A second SL etch is performed, wherein the second SL etch is to selectively etch the select gate material layer to form the select gate on the side of the control gate structure. The second SL etch ensures that the select gate material layer remaining on the outer step surface of the select gate is removed and the height and morphology of the select gate are corrected to meet the requirements.

[0024] A further improvement is that the material of the select gate material layer includes polysilicon.

[0025] A further improvement is that the material of the hard mask layer includes silicon nitride.

[0026] A further improvement is that the semiconductor substrate includes a silicon substrate.

[0027] A further improvement is that the gate dielectric layer includes a gate oxide layer formed by oxidizing the semiconductor substrate.

[0028] A further improvement is that the control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.

[0029] A further improvement is that the material of the control gate conductive material layer includes polysilicon.

[0030] A further improvement is that the process for forming the first sidewall spacer includes:

[0031] A first silicon oxide layer and a second silicon nitride layer are formed in sequence.

[0032] The second silicon nitride layer is etched and stopped on the top surface of the first silicon oxide layer, and the remaining second silicon nitride layer is located on the side of the control gate structure.

[0033] The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first sidewall spacer is formed by stacking the first silicon oxide layer and the second silicon nitride layer.

[0034] A further improvement is that, in the oxidation process for forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, and the third silicon oxide layer also serves as a component of the first sidewall spacer.

[0035] A further improvement is that two adjacent control gate structures form a gate combination structure.

[0036] In the gate combination structure, the first sides of the two control gate structures are adjacent; each selection gate is formed on the second side of the corresponding control gate structure; after the second SL etching is completed, the selection gate material layer is retained in the spacing area between the first sides of the two control gate structures; the subsequent process also includes: removing the selection gate material layer in the spacing area between the first sides of the two control gate structures.

[0037] Further improvements include:

[0038] Source and drain implantation is performed to form a source region and a drain region in the semiconductor substrate; in the gate combination structure, the source region and the side of the corresponding select gate are self-aligned, and the drain region is formed in the semiconductor substrate between the first sides of the two control gate structures and is located in common with the two control gate structures.

[0039] A further improvement is that the semiconductor substrate includes both a logic area and a storage area, and the control gate structure and the select gate are both located in the storage area.

[0040] The logic area is located outside the storage area and is a formation area of ​​logic devices.

[0041] The second gate dielectric layer of the logic device and the gate dielectric layer are formed simultaneously.

[0042] The second gate conductive material layer and the select gate material layer of the logic device are deposited simultaneously.

[0043] Unlike the prior art, in which anisotropic self-aligned etching is directly performed on the select gate material layer after deposition, thereby self-aligning the select gate on the side of the control gate structure to form a select gate, the present invention adds a hard mask layer after depositing the select gate material layer, and then makes a special arrangement for the self-aligned etching process for forming the select gate, and divides the self-aligned etching process into the first BT etching, the first SL etching, the second BT etching and the second SL etching. After the first BT etching opens the hard mask layer in the surface area, during the process of selectively etching the select gate material layer by the first SL etching, the select gate material layer on the side will not be consumed due to the protection of the side wall protection structure formed by the hard mask layer, so the top surface of the select gate material layer can be flattened and lowered, preventing the select gate material layer in the top area of ​​the side from being excessively consumed, resulting in unevenness and finally causing defects such as non-vertical side surfaces. The second BT etch can further push down the flat top surface of the select gate material layer to remove the sidewall protection structure, thereby revealing the vertical side of the select gate. At the same time, the dimensions of the top and bottom areas of the select gate at the side are uniform. The second SL etch can further modify the height and morphology of the select gate, ensuring that the select gate height meets the requirements and removing the residual select gate material layer outside the select gate. At the same time, it can further modify the morphology of the select gate, ultimately obtaining a select gate with good dimensional uniformity in terms of side verticality, height, and morphology. Therefore, the present invention can form the select gate using a sidewall process while improving the side verticality and dimensional uniformity of the select gate, thereby improving the process window and further reducing the size and chip area of ​​the device. Forming the select gate using a sidewall process can produce a 1.5T SONOS memory, which can reduce the size of the device. By further increasing the side verticality and dimensional uniformity of the select gate, the present invention can improve the controllability of the select gate size without corners, thereby improving the process window, and facilitating device performance improvement and further miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1A-1B Schematic diagram of the device structure in each step of the existing 1.5T SONOS memory manufacturing method;

[0046] Figure 2 is a flow chart of a method for manufacturing a 1.5T SONOS memory according to an embodiment of the present invention;

[0047] Figures 3A-3D 1.5T SONOS memory device structure diagram in each step of the manufacturing method of the embodiment of the present invention. DETAILED DESCRIPTION

[0048] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a 1.5T SONOS memory according to an embodiment of the present invention; FIG. Figures 3A to 3D , which is a schematic diagram of the device structure in each step of the manufacturing method of the 1.5T SONOS memory according to an embodiment of the present invention; the manufacturing method of the 1.5T SONOS memory according to an embodiment of the present invention includes the following steps:

[0049] Step S101: Figure 3A As shown, a selection gate material layer 207a is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer 207a covers the top surface, side surfaces and the top surface of the semiconductor substrate 201 outside the control gate structure of the control gate structure; a first sidewall 205 is provided between the selection gate material layer 207a and the side surfaces of the control gate structure, and a gate dielectric layer 206 is provided between the selection gate material layer 207a and the top surface of the semiconductor substrate 201.

[0050] In the embodiment of the present invention, the material of the select gate material layer 207 a includes polysilicon.

[0051] The semiconductor substrate 201 includes a silicon substrate.

[0052] The gate dielectric layer 206 includes a gate oxide layer formed by oxidizing the semiconductor substrate 201 .

[0053] The control gate structure includes a first ONO layer 202 and a control gate conductive material layer 203 stacked in sequence.

[0054] The first ONO layer 202 includes a silicon oxide tunneling layer, a silicon nitride storage layer, and a silicon oxide control layer stacked in sequence.

[0055] The control gate conductive material layer 203 is made of polysilicon.

[0056] A capping layer 204 is further formed on the top surface of the control gate conductive material layer 203 . The material of the capping layer 204 includes silicon oxide or silicon nitride.

[0057] In some embodiments, the process of forming the first sidewall spacer 205 includes:

[0058] A first silicon oxide layer and a second silicon nitride layer are formed in sequence.

[0059] The second silicon nitride layer is etched and stopped on the top surface of the first silicon oxide layer, and the remaining second silicon nitride layer is located on the side of the control gate structure.

[0060] The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first silicon oxide layer and the second silicon nitride layer are stacked to form a first sidewall spacer 205 .

[0061] During the oxidation process of forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, which also serves as a component of the first spacer 205. In this way, the first spacer 205 also has an ONO structure.

[0062] In some embodiments, two adjacent control gate structures form a gate combination structure. Figure 3A A gate assembly structure is shown.

[0063] In the gate assembly structure, the first side surfaces of the two control gate structures are adjacent to each other.

[0064] The space between the first side surfaces of the two control gate structures is completely filled with the select gate material layer 207 a .

[0065] Step S102: Figure 3A As shown, a hard mask layer 208 is formed on the top surface of the select gate material layer 207a.

[0066] In an embodiment of the present invention, the material of the hard mask layer 208 includes silicon nitride.

[0067] Step S103: Perform self-aligned etching to form a select gate 207 on the side of the control gate structure. The self-aligned etching includes the following steps:

[0068] Step S103a, as Figure 3B As shown, a first BT etch is performed. The first BT etch is non-selective. The first BT etch removes the hard mask layer 208 above the top surface of the control gate structure. The hard mask layer 208 on the side of the control gate structure is retained to form a sidewall protection structure. The hard mask layer 208 outside the control gate structure outside the sidewall protection structure is removed. In this application, non-selective etching means that there is no selectivity for different materials. For example, it can etch the material of the hard mask layer 208 and also etch the exposed select gate material layer 207a. When etching the hard mask layer 208, it is anisotropic etching from top to bottom, thereby forming a sidewall protection structure.

[0069] Step S103b, as Figure 3CAs shown, a first SL etch is performed. The first SL etch is selectively etching the select gate material layer 207a. The first SL etch has an etching thickness of the select gate material layer 207a that is less than or equal to the thickness of the select gate material layer 207a on the top surface of the control gate structure, thereby partially or completely removing the select gate material layer 207a on the top surface of the control gate structure, thereby lowering the top surface of the exposed select gate material layer 207a and improving the flatness of the top surface of the select gate material layer 207a. In the present application, the selective etching corresponding to the first SL etch is an etching with a high selectivity ratio for the select gate material layer 207a, that is, the etching rate of the select gate material layer 207a is much greater than the etching rate of the hard mask layer 208. The first SL etching is mainly used to remove the select gate material layer 207a on the top surface of the control gate structure. After the select gate material layer 207a on the top surface of the control gate structure is completely removed, the select gate material layer 207a is basically only located on the side of the control gate structure. Subsequently, it is only necessary to adjust the height of the select gate material layer 207a to form the required select gate 207. If the select gate material layer 207a on the top surface of the control gate structure is not completely removed, it is necessary to further remove the remaining select gate material layer 207a on the top surface of the control gate structure before adjusting the height and morphology of the select gate 207.

[0070] Typically, the first BT etching and the first SL etching constitute the first dry etching.

[0071] Step S103c, as Figure 3D As shown, a second BT etching is performed. The second BT etching is non-selective etching and pushes down the top surface of the select gate material layer 207a on the flat basis to ensure the vertical morphology of the side of the select gate 207. After the second BT etching is completed, the sidewall protection structure is removed.

[0072] Step S103d, as Figure 3D As shown, a second SL etching is performed. The second SL etching is to selectively etch the selection gate material layer 207a to form a selection gate 207 on the side of the control gate structure. The second SL etching ensures that the selection gate material layer 207a remaining on the outer step surface of the selection gate 207 is removed and the height and morphology of the selection gate 207 are corrected to meet the requirements.

[0073] Typically, the second BT etching and the second SL etching constitute the second dry etching.

[0074] like Figure 3DAs shown, in the gate combination structure, each selection gate 207 is formed on the second side of the corresponding control gate structure; after the second SL etching is completed, the selection gate material layer 207a is retained in the spacing area between the first sides of the two control gate structures; the subsequent process also includes: removing the selection gate material layer 207a in the spacing area between the first sides of the two control gate structures.

[0075] The follow-up also includes:

[0076] Source and drain implantation is performed to form source and drain regions in the semiconductor substrate 201; in the gate combination structure, the source region and the side of the corresponding select gate 207 are self-aligned, and the drain region is formed in the semiconductor substrate 201 between the first sides of the two control gate structures and is shared by the two control gate structures.

[0077] In some embodiments, the semiconductor substrate 201 includes both a logic region (not shown) and a storage region, with the control gate structure and select gate 207 both located in the storage region. The control gate structure is formed in the storage gate region, i.e., the CG region, and the select gate is formed in the select gate region, i.e., the SG region.

[0078] The logic area is located outside the memory area and is a region where logic devices are formed.

[0079] The second gate dielectric layer of the logic device and the gate dielectric layer 206 are formed simultaneously.

[0080] The second gate conductive material layer and the select gate material layer 207 a of the logic device are deposited simultaneously.

[0081] When the second gate conductive material layer is patterned and etched, the select gate material layer 207 a in the spaced region between the first side surfaces of the two control gate structures is also removed simultaneously.

[0082] Unlike the prior art, in which the select gate material layer 207a is directly anisotropically self-aligned etched after being deposited, thereby self-aligning the select gate 207 on the side of the control gate structure, in the embodiment of the present invention, a hard mask layer 208 is formed after depositing the select gate material layer 207a. A special configuration is then made for the self-aligned etching process for forming the select gate 207, which is divided into a first BT etching, a first SL etching, a second BT etching, and a second SL etching. After the first BT etching opens the hard mask layer 208 in the surface area, during the process of selectively etching the select gate material layer 207a in the first SL etching, the sidewall protection structure formed by the hard mask layer 208 prevents the side select gate material layer 207a from being consumed. Therefore, the top surface of the select gate material layer 207a can be flattened and lowered, thereby preventing the select gate material layer 207a in the top area from being excessively consumed, resulting in unevenness and ultimately non-vertical defects. The second BT etching can remove the sidewall protection structure on the basis of further pushing down the flat top surface of the selection gate material layer 207a, so that the vertical side of the selection gate 207 is exposed. At the same time, the sizes of the top area and the bottom area of ​​the selection gate 207 at the side are kept uniform; and the second SL etching can further modify the height and morphology of the selection gate 207, so that the height of the selection gate 207 meets the requirements and removes the residue of the selection gate material layer 207a outside the selection gate 207. At the same time, it can further modify the morphology of the selection gate 207, and finally obtain a selection gate 207 with good size uniformity whose side verticality, height and morphology meet the requirements. Therefore, the embodiment of the present invention can use the sidewall process to form the selection gate 207, while improving the side verticality and size uniformity of the selection gate 207, thereby improving the process window and further reducing the size of the device and the chip area. Forming the select gate 207 using a spacer process can produce a 1.5T SONOS memory device, thereby reducing the size of the device. The embodiments of the present invention further increase the side verticality and size uniformity of the select gate 207, thereby improving the controllability of the size of the select gate 207 and eliminating corners. This can increase the process window, thereby facilitating improved device performance and further miniaturization.

[0083] In an embodiment of the present invention, the 1.5T SONOS non-volatile memory achieves size miniaturization by shrinking the space between the CG and SG. By protecting the SG with HM and combining BT1-SL1-BT2-SL2, the memory area is further reduced while achieving good control of the SG polysilicon gate morphology and CD. Only SGs with good sidewall verticality and uniformity can be formed, reducing SG process variation. Without HM protection of the SG sidewalls, SG verticality and CD cannot be guaranteed. Here, BT1 represents the first BT etch, SL1 represents the first SL etch, BT2 represents the second BT etch, and SL2 represents the second SL etch.

[0084] The 1.5T SONOS structure can greatly reduce the CG / SG space, thereby achieving the goal of further shrinking the memory area. However, in existing methods, it is relatively difficult to form an SG structure with a vertical and flat surface morphology in a 1.5T SONOS structure. In the embodiment of the present invention, HM-protected SG sidewall self-aligned etching is used to form SG. Compared with the SG sidewall process without HM protection, the HM-protected SG process can be combined with the BT1-SL1-BT2-SL2 SG self-aligned etching scheme to achieve good control of the SG polysilicon gate morphology and size, significantly improving the verticality and uniformity of the SG sidewall, so that the memory area is further reduced while maintaining the uniformity of the SG size and reducing the variation of the SG process. The development of the method of the embodiment of the present invention improves the uniformity of the SG morphology and size, increases the process manufacturing window, and saves the memory area. The process manufacturing flow is simple and suitable for mass production.

[0085] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0086] The integrated process of the embodiment of the present invention improves the morphology of the self-aligned etched sidewall SG polysilicon gate, has no vertical footing, greatly reduces the risk of ion implantation penetration, and greatly increases the device window.

[0087] The integrated process of the embodiment of the present invention improves the self-aligned etched sidewall SG polysilicon gate morphology, enhances the verticality and uniformity of the SG sidewall, has good size controllability, and reduces the variation of the SG process.

[0088] The integration process of the embodiment of the present invention further reduces the memory area while improving the size controllability of the self-aligned etched Sidewall SG polysilicon gate, thereby further reducing the chip area and improving product competitiveness.

[0089] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A method for manufacturing a 1.5T SONOS memory, characterized in that: The steps include: Depositing a select gate material layer on an underlying structure, wherein a control gate structure is formed on the underlying structure, wherein the select gate material layer covers a top surface, side surfaces of the control gate structure, and a top surface of the semiconductor substrate outside the control gate structure; a first spacer is provided between the select gate material layer and the side surfaces of the control gate structure, and a gate dielectric layer is provided between the select gate material layer and the top surface of the semiconductor substrate; forming a hard mask layer on a top surface of the select gate material layer; Performing self-aligned etching to form a select gate on the side of the control gate structure, the self-aligned etching comprising the following steps: Performing a first starting etch, wherein the first starting etch is non-selective etching and removes the hard mask layer above the top surface of the control gate structure. The hard mask layer on the side of the control gate structure is retained to form a sidewall protection structure, and the hard mask layer outside the control gate structure outside the sidewall protection structure is removed; performing a first soft etch, wherein the first soft etch is to selectively etch the select gate material layer, wherein the etching thickness of the select gate material layer by the first soft etch is less than or equal to the thickness of the select gate material layer on the top surface of the control gate structure, so as to partially or completely remove the select gate material layer on the top surface of the control gate structure, thereby lowering the top surface of the exposed select gate material layer and improving the flatness of the top surface of the select gate material layer; Performing a second initial etching, wherein the second initial etching is non-selective etching and pushes down the top surface of the select gate material layer on a flat basis to ensure a vertical morphology of the side of the select gate, and after the second initial etching is completed, the sidewall protection structure is removed; A second soft etch is performed, wherein the second soft etch is to selectively etch the select gate material layer to form the select gate on the side of the control gate structure. The second soft etch ensures that the select gate material layer remaining on the step surface outside the select gate is removed and the height and morphology of the select gate are corrected to meet the requirements, so that the height of the select gate is lower than the height of the control gate and the morphology of the select gate is a sidewall vertical morphology.

2. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The material of the select gate material layer includes polysilicon.

3. The method for manufacturing a 1.5T SONOS memory according to claim 2, wherein: The material of the hard mask layer includes silicon nitride.

4. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

5. The method for manufacturing a 1.5T SONOS memory according to claim 4, wherein: The gate dielectric layer includes a gate oxide layer formed by oxidizing the semiconductor substrate.

6. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.

7. The method for manufacturing a 1.5T SONOS memory according to claim 6, wherein: The material of the control gate conductive material layer includes polysilicon.

8. The method for manufacturing a 1.5T SONOS memory according to claim 5, wherein: The process for forming the first sidewall spacer includes: forming a first silicon oxide layer and a second silicon nitride layer in sequence; Etching the second silicon nitride layer and stopping on the top surface of the first silicon oxide layer, with the remaining second silicon nitride layer being located on a side of the control gate structure; The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first sidewall spacer is formed by stacking the first silicon oxide layer and the second silicon nitride layer.

9. The method for manufacturing a 1.5T SONOS memory according to claim 8, wherein: During the oxidation process of forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, and the third silicon oxide layer also serves as a component of the first sidewall spacer.

10. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: Two adjacent control gate structures form a gate combination structure; In the gate assembly structure, the first sides of the two control gate structures are adjacent to each other; each select gate is formed on the second side of the corresponding control gate structure; After the second soft etching is completed, the select gate material layer remains in the spaced area between the first side surfaces of the two control gate structures. The subsequent process further includes: removing the select gate material layer in the spaced area between the first side surfaces of the two control gate structures.

11. The method for manufacturing a 1.5T SONOS memory according to claim 10, wherein: The follow-up also includes: Source and drain implantation is performed to form a source region and a drain region in the semiconductor substrate; in the gate combination structure, the source region and the side of the corresponding select gate are self-aligned, and the drain region is formed in the semiconductor substrate between the first sides of the two control gate structures and is located in common with the two control gate structures.

12. The method for manufacturing a 1.5T SONOS memory according to claim 10, wherein: The semiconductor substrate includes a logic area and a storage area, and the control gate structure and the select gate are both located in the storage area; The logic area is located outside the storage area and is a formation area of ​​logic devices; The second gate dielectric layer of the logic device and the gate dielectric layer are formed simultaneously; The second gate conductive material layer and the select gate material layer of the logic device are deposited simultaneously.

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