Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, which can greatly reduce the leakage current of the semiconductor device, thereby reducing the power consumption of the semiconductor device, further reducing the total power consumption of a logic chip, avoiding the loss of storage data of a storage chip as much as possible, and improving the reliability of the storage chip. And the reliability of the logic chip and the storage chip is improved. The semiconductor device may include a substrate, a first isolation layer, a first metal layer, a second isolation layer, and a channel layer. The substrate, the first isolation layer, the first metal layer and the second isolation layer can be stacked in the first direction. The semiconductor device may also include a first recess. The first groove can penetrate through the second isolation layer, the first metal layer and the first isolation layer, and it can be seen that the first groove is formed in the first direction, that is, the depth direction of the first groove is consistent with the first direction. The first cross section of the first groove can be T-shaped or I-shaped. The first cross section can be used for indicating the cross section of the first groove in the first direction. The channel layer can be arranged on the side wall and the bottom of the first groove.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same, a chip and an electronic device. Background Art

[0002] With the rapid development of semiconductor technology, semiconductor devices (such as transistors, etc.) used in logic chips, memory chips, etc. have been widely used. Semiconductor devices often have leakage current in the off state, which will affect the performance of semiconductor devices, and thus have an important impact on the performance of chips. For logic chips, excessive leakage current will cause the static power consumption of logic chips to be large. Since static power consumption accounts for a large proportion of the total power consumption of logic chips, logic chips will have problems such as increased operating temperature due to the large total power consumption, which will affect the performance and reliability of logic chips. For memory chips, semiconductor devices can be used as gating tubes. Excessive leakage current will increase the probability of failure of reading and writing data in storage units in memory chips, causing loss of stored data, which will also affect the performance and reliability of chips.

[0003] For vertical channel transistors, in order to reduce their leakage current, the channel layer in the related art often adopts a shell channel, and the setting direction of the shell channel can be perpendicular to the stacking direction of the substrate and the isolation layer. The shell channel can enhance the gate control ability of the transistor and reduce the conductive cross-sectional area of ​​the channel layer to reduce the leakage current of the semiconductor device. However, the related technology does not significantly reduce the leakage current. Therefore, there is an urgent need for a technical solution that can significantly reduce the leakage current of the semiconductor device. Summary of the invention

[0004] The present application provides a semiconductor device and a preparation method thereof, a chip and an electronic device, which can significantly reduce the leakage current of the semiconductor device, thereby reducing the power consumption of the semiconductor device, and then reducing the total power consumption of the logic chip. It can also avoid the loss of storage data of the memory chip as much as possible, and improve the reliability of the logic chip and the memory chip.

[0005] In a first aspect, the present application provides a semiconductor device, which may include a substrate, a first isolation layer, a first metal layer, a second isolation layer, and a channel layer.

[0006] Optionally, the substrate, the first isolation layer, the first metal layer and the second isolation layer may be stacked along the first direction. The semiconductor device may further include a first groove. The first groove may penetrate the second isolation layer, the first metal layer and the first isolation layer. It can be seen that the first groove is arranged along the first direction, that is, the depth direction of the first groove is consistent with the first direction. The first cross section of the first groove may be T-shaped or I-shaped. Among them, the first cross section may be used to indicate the cross section of the first groove in the first direction. The channel layer may be arranged on the sidewall and bottom of the first groove.

[0007] It is conceivable that the T-shape may be a regular T-shape or an inverted T-shape, and this application does not limit this.

[0008] In the semiconductor device provided by the present application, since the channel layer can be arranged on the side wall and the bottom of the first groove, and the first cross-section of the first groove can be T-shaped or I-shaped, then, compared with the shell channel adopted by the vertical channel semiconductor device in the related art, the semiconductor device provided by the present application increases the length of the channel layer. When the semiconductor device is in the off state, the electrons injected from the source into the channel layer will be greatly reduced, thereby greatly reducing the leakage current of the semiconductor device, and then reducing the power consumption of the semiconductor device.

[0009] Optionally, the materials of the first isolation layer and the second isolation layer may include but are not limited to silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, etc., or any combination thereof. The materials of the channel layer may include but are not limited to silicon, silicon germanium, silicon germanium tin, graphene, oxide semiconductors, III-V compound semiconductors, etc., or any combination thereof.

[0010] In a possible implementation, the semiconductor device provided by the present application may further include a first semiconductor layer. The first semiconductor layer may be located between the substrate and the first isolation layer. That is, the substrate, the first semiconductor layer, the first isolation layer, the first metal layer, and the second isolation layer are stacked along a first direction. The first semiconductor layer may serve as a drain or source of the semiconductor device, and the first metal layer may serve as a gate of the semiconductor device.

[0011] Optionally, the material of the first semiconductor layer may include but is not limited to silicon, germanium silicon, germanium tin silicon, oxide semiconductor, III-V compound semiconductor, etc., or any combination thereof. The material of the first metal layer may include but is not limited to titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, polysilicon, metal silicide, etc., or any combination thereof.

[0012] Further, the bottom of the first groove may be located on or inside the first surface of the first semiconductor layer, wherein the first surface may be used to indicate a surface of the first semiconductor layer away from the substrate.

[0013] In a possible implementation, the first groove may include a first portion and a second portion connected along a first direction. The first portion may be located inside the first isolation layer or inside the second isolation layer, and the second portion may be located inside the first metal layer. It is conceivable that when the first portion is located inside the first isolation layer, the first cross section is an inverted T-shape. When the first portion is located inside the second isolation layer, the first cross section is a positive T-shape. The second portion may be located inside the first metal layer.

[0014] Optionally, the first size may be greater than the second size. The first size may be used to indicate the size of the first part in the second direction, which may be understood as the width of the first part. The second size may be used to indicate the size of the second part in the second direction, which may be understood as the width of the second part. The second direction may be perpendicular to the first direction.

[0015] It can be seen that the first size is greater than the second size, the first cross-section is an inverted T-shape or a right T-shape, the channel layer can be arranged on the sidewall and bottom of the first groove, and the total length of the channel layer in the first part and the second part is increased, thereby reducing the leakage current of the semiconductor device and further reducing the power consumption of the semiconductor device.

[0016] Further, the difference between the first size and the second size can be of the same order of magnitude as the third size. The difference between the first size and the second size can be understood as the width difference between the first part and the second part. The third size can be used to indicate the size of the second part in the first direction, and can be understood as the depth of the second part. Then, it can be understood that the width difference between the first part and the second part and the depth of the second part can be of the same order of magnitude (e.g., nm level or um level).

[0017] Furthermore, the difference between the first size and the second size may be greater than or equal to one quarter of the third size. That is, the width difference between the first portion and the second portion may be greater than or equal to one quarter of the depth of the second portion. For example, the width difference between the first portion and the second portion may be greater than or equal to one third of the depth of the second portion.

[0018] In another possible implementation, the first groove may include a first portion, a second portion, and a third portion that are sequentially connected along the first direction. The first portion may be located inside the first isolation layer, the second portion may be located inside the first metal layer, and the third portion may be located inside the second isolation layer. It is conceivable that the first portion, the second portion, and the third portion may constitute a first groove having an I-shaped first cross section.

[0019] Optionally, both the first size and the fourth size may be greater than the second size. The first size may be used to indicate the size of the first part in the second direction, which may be understood as the width of the first part. The second size may be used to indicate the size of the second part in the second direction, which may be understood as the width of the second part. The fourth size may be used to indicate the size of the third part in the second direction, which may be understood as the width of the third part. The second direction may be perpendicular to the first direction.

[0020] It can be seen that the first size and the fourth size can both be larger than the second size, the first cross-section is an I-shape, the channel layer can be arranged on the sidewall and the bottom of the first groove, and the total length of the channel layer in the first part, the second part and the third part is further increased, thereby reducing the leakage current of the semiconductor device and further reducing the power consumption of the semiconductor device.

[0021] Further, the difference between the first dimension and the second dimension may be of the same order of magnitude as the third dimension, and the difference between the fourth dimension and the second dimension may be of the same order of magnitude as the third dimension. Among them, the difference between the first dimension and the second dimension may be understood as the width difference between the first part and the second part. The difference between the fourth dimension and the second dimension may be understood as the width difference between the third part and the second part. The third dimension may be used to indicate the size of the second part in the first direction, and may be understood as the depth of the second part. Then, it may be understood that the width difference between the first part and the second part and the depth of the second part may be of the same order of magnitude (e.g., nm level or um level). Similarly, the width difference between the third part and the second part and the depth of the second part may also be of the same order of magnitude (e.g., nm level or um level).

[0022] Furthermore, the difference between the first size and the second size may be greater than or equal to one quarter of the third size. In other words, the difference between the width of the first portion and the second portion may be greater than or equal to one quarter of the depth of the second portion.

[0023] Similarly, the difference between the fourth dimension and the second dimension may be greater than or equal to one quarter of the third dimension. That is, the width difference between the third portion and the second portion may also be greater than or equal to one quarter of the depth of the second portion.

[0024] Exemplarily, the width difference between the first portion and the second portion and the width difference between the third portion and the second portion may be greater than or equal to one third of the depth of the second portion.

[0025] In a possible implementation, the semiconductor device provided by the present application may further include a first dielectric layer. The first dielectric layer may be located inside the first groove. The material of the first dielectric layer may include but is not limited to silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, etc., or any combination thereof.

[0026] Further, the first dielectric layer may include a second groove. The semiconductor device may also include a second semiconductor layer and a second metal layer stacked along the first direction. The second semiconductor layer may be located inside the second groove. The second semiconductor layer and the second metal layer may constitute a source or drain of the semiconductor device. The material of the second semiconductor layer may include but is not limited to silicon, germanium silicon, germanium tin silicon, oxide semiconductor, III-V compound semiconductor, etc., or any combination thereof. The material of the second metal layer may include but is not limited to metal silicide, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof.

[0027] In a possible implementation, the semiconductor device provided in the present application may further include a second dielectric layer. The second dielectric layer may be arranged inside the first groove along the first direction, and the second dielectric layer may be located between the first metal layer and the channel layer. It is understandable that the second dielectric layer may serve as a gate dielectric layer of the semiconductor device. The material of the gate dielectric layer may include but is not limited to silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, etc., or any combination thereof.

[0028] In a second aspect, the present application provides a method for preparing a semiconductor device, which may include: forming a first isolation layer, a first metal layer, and a second isolation layer on a substrate along a first direction. Etching the second isolation layer, the first metal layer, and the first sacrificial layer to form a first groove. Forming a channel layer on the sidewall and bottom of the first groove.

[0029] Optionally, the first groove may pass through the second isolation layer, the first metal layer and the first isolation layer. It can be seen that the first groove is arranged along the first direction, that is, the depth direction of the first groove is consistent with the first direction. The first cross section of the first groove may be T-shaped or I-shaped. Among them, the first cross section may be used to indicate the cross section of the first groove in the first direction. It is conceivable that the T-shape may be a positive T-shape or an inverted T-shape, which is not limited in this application.

[0030] In the method for preparing a semiconductor device provided in the present application, since the channel layer can be arranged on the side wall and the bottom of the first groove, and the first cross-section of the first groove can be T-shaped or I-shaped, it can be seen that the semiconductor device prepared in the present application increases the length of the channel layer. When the semiconductor device is in the off state, the electrons injected from the source into the channel layer will be greatly reduced, thereby greatly reducing the leakage current of the semiconductor device, and further reducing the power consumption of the semiconductor device.

[0031] In a possible implementation, etching the second isolation layer, the first metal layer, and the first sacrificial layer to form the first groove may include: etching the second isolation layer, the first metal layer, and the first sacrificial layer along a first direction to form a third groove. Through the third groove, etching the first isolation layer and / or the second isolation layer along a second direction to form the first groove. The second direction may be perpendicular to the first direction.

[0032] It is conceivable that the first cross section of the first groove formed by etching the first isolation layer along the second direction may be an inverted T-shape. The first cross section of the first groove formed by etching the second isolation layer along the second direction may be a positive T-shape. The first cross section of the first groove formed by etching the first isolation layer and the second isolation layer along the second direction may be an I-shape.

[0033] In one example, the first groove may include a first portion and a second portion connected along a first direction. The first portion may be located inside the first isolation layer or inside the second isolation layer. It is conceivable that when the first portion is located inside the first isolation layer, the first cross section is an inverted T-shape. When the first portion is located inside the second isolation layer, the first cross section is a positive T-shape. The second portion may be located inside the first metal layer.

[0034] Optionally, the first size may be greater than the second size. The first size may be used to indicate the size of the first part in the second direction, which may be understood as the width of the first part. The second size may be used to indicate the size of the second part in the second direction, which may be understood as the width of the second part. The second direction may be perpendicular to the first direction.

[0035] It can be seen that the first size is greater than the second size, the first cross-section is an inverted T-shape or a right T-shape, the channel layer can be arranged on the sidewall and bottom of the first groove, and the total length of the channel layer in the first part and the second part is increased, thereby reducing the leakage current of the semiconductor device and further reducing the power consumption of the semiconductor device.

[0036] Further, the difference between the first size and the second size can be of the same order of magnitude as the third size. The difference between the first size and the second size can be understood as the width difference between the first part and the second part. The third size can be used to indicate the size of the second part in the first direction, and can be understood as the depth of the second part. Then, it can be understood that the width difference between the first part and the second part and the depth of the second part can be of the same order of magnitude (e.g., nm level or um level).

[0037] Furthermore, the difference between the first size and the second size may be greater than or equal to one quarter of the third size. That is, the width difference between the first portion and the second portion may be greater than or equal to one quarter of the depth of the second portion. For example, the width difference between the first portion and the second portion may be greater than or equal to one third of the depth of the second portion.

[0038] In another example, the first groove may include a first portion, a second portion, and a third portion that are sequentially connected along the first direction. The first portion may be located inside the first isolation layer, the second portion may be located inside the first metal layer, and the third portion may be located inside the second isolation layer. It is conceivable that the first portion, the second portion, and the third portion may constitute a first groove having an I-shaped first cross section.

[0039] Optionally, both the first size and the fourth size may be greater than the second size. The first size may be used to indicate the size of the first part in the second direction, which may be understood as the width of the first part. The second size may be used to indicate the size of the second part in the second direction, which may be understood as the width of the second part. The fourth size may be used to indicate the size of the third part in the second direction, which may be understood as the width of the third part. The second direction may be perpendicular to the first direction.

[0040] It can be seen that the first size and the fourth size can both be larger than the second size, the first cross-section is an I-shape, the channel layer can be arranged on the sidewall and the bottom of the first groove, and the total length of the channel layer in the first part, the second part and the third part is further increased, thereby reducing the leakage current of the semiconductor device and further reducing the power consumption of the semiconductor device.

[0041] Further, the difference between the first dimension and the second dimension may be of the same order of magnitude as the third dimension, and the difference between the fourth dimension and the second dimension may be of the same order of magnitude as the third dimension. Among them, the difference between the first dimension and the second dimension may be understood as the width difference between the first part and the second part. The difference between the fourth dimension and the second dimension may be understood as the width difference between the third part and the second part. The third dimension may be used to indicate the size of the second part in the first direction, and may be understood as the depth of the second part. Then, it may be understood that the width difference between the first part and the second part and the depth of the second part may be of the same order of magnitude (e.g., nm level or um level). Similarly, the width difference between the third part and the second part and the depth of the second part may also be of the same order of magnitude (e.g., nm level or um level).

[0042] Furthermore, the difference between the first size and the second size may be greater than or equal to one quarter of the third size. In other words, the difference between the width of the first portion and the second portion may be greater than or equal to one quarter of the depth of the second portion.

[0043] Similarly, the difference between the fourth dimension and the second dimension may be greater than or equal to one quarter of the third dimension. That is, the width difference between the third portion and the second portion may also be greater than or equal to one quarter of the depth of the second portion.

[0044] Exemplarily, the width difference between the first portion and the second portion and the width difference between the third portion and the second portion may be greater than or equal to one third of the depth of the second portion.

[0045] In a possible implementation, the preparation method provided in the present application may further include: forming a first semiconductor layer on the substrate. The first semiconductor layer may serve as a drain or source of the semiconductor device.

[0046] Optionally, the first semiconductor layer may be located between the substrate and the first isolation layer. That is, the substrate, the first semiconductor layer, the first isolation layer, the first metal layer and the second isolation layer are stacked along the first direction.

[0047] In another possible implementation, the preparation method provided in the present application may further include: forming a second dielectric layer on the sidewall of the first groove along the first direction, and the second dielectric layer may be located between the third metal layer and the channel layer, and may serve as a gate dielectric layer of the semiconductor device.

[0048] In another possible implementation, the preparation method provided by the present application may further include: filling a first dielectric layer inside the first groove. Etching the first dielectric layer along the first direction (i.e., etching back the first dielectric layer) to form a second groove. Forming a second semiconductor layer inside the second groove. Forming a second metal layer on the second semiconductor layer. The second semiconductor layer and the second metal layer may constitute a source or a drain of the semiconductor device.

[0049] In a third aspect, the present application provides a chip, which may include a capacitor and a semiconductor device provided by the first aspect and possible implementations thereof. The capacitor and the semiconductor device may be electrically connected.

[0050] Optionally, the chip may be a logic chip or a memory chip.

[0051] In a fourth aspect, the present application provides an electronic device, which may include a circuit board and a chip provided by the third aspect and possible implementations thereof. The chip may be arranged on the circuit board.

[0052] It should be understood that the second to fourth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0055] Figure 2 is another schematic structural diagram of the semiconductor device 100 in an embodiment of the present application;

[0056] Figure 3 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0057] Figure 4 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0058] Figure 5 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0059] Figure 6 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0060] Figure 7 is a schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0061] Figure 8 is another schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0062] Fig. 9 is another schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0063] Fig.10 is another schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0064] Fig.11 is another schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0065] Fig.12 is another schematic structural diagram of the first groove F1 in the embodiment of the present application;

[0066] Fig.13 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0067] Fig.14 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0068] Fig.15 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0069] Fig.16 Schematic diagram of transfer characteristic curves of semiconductor devices provided in embodiments of the present application and semiconductor devices provided in related technologies;

[0070] Fig.17 is a schematic flow chart of the preparation process 200 in an embodiment of the present application;

[0071] Fig.18 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0072] Fig.19 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0073] Fig. 20 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0074] Fig.21 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0075] Fig. 22 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0076] Fig.23 is another schematic flow chart of the preparation process 200 in the embodiment of the present application;

[0077] Fig.24 is a schematic flow chart of the preparation process 300 in an embodiment of the present application;

[0078] Fig.25 is a schematic flow chart of the preparation process 400 in an embodiment of the present application;

[0079] Fig.26 is a schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0080] Fig. 27 is another schematic structural diagram of a semiconductor device 100 in an embodiment of the present application;

[0081] Fig.28 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0082] Fig.29 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0083] Fig.30 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0084] Fig.31 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0085] Fig.32 is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application;

[0086] Fig.33 This is another schematic structural diagram of the semiconductor device 100 in the embodiment of the present application. DETAILED DESCRIPTION

[0087] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0088] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0089] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0090] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0091] With the rapid development of semiconductor technology, semiconductor devices (such as transistors, etc.) used in logic chips, memory chips, etc. have been widely used. Semiconductor devices often have leakage current in the off state, which will affect the performance of semiconductor devices, and thus have an important impact on the performance of chips. For logic chips, excessive leakage current will cause large static losses in logic chips. Since static losses account for a large proportion of the total power consumption of logic chips, logic chips will heat up due to the large total power consumption, which will affect the reliability of logic chips. For memory chips, excessive leakage current will increase the probability of failure to read and write data in the memory cells of the memory chips, causing the loss of stored data, which will also affect the reliability of logic chips.

[0092] In order to overcome the above-mentioned shortcomings, the present application provides a semiconductor device, such as Figures 1 to 6 The semiconductor device 100 may include a substrate 1, a first isolation layer 2, a first metal layer 3, a second isolation layer 4 and a channel layer 5. The first metal layer 3 may be used as a gate of the semiconductor device 100.

[0093] Optionally, the substrate 1, the first isolation layer 2, the first metal layer 3 and the second isolation layer 4 may be stacked along a first direction. Figure 1 Vertical orientation shown.

[0094] like Figures 7 to 9 As shown, the semiconductor device 100 may further include a first groove F1. The first groove F1 may penetrate the second isolation layer 4, the first metal layer 3 and the first isolation layer 2. It can be seen that the first groove F1 may be arranged along the first direction, that is, the depth direction of the first groove F1 is consistent with the first direction.

[0095] The cross section of the first groove F1 in the first direction may be defined as a first cross section. Then, the first cross section may be an I-shaped cross section, such as Figure 7The first cross section can also be a regular T-shape, such as Figure 8 Of course, the first cross section can also be an inverted T-shape, such as Fig. 9 That is, the first cross section may be T-shaped or I-shaped. The T-shape may be a positive T-shape or an inverted T-shape, which is not limited in the present embodiment. Figures 1 to 12 , the channel layer 5 may be disposed on the sidewall and the bottom of the first groove F1 .

[0096] In the semiconductor device 100 provided in the embodiment of the present application, since the channel layer 5 can be arranged on the sidewall and the bottom of the first groove F1, and the first cross section can be T-shaped or I-shaped, then, compared with the shell channel used in the semiconductor device with a vertical channel in the related art, the semiconductor device 100 provided in the embodiment of the present application increases the length of the channel layer 5, that is, increases Figures 1 to 6 In the portion of the channel layer 5 in the horizontal direction, when the semiconductor device 100 is in the off state, the electrons injected from the source into the channel layer 5 will be greatly reduced, thereby greatly reducing the leakage current of the semiconductor device 100 and further reducing the power consumption of the semiconductor device 100.

[0097] Optionally, the materials of the first isolation layer 2 and the second isolation layer 4 may include but are not limited to silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, etc., or any combination thereof. The materials of the channel layer 5 may include but are not limited to silicon, silicon germanium, silicon germanium tin, graphene, oxide semiconductors, III-V compound semiconductors, etc., or any combination thereof.

[0098] In a possible implementation, the semiconductor device 100 provided in the embodiment of the present application may further include a first semiconductor layer 6, such as Figures 1 to 6 As shown. The first semiconductor layer 6 may be located between the substrate 1 and the first isolation layer 2. That is, the substrate 1, the first semiconductor layer 6, the first isolation layer 2, the first metal layer 3 and the second isolation layer 4 may be stacked along a first direction. The first semiconductor layer 6 may serve as a drain or source of the semiconductor device 100, and the first metal layer 3 may serve as a gate of the semiconductor device 100.

[0099] Optionally, the material of the first semiconductor layer 6 may include, but is not limited to, silicon, germanium silicon, germanium tin silicon, oxide semiconductors, III-V compound semiconductors, etc., or any combination thereof. The material of the first metal layer 3 may include, but is not limited to, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, polysilicon, metal silicide, etc., or any combination thereof.

[0100] In one example, the semiconductor device 100 provided in the embodiment of the present application may further include a second dielectric layer 8, such as Figures 1 to 3The second dielectric layer 8 can be disposed inside the first groove F1 along the first direction, and the second dielectric layer 8 can be located between the first metal layer 3 and the channel layer 5. It can be understood that the second dielectric layer 8 can be used as a gate dielectric layer of the semiconductor device 100.

[0101] In another example, for Figures 4 to 6 In the semiconductor device 100 shown, the second dielectric layer 8 may include three parts, wherein the first part may be located between the first metal layer 3 and the channel layer 5, the second part may be located between the first isolation layer 2 and the first metal layer 3, and the third part may be located between the first metal layer 3 and the second isolation layer 4.

[0102] Optionally, the material of the second dielectric layer 8 may include but is not limited to silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium dioxide, yttrium oxide, silicon nitride, etc., or any combination thereof.

[0103] Below Figures 1 to 3 Taking the semiconductor device 100 as an example, the first groove F1 is described in detail.

[0104] like Figures 7 to 9 As shown, the bottom of the first groove F1 may be located at the first surface of the first semiconductor layer 6. Of course, the bottom of the first groove F1 may be located inside the first semiconductor layer 6, which is not limited in the present embodiment. The first surface may be used to indicate the surface of the first semiconductor layer 6 away from the substrate 1, i.e. Figures 7 to 12 The upper surface of the first semiconductor device 6.

[0105] In some embodiments, Fig.10 As shown, the first groove F1 may include a first portion A1, a second portion A2, and a third portion A3 that are sequentially connected along the first direction. Figure 7 , the first portion A1 may be located inside the first isolation layer 2, the second portion A2 may be located inside the first metal layer 3, and the third portion A3 may be located inside the second isolation layer 4. It is conceivable that the first portion A1, the second portion A2, and the third portion A3 may constitute a first groove F1 having an I-shaped first cross section, that is, Figure 7 The first groove F1 is shown.

[0106] For example, a direction perpendicular to the first direction may be defined as the second direction. In the embodiment of the present application, the second direction may be a horizontal direction. Fig.10As shown, the size of the first part A1 in the second direction can be defined as the first size L1, and the first size L1 can be understood as the width of the first part A1. The size of the second part A2 in the second direction can be defined as the second size L2, and the second size L2 can be understood as the width of the second part A2. The size of the third part A3 in the second direction can also be defined as the fourth size L4, and the fourth size L4 can be understood as the width of the third part A3.

[0107] Alternatively, if Fig.10 As shown, the first dimension L1 and the fourth dimension L4 can be greater than the second dimension L2. It can be seen that the first cross section can be an I-shaped. Figure 1 The channel layer 5 can be arranged on the sidewall and bottom of the first groove F1, and the total length of the channel layer 5 in the first part A1, the second part A2 and the third part A3 is further increased, thereby reducing the leakage current of the semiconductor device 100 and further reducing the power consumption of the semiconductor device 100.

[0108] Furthermore, if Fig.10 As shown, the dimension of the second portion A2 in the first direction may be defined as a third dimension L3, which may be understood as the depth of the second portion A2.

[0109] The difference between the first dimension L1 and the second dimension L2 may be of the same order of magnitude as the third dimension L3, and the difference between the fourth dimension L4 and the second dimension L2 may also be of the same order of magnitude as the third dimension L3. The difference between the first dimension L1 and the second dimension L2 may be understood as the width difference between the first portion A1 and the second portion A2. The difference between the fourth dimension L4 and the second dimension L2 may be understood as the width difference between the third portion A3 and the second portion A2. Then, it can be understood that the width difference between the first portion A1 and the second portion A2 and the depth of the second portion A2 may be of the same order of magnitude (e.g., nm level or um level). Similarly, the width difference between the third portion A3 and the second portion A2 and the depth of the second portion A2 may also be of the same order of magnitude (e.g., nm level or um level).

[0110] Furthermore, the difference between the first size L1 and the second size L2 may be greater than or equal to one quarter of the third size L3. That is, the difference between the widths of the first portion A1 and the second portion A2 may be greater than or equal to one quarter of the depth of the second portion A2.

[0111] Similarly, the difference between the fourth dimension L4 and the second dimension L2 may be greater than or equal to one quarter of the third dimension L3. That is, the width difference between the third portion A3 and the second portion A2 may also be greater than or equal to one quarter of the depth of the second portion A2.

[0112] Exemplarily, the width difference between the first portion A1 and the second portion A2 and the width difference between the third portion A3 and the second portion A2 may be greater than or equal to one third of the depth of the second portion A2.

[0113] In other examples, such as Fig.11 and Fig.12 As shown, the first groove F1 may include a first portion A1 and a second portion A2 communicating along the first direction.

[0114] refer to Fig.11 , the first portion A1 may be located inside the second isolation layer 4, and the second portion A2 may be located inside the first metal layer 3. It is conceivable that the first portion A1 and the second portion A2 may constitute a first groove F1 having a first cross section in the shape of a regular T, that is, Figure 8 The first groove F1 is shown.

[0115] refer to Fig.12 , the first portion A1 may be located inside the first isolation layer 2, and the second portion A2 may be located inside the first metal layer 3. It is conceivable that the first portion A1 and the second portion A2 may constitute a first groove F1 having a first cross-section in the shape of an inverted T, that is, Fig. 9 The first groove F1 is shown.

[0116] For example, Fig.11 and Fig.12 As shown, the first dimension L1 may be greater than the second dimension L2. It can be seen that the first cross section may be a regular T-shape. Figure 2 and Figure 3 The channel layer 5 may be disposed on the sidewall and the bottom of the first groove F1 , and the total length of the channel layer 5 in the first portion A1 and the second portion A2 is increased, thereby reducing the leakage current of the semiconductor device 100 , and further reducing the power consumption of the semiconductor device 100 .

[0117] Further, the difference between the first size L1 and the second size L2 can be of the same order of magnitude as the third size L3. The difference between the first size L1 and the second size L2 can be understood as the width difference between the first part A1 and the second part A2. Then, it can be understood that the width difference between the first part A1 and the second part A2 and the depth of the second part A2 can be of the same order of magnitude (for example, nm level or um level).

[0118] Furthermore, the difference between the first size L1 and the second size L2 may be greater than or equal to one quarter of the third size L3. That is, the difference between the widths of the first portion A1 and the second portion A2 may be greater than or equal to one quarter of the depth of the second portion A2.

[0119] For example, the width difference between the first portion A1 and the second portion A2 may be greater than or equal to one third of the depth of the second portion A2.

[0120] In a possible implementation, the semiconductor device 100 provided in the embodiment of the present application may further include a first dielectric layer 7, such as Figures 1 to 3 The first dielectric layer 7 may be located inside the first groove F1.

[0121] Optionally, the material of the first dielectric layer 7 may include but is not limited to silicon oxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, etc., or any combination thereof.

[0122] Further, Figures 1 to 3 Taking the semiconductor device 100 shown in FIG. 1 as an example, the first dielectric layer 7 may include a second groove F2, such as Figures 13 to 15 The semiconductor device 100 may further include a second semiconductor layer 9 and a second metal layer 10 stacked along the first direction, as shown in FIG. Figures 1 to 3 As shown. Combined Figures 1 to 3 as well as Figures 13 to 15 As shown, the second semiconductor layer 9 may be located inside the second groove F2 . The second semiconductor layer 9 and the second metal layer 10 may constitute a source or a drain of the semiconductor device 100 .

[0123] Optionally, the material of the second semiconductor layer 9 may include but is not limited to silicon, germanium silicon, germanium tin silicon, oxide semiconductor, III-V compound semiconductor, etc., or any combination thereof. The material of the second metal layer 10 may include but is not limited to metal silicide, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof.

[0124] Of course, the semiconductor device 100 may also include other material layers, which is not limited in the embodiment of the present application.

[0125] The semiconductor device provided in the embodiment of the present application and the semiconductor device including the shell channel provided in the related art are simulated respectively, and the following results are obtained: Fig.16 Schematic diagram of the transfer characteristic curve of the semiconductor device shown. Fig.16In the figure, the horizontal axis represents the gate voltage Vg, and the unit can be V. The vertical axis represents the drain current, and the unit can be uA. Curve F2 represents the drain current of the semiconductor device provided in the embodiment of the present application when the voltage Vds between the drain and the source is in the linear region (such as 0.1V), and curve F1 represents the drain current of the semiconductor device provided in the related art when the voltage Vds between the drain and the source is in the linear region (such as 0.1V). Curve F4 represents the drain current of the semiconductor device provided in the embodiment of the present application when the voltage Vds between the drain and the source is in the saturation region (such as 1V), and curve F3 represents the drain current of the semiconductor device provided in the related art when the voltage Vds between the drain and the source is in the saturation region (such as 1V). By comparison, it can be found that the drain current (i.e., on-state current) of the semiconductor device provided in the embodiment of the present application and the semiconductor device provided in the related technology in the on state is not much different, but the subthreshold swing of curve F4 is significantly lower than that of curve F3. Therefore, it can be determined that the leakage current of the semiconductor device provided in the embodiment of the present application is significantly reduced, and the gate has a stronger control ability over the channel layer, which is beneficial to reducing the power consumption of the semiconductor device.

[0126] The present application also provides a method for preparing a semiconductor device 100, such as Fig.17 The preparation process 200 may include the following steps:

[0127] Step S201: forming a first isolation layer 2, a first metal layer 3 and a second isolation layer 4 on a substrate 1 along a first direction, such as Fig.18 The first metal layer 3 can be used as a gate of the semiconductor device 100 .

[0128] Step S202: Etching the second isolation layer 4, the first metal layer 3 and the first sacrificial layer 2 to form a first groove F1. Figures 7 to 9 shown.

[0129] Step S203: forming a channel layer 5 on the sidewall and bottom of the first groove F1, such as Figures 19 to 21 shown.

[0130] Optionally, the first groove F1 may penetrate the second isolation layer 4, the first metal layer 3 and the first isolation layer 1. It can be seen that the first groove F1 is arranged along the first direction, that is, the depth direction of the first groove F1 is consistent with the first direction. The cross section of the first groove F1 in the first direction can be defined as a first cross section. Then, the first cross section can be an I-shaped cross section, such as Figure 7 The first cross section can also be a regular T-shape, such as Figure 8 Of course, the first cross section can also be an inverted T-shape, such as Fig. 9That is to say, the first cross section may be T-shaped or I-shaped. The T-shape may be a regular T-shape or an inverted T-shape, which is not limited in the present embodiment.

[0131] In the preparation process 200 of the semiconductor device 100 provided in the embodiment of the present application, since the channel layer 5 can be disposed on the sidewall and the bottom of the first groove F1, and the first cross section can be T-shaped or I-shaped, the length of the channel layer 5 is increased, that is, the length of the channel layer 5 is increased. Figures 1 to 6 In the portion of the channel layer 5 in the horizontal direction, the increase in the channel length can put the semiconductor device in an off state, and the electrons injected from the source into the channel layer 5 will be greatly reduced, thereby greatly reducing the leakage current of the semiconductor device 100, and further reducing the power consumption of the semiconductor device 100.

[0132] In some embodiments, the preparation process 200 provided in the embodiments of the present application may further include: forming a first semiconductor layer 6 on the substrate 1. The first semiconductor layer 7 may serve as a drain or a source of the semiconductor device 100.

[0133] Alternatively, if Fig.18 , the first semiconductor layer 6 may be located between the substrate 1 and the first isolation layer 2. That is, the substrate 1, the first semiconductor layer 6, the first isolation layer 2, the first metal layer 3 and the second isolation layer 4 may be stacked along the first direction.

[0134] In some other embodiments, in the above step S202, etching the second isolation layer 4, the first metal layer 3 and the first sacrificial layer 2 to form the first groove F1 may include:

[0135] Step S202A: Etching the second isolation layer 4, the first metal layer 3 and the first sacrificial layer 2 along the first direction to form a third groove F3. Fig. 22 shown.

[0136] Step S202B: etching the first isolation layer 2 and / or the second isolation layer 4 along the second direction through the third groove F3 to form a first groove F1. The second direction may be perpendicular to the first direction.

[0137] It is conceivable that the first isolation layer 2 and the second isolation layer 4 are etched respectively along the second direction, and the first cross section of the formed first groove F1 may be an I-shape, such as Figure 7 The second isolation layer 4 is etched along the second direction, and the first cross section of the formed first groove F1 may be a regular T-shape, such as Figure 8 The first isolation layer 2 is etched along the second direction, and the first cross section of the formed first groove F1 may be an inverted T-shape, such as Fig. 9 shown.

[0138] Continue to refer Figures 7 to 9 , the bottom of the first groove F1 may be located at the first surface of the first semiconductor layer 6. Of course, the bottom of the first groove F1 may be located inside the first semiconductor layer 6, which is not limited in the present embodiment. The first surface may be used to indicate the surface of the first semiconductor layer 6 away from the substrate 1, that is, Figures 7 to 12 The upper surface of the first semiconductor device 6.

[0139] In some embodiments, Fig.10 As shown, the first groove F1 may include a first portion A1, a second portion A2, and a third portion A3 that are sequentially connected along the first direction. Figure 7 , the first portion A1 may be located inside the first isolation layer 2, the second portion A2 may be located inside the first metal layer 3, and the third portion A3 may be located inside the second isolation layer 4. It is conceivable that the first portion A1, the second portion A2, and the third portion A3 may constitute a first groove F1 having an I-shaped first cross section, that is, Figure 7 The first groove F1 is shown.

[0140] For example, a direction perpendicular to the first direction may be defined as the second direction. In the embodiment of the present application, the second direction may be a horizontal direction. Fig.10 As shown, the size of the first part A1 in the second direction can be defined as the first size L1, and the first size L1 can be understood as the width of the first part A1. The size of the second part A2 in the second direction can be defined as the second size L2, and the second size L2 can be understood as the width of the second part A2. The size of the third part A3 in the second direction can also be defined as the fourth size L4, and the fourth size L4 can be understood as the width of the third part A3.

[0141] Alternatively, if Fig.10 As shown, the first dimension L1 and the fourth dimension L4 can be greater than the second dimension L2. It can be seen that the first cross section can be an I-shaped. Figure 1 The channel layer 5 can be arranged on the sidewall and bottom of the first groove F1, and the total length of the channel layer 5 in the first part A1, the second part A2 and the third part A3 is further increased, thereby reducing the leakage current of the semiconductor device 100 and further reducing the power consumption of the semiconductor device 100.

[0142] Furthermore, if Fig.10 As shown, the dimension of the second portion A2 in the first direction may be defined as a third dimension L3, which may be understood as the depth of the second portion A2.

[0143] The difference between the first dimension L1 and the second dimension L2 may be of the same order of magnitude as the third dimension L3, and the difference between the fourth dimension L4 and the second dimension L2 may also be of the same order of magnitude as the third dimension L3. The difference between the first dimension L1 and the second dimension L2 may be understood as the width difference between the first portion A1 and the second portion A2. The difference between the fourth dimension L4 and the second dimension L2 may be understood as the width difference between the third portion A3 and the second portion A2. Then, it can be understood that the width difference between the first portion A1 and the second portion A2 and the depth of the second portion A2 may be of the same order of magnitude (e.g., nm level or um level). Similarly, the width difference between the third portion A3 and the second portion A2 and the depth of the second portion A2 may also be of the same order of magnitude (e.g., nm level or um level).

[0144] Furthermore, the difference between the first size L1 and the second size L2 may be greater than or equal to one quarter of the third size L3. That is, the difference between the widths of the first portion A1 and the second portion A2 may be greater than or equal to one quarter of the depth of the second portion A2.

[0145] Similarly, the difference between the fourth dimension L4 and the second dimension L2 may be greater than or equal to one quarter of the third dimension L3. That is, the width difference between the third portion A3 and the second portion A2 may also be greater than or equal to one quarter of the depth of the second portion A2.

[0146] Exemplarily, the width difference between the first portion A1 and the second portion A2 and the width difference between the third portion A3 and the second portion A2 may be greater than or equal to one third of the depth of the second portion A2.

[0147] In other examples, such as Fig.11 and Fig.12 As shown, the first groove F1 may include a first portion A1 and a second portion A2 communicating along the first direction.

[0148] refer to Fig.11 , the first portion A1 may be located inside the second isolation layer 4, and the second portion A2 may be located inside the first metal layer 3. It is conceivable that the first portion A1 and the second portion A2 may constitute a first groove F1 having a first cross section in the shape of a regular T, that is, Figure 8 The first groove F1 is shown.

[0149] refer to Fig.12 , the first portion A1 may be located inside the first isolation layer 2, and the second portion A2 may be located inside the first metal layer 3. It is conceivable that the first portion A1 and the second portion A2 may constitute a first groove F1 having a first cross-section in the shape of an inverted T, that is, Fig. 9 The first groove F1 is shown.

[0150] For example, Fig.11 and Fig.12 As shown, the first dimension L1 may be greater than the second dimension L2. It can be seen that the first cross section may be a regular T-shape. Figure 2 and Figure 3 The channel layer 5 may be disposed on the sidewall and the bottom of the first groove F1 , and the total length of the channel layer 5 in the first portion A1 and the second portion A2 is increased, thereby reducing the leakage current of the semiconductor device 100 , and further reducing the power consumption of the semiconductor device 100 .

[0151] Further, the difference between the first size L1 and the second size L2 may be of the same order of magnitude as the third size L3. The difference between the first size L1 and the second size L2 may be understood as the width difference between the first portion A1 and the second portion A2. Then, it can be understood that the width difference between the first portion A1 and the second portion A2 and the depth of the second portion A2 may be of the same order of magnitude (e.g., nm level or um level).

[0152] Furthermore, the difference between the first size L1 and the second size L2 may be greater than or equal to one quarter of the third size L3. That is, the difference between the widths of the first portion A1 and the second portion A2 may be greater than or equal to one quarter of the depth of the second portion A2.

[0153] For example, the width difference between the first portion A1 and the second portion A2 may be greater than or equal to one third of the depth of the second portion A2.

[0154] In some embodiments, Fig.23 As shown, the preparation process 200 provided in the embodiment of the present application may further include the following steps before step S203:

[0155] Step S204: forming a second dielectric layer 8 on the sidewall of the first groove F1 along the first direction. Figures 19 to 21 The second dielectric layer 8 may be located between the third metal layer 3 and the channel layer 5 , and may serve as a gate dielectric layer of the semiconductor device 100 .

[0156] In some other embodiments, Fig.23 As shown, the preparation process 200 provided in the embodiment of the present application may further include the following steps after step 203:

[0157] Step S205: Fill the first groove F1 with the first dielectric layer 7. Figures 19 to 21 shown.

[0158] Step S206: Etching the first dielectric layer 7 along the first direction (ie, etching back the first dielectric layer 7) to form a second groove F2. Figures 13 to 15 shown.

[0159] Step S207: forming a second semiconductor layer 9 inside the second groove F2.

[0160] Step S208: forming a second metal layer 10 on the second semiconductor layer 9, such as Figures 1 to 3 The second semiconductor layer 9 and the second metal layer 10 may constitute a source or a drain of the semiconductor device 100 .

[0161] The present application also provides a method for preparing a semiconductor device 100, such as Fig.24 The preparation process 300 may include the following steps:

[0162] Step S301: forming a first semiconductor layer 6, a first isolation layer 2, a first metal layer 3 and a second isolation layer 4 in sequence on a substrate 1 along a first direction. Fig.18 The first metal layer 3 can be used as a gate of the semiconductor device 100 .

[0163] It can be imagined that the size of the first metal layer 3 in the first direction (which can be understood as the thickness of the first metal layer 3 ) can determine the size of the channel layer 5 in the first direction.

[0164] Step S302: Etching the second isolation layer 4, the first metal layer 3 and the first sacrificial layer 2 along the first direction to form a third groove F3. Fig. 22 shown.

[0165] Step S303: etching the first isolation layer 2 and the second isolation layer 4 along the second direction through the third groove F3 to form a first groove F1. Figure 7 shown.

[0166] It can be understood that the first isolation layer 2 and the second isolation layer 4 can be etched by a dry etching process or a wet etching process using the etching selectivity of different materials used in the first isolation layer 2, the second isolation layer 4 and the first metal layer 3. The size of the first isolation layer 2 and the second isolation layer 4 etched in the second direction can determine the size of the channel layer 5 in the second direction.

[0167] The present embodiment of the application takes etching of the first isolation layer 2 and the second isolation layer 4 as an example for explanation. Of course, the first isolation layer 2 or the second isolation layer 4 can also be etched to form a first groove F1 with a first cross section of a regular T-shape or an inverted T-shape, which is not limited in the present embodiment of the application.

[0168] Step S304: forming a second dielectric layer 8 on the sidewall of the first groove F1 along the first direction. Fig.19 shown.

[0169] Step S305: forming a channel layer 5 on the sidewall and bottom of the first groove F1. Fig.19shown.

[0170] Step S306: Fill the first groove F1 with the first dielectric layer 7. Fig.19 shown.

[0171] Step S307: Etching the first dielectric layer 7 along the first direction to form a second groove F2. Fig.13 shown.

[0172] Step S308: forming a second semiconductor layer 9 inside the second groove F2.

[0173] Step S309: forming a second metal layer 10 on the second semiconductor layer 9, such as Figure 1 shown.

[0174] The present application also provides another method for preparing a semiconductor device 100. Fig.25 The preparation process 400 may include the following steps:

[0175] Step S401: forming a first semiconductor layer 6, a first isolation layer 2, a sacrificial layer 11 and a second isolation layer 4 in sequence on a substrate 1 along a first direction. Fig.26 shown.

[0176] It is conceivable that the size of the sacrificial layer 11 in the first direction (which can be understood as the thickness of the sacrificial layer 11 ) can determine the size of the channel layer 5 in the first direction.

[0177] Step S402: Etching the second isolation layer 4, the sacrificial layer 11 and the first sacrificial layer 2 along the first direction to form a third groove F3. Fig. 27 shown.

[0178] Step S403: etching the first isolation layer 2 and the second isolation layer 4 along the second direction through the third groove F3 to form a first groove F1. Fig.28 shown.

[0179] It can be understood that the first isolation layer 2 and the second isolation layer 4 can be etched by a dry etching process or a wet etching process using the etching selectivity of different materials used in the first isolation layer 2, the second isolation layer 4 and the sacrificial layer 11. The size of the first isolation layer 2 and the second isolation layer 4 etched in the second direction can determine the size of the channel layer 5 in the second direction.

[0180] The present embodiment of the application takes etching of the first isolation layer 2 and the second isolation layer 4 as an example for explanation. Of course, the first isolation layer 2 or the second isolation layer 4 can also be etched to form a first groove F1 with a first cross section of a regular T-shape or an inverted T-shape, which is not limited in the present embodiment of the application.

[0181] Step S404: forming a channel layer 5 on the sidewall and bottom of the first groove F1. Fig.29 shown.

[0182] Step S405: Fill the first groove F1 with a first dielectric layer 7, such as Fig.29 shown.

[0183] Step S406: Etching the sacrificial layer 11 along the second direction to remove the sacrificial layer 11. Fig.30 shown.

[0184] Step S407: forming a second dielectric layer 8 and a first metal layer 3 along the second direction at the position where the sacrificial layer 11 is removed, such as Fig.31 The first metal layer 3 can be used as a gate of the semiconductor device 100 .

[0185] Step S408: Etching the first dielectric layer 7 along the first direction to form a second groove F2. Fig.32 shown.

[0186] Step S409: forming a second semiconductor layer 9 inside the second groove F2.

[0187] Step S410: forming a second metal layer 10 on the second semiconductor layer 9, such as Figure 4 shown.

[0188] It is conceivable that in step S401, multiple sacrificial layers and multiple isolation layers may be formed, and the multiple sacrificial layers and the multiple isolation layers may be alternately stacked, so that the channel layers at multiple positions may increase in size in the second direction, respectively, and a zigzag channel layer may be formed, and finally a semiconductor device 100 may be obtained, such as Fig.33 Of course, a channel layer of a shape can also be formed by a similar technical solution, and the total length of the channel layer can be increased without changing the size of the semiconductor device 100 in the first direction (which can be understood as the height of the semiconductor device 100), thereby further reducing the leakage current of the semiconductor device 100.

[0189] By comparing the preparation process 300 and the preparation process 400, it can be found that the preparation process 300 forms the gate first and then forms the channel layer, while the preparation process 400 forms the channel layer first and then forms the gate. Therefore, whether the preparation process 300 or the preparation process 400, or other preparation processes, the preparation of the semiconductor device can be achieved, and the embodiments of the present application are not limited thereto.

[0190] It should be understood that in various embodiments of the present application, the order of execution of the above processes does not mean the order of execution, and the order of execution of the processes does not constitute any limitation on the implementation process of the embodiments of the present application. In other words, the embodiments of the present application do not limit the order of steps, as long as the preparation of the semiconductor device 100 can be achieved.

[0191] The embodiment of the present application further provides a chip, which may include a capacitor and the semiconductor device 100. The capacitor and the semiconductor device 100 may be electrically connected.

[0192] Optionally, the chip can be a logic chip or a memory chip. Since the leakage current of the semiconductor device 100 provided in the embodiment of the present application is greatly reduced, the static power consumption of the logic chip is relatively small. Since the static power consumption accounts for a large proportion of the total power consumption of the logic chip, the total power consumption of the logic chip will also decrease as the static power consumption decreases, thereby improving the performance and reliability of the logic chip. At the same time, the semiconductor device, as a gate tube of the storage unit in the memory chip, can reduce the probability of failure of the storage unit to read and write data, avoid the loss of stored data as much as possible, and thus improve the reliability of the memory chip.

[0193] The embodiment of the present application further provides an electronic device, which may include a circuit board and a chip. The chip may be arranged on the circuit board.

[0194] Optionally, the electronic device may be a mobile phone, a computer, etc. Of course, the electronic device may also be other devices, which is not limited in the embodiments of the present application.

[0195] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: comprising a substrate, a first isolation layer, a first metal layer, a second isolation layer and a channel layer; Wherein, the substrate, the first isolation layer, the first metal layer and the second isolation layer are stacked along a first direction; The semiconductor device also includes a first groove, which runs through the second isolation layer, the first metal layer and the first isolation layer, and the first cross-section of the first groove is T-shaped or I-shaped, wherein the first cross-section is used to indicate the cross-section of the first groove in the first direction; the channel layer is arranged on the sidewall and bottom of the first groove.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a first semiconductor layer; The first semiconductor layer is located between the substrate and the first isolation layer, and serves as a drain or a source of the semiconductor device.

3. The semiconductor device according to claim 2, characterized in that The bottom of the first groove is located on a first surface or inside of the first semiconductor layer; wherein the first surface is used to indicate a surface of the first semiconductor layer away from the substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first groove includes a first portion and a second portion connected along the first direction; wherein the first portion is located inside the first isolation layer or inside the second isolation layer, and the second portion is located inside the first metal layer; The first size is greater than the second size; wherein the first size is used to indicate the size of the first part in a second direction, and the second size is used to indicate the size of the second part in the second direction, and the second direction is perpendicular to the first direction.

5. The semiconductor device according to claim 4, characterized in that The difference between the first size and the second size is of the same order of magnitude as a third size; wherein the third size is used to indicate the size of the second portion in the first direction.

6. The semiconductor device according to claim 5, characterized in that The difference between the first size and the second size is greater than or equal to one quarter of the third size.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that The first groove includes a first portion, a second portion and a third portion that are sequentially connected along the first direction; wherein the first portion is located inside the first isolation layer, the second portion is located inside the first metal layer, and the third portion is located inside the second isolation layer; The first size and the fourth size are both larger than the second size, wherein the first size is used to indicate the size of the first part in the second direction, the second size is used to indicate the size of the second part in the second direction, and the fourth size is used to indicate the size of the third part in the second direction, and the second direction is perpendicular to the first direction.

8. The semiconductor device according to claim 7, characterized in that The difference between the first size and the second size is of the same order of magnitude as the third size, and the difference between the fourth size and the second size is of the same order of magnitude as the third size; wherein the third size is used to indicate the size of the second part in the first direction.

9. The semiconductor device according to claim 8, characterized in that The difference between the first size and the second size is greater than or equal to one quarter of the third size, and the difference between the fourth size and the second size is greater than or equal to one quarter of the third size.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The semiconductor device further includes a first dielectric layer, and the first dielectric layer is located inside the first groove.

11. The semiconductor device according to claim 10, characterized in that The first dielectric layer includes a second groove, and the semiconductor device also includes a second semiconductor layer and a second metal layer; The second semiconductor layer and the second metal layer are stacked along the first direction, the second semiconductor layer is located inside the second groove, and the second semiconductor layer and the second metal layer constitute a source or a drain of the semiconductor device.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that The semiconductor device further includes a second dielectric layer, which is arranged inside the first groove along the first direction and between the first metal layer and the channel layer.

13. A method for preparing a semiconductor device, characterized in that: include: forming a first isolation layer, a first metal layer, and a second isolation layer on the substrate along a first direction; The second isolation layer, the first metal layer and the first sacrificial layer are etched to form a first groove; wherein the first groove penetrates the second isolation layer, the first metal layer and the first isolation layer, and a first cross section of the first groove is T-shaped or I-shaped, wherein the first cross section is used to indicate a cross section of the first groove in the first direction; A channel layer is formed on the sidewall and bottom of the first groove.

14. The preparation method according to claim 13, characterized in that: The etching the second isolation layer, the first metal layer and the first sacrificial layer to form a first groove comprises: Etching the second isolation layer, the first metal layer and the first sacrificial layer along the first direction to form a third groove; The first isolation layer and / or the second isolation layer is etched along a second direction through the third groove to form the first groove; wherein the second direction is perpendicular to the first direction.

15. The preparation method according to claim 13 or 14, characterized in that: The first groove includes a first portion and a second portion connected along the first direction; wherein the first portion is located inside the first isolation layer or inside the second isolation layer, and the second portion is located inside the first metal layer; The first size is greater than the second size; wherein the first size is used to indicate the size of the first part in a second direction, and the second size is used to indicate the size of the second part in the second direction, and the second direction is perpendicular to the first direction.

16. The preparation method according to claim 15, characterized in that: The difference between the first size and the second size is of the same order of magnitude as a third size; wherein the third size is used to indicate the size of the second portion in the first direction.

17. The preparation method according to claim 16, characterized in that: The difference between the first size and the second size is greater than or equal to one quarter of the third size.

18. The preparation method according to claim 13 or 14, characterized in that: The first groove includes a first portion, a second portion and a third portion that are sequentially connected along the first direction; wherein the first portion is located inside the first isolation layer, the second portion is located inside the first metal layer, and the third portion is located inside the second isolation layer; The first size and the fourth size are both larger than the second size, wherein the first size is used to indicate the size of the first part in the second direction, the second size is used to indicate the size of the second part in the second direction, and the fourth size is used to indicate the size of the third part in the second direction, and the second direction is perpendicular to the first direction.

19. The preparation method according to claim 18, characterized in that: The difference between the first size and the second size is of the same order of magnitude as the third size, and the difference between the fourth size and the second size is of the same order of magnitude as the third size; wherein the third size is used to indicate the size of the second part in the first direction.

20. The preparation method according to claim 19, characterized in that: The difference between the first size and the second size is greater than or equal to one quarter of the third size, and the difference between the fourth size and the second size is greater than or equal to one quarter of the third size.

21. The preparation method according to any one of claims 13 to 20, characterized in that: The preparation method further comprises: A first semiconductor layer is formed on the substrate; wherein the first semiconductor layer is located between the substrate and the first isolation layer and serves as a drain or source of the semiconductor device.

22. The preparation method according to any one of claims 13 to 21, characterized in that The preparation method further comprises: A second dielectric layer is formed on the sidewall of the first groove along the first direction.

23. The preparation method according to any one of claims 13 to 22, characterized in that: The preparation method further comprises: Filling a first dielectric layer in the first groove; Etching the first dielectric layer along the first direction to form a second groove; forming a second semiconductor layer inside the second groove; A second metal layer is formed on the second semiconductor layer; wherein the second semiconductor layer and the second metal layer constitute a source or a drain of the semiconductor device.

24. A chip, characterized in that: The invention comprises a capacitor and a semiconductor device as claimed in any one of claims 1 to 12; the capacitor is electrically connected to the semiconductor device.

25. The chip according to claim 24, characterized in that: The chip is a logic chip or a memory chip.

26. An electronic device, characterized in that: It comprises a circuit board and a chip as claimed in claim 24 or 25; the chip is arranged on the circuit board.

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