A shallow channel super junction MOS semiconductor device and its preparation process

Abstract

The present invention relates to the field of MOS semiconductor technology, and discloses a shallow channel super junction MOS semiconductor device and its preparation process, including a drain, a source, a semiconductor epitaxial layer, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer includes an N substrate layer and a drift layer; the interior of the drift layer is formed with a P well layer, a P layer 2 and an N well layer by ion implantation; the cross section of the gate is in a 'T' shape; the interior of the N well layer is formed with a P layer 1 by ion implantation, and the interior of the drift layer and located between two adjacent P layers 2 is formed with a narrow heavily doped N layer by ion implantation. After the gate voltage is connected, the present invention forms a charge channel inside the P layer 2, so that the N well layer and the drift layer can form a path, and the existence of the P layer 1 will inhibit the charges flowing inside the N well layer from converging to the gate region, which can greatly reduce the number of parasitic charges, thereby improving the response speed of the MOS semiconductor device.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a shallow channel super junction MOS semiconductor device and a preparation process thereof. Background Art

[0002] Power semiconductor devices are indispensable electronic devices for any electronic system, and are mainly used in various power supplies and drive loads. With the upgrading of power semiconductor devices, new power semiconductor devices are gradually developing towards achieving benefits such as energy saving, material saving, environmental protection and miniaturization.

[0003] The existing patent discloses a shallow channel super junction MOS semiconductor power device (publication number CN212907744U), which includes: an N-type heavily doped substrate, an N-type lightly doped drift region on the N-type heavily doped substrate, an N-type heavily doped region and a P-type well region on the N-type lightly doped drift region, wherein the N-type heavily doped region is arranged in the middle of the P-type well region, an N-type lightly doped region on the P-type well region and close to the N-type heavily doped region, and an N-type heavily doped source region on the N-type lightly doped region. In the technology disclosed in the patent, under the action of the access gate electric field, since the radiation range of the gate electric field is often limited, it can only have a stronger effect on the drift layer of the JEFT region close to the gate, which makes part of the charge inside the drift layer move to the JEFT region to form a conduction charge, while the other part will flow to the adjacent MOS cells. This arbitrary flow of partial charge will reduce the response speed of the MOS device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a shallow channel super junction MOS semiconductor device and a preparation process thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a shallow channel super junction MOS semiconductor device comprises a drain, a source, a semiconductor epitaxial layer, a gate, and a gate oxide layer covering the surface of the gate, wherein the semiconductor epitaxial layer comprises an N substrate layer and a drift layer; a P well layer, a P-layer II and an N well layer are formed inside the drift layer by ion implantation;

[0006] The gate has a cross section in a 'T' shape; a P-layer 1 is formed inside the N-well layer by ion implantation.

[0007] Furthermore, a narrow heavily doped N layer is formed inside the drift layer and between two adjacent P-layers by ion implantation.

[0008] Furthermore, a wide heavily doped N layer is formed inside the drift layer and between two adjacent P-layers by ion implantation, wherein the wide heavily doped N layer penetrates the drift layer and contacts the N substrate layer.

[0009] Furthermore, the P-well layer further includes a wide P-well layer, and the wide P-well layer penetrates the drift layer and contacts the N substrate layer.

[0010] Furthermore, the cross-sectional thickness of the P-layer 2 is the same as the cross-sectional thickness of the gate oxide layer.

[0011] A process for preparing a shallow channel super junction MOS semiconductor device comprises the following steps:

[0012] S. Using chemical cleaning to remove the oxide layer on the surface of the semiconductor epitaxial layer;

[0013] S. Forming a P-well layer, an N-well layer, a P-layer 1 and a P-layer 2 inside the drift layer by using ion implantation technology;

[0014] S. Forming a narrow heavily doped N layer or a wide heavily doped N layer by injecting high concentration phosphorus ions inside the drift layer and below the gate;

[0015] S. Conducting electrical performance difference test between a semiconductor including a P-layer 1 and a standard semiconductor not including a P-layer 1;

[0016] S. After the semiconductor containing the P-layer 1 passes the test, it is packaged.

[0017] Furthermore, in step S, whether the semiconductor including the P-layer 1 is qualified is determined based on the absolute value of the threshold voltage difference, the absolute value of the saturation current difference, and the absolute value of the parasitic capacitance difference between the semiconductor including the P-layer 1 and the standard semiconductor not including the P-layer 1, as follows:

[0018]

[0019] In the formula, Represents the quality factor of the tested semiconductor containing a P-layer, It represents the absolute value of the threshold voltage difference between a semiconductor containing a P-layer and a standard semiconductor without a P-layer. It represents the absolute value of the saturation current difference between a semiconductor containing a P-layer and a standard semiconductor without a P-layer. It represents the absolute value of the difference in parasitic capacitance between a semiconductor containing a P-layer and a standard semiconductor without a P-layer.

[0020] Furthermore, when When , it means that the semiconductor containing P-layer 1 under test has excellent performance;

[0021] when When , it means that the performance of the tested semiconductor containing P-layer 1 is qualified;

[0022] when When , it means that the performance of the tested semiconductor containing P-layer 1 is unqualified.

[0023] Beneficial effects:

[0024] 1. After the gate voltage is connected, the present invention forms a charge channel inside the P-layer 2, so that the N-well layer and the drift layer can form a path, and the existence of the P-layer 1 will inhibit the charges flowing inside the N-well layer from gathering toward the gate area, which can greatly reduce the amount of parasitic charges, thereby improving the response speed of the MOS semiconductor device.

[0025] 2. The present invention provides a narrow heavily doped N layer with a higher ion concentration, which makes it easier for the charges flowing in the drift layer to diffuse into the narrow heavily doped N layer, thereby maximally reducing the resistance of the charge channel connecting the N well layer and the drift layer.

[0026] 3. The present invention can efficiently and conveniently determine whether the performance of a semiconductor containing P-layer one is qualified by measuring the absolute value of the threshold voltage difference, the absolute value of the saturation current difference, and the absolute value of the parasitic capacitance difference between the semiconductor containing P-layer one and the standard semiconductor not containing P-layer one. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention;

[0028] Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0030] Figure 4 It is a structural schematic diagram of embodiment 4 of the present invention.

[0031] In the figure: 1, drain; 2, source; 3, gate oxide layer; 4, gate; 5, N substrate layer; 6, drift layer; 7, P well layer; 8, N well layer; 9, P-layer one; 10, P-layer two; 11, narrow heavily doped N layer; 1101, wide heavily doped N layer; 71, wide P well layer. DETAILED DESCRIPTION

[0032] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] like Figure 1-4 As shown, a process for preparing a shallow channel super junction MOS semiconductor device comprises the following steps:

[0034] Step 1: using chemical cleaning to remove the oxide layer on the surface of the semiconductor epitaxial layer;

[0035] Step 2: using ion implantation technology to form a P-well layer 7, an N-well layer 8, a P-layer 1 9 and a P-layer 2 10 inside the drift layer;

[0036] Step 3: forming a narrow heavily doped N layer 11 or a wide heavily doped N layer 1101 inside the drift layer 6 and below the gate 4 by injecting high concentration phosphorus ions;

[0037] Step 4: Conducting an electrical performance difference test on the semiconductor including the P-layer 9 and the standard semiconductor not including the P-layer 9;

[0038] Step 5: After the semiconductor including the P-layer 9 passes the test, it is packaged.

[0039] Whether the semiconductor including the P-layer 9 is qualified is determined based on the absolute value of the threshold voltage difference, the absolute value of the saturation current difference, and the absolute value of the parasitic capacitance difference between the semiconductor including the P-layer 9 and the standard semiconductor not including the P-layer 9, as follows:

[0040]

[0041] In the formula, Indicates the quality factor of the tested P-layer-9 semiconductor, represents the absolute value of the threshold voltage difference between a semiconductor containing a P-layer-9 and a standard semiconductor without a P-layer-9, It represents the absolute value of the saturation current difference between the semiconductor containing P-layer-9 and the standard semiconductor without P-layer-9. It represents the absolute value of the parasitic capacitance difference between a semiconductor containing a P-layer 9 and a standard semiconductor without a P-layer 9.

[0042] when When , it means that the semiconductor containing P-layer 9 tested has excellent performance;

[0043] when When , it means that the performance of the tested semiconductor containing P-layer 9 is qualified;

[0044] when When , it means that the performance of the semiconductor containing P-layer 9 tested is unqualified

[0045] The performance test is performed on any semiconductor device X. The absolute value of the threshold voltage difference between the semiconductor containing the P-layer-9 and the standard semiconductor without the P-layer-9 is taken as (Unit: V, absolute value of threshold voltage difference = |threshold voltage of semiconductor containing P-layer 9 - threshold voltage of semiconductor excluding P-layer 9|).

[0046] The absolute value of the saturation current difference between the semiconductor containing the P-layer-9 and the standard semiconductor without the P-layer-9 is (Unit: mA, absolute value of saturation current difference = |saturation current of semiconductor containing P-layer-9 - saturation current of semiconductor excluding P-layer-9|).

[0047] The absolute value of the parasitic capacitance difference between a semiconductor containing a P-layer and a standard semiconductor without a P-layer is (Unit: pF, absolute value of parasitic capacitance difference = |parasitic capacitance of semiconductor with P-layer 9 - parasitic capacitance of semiconductor without P-layer 9|). Then:

[0048]

[0049] From the above calculation, we can know that the quality coefficient of the detected semiconductor X is , that is, the performance of the tested semiconductor X containing the P-layer 9 is qualified.

[0050] Example 1

[0051] like Figure 1 As shown, a shallow channel super junction MOS semiconductor device includes a drain 1, a source 2, a semiconductor epitaxial layer, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4, wherein the semiconductor epitaxial layer includes an N substrate layer 5 and a drift layer 6; a P-well layer 7, a P-layer 10 and an N-well layer 8 are formed inside the drift layer 6 by ion implantation; the cross-sectional thickness of the P-layer 10 is the same as the cross-sectional thickness of the gate oxide layer 3. The cross-sectional shape of the gate 4 is 'T'; a P-layer 1 9 is formed inside the N-well layer 8 by ion implantation. After the gate voltage is connected, a charge channel is formed inside the P-layer 10, so that the N-well layer 8 and the drift layer 6 can form a path. The existence of the P-layer 1 9 will inhibit the charges flowing inside the N-well layer 8 from converging to the gate 4 region, which can greatly reduce the amount of parasitic charges.

[0052] Example 2

[0053] like Figure 2 As shown, a shallow channel super junction MOS semiconductor device includes a drain 1, a source 2, a semiconductor epitaxial layer, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4, the semiconductor epitaxial layer includes an N substrate layer 5 and a drift layer 6; the interior of the drift layer 6 is formed with a P well layer 7, a P-layer 2 10, and an N well layer 8 by ion implantation. A narrow heavily doped N layer 11 is formed by ion implantation inside the drift layer 6 and between two adjacent P-layers 2 10. Since the ion concentration of the narrow heavily doped N layer 11 is higher than that of the interior of the drift layer 6, the charges flowing in the drift layer 6 are more easily diffused to the narrow heavily doped N layer 11, thereby reducing the resistance of the charge channel connecting the N well layer 8 and the drift layer 6.

[0054] Example 3

[0055] like Figure 3 As shown, a shallow channel super junction MOS semiconductor device includes a drain 1, a source 2, a semiconductor epitaxial layer, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4, the semiconductor epitaxial layer includes an N substrate layer 5 and a drift layer 6; the interior of the drift layer 6 is formed with a P well layer 7, a P-layer 2 10, and an N well layer 8 by ion implantation. A wide heavily doped N layer 1101 is formed by ion implantation inside the drift layer 6 and between two adjacent P-layers 2 10, wherein the wide heavily doped N layer 1101 penetrates the drift layer 6 and contacts the N substrate layer 5. Since the ion concentration of the narrow heavily doped N layer 11 is higher than that of the interior of the drift layer 6, the charges flowing in the drift layer 6 are more easily diffused to the narrow heavily doped N layer 11, so that the resistance between the charge channel connecting the N well layer 8 and the drift layer 6 can be minimized.

[0056] Example 4

[0057] like Figure 4 As shown, a shallow channel super junction MOS semiconductor device includes a drain 1, a source 2, a semiconductor epitaxial layer, a gate 4, and a gate oxide layer 3 covering the surface of the gate 4. The semiconductor epitaxial layer includes an N substrate layer 5 and a drift layer 6; the interior of the drift layer 6 is formed with a P well layer 7, a P-layer 10, and an N well layer 8 by ion implantation. The P well layer 7 also includes a wide P well layer 71, which penetrates the drift layer 6 and contacts the N substrate layer 5. By using the wide P well layer 71, adjacent MOS cells (such as Figure 1 , 2 , 3, and 4 are all MOS cells. A MOS semiconductor is composed of a number of mutually parallel MOS cells. There is a phenomenon of interactive flow of charges in the drift layer 6, ensuring that the drain charges in a single MOS cell mainly flow into the N-well layer 8 through the drift layer 6, which can effectively improve the response speed of the MOS device.

[0058] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A shallow channel super junction MOS semiconductor device, comprising a drain (1), a source (2), a semiconductor epitaxial layer, a gate (4), and a gate oxide layer (3) covering the surface of the gate (4), characterized in that: The semiconductor epitaxial layer comprises an N substrate layer (5) and a drift layer (6); a P well layer (7), a second P-layer (10) and an N well layer (8) are formed inside the drift layer (6) by ion implantation; The gate (4) has a cross-section in a T-shape; a P-layer 1 (9) is formed inside the N-well layer (8) by ion implantation; the P-layer 1 (9) and the P-layer 2 (10) are respectively located on the upper and lower sides of the N-well layer (8), and the P-layer 1 (9) is not in ohmic contact with the source (2); A wide heavily doped N layer (1101) is formed by ion implantation inside the drift layer (6) and between two adjacent P-layers (10), wherein the wide heavily doped N layer (1101) penetrates the drift layer (6) and contacts the N substrate layer (5); The P-well layer (7) further comprises a wide P-well layer (71), wherein the wide P-well layer (71) penetrates the drift layer (6) and contacts the N substrate layer (5).

2. The shallow channel super junction MOS semiconductor device according to claim 1, characterized in that: A narrow heavily doped N layer (11) is formed inside the drift layer (6) and between two adjacent P-layers (10) by ion implantation.

3. The shallow channel super junction MOS semiconductor device according to claim 1, characterized in that: The cross-sectional thickness of the P-layer 2 (10) is the same as the cross-sectional thickness of the gate oxide layer (3).

4. A process for preparing a shallow channel super junction MOS semiconductor device, characterized in that: The preparation process of the shallow channel super junction MOS semiconductor device is applied to the shallow channel super junction MOS semiconductor device according to any one of claims 1 to 3, and the preparation process of the shallow channel super junction MOS semiconductor device comprises the following steps: S1. Using chemical cleaning to remove the oxide layer on the surface of the semiconductor epitaxial layer; S2, using ion implantation technology to form a P-well layer (7), an N-well layer (8), a P-layer 1 (9) and a P-layer 2 (10) inside the drift layer; S3, forming a narrow heavily doped N layer (11) or a wide heavily doped N layer (1101) by injecting high-concentration phosphorus ions inside the drift layer (6) and below the gate (4); S4, conducting an electrical performance difference test between a semiconductor including a P-layer one (9) and a standard semiconductor not including a P-layer one (9); S5. After the semiconductor including the P-layer 1 (9) passes the test, it is packaged.

5. The process for preparing a shallow channel super junction MOS semiconductor device according to claim 4, characterized in that: In step S4, whether the semiconductor including the P-layer 1 (9) has qualified performance is determined based on the absolute value of the threshold voltage difference, the absolute value of the saturation current difference, and the absolute value of the parasitic capacitance difference between the semiconductor including the P-layer 1 (9) and the standard semiconductor not including the P-layer 1 (9), as follows: In the formula, G represents the quality coefficient of the tested semiconductor containing a P-layer (9), u represents the absolute value of the threshold voltage difference between the semiconductor containing a P-layer (9) and a standard semiconductor without a P-layer (9), i represents the absolute value of the saturation current difference between the semiconductor containing a P-layer (9) and a standard semiconductor without a P-layer (9), and c represents the absolute value of the parasitic capacitance difference between the semiconductor containing a P-layer (9) and a standard semiconductor without a P-layer (9).

6. The process for preparing a shallow channel super junction MOS semiconductor device according to claim 5, characterized in that: When G ≥ 84%, it indicates that the semiconductor containing the P-layer 1 (9) tested has excellent performance; When 84>G≥65%, it means that the performance of the tested semiconductor containing P-layer 1 (9) is qualified; When G<65%, it means that the performance of the tested semiconductor containing the P-layer 1 (9) is unqualified.

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