Semiconductor device with robust zener diode and manufacturing method thereof

Abstract

The invention relates to a lateral semiconductor device and a manufacturing method thereof. The lateral semiconductor device comprises a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a semiconductor layer formed on the first insulating layer opposite the semiconductor substrate. The semiconductor layer includes a first region having a first conductivity type, a second region having a second conductivity type opposite the first conductivity type, and an intermediate region between the first region and the second region, the intermediate region defining a first lateral distance between the first region and the second region, the intermediate region includes a lower doping concentration than the first region and the second region. The doping concentration of the first region at the interface with the intermediate region and the doping concentration of the second region at the interface with the intermediate region exceed 1 * 1018 cm-3, and the first lateral distance between the first region and the second region is at most 800 nm.

Description

Technical Field

[0001] The present disclosure relates to a lateral semiconductor device including two doped regions in a semiconductor layer. More specifically, the lateral semiconductor device may be a silicon-on-insulator (SOI) device including a Zener diode. The present disclosure also relates to a method of manufacturing a semiconductor device. Background Art

[0002] The semiconductor chip in SOI technology can include a plurality of different devices. Different devices can form an integrated circuit (IC) therein. SOI technology can be used to realize low power and / or low voltage devices, for example, formed into a high voltage semiconductor chip with CMOS (complementary metal oxide semiconductor) technology. Therefore, the HV (high voltage) semiconductor device in CMOS (complementary metal oxide semiconductor) technology forms an interface between a standard CMOS device with an input voltage up to 5V and an industrial or consumer circuit that works with a signal voltage level higher than 30V or even higher than 200V.

[0003] The application of such HV semiconductor devices exists in various power conversions and electric drives up to the kW range, such as in power converters, robots and the automotive industry. Such HV semiconductor devices generally include a low voltage part as a low voltage domain and an HV part as a high voltage domain. In the low voltage part, most of the signal processing is completed at a low operating voltage. The HV part operates at a higher voltage level and provides a signal interface for power semiconductors using a higher voltage level and / or having a higher current drive and absorption capability. An example of such an HV semiconductor device is a gate driver circuit that enables a microcontroller or DSP (digital signal processor) to effectively turn on and off a power semiconductor switch. The HV termination separates two or more CMOS circuits in different voltage domains, and the potentials of different voltage domains may differ by hundreds of volts to several thousand volts. The lateral width of the HV termination depends on the voltage breakdown capability required between the voltage domains. The HV termination may include a field plate structure and generally occupies an important part of the HV semiconductor device. Examples of semiconductor devices integrated in SOI technology are MOSFETs, pn diodes, Zener diodes, etc.

[0004] There is a constant need to improve the electrical characteristics and manufacturability of such semiconductor devices. Summary of the invention

[0005] According to an embodiment, a lateral semiconductor device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The semiconductor layer includes a first region having a first conductivity type, a second region having a second conductivity type opposite to the first conductivity type, and an intermediate region between the first region and the second region, wherein the intermediate region includes a lower doping concentration than the first region and the second region, wherein the first region and the second region form a Zener diode.

[0006] According to another embodiment, a lateral semiconductor device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The semiconductor layer includes a first region having a first conductivity type, a second region having a second conductivity type opposite to the first conductivity type, and an intermediate region between the first region and the second region, the intermediate region defining a first lateral distance between the first region and the second region, wherein the intermediate region includes a lower doping concentration than the first region and the second region, wherein the doping concentration of the first region at an interface with the intermediate region and the doping concentration of the second region at an interface with the intermediate region exceeds 1×10 18 cm -3 , and wherein a first lateral distance between the first region and the second region is at most 800 nm.

[0007] According to another embodiment, a method for manufacturing a lateral semiconductor device includes providing a semiconductor stack, the semiconductor stack including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The method also includes forming a Zener diode by implanting a first dopant to form a first region having a first conductivity type in the semiconductor layer, and implanting a second dopant to form a second region having a second conductivity type opposite to the first conductivity type in the semiconductor layer, wherein the first dopant and the second dopant are implanted at a second lateral distance from each other to form an intermediate region between the first region and the second region, wherein the intermediate region includes a lower doping concentration than the first region and the second region.

[0008] According to another embodiment, a method for manufacturing a lateral semiconductor device includes providing a semiconductor stack, the semiconductor stack including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The method also includes the following steps: injecting a first dopant to form a first region having a first conductivity type in the semiconductor layer; injecting a second dopant to form a second region having a second conductivity type opposite to the first conductivity type in the semiconductor layer, wherein the first dopant and the second dopant are injected at a second lateral distance of 50nm to 800nm; and recrystallizing at least a portion of the first region and the second region after injecting the first dopant and the second dopant.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings, the present disclosure is shown by way of example and not limitation, in which the same reference numerals represent similar or identical elements. The elements in the accompanying drawings are not necessarily to scale with respect to each other. The features of the various examples shown may be combined unless they exclude each other.

[0011] Figure 1 A first exemplary embodiment of a Zener diode is shown;

[0012] Figure 2 A second exemplary embodiment of a Zener diode is shown;

[0013] Figure 3 An exemplary method of fabricating a lateral semiconductor device is shown;

[0014] Figure 4 An exemplary mask arrangement for a method of manufacturing a lateral semiconductor device is shown. DETAILED DESCRIPTION

[0015] Examples described herein provide a lateral semiconductor device including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The semiconductor layer includes a first region having a first conductivity type, a second region having a second conductivity type opposite to the first conductivity type, and an intermediate region between the first and second regions, wherein the intermediate region includes a lower doping concentration than the first region and the second region, wherein the first region and the second region form a Zener diode.

[0016] Examples described herein also provide a lateral semiconductor device including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The semiconductor layer includes a first region having a first conductivity type, a second region having a second conductivity type opposite to the first conductivity type, and an intermediate region between the first region and the second region, the intermediate region defining a first lateral distance between the first region and the second region, wherein the intermediate region includes a lower doping concentration than the first region and the second region, wherein the doping concentration of the first region at an interface with the intermediate region and the doping concentration of the second region at an interface with the intermediate region exceeds 1×10 18 cm -3 , and wherein a first lateral distance between the first region and the second region is at most 800 nm.

[0017] According to another embodiment, a method for manufacturing a lateral semiconductor device includes providing a semiconductor stack, the semiconductor stack including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The method also includes forming a Zener diode by implanting a first dopant to form a first region having a first conductivity type in the semiconductor layer, and implanting a second dopant to form a second region having a second conductivity type opposite to the first conductivity type in the semiconductor layer, wherein the first dopant and the second dopant are implanted at a second lateral distance from each other to form an intermediate region between the first region and the second region, wherein the intermediate region includes a lower doping concentration than the first region and the second region.

[0018] According to another embodiment, a method for manufacturing a lateral semiconductor device includes providing a semiconductor stack, the semiconductor stack including a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the first insulating layer opposite to the semiconductor substrate. The method also includes the following steps: injecting a first dopant to form a first region having a first conductivity type in the semiconductor layer; injecting a second dopant to form a second region having a second conductivity type opposite to the first conductivity type in the semiconductor layer, wherein the first dopant and the second dopant are injected at a second lateral distance of 50nm to 800nm; and recrystallizing at least a portion of the first region and the second region after injecting the first dopant and the second dopant. The semiconductor layer provided for each of the methods may be at least partially single crystalline.

[0019] The following examples of features may be combined with any of the above examples and with each other.

[0020] For example, the doping concentration of the first region at the interface with the middle region and the doping concentration of the second region at the interface with the middle region are greater than 1×1018 cm -3 In other words, at least near the middle region, the doping concentration of the first region may exceed 1×10 18 cm -3 At least near the middle region, the doping concentration of the second region may exceed 1×10 18 cm -3 The doping concentration of the first region may be at least 5 times, or even at least 10 times, greater than the doping concentration of the second region.

[0021] For example, the first lateral distance between the first region and the second region defined by the middle region is at most 800nm. For example, the first lateral distance can be at most 600nm. For example, the first lateral distance can be in the range of 50nm to 800nm ​​or in the range of 200nm to 600nm. The second lateral distance can be defined as the first lateral distance during the implantation process of the first dopant and the second dopant. The second lateral distance is the distance of the implantation region, and the first lateral distance is the distance between the semiconductor regions produced by the implantation. However, the first lateral distance and the second lateral distance can be slightly different. The second lateral distance can be at most 800nm ​​or at most 600nm. The second lateral distance can be in the range of 50nm to 800nm ​​or in the range of 200nm to 600nm.

[0022] For example, the first lateral distance is equal to the lateral extension of the intermediate region between the first region and the second region. In other words, the lateral gap between the first region and the second region may be completely occupied by the intermediate region at least along the vertical portion of the gap. The intermediate region may extend vertically over the entire thickness of the semiconductor layer. Thus, the vertical extension of the intermediate region may be equal to or greater than the vertical extension of the first region and / or the second region. The intermediate region may occupy the entire gap between the first region and the second region.

[0023] For example, the intermediate region completely separates the first region and the second region. Thus, the first region and the second region can, for example, be completely spaced apart from each other.

[0024] For example, each of the first region, the second region and the intermediate region adjoins the first insulating layer.Thus, all three regions may include respective boundary surfaces to the first insulating layer, which are oriented in the same plane and / or parallel to each other at the same vertical level.

[0025] For example, the lateral semiconductor device further includes a second insulating layer formed on the semiconductor layer opposite to the first insulating layer. The semiconductor layer may be at least partially sandwiched between the first insulating layer and the second insulating layer.

[0026] For example, each of the first region, the second region, and the intermediate region adjoins both the first insulating layer and the second insulating layer. Thus, all three regions may include respective boundary surfaces to the first insulating layer, the boundary surfaces being oriented in the same plane and / or parallel to each other at the same vertical level. Additionally or alternatively, all three regions may respectively include respective boundary surfaces to the second insulating layer, the boundary surfaces being oriented in the same plane and / or parallel to each other at the same vertical level.

[0027] For example, at least between the first insulating layer and the second insulating layer, the first region and the second region are connected only via the intermediate region. For example, the first region and the second region may be electrically connected only via the intermediate region.

[0028] For example, the middle region comprises only background doping. The background doping may be, for example, at most 1×10 16 cm -3 Background doping is defined as doping incorporated into the silicon layer during its fabrication (e.g. crystal growth and / or epitaxy). Background doping may be doping of the silicon layer after its formation without any additional addition of dopants, e.g. without any implantation or in-diffusion of dopants.

[0029] For example, the middle region includes at most 3×10 19 cm -3 For example, the doping concentration in the middle region is only up to 3×10 18 cm -3 Or even up to 3×10 17 cm -3 . Alternatively or additionally, the doping concentration of the intermediate region is at least twice less than the doping concentration of the first region and the second region. For example, the doping concentration of the intermediate region is at least one order of magnitude less than the doping concentration of both the first region and the second region. The pn junction between the first region and the second region can be formed in the intermediate region. The pn junction can be formed by diffusion of dopants from the first region and / or the second region into the intermediate region. In the thermal annealing step, an active pn junction can be formed after implanting both the first dopant and the second dopant, for example by diffusion from the first region and / or the second region into the intermediate region. The pn junction can be a pn junction formed between the first region and the second region. Therefore, the pn junction of the Zener diode between the first region and the second region can be located in the intermediate region.

[0030] For example, the middle region is single crystal. In the whole process of injecting the first region and the second region into the semiconductor layer, the middle region can be single crystal. In the whole process of injecting the first dopant and the second dopant into the first region and the second region, the middle region can be omitted. For example, during the injection of both the first dopant and the second dopant, the middle region can be covered by a mask arrangement. The mask arrangement can include a photoresist layer, a hard mask (for example, an oxide such as SiO or a nitride such as SiN), an oxide or nitride layer or a combination thereof. As a result of omitting the middle region during the injection process step, the dopant concentration is smaller compared to the first region and the second region. For example, the dopant concentration in the middle region is at least twice as small as the maximum value of the dopant concentration in the first region and the second region. For example, the dopant concentration in the middle region is at least one order of magnitude smaller or even at least two orders of magnitude smaller than the maximum value of the dopant concentration in the first region and the second region. In addition, after the injection of the first dopant and the second dopant, the lattice is not disturbed by the injection of the single crystal structure that leads to the middle region, while the lattice in the first region and the second region may be affected or even destroyed due to the high injection dose of the first dopant and the second dopant. In the absence of the middle region as a spacer, such crystal damage in the first region and the second region will cause the leakage current of the Zener diode to increase. The single crystal middle region can reduce the leakage current. In addition, the middle region can form a seed layer (seed layer) for at least part of the recrystallization of the first region and the second region. In the absence of the middle region as a seed layer, it may be impossible to recrystallize the first region and the second region. Therefore, the pn junction (which may be located in the middle region) may be surrounded by the single crystal portion of the first region and the second region. For example, each region in the first region, the second region and the middle region is at least partially single crystal. This can lead to even further reduced leakage current and increased life and electrical stability of the semiconductor device.

[0031] For example, the semiconductor layer may have a thickness of at most 400 nm. In another example, the semiconductor layer may have a thickness of at most 250 nm.

[0032] For example, the semiconductor device includes a first field stop region adjacent to the first semiconductor region and a second field stop region adjacent to the second semiconductor region, wherein the intermediate region further separates the first field stop region and the second field stop region. The intermediate region may protrude laterally from the gap between the first region and the second region to the gap between the first field stop region and the second field stop region. The first field stop region may laterally adjoin the first region and the intermediate region. The first field stop region may have a first conductivity type, but have a lower dopant concentration than the first region. The second field stop region may laterally adjoin the second region and the intermediate region. The second field stop region may have a second conductivity type, but have a lower dopant concentration than the second region. The first field stop region and the second field stop region may be sandwiched between a first insulating layer and a second insulating layer.

[0033] For example, the semiconductor device includes a conductive layer above the second insulating layer. The conductive layer may include highly doped polysilicon or preferably metal. The first region and the second region may contact the conductive layer via respective contact plugs extending through the second insulating layer. The conductive layer may be laterally segmented, wherein the first region and the second region are electrically connected to different portions of the conductive layer.

[0034] For example, the first insulating layer may, for example, include an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). In the case of silicon oxide, the oxide may, for example, be a thermally grown oxide or a deposited oxide. The first insulating layer may include more than one sublayer. Each of the sublayers of the first insulating layer may have a different chemical composition. For example, the second insulating layer may, for example, include an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). In the case of silicon oxide, the oxide may, for example, be a thermally grown oxide or a deposited oxide. The second insulating layer may include more than one sublayer. Each of the sublayers of the second insulating layer may have a different chemical composition.

[0035] Now refer to Figure 1 and Figure 2 Both figures schematically depict a lateral semiconductor device 1 . Figure 1 The view (b) and Figure 2 View (b) shows a cross section through the corresponding device 1 . Figure 1 View (a) and Figure 2 The view (a) of shows a vertical projection along the vertical axis z similar to a top view. The vertical axis z is perpendicular to the two transverse axes x, y.

[0036] Still refer to Figure 1 and Figure 2, the lateral semiconductor device 1 includes a semiconductor substrate 2. The semiconductor substrate 2 may be derived from a single crystal silicon wafer. The thickness of the semiconductor substrate 2 may be in the range of 20 μm to 200 μm. The device 1 includes a first insulating layer 3 above the semiconductor substrate 1. The device 1 also includes a semiconductor layer 4 above the first insulating layer 3. The semiconductor layer 4 may be the only semiconductor layer of the lateral semiconductor device 1 including active devices. In other words, the lateral semiconductor device 1 may not have any semiconductor layer above or below the semiconductor layer 4 including the electrically active semiconductor device. Therefore, the semiconductor layer 4 may be the only device layer of the lateral semiconductor device 1. The semiconductor layer 4 may have a thickness of 100 nm to 250 nm. The device 1 also includes a second insulating layer 5 above the semiconductor layer 4. The semiconductor layer 4 is sandwiched between the first insulating layer 3 and the second insulating layer 5.

[0037] The metallization comprises a metal layer 6 above the second insulating layer 5 and contact plugs 611, 621 extending through the second insulating layer 5. The second insulating layer 5 is laterally divided into portions 612, 622. The portions 612 and 622 each form a contact pad.

[0038] Still refer to Figure 1 and Figure 2 , the semiconductor layer 4 includes a first region 41 and a second region 42. The first region 41 has a first conductivity type, for example, an n-type. The second region 42 has a second conductivity type opposite to the first conductivity type, for example, a p-type. The first region 41 is connected to the first contact pad 612 via a first contact plug 611. The first contact plug 611 extends through the second insulating layer 5. The second region 42 is connected to the second contact pad 622 via a second contact plug 621. The second contact plug 621 extends through the second insulating layer 5. The first region 41 forms a cathode region of the Zener diode, and the second region forms an anode region of the Zener diode. The first contact pad 612 forms a cathode electrode of the Zener diode, and the second contact pad 622 forms an anode electrode of the Zener diode. The contact plugs 611, 621 may form an ohmic contact to the respective semiconductor regions 41, 42. The first region 41 and the second region 42 may each have at least 1×10 18 cm -3 of dopant concentration.

[0039] Now refer to Figure 1 , an overlapping region 45 is formed between the first region 41 and the second region 42. In the overlapping region 45, dopants having the first conductivity type and the second conductivity type are implanted. In the overlapping region 45, the implants for forming the first region 41 and the second region 42 overlap. Figure 14. The view (c) of FIG. 4 gives a schematic overview of the distribution of the first dopant 81 in the first region 41 and the second dopant 82 in the second region 42. In other words, both the first region and the second region extend into the overlapping region 45, where both the first dopant 81 and the second dopant 82 are present. Therefore, the overall doping concentration in the overlapping region 45 is higher when compared to the first region 41 or the second region 42. This results in increased crystal damage within the overlapping region 45. This may lead to increased leakage current and faster degradation of the semiconductor device 1.

[0040] Now refer to Figure 2 , the first region 41 and the second region 42 are separated by a first lateral distance d1 (parallel to the first lateral direction x). In other words, the first region 41 and the second region 42 do not border each other, or even overlap each other. They are separated from each other by the intermediate region 43. In the present embodiment, the first lateral distance d1 is in the range of 50 nm to 800 nm, preferably in the range of 200 nm to 600 nm. The intermediate region 43 is between the first region 41 and the second region 42. The intermediate region 43 includes a lower doping concentration than each of the first region 41 and the second region 42. The intermediate region 43 can be masked during the implantation of both the first region 41 and the second region 42 (see Figure 4 ). Figure 2 View (c) of FIG. 4 gives a schematic overview of the distribution of the first dopant 81 in the first region 41 and the second dopant 82 in the second region 42. In the intermediate region 43, the first dopant 81 and the second dopant 82 are absent or present but at a lower dose than in adjacent portions of the first region 41 and the second region 42.

[0041] Now refer to Figure 3, a method for manufacturing a lateral semiconductor device is provided. In a first step S1, a semiconductor stack including a semiconductor substrate 2, a first insulating layer 3 formed on the semiconductor substrate 2, and a semiconductor layer 4 formed on the first insulating layer 3 opposite to the semiconductor substrate 2 is provided. The semiconductor layer 4 is at least partially single crystalline. In a subsequent step, a Zener diode is formed by injecting (S2) a first dopant 81 to form a first region 41 having a first conductivity type in the semiconductor layer, and injecting (S3) a second dopant 82 to form a second region 42 having a second conductivity type opposite to the first conductivity type in the semiconductor layer 2. The first dopant 81 and the second dopant 82 are injected at a second lateral distance d2 (parallel to the first lateral direction x) between each other so as to form an intermediate region 43 between the first region 41 and the second region 42, wherein the intermediate region 43 includes a lower doping concentration than each of the first region 41 and the second region 42. In the present embodiment, the second lateral distance d2 is in the range of 50nm to 800nm, preferably in the range of 200nm to 600nm.

[0042] Now refer to Figure 4 , the implantation process steps S2 and S3 are described in more detail. During the implantation of the first dopant 81, parts of the semiconductor layer 4 are masked by the first mask arrangement 71. The first mask arrangement 71 covers (at least) parts of the semiconductor layer 4 intended to later form the second region 42 and the intermediate region 43. The first dopant 81 is implanted into the semiconductor layer 4 only where the first region 41 is intended to be formed. For example, at 1×10 15 cm -2 Up to 6×10 15 cm -2 During the implantation of the second dopant 82, parts of the semiconductor layer 4 are masked by the second mask arrangement 72. The second mask arrangement 72 covers (at least) parts of the semiconductor layer 4 which are intended to later form the first region 41 and the intermediate region 43. The second dopant 82 is implanted into the semiconductor layer 4 only where the second region 42 is intended to be formed. The second dopant 82 is implanted at a dose of 1×10 14 cm -2 Up to 4×10 15 cm -2 The term "implantation only" means implanting a certain area with a dose of 10%. "Implantation only" into a certain area is to be understood taking into account the technical possibilities and the intention of the mask device 71. Traces of dopants under the mask area cannot be excluded 100%. Therefore, "only" in this context means at least 99%. The mask arrangement 71, 72 may include a photoresist layer, a hard mask (e.g., an oxide such as SiO or a nitride such as SiN), an oxide or nitride layer or a combination thereof.

[0043] During the implantation of the first dopant 81 and the second dopant 82, the middle region 43 is masked. Therefore, during the implantation processes S2 and S3, the middle region 43 suffers a lower degree of crystal damage. Therefore, the crystal lattice of the middle region 43 remains intact. Now return to reference Figure 3 In a further step S4, at least a portion of the first region 41 and the second region 42 is recrystallized. This can be done by heating the semiconductor layer, for example in an oven, by rapid thermal annealing (RTA) or by laser thermal annealing (LTA).

[0044] During the tempering step, during recrystallization or in a separate tempering step, the dopants of the first region 41 and the second region 42 may diffuse into the intermediate region 43. Figure 2 example, even after diffusion is complete and in the final product, the intermediate region 43 includes at most 1×10 17 cm -3 According to the doping concentration Figure 2 In the example of, even after the diffusion is completed and in the final product, the middle region 43 includes a doping concentration that is at least ten times or even fifty times smaller than in the first region 41 and / or the second region 42. By diffusing the first dopant 81 and the second dopant 82 into the middle region 43, a pn junction of a Zener diode can be formed in the middle region 43.

[0045] Now refer to Figure 1 and Figure 2 , the semiconductor device 1 comprises a first field stop region 46 (in the second lateral direction y) adjacent to the first semiconductor region 41 and a second field stop region 47 (in the second lateral direction y) adjacent to the second semiconductor region 42. Figure 2 , the intermediate region 43 also separates the first field stop region 46 and the second field stop region 47. The intermediate region 43 protrudes laterally from the gap between the first region 41 and the second region 42 to the gap between the first field stop region and the second field stop region. The first field stop region 46 is laterally adjacent to the first region 41 (in the second lateral direction y) and the intermediate region 43 (in the first lateral direction x). The first field stop region 46 has a first conductivity type, but has a lower dopant concentration than the first region 41. The second field stop region 47 is laterally adjacent to the second region 42 (in the second lateral direction y) and the intermediate region 43 (in the first lateral direction x). The second field stop region 47 may have a second conductivity type, but has a lower dopant concentration than the second region 42. The first field stop region 46 and the second field stop region 47 are sandwiched between the first insulating layer and the second insulating layer.

[0046] Reference Figure 2, the distance d1 can be arbitrarily arranged between the contact plug 61 and the contact plug 62, but it is not purely random, because each of the semiconductor regions 41, 42 must not reach the corresponding opposite contact plug 61, 62 by diffusion. This will result in a resistor rather than a diode. In an embodiment, the first semiconductor region 41 has a higher doping concentration than the second semiconductor region 42. In this embodiment, the more highly doped portion of the two semiconductor regions 41, 42 has a greater lateral extension along the X-axis. More specifically, the first semiconductor region 41 has a greater lateral extension along the X-axis between the contact plug 61 and the contact plug 62 than the second semiconductor region 42. Due to the higher dopant concentration of the first semiconductor region 41, this achieves a lower total resistance of the Zener diode.

[0047] Although specific examples have been illustrated and described herein, it will be appreciated by those skilled in the art that various alternative implementations and / or equivalent implementations may be used to replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

[0048] It should be noted that the methods and devices described in this disclosure (including preferred embodiments thereof) can be used alone or in combination with other methods and devices disclosed in this disclosure. In addition, features outlined in the context of a device also apply to the corresponding method, and vice versa. In addition, all aspects of the methods and devices described in this disclosure can be combined arbitrarily. In particular, the features in the claims can be combined with each other in any manner.

[0049] It should be noted that the description and the accompanying drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included in its spirit and scope. In addition, all examples and implementations outlined in this document are primarily and explicitly intended to be for illustrative purposes only, to help the reader understand the principles of the proposed method and system. In addition, all statements of the principles, aspects and implementations of the present invention and specific examples thereof provided herein are intended to cover their equivalents.

Claims

1. A lateral semiconductor device (1), comprising: Semiconductor substrate (2); A first insulating layer (3) formed on the semiconductor substrate (2); A semiconductor layer (4) formed on the first insulating layer (3) opposite to the semiconductor substrate (2), the semiconductor layer (4) comprising: a first region (41) having a first conductivity type, a second region (42) having a second conductivity type opposite to the first conductivity type, and an intermediate region (43) between the first region (41) and the second region (42), wherein the intermediate region (43) comprises a lower doping concentration than the first region (41) and the second region (42), The first region (41) and the second region (42) form a Zener diode.

2. The lateral semiconductor device (1) according to claim 1, wherein: The doping concentration of the first region (41) at the interface with the middle region (43) and the doping concentration of the second region (42) at the interface with the middle region (43) are greater than 1×10 18 cm -3 .

3. The lateral semiconductor device (1) according to claim 1 or 2, wherein: A first lateral distance between the first region (41) and the second region (42) defined by the intermediate region is at most 800 nm.

4. A lateral semiconductor device (1), comprising: Semiconductor substrate (2); A first insulating layer (3) formed on the semiconductor substrate (2); A semiconductor layer (4) formed on the first insulating layer (3) opposite to the semiconductor substrate (2), the semiconductor layer (4) comprising: a first region (41) having a first conductivity type, a second region (42) having a second conductivity type opposite to the first conductivity type, and an intermediate region (43) between the first region (41) and the second region (42), the intermediate region (43) defining a first lateral distance between the first region (41) and the second region (42), wherein the intermediate region (43) comprises a lower doping concentration than the first region (41) and the second region (42), The doping concentration of the first region (41) at the interface with the middle region (43) and the doping concentration of the second region (42) at the interface with the middle region (43) are greater than 1×10 18 cm -3 ,and Wherein, the first lateral distance between the first region and the second region is at most 800 nm.

5. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The first lateral distance is equal to the lateral extension of the intermediate region (43) between the first region (41) and the second region (42).

6. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The intermediate region (43) completely separates the first region (41) from the second region (42).

7. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The intermediate region (43) extends vertically over the entire thickness of the semiconductor layer (4).

8. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: Each of the first region (41), the second region (42) and the intermediate region (43) is adjacent to the first insulating layer (3).

9. The lateral semiconductor device (1) according to any one of the preceding claims, further comprising a second insulating layer (5) formed on the semiconductor layer (4) opposite to the first insulating layer (3).

10. The lateral semiconductor device (1) according to claim 9, wherein: Each of the first region (41), the second region (42) and the intermediate region (43) adjoins both the first insulating layer (3) and the second insulating layer (5).

11. The lateral semiconductor device (1) according to claim 9 or 10, wherein: At least between the first insulating layer (3) and the second insulating layer (5), the first region (41) and the second region (42) are connected only through the intermediate region (43).

12. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The dopant concentration in the intermediate region (43) is at least two times smaller than the dopant concentration in the first region (41) or the second region (42).

13. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The middle region (43) includes less than 1×10 18 cm -3 of doping concentration.

14. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The intermediate region (43) is single-crystalline.

15. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: Each of the first region (41), the second region (42) and the intermediate region (43) is at least partially single crystalline.

16. A lateral semiconductor device (1) according to any one of the preceding claims, wherein: The semiconductor layer (4) has a thickness of at most 400 nm.

17. The lateral semiconductor device (1) according to any of the preceding claims, further comprising a first field stop region (46) adjoining the first semiconductor region (41) and a second field stop region (47) adjoining the second semiconductor region (42), wherein: The intermediate region (43) also separates the first field stop region (46) and the second field stop region (47).

18. A method for manufacturing a lateral semiconductor device (1), the method comprising: A semiconductor stack is provided, the semiconductor stack comprising: a semiconductor substrate (2), a first insulating layer (3) formed on the semiconductor substrate (2), and a semiconductor layer (4) formed on the first insulating layer (3) opposite to the semiconductor substrate (2); The Zener diode is formed by the following steps: implanting a first dopant (81) to form a first region (41) having a first conductivity type in the semiconductor layer (4), implanting a second dopant (82) to form a second region (42) having a second conductivity type opposite to the first conductivity type in the semiconductor layer (4), wherein the first dopant (81) and the second dopant (82) are implanted at a second lateral distance from each other to form an intermediate region (43) between the first region (41) and the second region (42), wherein the intermediate region (43) comprises a lower doping concentration than the first region (41) and the second region (42).

19. The method according to claim 18, further comprising: After implanting both the first dopant and the second dopant, the semiconductor layer (4) is thermally annealed to form an active pn junction.

20. The method according to claim 18 or 19, further comprising: After implanting the first dopant (81) and the second dopant (82), at least a portion of the first region (41) and the second region (42) are recrystallized.

21. A method for manufacturing a lateral semiconductor device (1), the method comprising: A semiconductor stack is provided, the semiconductor stack comprising: a semiconductor substrate (2), a first insulating layer (3) formed on the semiconductor substrate (2), and a semiconductor layer (4) formed on the first insulating layer (3) opposite to the semiconductor substrate (2); Implanting a first dopant (81) to form a first region (41) having a first conductivity type in the semiconductor layer (4); implanting a second dopant (82) to form a second region (42) having a second conductivity type opposite to the first conductivity type in the semiconductor layer (4), wherein the first dopant (81) and the second dopant (82) are implanted at a second lateral distance of 50 nm to 800 nm; After implanting the first dopant (81) and the second dopant (82), at least a portion of the first region (41) and the second region (42) are recrystallized.

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