Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. Embodiments of the present disclosure relate to forming isolation structures in gate structures to prevent current leakage through source / drain regions (EPIs), transistors, and silicon substrates. The isolation structures are arranged in a pattern having long isolation structures adjacent to short isolation structures. An isolation structure may be formed in the gate structure before or after a replacement gate sequence.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device structures and methods of forming the same. Background Art

[0002] As the semiconductor industry progresses to nanometer technology process nodes in pursuit of higher device density, higher performance and lower cost, challenges posed by manufacturing and design issues have led to the development of multi-gate devices such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors. In order to continue to provide the required scaling and increased density for multi-gate devices in advanced technology nodes, the gate pitch needs to continue to decrease.

[0003] The device layout may employ polysilicon (poly) segments formed as diffusion edge (PODE) or continuous polysilicon on diffusion edge (COPED) to avoid leakage between adjacent devices. A PODE pattern or CPODE pattern is used to form the polysilicon segments. As device dimensions shrink, such as gate pitch, design schemes such as PODE and CPODE schemes may face difficulties in providing the levels of device density, cell isolation, and device performance required for aggressive scaling of circuits and devices. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first length along the second direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second length along the second direction, the first gate structure is positioned adjacent to the second gate structure, and the first length is shorter than the second length.

[0005] According to an embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a first gate structure arranged on the plurality of fin structures and extending along a second direction; a second gate structure arranged on the plurality of fin structures and extending along the second direction; a first isolation structure arranged in the first gate structure, wherein the first isolation structure has a first length along the second direction; and a second isolation structure arranged in the second gate structure, wherein the second isolation structure comprises: a first segment having a first width along the first direction; a second segment having a second width along the first direction and a second length along the second direction, wherein the first width is greater than the second width; and a third segment having the first width, wherein the second segment is arranged between the first segment and the third segment, and the first isolation structure overlaps with the second segment of the second isolation structure.

[0006] According to an embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure among the plurality of gate structures, wherein the first opening has a first length along the second direction; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the second opening has a second length greater than the first length, and the second opening comprises: a narrow section; a first wide section and a second wide section extending from the narrow section, wherein the first opening overlaps with the narrow section of the second opening; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read together with the accompanying drawings, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A-Figure 1D The pattern design of the isolation structure according to an embodiment of the present disclosure is schematically shown.

[0009] Figure 2A-2C Variations of pattern designs of isolation structures according to embodiments of the present disclosure are schematically shown.

[0010] Figure 3A is a schematic top view of a semiconductor device showing a patterned design formed in a photoresist layer.

[0011] Figure 3B It is along Figure 3A Schematic cross-sectional view of a semiconductor device taken along line 3B-3B.

[0012] Figure 3C After the patterned design is converted into a mask layer Figure 3A Schematic cross-sectional view of a semiconductor device.

[0013] Figure 4A The etching bias when patterning the hard mask layer under different process conditions is schematically shown.

[0014] Figure 4B Adjusting the etch bias by applying compressive stress to the substrate is schematically shown.

[0015] Figure 4C Adjusting the etching bias by applying tensile stress to the substrate is schematically shown.

[0016] Figure 4D The use of a combination of stress, feature length, and pattern density to tune the etch bias is schematically illustrated.

[0017] Figure 5A-5D The diagram schematically illustrates a passivation-oriented etching operation when forming a trench of an isolation structure according to an embodiment of the present disclosure.

[0018] Figure 6 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0019] Figure 7A-7B , Figure 8A-8B , Figure 9A-9B , Figure 10A-10B , Figure 11A-11B , Figure 12A-12B and Figure 13A-13B Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0021] For ease of description, spatially relative terms such as "below," "beneath," "down," "above," "on," "top," "up," and the like may be used herein to describe the relationship of one element or feature relative to another (one or more) elements or (one or more) features as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] The foregoing summarizes some aspects of the embodiments described in the present disclosure. Although some of the embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, fin FETs, horizontal gate all around (HGAA) FETs, vertical gate all around FETs, and other suitable devices. It will be readily appreciated by those of ordinary skill in the art that other modifications that may be made within the scope of the present disclosure are also contemplated. In addition, although the method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. In the present disclosure, source / drain regions refer to source and / or drain. Source and drain may be used interchangeably.

[0023] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing patterns to be created with, for example, a smaller pitch than is achievable using a single direct photolithography process.

[0024] Embodiments of the present disclosure relate to forming an isolation structure in a gate structure to prevent current leakage through a source / drain region (EPI), a transistor, and a silicon substrate. The isolation structure can be formed in the gate structure before or after a replacement gate sequence. A continuous polysilicon on diffusion edge (CPODE) process (including a silicon gate etch process) can be performed before the replacement gate sequence. A continuous metal on diffusion edge (CMODE) process (including a metal gate etch process) can be performed after the replacement gate sequence.

[0025] Embodiments of the present disclosure relate to a method for a patterning process for CPODE or CMODE to avoid photoresist stripping or pattern merging. First, multiple fin structures are formed along the x-direction. Each fin structure may include a type of epitaxial semiconductor material for a FinFET structure or a multilayer epitaxial semiconductor layer of a GAA structure. Then, multiple gate structures are formed along the y-direction above the fin structure. The gate structure has a gate pitch along the x-direction. Then, source / drain regions are formed along the fin structure and between the gate structures. First, a CPODE or CMODE opening pattern is formed in a hard mask layer. The CPODE or CMODE pattern includes a group of isolation openings along a group of adjacent gate structures, i.e., along the y-direction. Then, the isolation material is filled to replace the removed portions of the semiconductor substrate, the fin structure, and the gate structure.

[0026] According to an embodiment of the present disclosure, a CPODE or CMODE pattern includes isolation openings having different lengths along the y direction. In some embodiments, a CPODE or CMODE pattern includes a long isolation trench and a short isolation trench disposed adjacent to each other. The short isolation trench overlaps a portion of the long isolation trench. In some embodiments, the portion of the long isolation trench overlapping the short isolation trench has a reduced width along the x direction.

[0027] In some embodiments, the hard mask layer is configured to apply tensile stress to the semiconductor substrate. In some embodiments, a passivation oriented etching process is performed to transfer the CPODE or CMODE pattern from the hard mask layer to the semiconductor substrate.

[0028] As the gate pitch decreases, the width variation of the isolation opening avoids photoresist stripping, pattern merging, and pattern loading in subsequent processes. The arrangement of short trenches adjacent to long trenches, the application of tensile stress to the substrate, and the use of a passivation oriented etching process lead to a greater etching depth in the substrate, thereby ensuring isolation between the source / drain region and the transistor.

[0029] Figure 1A-Figure 1D The pattern design of the isolation structure according to an embodiment of the present disclosure is schematically shown. Figure 1A is a schematic top view of a semiconductor device 10 according to the present disclosure. Figure 1B , Figure 1C and Figure 1D Along the Figure 1A Schematic cross-sectional views of the semiconductor device 10 taken along lines 1B-1B, 1C-1C, and 1D-1D in FIG.

[0030] The semiconductor device 10 includes a plurality of transistors formed in and on a semiconductor substrate 12. In particular, the semiconductor device 10 includes a plurality of fin structures 14 formed on the semiconductor substrate 12 along the x direction. The fin structure 14 may include a single channel (for a FinFET device) or a plurality of channels (for a GAA device). A plurality of gate structures 16 (16a, 16b, 16c, collectively referred to as 16) are formed on the fin structure 14 along the y direction. The source / drain region 18 is formed by the fin structure 14 between the gate structures 16. The gate structure 16 has a gate pitch GP. In some embodiments, the gate pitch GP is less than 50nm, for example, the gate pitch is between about 20nm and about 30nm. The gate structure 20 may have a gate width GW along the x direction. The source / drain region 18 and the gate structure 16 therebetween form a transistor. Isolation structures 20 are formed in portions of gate structures 16 and extend into semiconductor substrate 12 to electrically isolate source / drain regions 18 on opposite sides of isolation structures 20 (isolation structures 20a, 20b, 20c are shown, collectively referred to as isolation structures 20). Isolation structures 20 may be formed by a CPODE process or a CMODE process.

[0031] like Figure 1A As shown, isolation structures 20a, 20b are formed side by side in the continuously adjacent gate structures 16a, 16b. The isolation structures 20a, 20b replace a portion of the gate structures 16a, 16b, cut the fin structure 14 below, and extend into the semiconductor substrate 12. The isolation structures 20a, 20b cut the fin structure 14 and electrically isolate the source / drain region 18l on the left from the isolation region 18r on the right. The source / drain region 18 between the isolation structures 20 becomes a dummy source / drain region 18d.

[0032] During the formation of the isolation structure 20 by the CPODE process or the CMODE process, a hard mask is first formed over the gate structure 16, and then a photolithography process is performed to form a mask opening in the hard mask. Embodiments of the present disclosure provide a CPODE or CMODE pattern that avoids photoresist stripping and enables the formation of trenches for the isolation structure to prevent current leakage. It has been observed that a mask opening having a wider width along the x-direction results in a larger etching depth in the semiconductor substrate 12, while a mask opening having a narrower width along the x-direction results in a smaller etching depth in the semiconductor substrate 12.

[0033] As the gate pitch decreases, it becomes increasingly challenging to form mask openings side by side. For example, photoresist defects such as stripping and scum may occur. The gate pattern may include a 1D gate pitch and a 2D gate pitch. The 1D gate pitch refers to the pitch along the direction of the fin structure (ie, the x direction). The 2D gate pitch refers to the pitch along the direction perpendicular to the fin structure (ie, the y direction). The gate pitch discussed below refers to the 1D gate pitch. It is also observed that the mask spacing along the x direction needs to be less than about 50% of the 1D gate pitch to avoid stripping. When the gate pitch decreases, the mask spacing width may need to be greater than 50% of the gate pitch to achieve sufficient etching depth in the semiconductor substrate 12 to provide isolation. Embodiments of the present disclosure provide a mask opening design that avoids photoresist defects without compromising the isolation function.

[0034] In some embodiments, the isolation structure 20 is formed in two or more adjacent gate structures 16. In some embodiments, the isolation structures 20 formed in two or more adjacent gate structures 16 have different lengths along the y direction. For example, the long isolation structure 20 is positioned adjacent to and parallel to the short isolation structure 20. By arranging the short isolation structure 20 next to the long isolation structure 20, the isolation structure 20 can be formed without causing photoresist defects. The short isolation structure and the long isolation structure overlap each other. In some embodiments, the short isolation structure overlaps the long isolation structure along its entire length. In some embodiments, the long isolation structure may include a narrow section that overlaps the short isolation structure.

[0035] like Figure 1A As shown, the isolation pattern may include a short isolation structure 20a formed along the gate structure 16a and a long isolation structure 20b formed along the gate structure 16b. The gate structures 16a and 16b may be directly adjacent to each other. The short isolation structure 20a and the long isolation structure 20b may overlap by a certain length.

[0036] In some embodiments, the isolation structure 20 within one gate structure 16 may include a single segment having a width in the x-direction. For example, the short isolation structure 20a has a single width along its entire length. The short isolation structure 20a has a length L1 along the y-direction and a width W1 along the x-direction. In some embodiments, the width W1 is greater than about 50% of the gate pitch GP. For example, the width W1 is in the range between about 0.5GP and about 0.6GP. The length L1 of the short isolation structure 20a may be in the range between about 2 times of W1 and 10 times of W1. The length L1 may be selected according to the circuit design. In some embodiments, the length L1 may be selected to ensure that the isolation structure 20a reaches a sufficient depth in the semiconductor substrate 12.

[0037] In some embodiments, the isolation structure 20 in one gate structure 16 may include two or more sections with different widths. For example, the long isolation structure 20b has sections with different widths. Figure 1A In the example of , the long isolation structure 20b has a narrow section 20bn and at least one wide section 20bw extending from the narrow section 20bn. In some embodiments, the narrow section 20bn of the long isolation structure 20b overlaps the short isolation structure 20a. In some embodiments, the narrow section 20bn has a width W2 along the x-direction and a length L2 along the y-direction. The wide section 20bw has a width W3 along the x-direction and a length L3 along the y-direction. The width W2 is smaller than the width W1 and the width W3. In some embodiments, the width W3 is in a range between about 0.5GP and about 0.6GP. The width W2 is in a range between about 0.25GP and 0.5GP. In some embodiments, the width W1 and the width W2 are selected so that the average width of the isolation structure 20 is less than 0.5GP, for example, the average width of the isolation structure 20 is between about 0.4GP and 0.45GP.

[0038] In some embodiments, the length L2 is equal to or greater than the length L1, so that the narrow section 20bn of the long isolation structure 20b overlaps the entire length L1 of the short isolation structure 20a. By positioning the short isolation structure 20a including the wide section immediately adjacent to the narrow section 20bn of the long isolation structure, the embodiments of the present disclosure ensure that the short isolation structure 20a has sufficient width to achieve sufficient depth to provide isolation across the fin structure 14 during manufacturing without causing photoresist defects. In some embodiments, the length L3 can be long enough to cover one or more fin structures 14.

[0039] The short isolation structure 20a may extend over one or more fin structures 14. Figure 1B As shown, the fin structure 14 is formed on the semiconductor substrate 12. The lower portion of the fin structure 14 is surrounded by a shallow trench isolation (STI) layer 22. The isolation structure 20a cuts through the two fin structures 14 below and extends into the semiconductor substrate 12. In some embodiments, the isolation structure 20a extends into the semiconductor substrate 12 to a depth D1 along the z-direction. The depth D1 is selected to ensure that the isolation structure 20a electrically isolates the source / drain region 18l from the source / drain region 18r, as shown in FIG. Figure 1A In some embodiments, the depth D1 is in a range between about 20 nm and about 90 nm.

[0040] The long isolation structure 20b is adjacent to the isolation structure 20a. The isolation structure 20b includes two wide segments 20bw connected by a narrow segment 20bn. The narrow segment 20bn has a length L2 or substantially equal to the length of the short isolation structure 20a, thereby providing a spacing 24ab wider than about 50% of the gate pitch GP. The wide segment 20bw is formed by both ends of the narrow segment 20bn. Alternatively, the long isolation structure 20b may include only one wide segment 20bw and one narrow segment 20bn. The wide segment 20bw may have a length L3. The length L3 may be long enough to cover one or more fin structures 14. As shown in FIG. Figure 1C As shown, the long isolation structure 20b cuts the four fin structures 14 below and extends into the semiconductor substrate 12. In some embodiments, the narrow section 20bn of the long isolation structure 20b extends into the semiconductor substrate 12 along the z-direction to a depth D2, while the wide section 20bw of the long isolation structure 20b extends into the semiconductor substrate to a depth D1. The depth D2 is less than the depth D1. In some embodiments, the depth D2 is in a range between about 0 nm and about 70 nm. In some embodiments, the difference between D1 and D2 is less than about 60 nm. In some embodiments, the ratio of D1:D2 is in a range between about 1.2 and about 3.0, for example, between about 1.5 and about 2.0.

[0041] In some embodiments, at the depth D2, the isolation structure 20b may not be sufficient to isolate the source / drain regions 18 on the opposite side of the isolation structure 20a. Therefore, the wide section 20bw of the long isolation structure 20b provides electrical isolation on the underlying fin structure 14. The narrow section 20bn of the isolation structure 20b does not provide electrical isolation on the underlying fin structure 14. The fin structure 14 below the narrow section 20bn of the long isolation structure 20b relies on the short isolation structure 20a for electrical isolation.

[0042] As described above, embodiments of the present disclosure arrange short isolation structures and long isolation structures to achieve effective isolation while avoiding photoresist defects. The short isolation and long isolation can be arranged in various designs. Figure 2A-2C Variations of pattern designs of isolation structures according to embodiments of the present disclosure are schematically shown.

[0043] Figure 2A 1 is a schematic top view of a semiconductor device 10a according to an embodiment of the present disclosure. The semiconductor device 10a is similar to the semiconductor device 10 with different arrangements of short isolation structures and long isolation structures. In the semiconductor device 10, one short isolation structure 20a is placed on one side of a long isolation structure 20b. In the semiconductor device 10a, two short isolation structures 20a are arranged on opposite sides of a long isolation structure 20b. Figure 2AIn FIG. 2 , the long isolation structure 20 b includes a narrow section 20 bn , and the two short isolation structures 20 a are located on opposite sides of the narrow section 20 bn .

[0044] Figure 2B 1 is a schematic top view of a semiconductor device 10b according to an embodiment of the present disclosure. The semiconductor device 10b is similar to the semiconductor device 10 with a different arrangement of short isolation structures and long isolation structures. In the semiconductor device 10b, two long isolation structures 20b are arranged on opposite sides of one short isolation structure 20a. Figure 2B In the embodiment of the present invention, at least one long isolation structure 20b includes a narrow section 20bn, and a short isolation structure 20a is positioned beside the narrow section 200bn.

[0045] Figure 2C 1 is a schematic top view of a semiconductor device 10c according to an embodiment of the present disclosure. The semiconductor device 10c is similar to the semiconductor device 10 with different arrangements of short isolation structures and long isolation structures. In the semiconductor device 10c, two or more long isolation structures 20b and two or more short isolation structures 20a are alternately arranged. Each long isolation structure 20b includes a narrow section 20bn, and the short isolation structure 20a is positioned adjacent to the narrow section 20bn.

[0046] In addition to employing isolation patterns with short isolation structures adjacent to long isolation structures, embodiments of the present disclosure also apply stress to the semiconductor during patterning and use a passivation oriented etch process to improve performance.

[0047] Figure 3A is a schematic top view of semiconductor device 10 showing a patterned design formed in a photoresist layer. Figure 3B It is along Figure 3A Schematic cross-sectional view of semiconductor device 10 taken along line 3B-3B in FIG. Figure 3A-3B As shown, before forming the isolation pattern, a mask layer 46 and three photoresist layers are sequentially deposited on the semiconductor device 10. The three photoresist layers may include a carbon-based bottom layer 30, an oxide-based middle layer 28, and a top photoresist layer 24. After the photolithography process, a developed pattern is formed in the photoresist layer 24, such as Figure 3A and Figure 3B As shown. The pattern after development is similar to the isolation pattern finally formed in the semiconductor device 10, but there are some differences to adapt to the pattern transfer rules. In some embodiments, the pattern after development may include a short opening 26a disposed adjacent to the long opening 26b. In some embodiments, the long opening 26b may include a narrow section 26bn and two wide sections 26bw extending from the narrow section 26bn. The narrow section 26bn of the long opening 26b overlaps the short opening 26a along the y direction.

[0048] The developed pattern is then transferred to mask layer 46 using one or more etching processes. Figure 3C 4 is a schematic cross-sectional view of the pattern transferred to the mask layer 46. Figure 3C As shown, openings 48a, 48b are formed through the mask layer 46. The openings 48a, 48b may be collectively referred to as post-hard mask patterns. Due to process limitations, there is an etching bias or difference between the post-development pattern and the post-hard mask pattern. However, the amount of bias between the patterns varies due to changes in pattern density and feature size. In other words, there is an etching bias load due to changes in pattern density and feature size. The embodiments of the present disclosure use a combination of long features and short features and a hard mask layer 46 that applies tensile stress to the semiconductor substrate 12 to reduce the etching bias load.

[0049] Figure 4A The loading of the etch bias when patterning the hard mask layer under different process conditions is schematically shown. Figure 4A The x-axis represents the pitch size. For example, the gate pitch GP in the semiconductor device 10 represents the pitch size of the isolation opening 20. The y-axis represents the etching bias calculated between the post-development pattern obtained from the post-development inspection and the post-hard mask pattern obtained from the post-hard mask etching inspection. Figure 4A As shown, the etch bias increases with increasing pitch size. In other words, when the feature size is large and the pattern density is low, the absolute value of the etch bias is higher; and when the feature size is small and the pattern density is high, the absolute value of the etch bias is lower. Curve 402 shows that for a pattern with short trenches, the etch bias decreases with the pitch size. Curve 404 shows that for a pattern with long trenches, the etch bias decreases with the pitch size. Curve 406 shows that for a pattern with intermediate trenches, the etch bias decreases with the pitch size. Curves 402, 404, and 406 indicate that short trenches have less etch bias loading.

[0050] As semiconductor devices shrink, it is desirable to limit etch bias loading to the high density application area marked by 408. Since the loading effect of the etch bias is less pronounced for the short trenches, the short trenches can be formed close to the target CD. When the long and short trenches are modified to avoid photoresist stripping, the short trenches can remain unchanged and the CD design of the long trenches can be modified.

[0051] In addition, a passivation oriented etch process and / or stress adjustment can be used to compensate for the CD and trench depth of long trenches. Figure 4A As shown by the dashed line enclosing curves 402, 404, and 406, applying a tensile stress to the substrate being processed may reduce the etch bias across the pitch size, while applying a compressive stress to the substrate being processed may increase the etch bias across the pitch size.

[0052] In some embodiments, hard mask layer 46 can be selected to apply appropriate stress to the semiconductor substrate to reduce etch bias loading. In some embodiments, hard mask layer 46 can be selected to apply tensile stress to the substrate to reduce etch bias. In some embodiments, the hard mask layer can be a silicon nitride layer. In some embodiments, hard mask layer 46 can be selected to apply tensile stress in an amount between about 0.8 GPa and about 1.2 GPa, such as about 1 GPa.

[0053] Figure 4B The effect of hard mask layer 46 exerting compressive stress on substrate 12 is schematically illustrated. By exerting compressive stress on substrate 12, hard mask layer 46 shrinks the surface area of ​​substrate 12, resulting in an opening having a reduced or compressed CD.

[0054] Figure 4C The effect of hard mask layer 46 applying tensile stress on substrate 12 is schematically illustrated. By applying tensile stress to substrate 12, hard mask layer 46 expands the surface area of ​​substrate 12, resulting in an opening with an increased CD.

[0055] Figure 4D Schematic diagram showing the use of a combination of stress, feature length, and pattern density to tune the etch bias. Figure 4D In the figure, four patterns are characterized by (1) long trench and low density; (2) short trench and low density; (3) long trench and high density; and (4) short trench and high density, which are etched from a hard mask layer with tensile stress and a hard mask layer with compressive stress. The resulting patterns have various etch biases in the hard mask layer.

[0056] In some embodiments, a passivation oriented etching process can be used to control the etching rate and achieve a desired etching depth in a semiconductor substrate. A passivation oriented etching process refers to an etching operation in which the etching rate is limited and / or is largely determined by the passivation effect. A passivation oriented etching process is different from an etchant oriented etching process, which refers to an etching operation with an etching rate that is not limited by the passivation effect.

[0057] In the passivation orientation etching operation, a large amount of polymer and byproducts are generated to passivate the sidewalls of the etched trench. In some embodiments, the byproducts are still active for chemical reactions and etching of semiconductor materials can be performed. In other embodiments, the byproducts are not active for chemical reactions, so that the etching of semiconductor materials is stopped by the byproducts.

[0058] The etching rate ER can be determined by the following equation:

[0059]

[0060] Among them, S is the sticking coefficient, Y is the yield, and Γ is the flux.

[0061] In addition, the desorption rate of the byproducts may affect the etching rate. The following table presents the boiling points (BP) of the byproducts of selected etchants at 1 atmosphere:

[0062]

[0063] As shown in Table 1, the byproduct desorption rate of SiF4 is greater than that of SiCl4, which is greater than that of SiBr4. Therefore, HBr-based etching operations result in severe byproduct accumulation, leading to a passivation-oriented process. On the other hand, Cl / F-based etching operations result in rapid removal of byproducts by desorption, resulting in an etchant-oriented process. It is noted that the pressure in the etching chamber can be much lower than 1 atm; however, the trend of the byproduct desorption rate is expected to remain unchanged.

[0064] Figure 5A-5D The passivation orientation etching operation in forming the trench 56 of the isolation structure 20 is schematically illustrated. Figure 5A-Figure 5B The isolation trench 56 is schematically shown. Figure 5B As shown, the passivation oriented etching operation etches trench 56 to a vertical depth d1. The passivation oriented etching operation forms byproducts 47 on hard mask layer 46 and on the sidewalls of trench 56. Byproducts 47 may be, for example, a polymer film.

[0065] For the passivation orientation etching operation in the isolation trench 56, the total reaction area A1 is equal to the width w times the length l plus the depth d1 times twice the length l1:

[0066] A1≈(w×l)+2(d1×l1)

[0067] It has been found that in isolated patterns, e.g. Figure 5A-5B The passivation oriented etching operation forms the isolation trench 56 having a relatively shallow vertical etching depth d1.

[0068] Figure 5C and Figure 5D FIG. 2 shows the etchant orientation etching operation when forming the closely spaced trenches 56. Figure 5D As shown, the etchant-oriented etching operation etches the densely arranged trenches 56 to a vertical depth d2. The passivation-oriented etching operation forms byproducts 47 on the hard mask layer 46 and on the sidewalls of the densely arranged trenches 56.

[0069] For the passivation orientation etch operation in the dense region 1002, the total reaction area A2 is equal to the width w times the length l plus n times twice the depth d2 times the length l2, where n is the number of fin structures in the dense region:

[0070] A2≈(w×l)+n×2(d2×l2)

[0071] It has been found that in dense patterns, e.g. Figure 5C-5D In the isolation trench 56, the etchant is directed to etch a trench having a relatively deep vertical etch depth d2.

[0072] Figure 6 is a flow chart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 7A-7B and Figure 13A-13B Various stages of manufacturing a semiconductor device 300 according to an embodiment of the present disclosure are schematically illustrated. The semiconductor device 300 may include an isolation structure similar to the semiconductor devices 10, 10a, 10b, 10c, and 10d.

[0073] The method 100 begins at operation 102, where a plurality of semiconductor fins 320 are formed over a substrate 310, such as Figure 7A-7B shown. Fig. 7A is a cross-sectional view of the semiconductor device 300 along the x-direction. Figure 7B is a schematic cross-sectional view of the semiconductor device 300 along the y direction.

[0074] Substrate 310 may include a single crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Substrate 310 may include various doping configurations depending on the circuit design. For example, different doping profiles (e.g., n-well, p-well) may be formed in substrate 310 in regions designed for different device types, such as n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). In some embodiments, substrate 310 may be a silicon-on-insulator (SOI) substrate including an insulator structure for enhancement.

[0075] The semiconductor fins 320 are formed on and in the substrate 310. The semiconductor fins 320 can be formed by patterning a hard mask deposited on the semiconductor stack and one or more etching processes. The semiconductor fins 320 are formed along the x-direction. Each semiconductor fin 320 includes a well portion 312 formed by the semiconductor substrate 310 and a semiconductor stack including sacrificial semiconductor layers 314 and semiconductor channel layers 316 that are alternately stacked.

[0076] An isolation layer 322 is then formed in the trenches between the semiconductor fins 320. The isolation layer 322 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 322 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, or combinations thereof. In some embodiments, the isolation layer is formed to cover the semiconductor fins 320 by a suitable deposition process, such as atomic layer deposition (ALD), and then a recess is etched using a suitable anisotropic etching process to expose the channel portion 318 of the semiconductor fin.

[0077] In some embodiments, dielectric fins (not shown) may be formed between semiconductor fins 320. Dielectric fins may be formed during deposition and etch-back of isolation layer 322.

[0078] In operation 104, a sacrificial gate structure 328 and a spacer layer 330 are formed over the semiconductor fin 320, such as Figure 7A-7B As shown. Sacrificial gate dielectric layer 324 is deposited on the exposed surface of semiconductor device 300. Sacrificial gate dielectric layer 324 can be conformally formed on semiconductor fin 320 and isolation layer 322. In some embodiments, sacrificial gate dielectric layer 324 can be deposited by CVD process, sub-atmospheric CVD (SACVD) process, FCVD process, ALD process, PVD process or other suitable process. Sacrificial gate dielectric layer 324 can include one or more layers of dielectric material, such as SiO2, SiN, high-K dielectric material and / or other suitable dielectric material.

[0079] A sacrificial gate electrode layer 326 is deposited over the sacrificial gate dielectric layer 324. The sacrificial gate electrode layer 326 may be blanket deposited over the sacrificial gate dielectric layer 324. The sacrificial gate electrode layer 326 includes silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer 326. The sacrificial gate electrode layer 326 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A patterning operation is performed over the sacrificial gate dielectric layer 324 and the sacrificial gate electrode layer 326 to form a sacrificial gate structure 328 that covers the portion of the semiconductor fin 320 that is designed as the channel region.

[0080] A gate sidewall spacer 330 is then formed on the sidewalls of each sacrificial gate structure 328. After forming the sacrificial gate structure 328, the gate sidewall spacer 330 may be formed by blanket deposition of an insulating material followed by anisotropic etching to remove the insulating material from horizontal surfaces. The gate sidewall spacer 330 may have a thickness in a range between about 3 nm and about 8 nm. In some embodiments, the insulating material of the gate sidewall spacer 330 is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. Fig. 7A In the embodiment, the gate sidewall spacer 330 includes two layers. In other embodiments, the gate sidewall spacer 330 can be formed of fewer or more dielectric material layers.

[0081] The semiconductor fin 320 is etched back to form source / drain recesses. The end of the semiconductor layer 314 is selectively removed and an inner spacer 332 is formed therein.

[0082] In operation 106, source / drain regions 340 are formed by epitaxial growth methods using CVD, ALD, or molecular beam epitaxy (MBE), such as Figure 7A-7B As shown. The source / drain region 340 may include one or more layers of Si, SiP, SiC, and SiCP for NFETs, or one or more layers of Si, SiGe, Ge for PFETs. For PFETs, p-type dopants such as boron (B) may also be included in the source / drain region 340.

[0083] A contact etch stop layer (CESL) 342 and an interlayer dielectric (ILD) layer 344 are formed over the exposed surface. The CESL 342 is formed over the epitaxial source / drain regions 340 and the gate sidewall spacers 330. The CESL 342 may include Si3N4, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD. The interlayer dielectric (ILD) layer 344 is formed over the shrink etch stop layer (CESL) 342. Materials for the ILD layer 344 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may be used for the ILD layer 344. After the ILD layer 344 is formed, a planarization operation, such as CMP, is performed to expose the sacrificial gate electrode layer 326 for subsequent removal of the sacrificial gate structure 328. During the removal of the sacrificial gate structure 328, the ILD layer 344 protects the epitaxial source / drain regions 340.

[0084] In operation 108, a mask layer 348 is deposited on the semiconductor device 300, such as Figure 7A-7BAs shown. Mask layer 348 may include one or more dielectric layers. Mask layer 348 may be deposited over sacrificial gate structure 328, gate spacer 330, CESL 342, and ILD layer 344. In some examples, one or more mask layers may be or include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be deposited by CVD, PVD, ALD, or other deposition techniques. In some embodiments, the composition and thickness of mask layer 348 may be selected to apply a tensile stress to substrate 312, similar to Figure 4C The hard mask layer 46 in the substrate 312. By applying tensile stress to the substrate 312, the etching bias loading in the subsequent etching process can be reduced. In some embodiments, the mask layer 348 can be silicon nitride, and its thickness ranges between about 650 angstroms and 850 angstroms, for example, between about 730 angstroms and about 750 angstroms.

[0085] In operation 110, a photolithography process is performed to form a CPODE pattern in a photoresist layer, such as Figure 8A-8B In some embodiments, a three-layer photoresist stack is deposited, the three-layer photoresist stack including a bottom layer 350, a back anti-reflective coating (BARC) 352, and a photoresist (PR) layer 354. A photolithography process is performed to form a CPODE pattern.

[0086] In some embodiments, the CPODE pattern may include a long opening 356 and a short opening 358 aligned with the sacrificial gate structure 328. The long opening 356 and the short opening 358 are aligned with two adjacent sacrificial gate structures 328. The short opening 358 is shaped to form a short section of the isolation structure 20 described above. The long opening 356 may include a narrow section and two wide sections. The narrow section of the long opening 356 overlaps with the short opening 358.

[0087] Long openings 356 and short openings 358 may be arranged in a pattern to achieve isolation on semiconductor fins 320. Long openings 356 and short openings 358 may form a pattern similar to the isolation patterns described in semiconductor devices 10, 10a, 10b, 10c, and 10d.

[0088] like Fig. 8A As shown, long openings 356 and short openings 358 are positioned along two adjacent sacrificial structures 328. By positioning long openings 356 next to short openings 356, the spacing between openings 356, 358 can be maintained at a size to avoid photoresist defects (eg, lift-off).

[0089] In operation 112, the CPODE pattern is transferred to the mask layer 348, as shown in FIG. Figure 9A-9BAs shown. In some embodiments, the CPODE pattern can be transferred to the mask layer 348 by a suitable etching process. As described above, the combination of the short trench and long trench design and the tensile stress applied by the hard mask layer 246 reduces the etching bias loading. After operation 112, a portion of the sacrificial gate structure 328 is exposed. The long opening 356 in the mask layer 348 can be wider than the sacrificial gate electrode layer 326 along the x-direction, while the short opening 356 in the mask layer 349 can expose a portion of the sacrificial gate electrode 326.

[0090] In operation 114, an etching process is performed to selectively remove the sacrificial gate electrode layer 326, such as Figure 10A-10B In some embodiments, when the sacrificial gate electrode layer 326 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 326 without removing the dielectric material of the ILD layer 342, the CESL 344, and the sidewall spacer 330. Fig. 10A As shown, the gate sacrificial gate electrode layer 326 may be substantially removed beneath the long openings 356 and the short openings 358 in the mask layer 348 , thereby exposing the gate spacers 330 .

[0091] In operation 116, an etching process is performed to remove the sacrificial gate dielectric layer 324, such as Figure 11A-11B As shown. The sacrificial gate dielectric layer 324 may be removed by any suitable etching process, such as plasma dry etching and / or wet etching. After operation 116, the semiconductor fins 320 exposed by the openings 356, 358 are exposed.

[0092] In operation 118, an etching process is performed to remove the semiconductor fins 320 and into the semiconductor substrate 310, and to form isolation openings 362, 364, as shown in FIG. Figure 12A-12B The etching process may include one or more plasma etching operations configured to selectively remove semiconductor material to form a self-aligned CPODE opening in the semiconductor substrate 310. In some embodiments, the self-aligned etching process may be performed by one or more plasma etching operations.

[0093] In some embodiments, a passivation orientation etching operation is performed to remove semiconductor material through openings 356, 358. In some embodiments, the passivation orientation etching process can be achieved by HBr-based plasma etching. In some embodiments, O2 or CO2 can be added to HBr. In some embodiments, at the beginning of the etching process, a polymer protective layer can be deposited on the top of the hard mask layer 348 to increase the etching selectivity of the semiconductor material (e.g., silicon) relative to the material (e.g., SiN) in the hard mask layer 348. In addition, a passivation layer can be formed during the etching process to facilitate a self-aligned etching process. In some embodiments, the passivation layer can be based on silicon oxide. In some embodiments, a precursor containing SiCl4, O2, and HBr can be used to perform the passivation process. In some embodiments, a penetration operation can be performed to remove excess passivation layers. In some embodiments, the penetration operation can be an etching process based on a fluorine-containing etchant (e.g., CF4, CHF3, CH2F2, and C4F6 or a combination thereof).

[0094] In some embodiments, the plasma etching process may be a high-density plasma process. The etching process may be performed using a processing chamber with an ICP (inductively coupled plasma) or a resonant antenna plasma source. The plasma may be driven by an RF power generator using an AC current operating at a frequency multiple of 13.56 MHz and 27 MHz. The processing chamber may operate at a pressure in the range of about 1 mTorr to about 200 mTorr. The etching process may be performed at a temperature range between about 10 degrees Celsius and about 200 degrees Celsius. The RF power generator may operate at a power level between about 0 W and about 2500 W. In some embodiments, an RF bias power may be applied to a substrate pedestal in the processing chamber. The RF bias power may be in the range of about 0 W to about 2000 W. In some etching operations, the etching plasma may be pulsed with a duty cycle in the range of about 5% to 95%. In some embodiments, the plasma operation may be performed only with a bias power, i.e., with zero plasma power, to enhance etching directionality.

[0095] After operation 118, isolation openings 362, 364 are formed through long opening 356 and short opening 358 in mask layer 348, respectively. In some embodiments, isolation opening 364 extends deeper into semiconductor substrate 310 than a section of isolation opening 364 corresponding to a narrow section of long opening 356 overlapping short opening 358. Opening 364 may have a depth D1 below isolation layer 322 along the z-direction. Opening 362 may have a depth D2 below isolation layer 322 along the z-direction. Depth D1 is greater than depth D2.

[0096] In operation 120, openings 362 and 364 are filled with an isolation material to form isolation structures 366, 368, as shown in FIG. Figure 13A-13B As shown. In some embodiments, a filling material is deposited in the openings 362, 264 to replace the removed semiconductor substrate 310, the semiconductor fin 320, and the segments of the sacrificial gate structure 3. The filling material may be an insulating material. In some examples, the filling material may be a single insulating material, while in other examples, the filling material may include a plurality of different insulating materials, such as a multilayer configuration. The filling material may be or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be deposited by CVD, PVD, ALD, or other deposition techniques. In some embodiments, a liner layer 365 may be formed before depositing the filling material. After depositing the liner layer 365 and the filling material, a CMP process may be performed to expose the sacrificial gate structure 328 for subsequent processes.

[0097] The isolation structure 368 extends sufficiently deep into the semiconductor substrate 310 and provides electrical isolation between the source / drain regions 340 on opposite sides.

[0098] In operation 122, a replacement gate process is performed, such as Figure 13A-13B As shown. First, the sacrificial gate structure 328 is removed. In particular, the sacrificial gate electrode layer 326 and the sacrificial gate dielectric layer 324 are removed in sequence to expose the semiconductor fin 320. The sacrificial semiconductor layer 314 is then removed to expose the channel layer, i.e., the semiconductor layer 316. A replacement gate structure 374 is then formed around the semiconductor layer 316. The gate dielectric layer 370 is formed on the semiconductor layer 316, and the gate electrode layer 372 is formed on the gate dielectric layer 370. The gate dielectric layer 370 and the gate electrode layer 372 may be referred to as a replacement gate structure 374.

[0099] The gate dielectric layer 370 may be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 370. The gate dielectric layer 370 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0100] The gate electrode layer 372 is formed on the gate dielectric layer 370. The gate electrode layer 372 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 372 can be formed by CVD, ALD, electroplating or other suitable methods.

[0101] The semiconductor device 300 is a GAA device. The method 100 can also be used to manufacture FinFET devices.

[0102] Embodiments of the present disclosure may also be used to form isolation structures in a CMODE process. The CMODE process is similar to the CPODE process described above, except that a replacement gate process (eg, operation 122 in method 100) is performed before forming the isolation structure (eg, operations 108-120 in method 100).

[0103] Various embodiments or examples described herein provide several advantages over the prior art. The method according to the present disclosure enables gate pitch scaling in CPODE or CMODE processes without photoresist defects or performance loss.

[0104] It should be understood that not all advantages are necessarily discussed herein, that all embodiments or examples do not require a particular advantage, and that other embodiments or examples may provide different advantages.

[0105] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first length along the second direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second length along the second direction, the first gate structure is located adjacent to the second gate structure, and the first length is shorter than the second length.

[0106] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a first gate structure disposed on the plurality of fin structures and extending along a second direction; a second gate structure disposed on the plurality of fin structures and extending along the second direction; a first isolation structure disposed in the first gate structure, wherein the first isolation structure has a first length along the second direction; and a second isolation structure disposed in the second gate structure, wherein the second isolation structure includes: a first segment having a first width along the first direction; a second segment having a second width along the first direction and a second length along the second direction, wherein the first width is greater than the second width; and a third segment having the first width, wherein the second segment is disposed between the first segment and the third segment, and the first isolation structure overlaps with the second segment of the second isolation structure.

[0107] Some embodiments provide a method for forming a semiconductor device. The method includes: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer on the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern includes: a first opening aligned with a first gate structure among the plurality of gate structures, wherein the first opening has a first length along the second direction; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the second opening has a second length greater than the first length, and the second opening includes: a narrow section; a first wide section and a second wide section extending from the narrow section, wherein the first opening overlaps the narrow section of the second opening; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0108] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

[0109] Example 1 is a semiconductor device, comprising: a semiconductor substrate; a fin structure located on the semiconductor substrate and extending along a first direction; a plurality of gate structures crossing the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first length along the second direction; and a second isolation structure formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second length along the second direction, the first gate structure is positioned adjacent to the second gate structure, and the first length is shorter than the second length.

[0110] Example 2 is a semiconductor device described in Example 1, wherein the first isolation structure has a first width along the first direction, and the second isolation structure includes: a narrow segment having a second width along the first direction; and a wide segment extending from the narrow segment, wherein the second width is smaller than the first width, and the narrow segment overlaps with the first isolation structure along the second direction.

[0111] Example 3 is the semiconductor device described in Example 2, wherein the plurality of gate structures are uniformly distributed along the first direction with a gate pitch, and the first length is greater than 0.5 times the gate pitch.

[0112] Example 4 is the semiconductor device of Example 3, wherein the first length is in a range between approximately 2 times and 10 times the gate pitch.

[0113] Example 5 is the semiconductor device of Example 4, wherein the narrow section of the second isolation structure has a third length along the second direction, and the third length is equal to or greater than the first length.

[0114] Example 6 is a semiconductor device as described in Example 2, wherein the first isolation structure cuts through the fin structure and extends into the semiconductor substrate to a first depth, a narrow section of the second isolation structure cuts through the fin structure and extends into the semiconductor substrate to a second depth, and the first depth is greater than the second depth.

[0115] Example 7 is the semiconductor device of Example 1, wherein the fin structure includes a single channel.

[0116] Example 8 is the semiconductor device of Example 1, wherein the fin structure includes two or more channels.

[0117] Example 9 is a semiconductor device, comprising: a semiconductor substrate; a plurality of fin structures located on the semiconductor substrate and extending along a first direction; a first gate structure arranged on the plurality of fin structures and extending along a second direction; a second gate structure arranged on the plurality of fin structures and extending along the second direction; a first isolation structure arranged in the first gate structure, wherein the first isolation structure has a first length along the second direction; and a second isolation structure arranged in the second gate structure, wherein the second isolation structure comprises: a first segment having a first width along the first direction; a second segment having a second width along the first direction and a second length along the second direction, wherein the first width is greater than the second width; and a third segment having the first width, wherein the second segment is arranged between the first segment and the third segment, and the first isolation structure overlaps with the second segment of the second isolation structure.

[0118] Example 10 is the semiconductor device of Example 9, wherein the second length is equal to or greater than the first length.

[0119] Example 11 is the semiconductor device of Example 10, wherein the first isolation structure has a third width along the first direction, and the third width is greater than the second width.

[0120] Example 12 is the semiconductor device described in Example 11, further comprising: a third isolation structure disposed in a third gate structure, wherein the third isolation structure has the first length and the second width, and the first isolation structure and the third isolation structure are disposed on opposite sides of the second isolation structure.

[0121] Example 13 is the semiconductor device described in Example 12, further comprising: a third isolation structure disposed in a third gate structure, wherein the second isolation structure and the third isolation structure are disposed on opposite sides of the first isolation structure.

[0122] Example 14 is a semiconductor device described in Example 13, wherein the third isolation structure includes: a first segment having the first width along the first direction; a second segment having the second width along the first direction and the second length along the second direction; and a third segment having the first width, wherein the second segment is disposed between the first segment and the third segment, and the first isolation structure overlaps with the second segment of the third isolation structure.

[0123] Example 15 is a method for forming a semiconductor device, comprising: forming a plurality of fin structures on a substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; forming a pattern in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure among the plurality of gate structures, wherein the first opening has a first length along the second direction; and a second opening aligned with a second gate structure among the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the second opening has a second length greater than the first length, and the second opening comprises: a narrow section; a first wide section and a second wide section extending from the narrow section, wherein the first opening overlaps with the narrow section of the second opening; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and depositing a dielectric layer to fill the first isolation opening and the second isolation opening.

[0124] Example 16 is the method of Example 15, wherein depositing the mask layer includes applying tensile stress to the semiconductor substrate using the mask layer.

[0125] Example 17 is the method described in Example 16, wherein forming the first isolation opening and the second isolation opening includes: etching the first gate structure and the second gate structure to expose the fin structure; and etching through the fin structure and into the substrate using a passivation orientation process.

[0126] Example 18 is the method of Example 17, wherein forming the plurality of gate structures includes forming a plurality of sacrificial gate structures, and the method further includes: performing a replacement process after depositing the dielectric layer.

[0127] Example 19 is the method of Example 15, wherein the pattern further includes: a third opening aligned with a third gate structure, wherein the third opening has the first length, and the first opening and the third opening are disposed on opposite sides of the second opening.

[0128] Example 20 is the method of Example 15, wherein the pattern further includes: a third opening aligned with a third gate structure, wherein the third opening has the second length, and the second opening and the third opening are disposed on opposite sides of the first opening.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A fin structure, located on the semiconductor substrate and extending along a first direction; A plurality of gate structures straddling the fin structure along a second direction; a plurality of source / drain regions located above the fin structure and between the plurality of gate structures; a first isolation structure formed in a first gate structure among the plurality of gate structures, wherein the first isolation structure has a first length along the second direction; and A second isolation structure is formed in a second gate structure among the plurality of gate structures, wherein the second isolation structure has a second length along the second direction, the first gate structure is positioned adjacent to the second gate structure, and the first length is shorter than the second length.

2. The semiconductor device according to claim 1, wherein The first isolation structure has a first width along the first direction, and the second isolation structure includes: a narrow section having a second width along the first direction; A wide section extends from the narrow section, wherein the second width is smaller than the first width, and the narrow section overlaps the first isolation structure along the second direction.

3. The semiconductor device according to claim 2, wherein: The plurality of gate structures are uniformly distributed along the first direction with a gate pitch, and the first length is greater than 0.5 times of the gate pitch.

4. The semiconductor device according to claim 3, wherein: The first length is in a range between about 2 and 10 times the gate pitch.

5. The semiconductor device according to claim 4, wherein: The narrow section of the second isolation structure has a third length along the second direction, and the third length is equal to or greater than the first length.

6. The semiconductor device according to claim 2, wherein: The first isolation structure cuts through the fin structure and extends into the semiconductor substrate to a first depth, a narrow section of the second isolation structure cuts through the fin structure and extends into the semiconductor substrate to a second depth, and the first depth is greater than the second depth.

7. The semiconductor device according to claim 1, wherein The fin structure includes a single channel.

8. The semiconductor device according to claim 1, wherein The fin structure includes two or more channels.

9. A semiconductor device comprising: Semiconductor substrate; A plurality of fin structures are located on the semiconductor substrate and extend along a first direction; A first gate structure, disposed on the plurality of fin structures and extending along a second direction; A second gate structure, disposed on the plurality of fin structures and extending along the second direction; A first isolation structure disposed in the first gate structure, wherein the first isolation structure has a first length along the second direction; and A second isolation structure is provided in the second gate structure, wherein the second isolation structure comprises: a first section having a first width along the first direction; a second segment having a second width along the first direction and a second length along the second direction, wherein the first width is greater than the second width; and The third section has the first width, wherein the second section is disposed between the first section and the third section, and the first isolation structure overlaps the second section of the second isolation structure.

10. A method of forming a semiconductor device, comprising: forming a plurality of fin structures on the substrate along a first direction; forming a plurality of gate structures across the plurality of fin structures; depositing a mask layer over the plurality of gate structures; A pattern is formed in the mask layer, wherein the pattern comprises: a first opening aligned with a first gate structure of the plurality of gate structures, wherein the first opening has a first length along the second direction; and a second opening aligned with a second gate structure of the plurality of gate structures, wherein the first gate structure and the second gate structure are adjacent to each other, the second opening has a second length greater than the first length, and the second opening comprises: Narrow section; a first wide section and a second wide section extending from the narrow section, wherein the first opening overlaps the narrow section of the second opening; forming a first isolation opening and a second isolation opening using the pattern in the mask layer; and A dielectric layer is deposited to fill the first isolation opening and the second isolation opening.

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