Transistor, preparation method of transistor and communication equipment

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a transistor, a preparation method of the transistor and communication equipment, and the transistor comprises a substrate, an isolation layer, a gate layer, a dielectric layer, a channel layer, a source drain layer and a passivation layer. The substrate is arranged on the bottommost layer of the transistor; the isolation layer is arranged on the surface of the substrate; the dielectric layer is arranged on the surface of the gate layer; the channel layer is arranged on the surface of the dielectric layer; the channel layer comprises a first region and a second region; the source-drain layer is arranged on the surface of the first region of the channel layer, and the passivation layer is arranged on the surface of the second region of the channel layer; and the channel layer is made of a carbon nano tube. The transistor provided by the invention can realize an encryption communication function through two modes of ASC II code and Morse code, and has great potential for being applied to the fields of Internet of Things and artificial intelligence in the future.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a transistor, a method for manufacturing a transistor, and a communication device. Background Art

[0002] The rapid development of the Internet of Things has put forward higher requirements for physical terminals, which need to integrate multiple functions such as perception, storage, and data communication to meet increasingly complex application scenarios. Therefore, it is crucial to develop a transistor that can integrate perception, storage, and communication at the same time. Summary of the invention

[0003] In view of the above problems, the present application provides a transistor, a method for preparing a transistor and a communication device. The transistor exhibits advantages in high-sensitivity sensing, long-cycle storage and high-efficiency logic calculation, and can meet the requirements of complex application scenarios, such as integrated perception, storage, computing and data communication and other application scenarios. Especially in the field of communications, the transistor described in the present application can realize encrypted communication functions through both ASCII code and Morse code, and has great potential for future applications in the fields of Internet of Things and artificial intelligence.

[0004] In a first aspect, the present application provides a transistor, the transistor comprising a substrate, an isolation layer, a gate layer, a dielectric layer, a channel layer, a source-drain layer, and a passivation layer;

[0005] The substrate is arranged at the bottom layer of the transistor;

[0006] The isolation layer is arranged on the surface of the substrate;

[0007] The dielectric layer is arranged on the surface of the gate layer;

[0008] The channel layer is arranged on the surface of the dielectric layer;

[0009] The channel layer includes a first region and a second region;

[0010] The source-drain layer is disposed on the surface of the first region of the channel layer, and the passivation layer is disposed on the surface of the second region of the channel layer;

[0011] The material of the channel layer includes carbon nanotubes (CNT).

[0012] In the technical solution of the implementation mode of the present application, carbon nanotubes have excellent electrical properties such as high electron mobility, high hole mobility, stable physical and chemical properties and one-dimensional direct band gap. As the material of the channel layer, the transistors formed by carbon nanotubes have advantages in high-sensitivity sensing, long-cycle storage and high-efficiency logic calculation, and can meet complex application scenarios, such as integrated perception, storage, computing and data communication. Especially in the field of communications, the transistors described in the present application can realize encrypted communication functions through two methods: ASCII code and Morse code, and have great potential for future applications in the fields of Internet of Things and artificial intelligence.

[0013] In some embodiments, the thickness of the channel layer is ≤5 nm.

[0014] In the technical solution of the implementation mode of the present application, the reason why the thickness of the channel layer is within the above range is that the deposition of CNTs on the hafnium oxide substrate mainly relies on hydrogen bonding. Therefore, the density of CNTs deposited on the hafnium oxide substrate is related to the number of hydroxyl groups on the substrate surface. The density cannot be infinite, so there is an upper limit to the thickness.

[0015] In some embodiments, the gate layer includes a first gate layer and a second gate layer;

[0016] The second gate layer is close to the dielectric layer.

[0017] In some embodiments, the material of the first gate layer includes titanium nitride and / or titanium;

[0018] The material of the second gate layer includes at least one of tungsten W, palladium Pd, aluminum Al or gold Au.

[0019] In some embodiments, the material of the dielectric layer includes at least one of hafnium oxide, aluminum oxide, or silicon oxide.

[0020] In some embodiments, the source-drain layer includes a source region and a drain region;

[0021] The source region and the drain region are arranged opposite to each other on the surface of the channel layer.

[0022] In some embodiments, the material of the passivation layer includes yttrium trioxide;

[0023] The thickness of the passivation layer is ≤10 μm.

[0024] In the technical solution of the implementation mode of the present application, the reason why the thickness of the passivation layer is within the above range is that: a higher thickness will affect the photosensitivity of the CNT material and thus affect the photoelectric properties.

[0025] In some embodiments, the substrate is made of a heavily P-type doped silicon wafer;

[0026] The material of the isolation layer is silicon dioxide.

[0027] In a second aspect, the present application provides a method for manufacturing a transistor, the method comprising the following steps:

[0028] First, an isolation layer is formed on the surface of the substrate, and then a gate layer is arranged on the surface of the isolation layer, a dielectric layer is arranged on the surface of the gate layer, a channel layer is arranged on the surface of the dielectric layer, a source and drain layer is arranged in a first area of ​​the channel layer, and a passivation layer is arranged in a second area of ​​the channel layer, wherein the material of the channel layer includes carbon nanotubes, to obtain the transistor.

[0029] Preferably, the gate layer is provided by sequentially depositing a raw material for a first gate layer and a raw material for a second gate layer, and etching to form the first gate layer and the second gate layer to obtain the gate layer.

[0030] Preferably, after the gate layer is formed, a dielectric layer is disposed on the surface of the gate layer and on the surface of the isolation layer that is not in contact with the gate layer.

[0031] Preferably, the channel layer is provided by depositing carbon nanotubes and etching.

[0032] In a third aspect, the present application provides a communication device, the communication device comprising the transistor described in the first aspect, or the communication device obtained by the preparation method described in the second aspect;

[0033] Preferably, the signal conversion method in the communication device includes Morse code and / or ASCII code.

[0034] In the technical solution of the implementation mode of the present application, the transistor can be used in the communication field on the basis of having sensing and storage functions, laying the foundation for the subsequent multi-functional integration of a single device.

[0035] The transistor can realize encrypted communication functions through ASCII code and Morse code, and has great potential for future applications in the fields of Internet of Things and artificial intelligence.

[0036] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 A schematic diagram of the structure of a transistor according to an embodiment of the present application;

[0039] Figure 2 This is a schematic structural diagram of a transistor after an isolation layer is formed on a substrate during the preparation process of an embodiment of the present application;

[0040] Figure 3 This is a schematic structural diagram of a transistor after a gate layer is formed on an isolation layer during the preparation process of an embodiment of the present application;

[0041] Figure 4 This is a schematic structural diagram of a transistor after a dielectric layer is formed on a gate layer during the preparation process of an embodiment of the present application;

[0042] Figure 5 This is a schematic structural diagram of a transistor after a source / drain layer and a channel layer are formed on a dielectric layer during the preparation process of the transistor according to one embodiment of the present application;

[0043] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 Different output signal diagrams obtained by performing signal conversion according to Morse code in a transistor of one embodiment of the present application;

[0044] Fig.12 This is a result diagram showing long-period storage characteristics obtained by performing signal conversion according to Morse code in a transistor of one embodiment of the present application;

[0045] Fig.13 This is a result diagram showing high sensitivity characteristics obtained by performing signal conversion according to Morse code in a transistor of one embodiment of the present application;

[0046] Fig.14 This is an output signal diagram obtained by performing signal conversion according to ASCII code for a transistor in one embodiment of the present application.

[0047] The reference numerals in the specific implementation manner are as follows:

[0048] 1-substrate; 2-isolation layer; 31-first gate layer; 32-second gate layer; 4-dielectric layer; 5-channel layer; 61-source region; 62-drain region; 7-passivation layer. DETAILED DESCRIPTION

[0049] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0051] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0052] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] The "range" disclosed in the present application is defined in the form of a lower limit and an upper limit, and a given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundaries of the particular range. The range defined in this way can be inclusive or exclusive of the end values, and can be arbitrarily combined, that is, any lower limit can be combined with any upper limit to form a range. For example, if a range of 60 to 120 and 80 to 110 is listed for a particular parameter, it is understood that a range of 60 to 110 and 80 to 120 is also expected. In addition, if the minimum range values ​​1 and 2 are listed, and if the maximum range values ​​3, 4 and 5 are listed, the following ranges can all be expected: 1-3, 1-4, 1-5, 2-3, 2-4 and 2-5. In the present application, unless otherwise specified, the numerical range "ab" represents an abbreviation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "2-10" means that all real numbers between "2-10" are listed in this document, and "2-10" is just an abbreviation of these numerical combinations. In addition, when a parameter is expressed as an integer ≥ 2, it is equivalent to disclosing that the parameter is, for example, an integer of 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0054] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0055] The rapid development of the Internet of Things has put forward higher requirements on physical terminals. In the existing technology, transistors have the problem of difficulty in balancing high-sensitivity sensing and long-cycle storage, which limits their ability to meet complex application scenarios.

[0056] The present application introduces carbon nanotubes into transistors, thereby making the transistors show advantages in high-sensitivity sensing, long-cycle storage, and high-efficiency logic calculation. The present application provides a transistor, a method for preparing the transistor, and an electrical device.

[0057] [transistor]

[0058] The present application provides a transistor, which includes a substrate, an isolation layer, a gate layer, a dielectric layer, a channel layer, a source-drain layer, and a passivation layer;

[0059] The substrate is arranged at the bottom layer of the transistor;

[0060] The isolation layer is arranged on the surface of the substrate;

[0061] The dielectric layer is arranged on the surface of the gate layer;

[0062] The channel layer is arranged on the surface of the dielectric layer;

[0063] The channel layer includes a first region and a second region;

[0064] The source-drain layer is disposed on the surface of the first region of the channel layer, and the passivation layer is disposed on the surface of the second region of the channel layer;

[0065] The material of the channel layer includes carbon nanotubes.

[0066] In the technical solution of the embodiment of the present application, carbon nanotubes have excellent electrical properties such as high electron mobility, high hole mobility, stable physical and chemical properties and one-dimensional direct band gap. As the material of the channel layer, the transistor formed by carbon nanotubes has advantages in high-sensitivity sensing, long-cycle storage and high-efficiency logic calculation, and can meet the requirements of complex application scenarios, such as integrated perception, storage, computing and data communication. Especially in the field of communications, the transistor described in the present application can realize encrypted communication functions through two methods: ASCII code and Morse code, and has great potential for future applications in the fields of Internet of Things and artificial intelligence.

[0067] In some embodiments, the thickness of the channel layer is ≤5 nm, for example, 2 nm, 3 nm, 4 nm, etc.

[0068] In the technical solution of the embodiment of the present application, the reason why the thickness of the channel layer is within the above range is that the deposition of CNTs on the hafnium oxide substrate mainly relies on hydrogen bonding. Therefore, the density of CNTs deposited on the hafnium oxide substrate is related to the number of hydroxyl groups on the substrate surface. The density cannot be infinite, so there is an upper limit to the thickness.

[0069] In some embodiments, the gate layer includes a first gate layer and a second gate layer;

[0070] The second gate layer is close to the dielectric layer.

[0071] In some embodiments, the material of the first gate layer includes titanium nitride and / or titanium;

[0072] The material of the second gate layer includes at least one of tungsten W, palladium Pd, aluminum Al or gold Au.

[0073] In some embodiments, the dielectric layer is made of at least one of hafnium oxide, aluminum oxide, or silicon oxide.

[0074] In some embodiments, the source-drain layer includes a source region and a drain region;

[0075] The source region and the drain region are arranged opposite to each other on the surface of the channel layer.

[0076] In some embodiments, the material of the passivation layer includes yttrium trioxide;

[0077] The thickness of the passivation layer is ≤10 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, etc.

[0078] In the technical solution of the embodiment of the present application, the reason why the thickness of the passivation layer is within the above range is that a higher thickness will affect the photosensitivity of the CNT material and thus affect the photoelectric properties.

[0079] In some embodiments, the material of the substrate includes a heavily P-type doped silicon wafer;

[0080] The material of the isolation layer includes silicon dioxide.

[0081] In the present application, the heavily P-type doped silicon wafer refers to a silicon wafer into which a high concentration of P-type dopants, such as boron (B), aluminum (Al), etc., are added to increase the hole concentration of the material, thereby changing its electrical properties.

[0082] In some embodiments, the present application provides a method for preparing a transistor, the method comprising the following steps:

[0083] First, an isolation layer is formed on the surface of the substrate, and then a gate layer is arranged on the surface of the isolation layer, a dielectric layer is arranged on the surface of the gate layer, a channel layer is arranged on the surface of the dielectric layer, a source and drain layer is arranged in a first area of ​​the channel layer, and a passivation layer is arranged in a second area of ​​the channel layer, wherein the material of the channel layer includes carbon nanotubes, to obtain the transistor.

[0084] Preferably, the gate layer is provided by sequentially depositing a raw material for a first gate layer and a raw material for a second gate layer, and etching to form the first gate layer and the second gate layer to obtain the gate layer.

[0085] Preferably, after the gate layer is formed, a dielectric layer is disposed on the surface of the gate layer and on the surface of the isolation layer that is not in contact with the gate layer.

[0086] Preferably, the channel layer is provided by depositing carbon nanotubes and etching.

[0087] In some embodiments, the method for preparing the transistor comprises the following steps:

[0088] (1) providing a substrate;

[0089] (2) providing an isolation layer on the surface of the substrate;

[0090] (3) sequentially disposing a first gate layer and a second gate layer on the surface of the isolation layer, and etching to form a gate layer;

[0091] (4) a dielectric layer is disposed on the surface of the gate layer and the exposed surface of the isolation layer, wherein the dielectric layer is coated on the gate layer and disposed on the surface of the isolation layer;

[0092] (5) Arranging a CNT film on the surface of the dielectric layer;

[0093] (6) setting a source region and a drain region in a first region on the surface of the CNT film to form a source-drain layer;

[0094] (7) Partially etching the CNT film to form a channel layer;

[0095] (8) A passivation layer is provided in the second region between the source region and the drain region to obtain the transistor.

[0096] In some embodiments, the present application provides a communication device, which includes the transistor described in the first aspect.

[0097] In the technical solution of the embodiment of the present application, the transistor, in addition to having sensing and storage functions, can also be used in the communication field, laying the foundation for the subsequent single device to achieve multi-functional integration.

[0098] In some embodiments, the signal conversion method in the communication device includes Morse code and / or ASCII code.

[0099] In the technical solution of the embodiment of the present application, the transistor can realize encrypted communication functions through two methods: ASCII code and Morse code, and has great potential for future applications in the fields of Internet of Things and artificial intelligence.

[0100] Example 1

[0101] An embodiment of this embodiment provides a transistor, whose structure is as follows Figure 1 As shown, the transistor is obtained by the following preparation method:

[0102] Step 1, providing a heavily P-type doped silicon wafer as a substrate;

[0103] Step 2: Figure 2 As shown, silicon dioxide is deposited on the surface of the substrate 1 to form an isolation layer 2;

[0104] Step 3: Figure 3 As shown, titanium nitride and tungsten are sequentially deposited on the surface of the isolation layer 2, and then etched to form a first gate layer 31 and a second gate layer 32, thereby obtaining a gate layer;

[0105] Step 4: Figure 4 As shown, a hafnium oxide dielectric layer 4 is deposited on the surface of the gate layer and the exposed surface of the isolation layer, and the dielectric layer is coated on the gate layer and arranged on the surface of the isolation layer;

[0106] Step 5: Figure 5 As shown, a 2.3 nm thick CNT film is deposited on the surface of the dielectric layer; a source region 61 and a drain region 62 are arranged opposite to each other in the first region on the surface of the CNT film to form a source-drain layer; and the CNT film is partially etched to form a channel layer 5;

[0107] Step 6: deposit a 7 nm passivation layer 7 made of yttrium trioxide in the second region between the source region and the drain region, and anneal the device to obtain the transistor.

[0108] Example 2

[0109] An embodiment of the present embodiment provides a transistor, wherein the transistor is obtained by the following preparation method:

[0110] Step 1, providing a heavily P-type doped silicon wafer as a substrate;

[0111] Step 2, depositing silicon dioxide on the surface of the substrate to form an isolation layer;

[0112] Step 3, depositing titanium nitride and gold on the surface of the isolation layer in sequence, etching to form a first gate layer and a second gate layer, thereby obtaining a gate layer;

[0113] Step 4: depositing a hafnium oxide dielectric layer on the surface of the gate layer and the exposed surface of the isolation layer, wherein the dielectric layer is coated on the gate layer and disposed on the surface of the isolation layer;

[0114] Step 5, depositing a 5 nm thick CNT film on the surface of the dielectric layer; arranging a source region and a drain region in a first region on the surface of the CNT film to form a source-drain layer; and partially etching the CNT film to form a channel layer;

[0115] Step 6: deposit a 10 nm yttrium trioxide passivation layer in the second region between the source region and the drain region, and anneal the device to obtain the transistor.

[0116] Example 3

[0117] An embodiment of the present embodiment provides a transistor, wherein the transistor is obtained by the following preparation method:

[0118] Step 1, providing a heavily P-type doped silicon wafer as a substrate;

[0119] Step 2, depositing silicon dioxide on the surface of the substrate to form an isolation layer;

[0120] Step 3, depositing titanium nitride and palladium on the surface of the isolation layer in sequence, etching to form a first gate layer and a second gate layer, thereby obtaining a gate layer;

[0121] Step 4, depositing a hafnium oxide dielectric layer on the surface of the gate layer and the exposed surface of the isolation layer, wherein the dielectric layer is coated on the gate layer and disposed on the surface of the isolation layer;

[0122] Step 5, depositing a 2 nm thick CNT film on the surface of the dielectric layer; arranging a source region and a drain region in a first region on the surface of the CNT film to form a source-drain layer; and partially etching the CNT film to form a channel layer;

[0123] Step 6: deposit a 4 nm yttrium trioxide passivation layer in the second region between the source region and the drain region, and anneal the device to obtain the transistor.

[0124] Application Testing

[0125] The transistor described in Example 1 is tested as follows:

[0126] Test method: The gate voltage is applied to the back gate electrode, the drain voltage is applied to the drain electrode, the pulse tube illuminates the transistor channel position, and the leakage current of the transistor is tested.

[0127] 1. The transistor is converted into a signal in accordance with the Morse code. The result is as follows: Figure 6-Figure 13 As shown. Among them, the pulse light signal is used as the input signal, I ds As the output signal, a light input with a short pulse width represents "·", and a light input with a long pulse width represents "-".

[0128] like Figure 6-11 As shown in the figure, the transistor can obtain different I ds , thereby different input signals can be distinguished and converted into corresponding information according to the Morse code to realize the communication function, that is, by programming light with different pulse widths as the input signal of the transistor to simulate the long and short signals of the Morse code, different current modulation is realized, thereby realizing the communication function.

[0129] like Fig.12 As shown, the output signal can remain stable for a long time, indicating that the transistor described in the present application has the advantage of long-term storage.

[0130] like Fig.13 For example, the wavelength of the light is 450nm and the intensity is 14mW / cm 2 When a light pulse with a frequency of 90 Hz stimulates the transistor, the current of the transistor will change significantly, indicating that the electrical signal can change significantly when an extremely short pulse width light signal stimulates the transistor, indicating that the transistor described in this application has the advantage of high sensitivity.

[0131] 2. The transistor is converted into a signal in accordance with the ASCII code. The result is as follows: Fig.14As shown, under the power density and gate voltage changes shown in the figure, a signal conversion diagram is obtained, in which the light signal and the gate voltage signal are input signals, I ds is the output signal. The input of pulsed light is signal "1", and the input of no pulsed light is signal "0". The input of pulsed gate voltage is signal "1", and the input of no pulsed gate voltage is signal "0". There are four combinations of optical signal and electrical signal (00), (01), (10) and (11). The four different input signals correspond to different output signals I ds Different input signals can be distinguished by the difference in output signals. Four output signals form a group, which are converted into corresponding information through ASCII code to realize the communication function. In summary, by programming pulse light signals and pulse voltage signals as input signals, different current outputs are realized, and the communication function is realized by converting them into corresponding information through ASCII code.

[0132] In summary, the transistor described in this application demonstrates advantages in high-sensitivity sensing, long-cycle storage, and high-efficiency logic computing, and can meet complex application scenarios, such as integrated sensing, storage, computing, and data communication.

[0133] Comparative Example 1

[0134] The difference between this comparative example and Example 1 is that the material of the channel layer and the material of the passivation layer are replaced by only yttrium oxide instead of the combination of carbon nanotubes and yttrium oxide, and the rest are the same as Example 1.

[0135] The results show that the transistor described in Comparative Example 1 cannot be turned on compared to that in Example 1.

[0136] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A transistor, characterized in that: The transistor comprises a substrate, an isolation layer, a gate layer, a dielectric layer, a channel layer, a source-drain layer and a passivation layer; The substrate is arranged at the bottom layer of the transistor; The isolation layer is arranged on the surface of the substrate; The dielectric layer is arranged on the surface of the gate layer; The channel layer is arranged on the surface of the dielectric layer; The channel layer includes a first region and a second region; The source-drain layer is disposed on the surface of the first region of the channel layer, and the passivation layer is disposed on the surface of the second region of the channel layer; The material of the channel layer includes carbon nanotubes.

2. The transistor according to claim 1, characterized in that The thickness of the channel layer is ≤5 nm.

3. The transistor according to claim 1 or 2, characterized in that: The gate layer includes a first gate layer and a second gate layer; The second gate layer is close to the dielectric layer.

4. The transistor according to claim 3, characterized in that The material of the first gate layer includes titanium nitride and / or titanium; The material of the second gate layer includes at least one of tungsten, palladium, aluminum or gold.

5. The transistor according to any one of claims 1 to 4, characterized in that: The material of the dielectric layer includes at least one of hafnium oxide, aluminum oxide or silicon oxide.

6. The transistor according to any one of claims 1 to 5, characterized in that: The source-drain layer includes a source region and a drain region; The source region and the drain region are arranged opposite to each other on the surface of the channel layer.

7. The transistor according to any one of claims 1 to 6, characterized in that: The material of the passivation layer includes yttrium trioxide; The thickness of the passivation layer is ≤10 μm.

8. The transistor according to any one of claims 1 to 7, characterized in that: The material of the substrate includes a heavily P-type doped silicon wafer; The material of the isolation layer includes silicon dioxide.

9. A method for preparing a transistor, characterized in that: The preparation method comprises the following steps: First, an isolation layer is formed on the surface of the substrate, and then a gate layer is arranged on the surface of the isolation layer, a dielectric layer is arranged on the surface of the gate layer, a channel layer is arranged on the surface of the dielectric layer, a source-drain layer is arranged in a first region of the channel layer, and a passivation layer is arranged in a second region of the channel layer, wherein the material of the channel layer includes carbon nanotubes, to obtain the transistor; Preferably, the gate layer is provided by sequentially depositing a raw material for a first gate layer and a raw material for a second gate layer, etching to form the first gate layer and the second gate layer, and obtaining the gate layer; Preferably, after forming the gate layer, a dielectric layer is disposed on the surface of the gate layer and on the surface of the isolation layer that is not in contact with the gate layer; Preferably, the channel layer is provided by depositing carbon nanotubes and etching.

10. A communication device, characterized in that: The communication device comprises the transistor according to any one of claims 1 to 8, or the transistor obtained by the preparation method according to claim 9; Preferably, the signal conversion method in the communication device includes Morse code and / or ASCII code.

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