Node compressibility based bounding volume hierarchy (BVH) widening

Abstract

Systems and techniques are provided for widening a layered structure for ray tracing. For example, a process may include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; and determining one or more candidate hierarchical acceleration data structures, each candidate hierarchical acceleration data structure comprising the plurality of primitives. A cost metric for the one or more candidate hierarchical acceleration data structures may be determined, and based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures may be determined. An output hierarchical acceleration data structure may be generated based on the compressibility prediction.

Description

Technical Field

[0001] The present disclosure generally relates to graphics processing. For example, aspects of the present disclosure relate to systems and techniques for determining shadow rays using a hierarchical structure for ray tracing. Background Art

[0002] Ray tracing is a computer graphics technique that can be used to generate images by tracing the path of light through a three-dimensional scene, simulating interactions with objects illuminated by the light source, and determining ray intersections. Ray intersections can include ray-primitive intersections or ray-object intersections. Primitives are geometric shapes that can be used to construct or model larger three-dimensional objects. For example, primitives can include triangles or polygons.

[0003] Ray tracing can be used to generate realistic images of three-dimensional scenes, including shadows. Scene geometry can be stored in acceleration data structures that group scene primitives. Acceleration data structures can be used to speed up the process of ray tracing by improving the efficiency of ray intersection tests and / or calculations. For example, a bounding volume hierarchy (BVH) is an acceleration data structure that can group scene primitives in a hierarchical tree of bounding volumes that encapsulate one or more of the scene primitives. Ray tracing can be performed by traversing these hierarchical structures to determine ray-primitive and / or ray-object intersections. Summary of the invention

[0004] In some examples, systems and techniques are described for performing a widening of a bounding volume hierarchy (BVH) based on a compressibility determination or prediction for one or more candidate BVH nodes. For example, a compressibility determination or prediction may be determined for one or more BVH leaf nodes of a candidate widened BVH. According to at least one illustrative example, a method for ray tracing is provided, the method comprising: obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determining one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the plurality of primitives; determining a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determining a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generating an output hierarchical acceleration data structure based on the compressibility prediction.

[0005] In another example, an apparatus for ray tracing is provided, the apparatus comprising a memory (e.g., configured to store data, such as graphics data, one or more images, etc.) and one or more processors (e.g., implemented in a circuit) coupled to the memory. The one or more processors are configured and may: obtain a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determine one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the plurality of primitives; determine a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determine a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generate an output hierarchical acceleration data structure based on the compressibility prediction.

[0006] In another example, a non-transitory computer-readable medium having instructions stored thereon is provided, which instructions, when executed by one or more processors, cause the one or more processors to: obtain a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determine one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the plurality of primitives; determine a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determine a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generate an output hierarchical acceleration data structure based on the compressibility prediction.

[0007] In another example, an apparatus for ray tracing is provided. The apparatus includes: a component for obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; a component for determining one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the plurality of primitives; a component for determining a cost metric of the one or more candidate hierarchical acceleration data structures; a component for determining a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures based on the cost metric; and a component for generating an output hierarchical acceleration data structure based on the compressibility prediction.

[0008] In some aspects, one or more of the above-mentioned devices are or are part of: a camera, a mobile device (e.g., a mobile phone or so-called "smart phone" or other mobile device), a wearable device, an extended reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, or a mixed reality (MR) device), a personal computer, a laptop computer, a server computer, or other device. In some aspects, a device includes one or more cameras for capturing one or more images. In some aspects, the device also includes a display for displaying one or more images, notifications, and / or other displayable data. In some aspects, the device may include one or more sensors that can be used to determine the position and / or posture of the device, the state of the device, and / or for other purposes.

[0009] This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification of this patent, any or all drawings, and each claim.

[0010] The foregoing and other features and aspects will become more apparent upon reference to the following description, claims and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Exemplary aspects of the present application are described in detail below with reference to the following drawings:

[0012] Figure 1A An example of a ray tracing process according to some examples is illustrated;

[0013] Figure 1B illustrates an example of a ray tracing process including one or more shadow rays according to some examples;

[0014] Figure 1C An example of a ray tracing process including one or more occluded shadow rays according to some examples is illustrated;

[0015] Figure 2A illustrates an example of a bounding volume including one or more primitives representing portions of a surface in a scene according to some examples;

[0016] Figure 2B Illustrate the organization according to some examples Figure 2A An example of a bounding volume hierarchy (BVH) of a bounding volume;

[0017] Figure 3A An example of a scene object and an object space bounding volume encapsulating the scene object according to some examples is illustrated;

[0018] Figure 3B The encapsulation according to some examples is illustrated Figure 3A An example of object space bounding volumes for and world space bounding volumes for scene objects;

[0019] Figure 4A illustrates an example of an acceleration data structure including a top-level acceleration structure (TLAS) and a bottom-level acceleration structure (BLAS) according to some examples;

[0020] Figure 4B illustrates an example of an acceleration data structure including leaf nodes containing triangles and leaf nodes containing bounding volumes according to some examples;

[0021] Figure 5 is a simplified block diagram illustrating an example ray tracing system according to some examples;

[0022] Figure 6 An example of a binary bounding volume hierarchy (BVH) that organizes one scene primitive per leaf node according to some examples is illustrated;

[0023] Fig. 7A The widening based on some examples is illustrated Figure 6 An example of an 8-wide BVH for a binary BVH as depicted in FIG.

[0024] Figure 7B Some examples are provided for Figure 6 An example of an 8-wide compressed BVH generated by performing widening and compression on the binary BVH depicted in;

[0025] Figure 8 illustrates an example of an 8-wide BVH that may be generated using leaf node compression prediction according to some examples;

[0026] Fig. 9 is a flowchart illustrating an example of a process for graphics processing according to some examples of the present disclosure; and

[0027] Fig.10 is a block diagram illustrating an example of a computing system for implementing certain aspects described herein. DETAILED DESCRIPTION

[0028] Certain aspects of the present disclosure are provided below. Some of these aspects can be applied independently, and some of them can be applied in combination, which is obvious to those skilled in the art. In the following description, specific details are set forth for explanation purposes to provide a thorough understanding of various aspects of the application. However, it is apparent that various aspects can be implemented without these specific details. Each drawing and description are not intended to be restrictive.

[0029] The following description provides only example aspects and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the following description of the example aspects will provide a description that can be used to implement the example aspects to those skilled in the art. It should be understood that various changes can be made to the function and arrangement of elements without departing from the essence and scope of the present application as set forth in the appended claims.

[0030] Ray tracing is a graphics processing and rendering technique that can be used to produce photo-realistic images by modeling the transport of light to simulate optical effects. Ray tracing can realistically simulate the lighting of a three-dimensional (3D) scene and its objects by rendering physically correct reflections, refractions, shadows, and / or indirect lighting in a two-dimensional (2D) view of the scene.

[0031] Ray tracing can be a computationally intensive technique. For example, the computational resources (e.g., computation time) used to ray trace a single frame can increase with the number of rays traced per frame and / or can increase with the computational resources (e.g., computation time) spent tracing each individual ray. Due to this computational complexity, ray tracing can generally be limited to non-real-time uses. Real-time ray tracing has long been sought for uses such as rendering video games, virtual reality (VR), and augmented reality (AR) experiences. Real-time ray tracing has recently become possible through the use of, for example, hardware accelerators and / or graphics processing units (GPUs), which can provide parallelization of the underlying computations for each individual ray cast into a scene.

[0032] The number of rays that can be cast into a scene for each frame is typically relatively small, since the rendering time for each frame cannot exceed a certain maximum amount without sacrificing real-time performance. By increasing the number of rays cast into a scene per frame, image quality when using real-time ray tracing can be improved. For example, the number of rays cast into a scene per frame can be increased by increasing parallelization (e.g., providing additional computing resources that allow more rays to be traced simultaneously). However, hardware upgrades can incur high upfront costs and may be difficult or impossible to retrofit to existing systems and platforms. A scalable and efficient solution is desired that can improve the real-time performance (e.g., image quality) of existing ray tracing hardware.

[0033] Described herein are systems, apparatus, processes (also referred to as methods), and computer-readable media (collectively, "systems and techniques") that can provide accelerated ray tracing operations based on one or more acceleration data structures. For example, as described in more detail herein, systems and techniques can be used to generate one or more binary bounding volume hierarchies (BVHs) based on widening and / or performing leaf node compression. In some examples, systems and techniques can perform compressed-aware BVH widening using one or more leaf node compressibility factors or predictions. For example, systems and techniques can determine or predict the compressibility of one or more BVH leaf nodes, and the predicted compressibility information can be used to perform BVH widening without generating one or more wide BVH nodes that are incompressible (e.g., cannot be compressed within a predetermined or fixed number of bytes). In an illustrative example, BVH widening can be performed based on predicting whether a candidate wide BVH leaf node can be compressed within 64 bytes. If the candidate wide BVH leaf node can be compressed using 64 bytes, the BVH widening can include the candidate wide BVH leaf node. BVH widening may exclude a candidate wide BVH leaf node from consideration if the candidate wide BVH leaf node is not compressible using 64 bytes.

[0034] Various aspects of the application will be described with reference to the accompanying drawings.

[0035] Figure 1A 1 is a diagram illustrating an example of a ray tracing technique 100. As illustrated, a ray tracing system may perform ray tracing by projecting a plurality of rays (e.g., ray 152a, ray 152b, and ray 152c) from a virtual or imaginary view camera 110 (e.g., which determines a view into a 3D scene) through pixels 140 of a 2D view plane into a 3D scene. In some examples, rays 152a-152c may also be referred to as "primary rays." Each primary ray may pass through a particular one of pixels 140 (e.g., such as Figure 1A 140). In some cases, when rendering a 3D scene, each primary ray may pass through a different one of pixels 140. Multiple rays may also be used for some (or all) of pixels 140. Then, after casting one or more of primary rays 152a-152c, the ray tracing system may trace the path of each primary ray to determine whether the ray returns to light source 120 in the 3D scene. Multiple different primary rays may be processed in parallel (e.g., because primary rays interact with various objects, surfaces, light sources, etc. in the 3D scene, but not with other primary rays).

[0036] In the example of the ray tracing technique 100, each primary ray 152a-152c originates from a virtual or imaginary view camera 110 (e.g., sharing a common origin) and is cast through a particular pixel of the plurality of pixels 140 located on a 2D view plane (e.g., as described above). In the event that a particular one of the primary rays 152a-152c reaches a light source (e.g., light source 120) in the 3D scene, then information from that ray contributes to the final color and / or lighting level of the pixel (e.g., from pixel 140) through which the particular ray is cast.

[0037] For example, when a ray projected into a scene intersects one or more objects (e.g., such as object 130), color and lighting information from the intersection point on the surface of the object may contribute to the final color and lighting level of a pixel (e.g., pixel 140) associated with the ray (e.g., primary rays 152a-152c). The color and lighting information may be determined based on whether the ray-object intersection point is directly illuminated by a light source (e.g., light source 120) or is obscured (e.g., shaded). The color and lighting information of the ray-object intersection point may be determined by casting one or more shadow rays from the ray-object intersection point to a light source within the scene, as will be described in more depth below. If the shadow ray does not intersect an object on its path to the light source, the ray-object intersection point (e.g., also referred to as a "hit point") is illuminated. If the shadow ray does intersect another object, the hit point may be obscured (e.g., an object intersected by the shadow ray may cast a shadow on the hit point). Similarly, different objects may have different surface properties that reflect, refract, and / or absorb light in different ways, which also contribute to the final pixel color and / or lighting level. Light may also reflect from an object and hit other objects in the scene or travel through the surface of a transparent object, etc. before reaching a light source (e.g., light source 120).

[0038] For example, Figure 1A , a first primary ray 152a is projected into the scene and intersects the object 130, resulting in the generation of a first shadow ray 162a. The first shadow ray 162a is projected between the point of impact (e.g., where the first primary ray 152a intersects the object 130) and the light source 120, and can be used to determine whether the point of impact between the first primary ray 152a and the object 130 is directly illuminated by the light source 120 or is obscured by additional scene objects. As illustrated, the first shadow ray 162a reaches the light source 120, and thus can contribute color or lighting information for rendering a particular one of the pixels 140 through which the first primary ray 152 is projected. The intersection between the first primary ray 152a and the object 130 (e.g., the point of impact) can also be used to generate one or more reflected rays, such as Figure 1A. The first reflected ray 156a does not reach the light source 120 and therefore cannot directly contribute color or lighting information back to the pixel 140. In some cases, the first reflected ray 156a may intersect with additional scene objects (not shown) and may contribute color and / or lighting information for these additional intersection points between the reflected ray and one or more additional scene objects. The same or similar scenes are illustrated for the second main ray 152b and the associated second shadow ray 162b (e.g., which reaches the light source 120) and the second reflected ray 156b (e.g., which does not reach the light source 120) and the third main ray 152c and the associated third shadow ray 162c (e.g., which reaches the light source 120) and the third reflected ray 156c (which does not reach the light source 120).

[0039] Figure 1B 1 is a diagram illustrating another example of a ray tracing process 100b. Here, a primary ray 152 is projected through a pixel grid 140b and into a scene including an object 130. For example, the primary ray 152 is projected from an origin / viewpoint through a particular pixel 141 (e.g., included in the pixel grid 140b) and intersects the object 130. Then, the point of impact or ray-object intersection between the primary ray 152 and the object 130 is used as an origin to generate and project a shadow ray 162. As described above, the shadow ray 162 may be projected from the point of impact to the light source 120. As shown in FIG. Figure 1B As depicted in , shadow ray 162 reaches light source 120 without intersecting any other objects or scene primitives, and illumination and color information for pixel 141 may be determined based on light source 120 directly illuminating the impact point.

[0040] Figure 1C is a diagram illustrating another example of the ray tracing process 100 c . Figure 1C The diagram and Figure 1B , but with the addition of an additional object 135 (e.g., an additional scene primitive) along a direct path between the impact point (e.g., where the primary ray 152 intersects the object 130) and the light source 120. Here, when a shadow ray 164 is generated and cast from the impact point to the light source 120, the shadow ray 164 intersects the additional object 135 and does not reach the light source 120. Since the shadow ray 164 does not reach the light source 120, the impact point can be considered to be blocked or shaded by the additional object 135. For example, based on the intersection between the shadow ray 164 and the additional object 135, the illumination and color information of the pixel 141 can be determined based on the impact point being blocked or shaded (e.g., blocked or shaded relative to the light source 120). In some examples, after the shadow ray is generated and cast in response to determining the impact point between the primary ray and the scene object / primitive, the processing of the shadow ray can be terminated when the shadow ray intersects the light source or another scene primitive (e.g., whichever comes first).

[0041] As previously mentioned, each interaction between a ray and an object (e.g., a scene object, a primitive, a surface within a 3D scene, etc.) can contribute color and / or lighting information back to a particular pixel through which the primary ray is cast. In some cases, tracing a greater number of interactions per ray can provide increased visual fidelity (e.g., quality) of the rendered scene at the expense of increased computational cost (e.g., time). For example, a ray tracing method that prioritizes speed over quality may only calculate or otherwise determine the first reflection of each ray, while a ray tracing method that prioritizes quality over speed may determine three or more reflections per ray. In some cases, after observing a maximum number of reflections or a ray that travels a certain distance without intersection, the ray may stop traveling and the value of the pixel may be updated. In some cases, the ray may stop traveling and the value of the pixel may be updated based on the ray that travels a certain distance without reflection (e.g., reflection is one possible result of intersection). In some cases, the number of rays cast through each pixel of the 2D viewing plane may be adjusted based on a similar tradeoff between computational cost and visual fidelity.

[0042] As a result, ray tracing becomes very expensive in terms of the time and / or computational power required to render realistic-looking scenes, based on, for example, the number of rays cast into a scene and the number of additional rays traced for secondary reflections and refractions. Due to this computational complexity, ray tracing is typically limited to non-real-time uses (e.g., scenes or visual effects that may be pre-rendered for film and television). Real-time ray tracing has long been sought for use cases such as rendering video games, virtual reality (VR), and augmented reality (AR) experiences, etc.

[0043] Real-time ray tracing has recently become possible, and is typically performed by hardware accelerators and / or graphics processing units (GPUs), which can provide parallelization of the underlying calculations for each individual ray cast into the scene. The number of rays that can be cast into the scene for each frame is typically relatively small, since the rendering time per frame cannot exceed a certain maximum amount without losing real-time performance.

[0044] Image quality when using real-time ray tracing can be improved by increasing the number of rays cast into the scene per frame. This can be achieved by increasing parallelization (e.g., providing additional computing resources that allow more rays to be traced simultaneously). However, hardware upgrades come with high upfront costs and may be difficult or impossible to retrofit to existing systems and platforms. A scalable and efficient solution is desired that can improve the real-time performance of existing ray tracing hardware. For example, the number of rays cast into the scene per frame can also be increased by tracing each ray more efficiently (e.g., reducing the computation time per ray tracing operation allows more ray tracing operations to be performed within the same fixed rendering time per frame).

[0045] One example of a ray tracing acceleration technique utilizes a tree-based (e.g., hierarchical) acceleration structure to improve the efficiency of ray intersection testing (e.g., also referred to as "collision testing" and / or "hit testing") and / or other ray tracing operations. For example, ray intersection testing may include, but is not limited to, determining whether a primary ray intersects one or more scene objects or primitives (e.g., after the primary ray is cast into the scene); determining whether a shadow ray intersects additional scene objects or primitives (e.g., after the shadow ray is cast from the primary ray impact point to the light source); and determining whether a reflected ray intersects additional scene objects or primitives (e.g., after the reflected ray is cast from the impact point, using a calculated reflection angle).

[0046] The scene can be converted into a bounding volume hierarchy (BVH), which is a hierarchical tree structure (e.g., a hierarchical acceleration data structure) composed of increasingly dense bounding volumes (also called "bounding regions", such as bounding boxes or "axis-aligned bounding boxes" (AABBs)). Figure 2A An example is illustrated in which a scene 200a containing a plurality of triangle primitives 252a-252e is arranged into a series of increasingly tight bounding boxes 256a-256e. The scene may contain hundreds, thousands, or more primitives, but for clarity, only five triangle primitives 252a-252e are depicted. The bounding boxes 256a-256e may be AABBs, which are bounding boxes with a minimum area or volume within which all points of the enclosed primitives (e.g., triangle primitives 252a-252e) may be located. The bounding boxes may be axis-aligned so that the edges of each bounding box 256a-256e are parallel to coordinate axes (e.g., x-axis, y-axis, and z-axis). Figure 2B Illustrated with Figure 2A 256a-256e and triangle primitives 252a-252e are associated with each other. The hierarchical data structure 200b may be a BVH. For example, the BVH root node 262a may correspond to Figure 2ASimilarly, the intermediate BVH node 262b may correspond to Figure 2A The bounding box 256b of the intermediate BVH node 262c may correspond to Figure 2A The bounding box 256c, and so on.

[0047] BVH root node (e.g., Figure 2B The BVH root node 262a) contains the AABB (e.g., Figure 2A The BVH leaf node is populated with a bounding box 256a) that encapsulates all individual scene or object geometries contained in the BVH leaf node. Each primitive in the BVH root node is assigned to a left child or a right child. The child nodes contain AABBs that contain their assigned geometry, and the geometry is likewise recursively assigned to the left child or the right child until the BVH leaf node contains a small number of primitives, such as four or fewer. Depending on the extent of any scene changes and / or object deformations, the next frame and any subsequent frames may require one or more new BVH build operations or BVH reassembly / update operations based on the scene changes.

[0048] As mentioned previously, testing the intersection of each ray for each primitive in the scene may be inefficient and computationally expensive. BVHs can be used to accelerate ray intersection testing techniques, as well as other ray tracing operations. For example, BVHs can be used to efficiently traverse during collision checks associated with primary rays, shadow rays, reflected rays, etc. Instead of testing for each primitive in the scene, the intersection of each ray can be measured for a BVH bounding box (e.g., using a depth-first tree traversal process). As mentioned previously, bounding boxes enclose or surround different amounts of scene geometry or primitives and become increasingly dense with the depth of the BVH tree structure.

[0049] Bounding boxes (e.g., AABBs or other bounding boxes) or other bounding regions can be defined relative to world space or object space. World space can be thought of as a constant (e.g., the coordinate space of the entire 3D scene). Objects can exist in their own coordinate space, which is called object space (e.g., the coordinate space in which the object is modeled or created). For example, Figure 3A and Figure 3B is a diagram depicting object space and world space AABBs (axis aligned bounding boxes) for the same geometry. Here, Figure 3AAn object space AABB 320 of a geometric scene object 310 is illustrated. A scene object may include a 3D or graphical object that exists in a 3D scene on which ray tracing is performed. In some cases, a geometric scene object may be a scene object that includes geometric primitives such as triangles. In some examples, a scene object may include an AABB or other object representation. Object space AABB 320 and scene object 310 are shown in object space 300a of scene object 310. Figure 3B The same geometric scene object 310 is illustrated, but transformed into the world space 300b of a scene (eg, a scene to which the scene object 310 belongs or is located).

[0050] Ray tracing can utilize a two-level acceleration structure system, such as the top-level acceleration structure (TLAS) and the bottom-level acceleration structure (BLAS), such as Figure 4A For example, Figure 4A TLAS 410 and BLAS 430 are illustrated and will be described in more depth below.

[0051] TLAS 410 is constructed in world space. TLAS primitives are instances of BLAS, which are defined in object space. TLAS can be constructed as a BVH whose leaf nodes contain BLAS. For example, TLAS leaf nodes 422, 424, 426 and 428 each contain one of the two BLAS 440 and 460 or are otherwise associated with it. Translation matrices can be encoded in TLAS leaf nodes to perform conversions from world space to object space and / or vice versa, as described in more depth below.

[0052] A BLAS can be constructed for each object in the scene (called a scene object). For example, Figure 4A A BLAS 440 that may be constructed for a first unique scene object and a BLAS 460 that may be constructed for a second unique scene object are illustrated. The BLAS primitives may be triangles or AABBs that are procedural primitives used to construct the scene objects. An underlying BVH is constructed on a collection of these triangles or AABBs of scene objects, where each BLAS leaf node contains a small number (e.g., up to four, five, or some other number) of triangles or AABBs. For example, in Figure 4A In the context of , BLAS leaf nodes 452-458 and 472-478 may each contain some number of triangles, AABBs, or other primitives used to construct scene objects. In some examples, the BLAS may also be referred to as a "bottom layer BVH". Multiple instances of the same BLAS may be included in a TLAS. For example, if the TLAS includes a car object, the BLAS for the tires may be included four times. Figure 4A As illustrated in , the same BLAS may also be included in or referenced by multiple TLASs.

[0053] In some examples, a TLAS may be created using an object-to-world matrix that transforms inputs expressed in object space coordinates to outputs expressed in world space coordinates. The world-to-object matrix may apply the transformation in the opposite direction (e.g., transforming inputs expressed in world space coordinates to outputs expressed in object space coordinates). In some cases, a TLAS may be constructed on a set of BLASs by using the object-to-world matrix to compute the world space AABBs of each BLAS (e.g., the world space AABBs of BLAS root nodes 442 and 462). A BVH is then constructed on these world space AABBs of the BLAS root nodes, and the BVH may be referred to as a top-level BVH or TLAS 410. In some cases, similar or identical techniques may be used to perform TLAS and BLAS creation. For example, the same SAH (surface area heuristic) based algorithm or method may be used for both TLAS and BLAS construction.

[0054] Figure 4B 4 is a diagram illustrating an example of an acceleration data structure 400b that includes or stores both triangles and bounding volumes. In some examples, the acceleration data structure 400b may be a BVH (e.g., Figure 4B ), but it should be noted that other hierarchical tree structures and / or other acceleration data structures may also be utilized. Figure 4B As illustrated in FIG. 4 , the acceleration data structure 400 b (e.g., BVH) includes a BVH root node 460, which includes a plurality of bounding volumes 471-478. The bounding volumes 471-478 may correspond to or be otherwise constructed for child nodes of the BVH root node 460. For example, eight bounding volumes 471-478 may be AABBs of eight corresponding child nodes of the BVH root node 460.

[0055] exist Figure 4BIn the example of , acceleration data structure 400b has a branching factor of 8. The branching factor of an acceleration data structure is the maximum number of child nodes that can be associated with or contained by any parent node within the acceleration data structure. The number of child nodes associated with some internal nodes may be less than the branching factor. For example, acceleration data structure 400b has a branching factor of 8, but some internal nodes within acceleration data structure 400b may have less than 8 child nodes. It should be noted that larger or smaller branching factors may also be used to generate acceleration structures, such as acceleration data structure 400b. In the case where acceleration data structure 400b uses a larger or smaller branching factor, the BVH root node 460 and / or BVH internal nodes (e.g., shown here as BVH internal nodes 471-478) may also include a greater or lesser number of bounding volumes or AABBs.

[0056] As mentioned above, BVH root node 460 includes the AABBs of its eight child nodes 471-478. In some examples, the AABBs of child nodes 471-478 may be stored in a data structure of BVH 400b (e.g., included in the information representation of the parent node). For example, BVH root node 460 may include an index to a data storage or memory location where one or more of its child nodes 471-478 may be obtained or retrieved. In an illustrative example, BVH root node 460 includes an index to only the first child node (e.g., BVH internal node 471), with the remaining child nodes (e.g., nodes 472-478) stored adjacent to the memory index of the first child node 471.

[0057] Child node 471 is Figure 4B 471 is depicted as a BVH internal node 471 because node 471 is neither a root nor a leaf of BVH 400b. An internal node of BVH 400b (e.g., such as node 471) may have a number of child nodes that is less than or equal to the branching factor, which is 8 for BVH 400b. In some examples, an internal BVH node (e.g., such as node 471) may contain a bounding volume or AABB for each of its child nodes, as previously described with respect to BVH root node 460. BVH internal node 471 includes a plurality of bounding volumes 481-488, which in this case represent the eight child nodes of internal node 471. Figure 4B As illustrated in , the child nodes of internal node 471 are BVH leaf nodes (eg, leaf nodes of BVH acceleration data structure 400b).

[0058] For example, the child nodes of internal node 471 include BVH leaf node 481 and BVH leaf node 482 (internal node 471 includes additional child nodes 483-488, which are separated from each other for clarity). Figure 4BThe leaf node layer of the BVH 400b omits these additional child nodes). As illustrated, the BVH leaf node 481 includes two triangles 481a and 481b, which are geometric primitives that can be used to construct the scene object or model represented by the BVH 400b. In some cases, the triangles 481a-481b can be encapsulated by corresponding AABBs stored in the internal nodes 471 of the BVH leaf node 481. In an illustrative example, the coordinates of the triangles 481a-481b can be directly stored in the underlying data structure of the BVH 400b, rather than being retrieved from an external data storage or data location. For example, the coordinates (e.g., vertices) of the triangles 481a-481b can be stored in the BVH leaf node 481 itself.

[0059] Figure 4B BVH leaf node 482 is depicted as including four bounding volumes (e.g., AABBs) 482a, 482b, 482c, and 482d. In one illustrative example, bounding volumes 482a-482d may be AABBs of program primitives (e.g., representing spheres or other user-defined shapes). In some examples, bounding volumes 482a-482d may be AABBs of instances of the BVH. As described above with respect to BVH leaf node 481, it should be noted that the four bounding volumes 482a-482d may be encapsulated by corresponding AABBs stored in internal node 471 of BVH leaf node 472. Although Figure 4B BVH internal node 471 is depicted as including child nodes containing triangles (e.g., BVH leaf node 481) and child nodes containing bounding volumes (e.g., BVH leaf node 482), but in some examples, the BVH acceleration data structure 400b as a whole may include only leaf nodes containing triangles or may include only leaf nodes containing bounding volumes.

[0060] In some examples, the ray tracing process can include multiple different stages. For example, the stages of the example ray tracing process can include: bounding volume hierarchy (BVH) construction and refinement, ray generation, BVH traversal, ray-triangle intersection, and ray box intersection. There can also be different steps during BVH construction, including partitioning triangles into multiple groups, forming bounding boxes around each group, and recursively partitioning each group. Additionally, several partitioning methods can be used during BVH construction, which can result in a certain number of possible solutions, such as 2 n(log(n)) One or more of these improved solutions may result in improved ray tracing performance.

[0061] Aspects of ray tracing may also utilize various bounding volume hierarchy algorithms, such as split bounding volume hierarchy (SBVH) and linear bounding volume hierarchy (LBVH). In some cases, SBVH may result in slower build times and better quality than LBVH. Likewise, LBVH may result in faster build times and worse quality than SBVH. In some cases, the ray tracing process may utilize bounding volume hierarchy refinement. For example, in bounding volume hierarchy refinement, given a binary BVH with one triangle per leaf, ray tracing techniques may be used to permute a tree topology (e.g., a tree topology of a binary BVH). In some aspects, bounding volume hierarchy refinement may utilize different algorithms (e.g., treelet reconstruction BVH (TRBVH), parallel reinsertion BVH (PRBVH). In some examples, the ray tracing process may utilize BVH widening, which may convert a binary tree (e.g., BVH) to a wide BVH (e.g., 8-branch wide BVH). In some examples of BVH widening, interior nodes may include up to eight AABBs and leaf nodes may include up to four primitives or triangles.

[0062] A binary BVH may organize a set of primitives (e.g., triangles, AABBs, etc.) into multiple hierarchical levels, where the set of primitives is included in the bottom layer of the hierarchy. For example, a binary BVH may include a root node with two child nodes, each of which is an internal node of the binary BVH. The internal nodes themselves may each have two child nodes, each of which may also be a BVH internal node. At the bottom layer of the binary BVH, a BVH internal node may have up to two child nodes, each of which is a leaf node of the binary BVH. In a binary BVH, each BVH leaf node may include a scene primitive (e.g., a triangle, an AABB, etc.).

[0063] BVH widening may be applied to a given BVH (e.g., such as a binary BVH) or otherwise performed for a given BVH to reduce the depth of the given BVH. For example, BVH widening may be performed for a binary BVH having multiple hierarchical levels to generate a widened BVH having fewer hierarchical levels (e.g., fewer hierarchical levels than the input binary BVH). In some examples, the widened BVH may include only two levels (e.g., a root node and a plurality of leaf nodes associated with the root node). Although a binary BVH may include up to two primitives per BVH leaf node, in some aspects, the widened BVH may include two or more primitives per BVH leaf node. In some examples, the widened BVH may include one or more wide BVH internal nodes, each of which is associated with up to 8 child nodes. Up to eight child nodes of a wide BVH internal node may include additional wide BVH internal nodes, wide BVH leaf nodes, or a combination of both. In some cases, a wide BVH leaf node may include or otherwise be associated with up to four triangles.

[0064] In some examples, the BVH widening technique may generate a widened BVH based on determining one or more cost metrics associated with a binary BVH. For example, the BVH widening may be performed based on a surface area heuristic (SAH) determined for or associated with an input binary BVH. Based on the SAH, up to four triangles may be assigned to a given wide BVH leaf node. In some cases, storing four triangles per leaf node (e.g., per wide BVH leaf node) may increase the node size associated with the wide BVH. For example, the node size may be 64 bytes, which may not be sufficient to store four triangles (e.g., if uncompressed, up to 144 bytes of storage may be required).

[0065] In some cases, compression may be performed for some (or all) of the wide BVH nodes included in the wide BVH. For example, a binary BVH may be widened into a wide BVH (e.g., an 8-wide BVH with up to eight internal child nodes) based on the SAH. Compression may be performed for some or all of the resulting wide BVH leaf nodes. In some cases, the compressed BVH leaf node may be larger than a predetermined size (e.g., 64 bytes). For example, when the compressed BVH node includes four triangles and there is little or no redundancy between them, the compressed BVH leaf node may be larger than 64 bytes. When the compressed BVH leaf node is larger than (or will be larger than) a predetermined size (e.g., 64 bytes), at compression time, the uncompressed BVH leaf node may be split into a plurality of compressible BVH leaf nodes. For example, an uncompressed BVH leaf node may be converted into a BVH internal node, wherein a plurality of new, compressible BVH leaf nodes form child nodes of the newly created BVH internal node.

[0066] Splitting one or more wide BVH leaf nodes into multiple compressible child nodes may introduce additional hierarchy and complexity to the widened BVH and may result in a suboptimal widened BVH. Systems and techniques are needed that can be used to perform BVH widening and leaf node compression without generating multiple compressible child nodes for incompressible wide BVH leaf nodes.

[0067] As previously described, systems and techniques are described herein that can provide perceptually compressed BVH widening. For example, systems and techniques can determine or predict the compressibility of one or more BVH leaf nodes, and the predicted compressibility information can be used to perform BVH widening without generating one or more wide BVH nodes that are incompressible (e.g., cannot be compressed within a predetermined or fixed number of bytes). In an illustrative example, BVH widening can be performed based on predicting whether a candidate hierarchical acceleration data structure leaf node (e.g., a candidate wide BVH leaf node) can be compressed within 64 bytes. If the candidate wide BVH leaf node can be compressed using 64 bytes, then BVH widening can include the candidate wide BVH leaf node. If the candidate wide BVH leaf node cannot be compressed using 64 bytes, then BVH widening can exclude the candidate wide BVH leaf node from consideration.

[0068] Figure 5 is a diagram illustrating an example ray tracing system 500 according to some examples of the present disclosure. The ray tracing system 500 can implement the systems and techniques disclosed herein, including the aspects described above and related Figure 6 A through 7. The ray tracing system 500 may perform various tasks and operations, such as, for example, ray tracing tasks and operations (e.g., ray-primitive intersection, ray-bounding volume intersection, ray-triangle intersection, ray-AABB intersection, acceleration data structure construction and / or updating, rendering, etc.).

[0069] exist Figure 5 In the example shown, the ray tracing system 500 includes a storage device 502, a computing component 510, a ray tracing engine 520, an acceleration data structure engine 522, a node acquisition and cache engine 524, and a graphics processing engine 526. It should be noted that Figure 5 The components 502 to 526 shown are non-limiting examples provided for purposes of illustration and explanation, and other examples may include Figure 5 More, fewer, and / or different components than those shown may be included. For example, in some cases, ray tracing system 500 may include Figure 5 One or more display devices, one or more other processing engines, one or more other hardware components, and / or one or more other software and / or hardware components not shown. Figure 8 An example architecture and example hardware components that may be implemented by ray tracing system 500 are further described.

[0070] Reference to any of the components of ray tracing system 500 in the singular or plural should not be construed as limiting the number of such components implemented by ray tracing system 500 to one or more than one. For example, reference to a processor in the singular should not be construed as limiting the number of processors implemented by ray tracing system 500 to one. One of ordinary skill in the art will recognize that reference to a processor in the singular is not limited to one. Figure 5 , ray tracing system 500 may include only one of such components or more than one of such components.

[0071] Ray tracing system 500 may be part of or implemented by a single computing device or multiple computing devices. In some examples, ray tracing system 500 may be part of an electronic device (or devices) such as a desktop computer, a laptop or notebook computer, a tablet computer, a set-top box, a smart TV, a display device, a game console, a video streaming device, an IoT (Internet of Things) device, a smart wearable device (e.g., a head-mounted display (HMD), smart glasses, an extended reality (XR) device (e.g., a VR headset or head-mounted display (HMD), an AR headset, HMD or glasses, etc.), or any other suitable electronic device.

[0072] In some implementations, the storage device 502, the computing component 510, the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and the graphics processing engine 526 can be part of the same computing device. For example, in some cases, the storage device 608, the computing component 510, the ray tracing engine 520, the acceleration data structure engine 522, and the graphics processing engine 526 can be integrated into a smart phone, a laptop computer, a tablet computer, a smart wearable device, a gaming system, and / or any other computing device. In other implementations, the storage device 502, the computing component 510, the ray tracing engine 520, the acceleration data structure engine 522, and the graphics processing engine 526 can be part of two or more separate computing devices. For example, in some cases, some of the components 502 to 526 can be part of or implemented by one computing device, and the remaining components can be part of or implemented by one or more other computing devices.

[0073] Storage 502 may be any storage device for storing data. In addition, storage 502 may store data from any of the components of ray tracing system 500. For example, storage 502 may store data from computing component 510, data from ray tracing engine 520, data from acceleration data structure engine 522, data from node acquisition and cache engine 524, and / or data from graphics processing engine 526. In some examples, storage 502 may include one or more buffers and / or caches for storing data for processing by computing component 510. In some examples, one or more buffers and / or caches may be general and available for use by some (or all) of computing components 510. In some examples, one or more buffers and / or caches may be provided for specific computing components in computing component 510.

[0074] The computing component 510 may include a central processing unit (CPU) 512, a graphics processing unit (GPU) 514, a memory 516, a ray tracing unit 518, and / or one or more hardware accelerator components 519. In some implementations, the computing component 510 may include other processors or computing components, such as one or more digital signal processors (DSPs), one or more neural processing units (NPUs), and / or other processors or computing components. The computing component 510 may perform various operations, such as ray-primitive intersection, ray-bounding volume intersection, ray-AABB intersection, acceleration data structure construction, acceleration data structure update, scene rendering, rasterization, geometry processing, pixel processing, visibility processing, etc.

[0075] Operations for the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and the graphics processing engine 526 (as well as any other processing engines) may be implemented by any of the computing components 510. In some cases, operations of one or more of the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and the graphics processing engine 526 may be performed by the CPU 512. In one illustrative example, operations of one or more of the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and the graphics processing engine 526 may be performed by the GPU 514. In some cases, operations of one or more of the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and the graphics processing engine 526 may be performed by the RTU 518 and / or one or more hardware accelerators 519.

[0076] In some cases, operations of one or more of ray tracing engine 520, acceleration data structure engine 522, node fetch and cache engine 524, and graphics processing engine 526 may be performed by one or more combinations of CPU 512, GPU 514, RTU 518, and hardware accelerator 519. In some cases, computing component 510 may include other electronic circuitry or hardware, computer software, firmware, or any combination thereof to perform any of the various operations described herein.

[0077] In some examples, ray tracing engine 520 may include one or more ray tracing application programming interfaces (APIs). In one example, ray tracing engine 520 may include one or more ray intersection engines. For example, ray tracing engine 520 may include one or more ray-primitive intersection engines and / or may include one or more ray-bounding volume intersection engines. In some cases, ray tracing engine 520 may include one or more ray-triangle intersection engines and / or may include one or more ray-AABB intersection engines. For example, ray tracing engine 520 may use one or more hardware accelerated ray tracing engines (RTUs) and / or arithmetic logic units (ALUs) to implement one or more ray intersection engines.

[0078] In one illustrative example, the ray tracing engine 520 may communicate with the RTU 518 (and / or the hardware accelerator 519) to perform ray-primitive (e.g., ray-triangle) intersections and / or ray-bounding volume (e.g., ray-AABB) intersections. For example, in some cases, the ray tracing engine 520 may provide one or more input and / or control signals to the RTU 518 (and / or the hardware accelerator 519). The RTU 518 (and / or the hardware accelerator 519) may use the input and control signals from the ray tracing engine 520 to perform ray-primitive intersections and / or ray-bounding volume intersections, and may communicate ray intersection results back to the ray tracing engine 520.

[0079] In some examples, the acceleration data structure engine 522 may construct or generate one or more acceleration data structures. The acceleration data structure generated by the acceleration data structure engine 522 may be used by one or more of the ray tracing engine 520, the node acquisition and cache engine 524, and the graphics processing engine 526. In an illustrative example, the acceleration data structure engine 522 may construct or generate a bounding volume hierarchy (BVH). In some cases, the acceleration data structure engine 522 may generate a two-level acceleration structure (e.g., an acceleration data structure including a TLAS and one or more BLAS). The acceleration data structure engine 522 may be implemented using the CPU 512, the GPU 514, or a combination of the two. In some examples, the acceleration data structure engine 522 may be implemented additionally or alternatively using one or more dedicated hardware accelerator components in the dedicated hardware accelerator component 519.

[0080] In some examples, the graphics processing engine 526 may include a graphics processing pipeline. For example, the graphics processing engine 526 may include, but is not limited to, one or more of a geometry processing stage, a visibility stage, a rasterization stage, and a pixel processing pipeline. In some examples, the graphics processing engine 526 may communicate with or access a memory 516 of the computing component 510. The memory 516 may include one or more of a system memory, a frame buffer, a graphics memory, one or more caches, and the like. In some examples, the graphics processing engine 526 may communicate with one or more of the RTU 518 (e.g., of the computing component 510) and / or the hardware accelerator 519 and / or the ray tracing engine 520.

[0081] In some cases, the ray tracing system 500 (e.g., using the ray tracing engine 520, the acceleration data structure engine 522, the node acquisition and cache engine 524, and / or the graphics processing engine 526) may obtain an acceleration data structure including one or more primitives of the scene object. For example, the ray tracing system 500 may obtain the acceleration data structure from the storage device 502 and / or the memory 516. In some cases, the acceleration data structure engine 522 may be used to generate or construct the acceleration data structure.

[0082] The acceleration data structure engine 522 may obtain one or more representations of scene objects or other scene geometry and generate and / or update a BVH or other acceleration data structure that includes the scene objects or scene geometry. In some examples, the acceleration data structure engine 522 may obtain the representations of the scene objects or other scene geometry at least in part from one or more of the storage device 502 and the memory 516. In some cases, the acceleration data structure engine 522 may obtain the representations of the scene objects or other scene geometry from the ray tracing engine 520 (and / or one or more of the computing components 510).

[0083] The acceleration data structure engine 522 can operate on representations of scene objects and scene geometry using both object space representations and world space representations. In some examples, the acceleration data structure engine 522 can use one or more object-to-world matrices and / or world-to-object matrices to transform scene objects / geometry from object space representation to world space representation and from world space representation to object space representation, respectively.

[0084] Figure 6 An example binary BVH 600 including a set of internal nodes and a set of leaf nodes is depicted. For example, binary BVH 600 includes a set of internal nodes B1-B12 (e.g., also referred to as internal nodes 601-612, respectively). In some cases, node B1 can be a BVH root node that is not associated with a parent node. In some examples, node B1 can be a BVH root node that is associated with a parent node ( Figure 6 ) and the associated BVH internal nodes.

[0085] As previously mentioned, a binary BVH (e.g., such as binary BVH 600) may include one bounding box per internal node. The bounding box may be an AABB. A given internal node may store a bounding box (e.g., an AABB) that encloses its two child nodes. For example, node B1 may store an AABB that encloses its child internal nodes B2 and B3; node B3 may store an AABB that encloses its child internal nodes B6 and B7; etc.

[0086] In some cases, an internal node stores an AABB that encapsulates the corresponding AABBs of its two child nodes, where both child nodes are internal nodes of the binary BVH 600 (e.g., such as the examples described above). In some cases, the two child nodes may include an internal node and a leaf node. In a binary BVH (e.g., such as the binary BVH 600), each leaf node may store a triangle. For example, internal node B2 may store an AABB that encapsulates its child internal node B4 and an AABB that encapsulates a leaf node associated with triangle T2. In some cases, both child nodes of a given internal node may be leaf nodes. For example, the two child nodes of BVH internal node B9 are BVH leaf nodes that store triangles T9 and T10, respectively; the two child nodes of BVH internal node B12 are BVH leaf nodes that store triangles T7 and T8, respectively; etc.

[0087] In some aspects, a binary BVH (e.g., such as binary BVH 600) may be inefficient to traverse during one or more ray tracing operations. For example, based on a binary BVH that includes only a single primitive (e.g., a triangle) per leaf node and only a single bounding box (e.g., an AABB) per interior node, the binary BVH may include multiple hierarchical levels that must be traversed before reaching a leaf node storing a triangle or other scene primitive. For example, in order to reach a leaf node storing triangle T10, the example binary BVH 600 must be traversed from B1-B2-B4-B5-B8-B9 before reaching the leaf node storing triangle T10.

[0088] In some examples, BVH widening may be performed to widen a binary BVH (eg, binary BVH 600 ) and reduce the number of hierarchical levels between a root node and BVH leaf nodes storing triangles or other scene primitives. Fig. 7A An example widened BVH 700a is illustrated that includes a wide BVH internal node 702 and four wide BVH leaf nodes 722, 724, 726, 728. In one illustrative example, the wide BVH internal node 702 may include Figure 6 The same thirteen triangles T1-T13 are depicted in the binary BVH 600.

[0089] BVH widening may be performed based on one or more cost metrics, which may include a surface area heuristic (SAH). In some aspects, a SAH may be determined for or associated with each node of a given BVH and / or a given BVH hierarchical level. The SAH may be used to provide an estimate of the ray tracing performance of a portion (or all) of a BVH or other acceleration data structure. In some examples, the BVH nodes of a given BVH level may be sorted in ascending or descending order by the SAH. For example, the BVH nodes may be sorted by the SAH so that the nodes with the smallest SAH are traversed first and the nodes with the largest SAH are traversed last; alternatively, the BVH nodes may be sorted by the SAH so that the nodes with the smallest SAH are traversed last and the nodes with the largest SAH are traversed first. Various other SAH sorting orders and / or traversal orders may also be utilized based on the SAH being used to provide an estimate of the ray tracing performance of some (or all) of a given BVH.

[0090] In one illustrative example, BVH widening may be performed for binary BVH 600 to generate widened BVH 700a based on SAH optimization. For example, widened BVH 700a may be a BVH with the lowest SAH that includes all thirteen triangles T1-T13 included in the original (e.g., input) binary BVH 600. Widened BVH 700a includes two hierarchical levels (e.g., a top layer including wide BVH interior nodes 702 and a bottom layer including wide BVH leaf nodes 722-728). Widened BVH 700a may be used to accelerate ray tracing performance based on reducing the average traversal time of widened BVH 700a.

[0091] For example, to reach the binary BVH 600 (e.g., Figure 6 The leaf node storing triangle T10 in widened BVH 700a may be reached by traversing from wide BVH internal node 702 to wide BVH leaf node 724, although the leaf node storing triangle T10 in widened BVH 700a may be reached by traversing from wide BVH internal node 702 to wide BVH leaf node 724.

[0092] In one illustrative example, widened BVH 700a may be an 8-wide BVH. An 8-wide BVH may include up to 8 child nodes per internal node (e.g., wide BVH internal node 702 may include up to 8 child nodes, although Fig. 7A Only 4 child nodes are depicted in FIG. 8 ). A leaf node of a wide BVH may include up to four triangles or other scene primitives. For example, wide BVH leaf nodes 724 and 728 each include four triangles (e.g., wide BVH leaf node 724 includes triangles T4, T9, T10, and T3; wide BVH leaf node 728 includes triangles T7, T8, T11, and T13).

[0093] As previously mentioned, transforming the binary BVH 600 into an 8-wide BVH 700a can reduce the number of hops that a GPU or other processor traverses when performing ray tracing operations (e.g., such as ray box intersection, ray-triangle intersection, etc.). However, as previously mentioned, the amount of storage space required to store up to four triangles in a given leaf node can be greater than the predetermined maximum size of each leaf node. For example, the maximum size of a leaf node (and / or each node included in the 8-wide BVH 700a) can be 64 bytes. In some cases, the size of the uncompressed data associated with storing four triangles can be 144 bytes (e.g., each uncompressed triangle can require 36 bytes of storage), which exceeds the 64-byte maximum size of each leaf node.

[0094] One or more compression algorithms may be used to compress BVH leaf nodes that exceed a predetermined maximum size (e.g., 64 bytes). In some cases, compression is performed based on one or more redundancies present in the underlying data associated with the triangles stored in a given BVH leaf node. For example, compression may be performed to eliminate or reduce storage requirements associated with redundancies, such as shared vertices between two or more triangles stored in a given BVH leaf node, shared or overlapping areas enclosed by two or more triangles stored in a given BVH leaf node, and the like.

[0095] In some cases, widening a BVH leaf node (e.g., such as Fig. 7A 722-728) may not be compressible to a size less than a predetermined maximum node size. For example, the four triangles T4, T9, T10, and T3 stored in the wide BVH leaf node 724 may be associated with a compressed size that exceeds the 64-byte maximum size of the wide BVH leaf node 724. In some examples, based on a lack of redundancy in the underlying data associated with the triangles T4, T9, T10, and T3, the four triangles T4, T9, T10, and T3 may not be compressed within 64 bytes (e.g., the four triangles may not have any shared vertices or overlapping areas on which compression can be performed). In some aspects, a wide BVH leaf node that cannot be compressed to 64 bytes or less may also be referred to herein as "incompressible" and / or "incompressible leaf node."

[0096] In some examples, an incompressible leaf node is split into multiple smaller leaf nodes, each of which is compressible. The incompressible leaf node can be converted to an internal node of the BVH, and each of the multiple compressible smaller leaf nodes is assigned as a new child node (e.g., a child node of the internal node converted from the incompressible leaf node).

[0097] For example, Figure 7B A widened and compressed BVH 700b is illustrated. In some aspects, the widened and compressed BVH 700b can be based on Fig. 7A 8-wide compressed BVH generated by performing leaf node compression on the optimal 8-wide BVH 700a depicted in FIG. 8. For example, compressed wide BVH leaf node 752 may store compressed data associated with triangles T1 and T2, which are triangles stored in Fig. 7A The same two triangles in the corresponding uncompressed wide BVH leaf node 722 illustrated in Fig. 7A The wide BVH leaf node 722 can be compressed into Figure 7B Similarly, compressed wide BVH leaf node 754 may store compressed data associated with triangles T6, T5, and T12, which are triangles stored in Fig. 7A The same three triangles in the corresponding uncompressed wide BVH leaf node 726 illustrated in Fig. 7A The wide BVH leaf node 726 can be compressed into Figure 7B of the compressed wide BVH leaf node 754).

[0098] Fig. 7A The uncompressed wide BVH leaf node 724 illustrated in FIG. 7 may be incompressible (e.g., based on including four triangles T4, T9, T10, and T3, which together may exceed the 64-byte maximum node size even after compression). In some aspects, as previously mentioned, the incompressible wide leaf node may be generated based on converting each incompressible wide leaf node into an internal node and splitting the triangles associated with the incompressible wide leaf node into multiple new child nodes. Figure 7B The widening and compression of the BVH700b. For example, Fig. 7A The incompressible wide BVH leaf node 724 can be converted to Figure 7B , and triangles T4, T9, T10, and T3 may be split into two new child nodes: a compressed wide BVH leaf node 762 (e.g., storing compressed data associated with triangles T4, T9, and T10) and a compressed wide BVH leaf node 764 (e.g., storing compressed data associated with triangle T3).

[0099] Similarly, Fig. 7A The uncompressed wide BVH leaf node 728 illustrated in FIG. 7 may be incompressible (e.g., based on the inclusion of four triangles T7, T8, T11, and T13, which together may exceed the 64-byte maximum node size even after compression). Fig. 7A The incompressible wide BVH leaf node 728 can be converted to Figure 7B , and triangles T7, T8, T11, and T13 may be split into two new child nodes: a compressed wide BVH leaf node 766 (e.g., storing compressed data associated with triangles T7 and T8) and a compressed wide BVH leaf node 768 (e.g., storing compressed data associated with triangles T11 and T13).

[0100] In some aspects, the 8-wide compressed BVH 700b implemented based on the maximum node size (e.g., 64 bytes) may be different from the calculated optimal 8-wide BVH 700a (e.g., the best based on the SAH), which may be calculated without reference to the maximum node size. Fig. 7AThe calculated optimal 8-wide BVH 700a illustrated in can be the optimal 8-wide BVH for storing the 13 triangles T1-T13 in a BVH that minimizes the SAH. The optimization of the underlying binary BVH 600 (e.g., for generating the optimal 8-wide BVH 700a) can be performed without analyzing the maximum node size (e.g., 64 bytes) and whether each candidate widened BVH leaf node included in the calculated optimal 8-wide BVH 700a is compressible in view of the maximum node size. For example, Fig. 7A The calculated optimal 8-wide BVH 700a may generate four widened BVH leaf nodes 722-728 (eg, Fig. 7A The computed 8-wide BVH 700a may include one or more candidate widened BVH leaf nodes that are not compressible within the maximum node size of 64 bytes).

[0101] Widen incompressible candidate BVH leaf nodes (e.g., such as Fig. 7A The SAH of the resulting widened and compressed BVH 700b can be increased by splitting the widened BVH leaf nodes 724 and 726) into multiple new child nodes each small enough to be compressed within the maximum node size (e.g., 64 bytes). For example, based on including more internal nodes and more leaf nodes, Figure 7B The compression widening BVH 700b illustrated in FIG. 7 may have a Fig. 7A The calculated optimal widened BVH 700a illustrated in FIG. 700a has a larger SAH. For example, Fig. 7A The calculated optimal 8-wide BVH 700a illustrated in FIG. 700a includes only two levels, and each of the thirteen triangles T1-T13 can be reached in a single traversal step starting from the root node 702. After performing compression, the resulting compressed and widened BVH 700b includes three levels, so that only five of the thirteen triangles (e.g., triangles T1, T2, T5, T6, and T12) can be reached in a single traversal step starting from the root node 702; the remaining seven triangles (e.g., T4, T9, T10, T3, T7, T8, T11, and T13) each require multiple traversal steps starting from the root node 702.

[0102] The systems and techniques described herein can be used to perform compression-aware BVH widening, as described in more depth below. In some examples, an estimate of leaf node compressibility can be determined and / or analyzed during BVH widening so that the resulting widened BVH does not include any widened BVH nodes that are not compressible (e.g., each widened BVH leaf node can be compressed to a maximum node size of 64 bytes or less).

[0103] In one illustrative example, systems and techniques may exclude one or more candidate hierarchical acceleration data structures from consideration based on an estimate or prediction of the compressibility of a BVH leaf node determined before or during BVH widening. In some examples, the candidate hierarchical acceleration data structure may be a candidate widened BVH tree configuration that includes one or more BVH leaf nodes that cannot be compressed within a maximum node size (e.g., 64 bytes). In some aspects, even if the candidate widened BVH tree configuration is associated with an optimal SAH, the candidate widened BVH tree configuration may be excluded from consideration during BVH widening based on the candidate widened BVH tree configuration including at least one incompressible leaf node.

[0104] In some aspects, checking the compressibility of each possible leaf node combination and / or widened BVH configuration can be a computationally expensive and time consuming process. In one illustrative example, systems and techniques can perform compression prediction (e.g., compressibility prediction) to predict whether a given set of triangles received as input can be compressed within a given maximum node size. For example, systems and techniques can perform compression prediction (e.g., compressibility prediction) to predict whether a set of triangles included in a given candidate widened BVH leaf node can be compressed using 64 bytes or less.

[0105] In some aspects, systems and techniques may perform BVH widening for a given BVH (e.g., a binary BVH) based on determining a candidate widened BVH tree configuration having an optimal or best SAH and determining an estimate or prediction of leaf node compressibility for each leaf node included in the candidate widened BVH. If the estimate or prediction of the leaf node compressibility prediction is less than or equal to a maximum node size (e.g., 64 bytes), the given candidate widened BVH may be output as a widened BVH for compression. For example, an output hierarchical acceleration data structure may be generated, wherein the output hierarchical acceleration data structure is the same as the given candidate widened BVH. In some outputs, the output hierarchical acceleration data structure may be generated to be the same as a candidate hierarchical acceleration data structure having an optimal or best cost metric (e.g., SAH) that also has a compressibility prediction that is less than or equal to the maximum node size. In response to determining that at least one leaf node included in the candidate widened BVH is associated with an estimate or prediction of compressibility (e.g., compressibility prediction) that is greater than a maximum node size (e.g., 64 bytes), the candidate widened BVH can be excluded, and the same process described above can be used to consider candidate widened BVH tree configurations with suboptimal SAHs until a candidate widened BVH that does not include any incompressible leaf nodes is identified. In some examples, the above-described candidate widened BVH leaf node compression check can be performed before or as part of a decision to create a candidate widened BVH leaf node. For example, if the candidate widened BVH node passes the compression check (e.g., can be compressed using 64 bytes or less), the system and technology can add (e.g., create) the candidate widened BVH node to the widened BVH. If the candidate widened BVH node does not pass the compression check (e.g., cannot be compressed using 64 bytes or less), the system and technology can assign a high cost (e.g., a high SAH) to the incompressible candidate widened BVH node. In some examples, systems and techniques can assign the highest cost (eg, highest SAH) to the incompressible candidate widening BVH nodes.

[0106] In some aspects, a compressibility metric associated with a candidate hierarchical acceleration data structure (e.g., BVH) may be determined based at least in part on a cost metric (such as a SAH or other cost metric). For example, a compressibility metric associated with a candidate hierarchical acceleration data structure (e.g., BVH) may be determined based at least in part on a SAH determined for the candidate hierarchical acceleration data structure. In an illustrative example, the compressibility metric may be determined based on the order of the cost metrics (e.g., SAH) determined for two or more candidate BVHs. For example, a compressibility metric associated with a candidate BVH having the best (e.g., lowest or highest) cost metric (e.g., lowest SAH) may be determined first. Subsequently, in response to determining that the compressibility metric associated with the candidate BVH having the best cost metric (e.g., lowest SAH) is not less than a predetermined threshold, a compressibility metric associated with a different candidate BVH having a second-best cost metric (e.g., second-lowest SAH) may be determined. In some aspects, the predetermined threshold may be the maximum size of a leaf node of a widened BVH. In an illustrative example, the predetermined threshold may be 64 bytes.

[0107] Figure 8 An example of a compressively sensed widened BVH 800 is illustrated. In some aspects, the compressively sensed widened BVH 800 may also be referred to as a widened BVH with leaf node compressibility prediction. In one illustrative example, the compressively sensed widened BVH 800 may use a binary BVH as input (e.g., such as Figure 6 600) as illustrated in FIG.

[0108] The perceptually compressed widened BVH 800 is illustrated as an 8-wide BVH (e.g., each widened internal BVH node may include up to 8 child nodes, and each compressed wide BVH leaf node may include up to 4 triangles or other scene primitives). In some examples, various other widened BVH sizes or dimensions (e.g., 4-wide, 16-wide, etc.) may also be utilized.

[0109] The compressed sensing widened BVH 800 includes a wide BVH internal node 802 that stores bounding boxes or AABBs for five internal nodes B1, B2, B3, B4, and B5 (e.g., 811-815, respectively). In some examples, the wide BVH internal node 802 may include bounding boxes (e.g., AABBs) for a greater or lesser number of internal nodes. For example, in some cases, the wide BVH internal node 802 may store bounding boxes or AABBs for up to eight internal nodes.

[0110] The internal nodes stored in or associated with the wide BVH internal node 802 may collectively store, include, or contain information for Figure 6600 (which may be provided as input to the presently disclosed systems and techniques for compressive sensing BVH widening). The 13 triangles T1-T13 may be included in a compressible wide BVH leaf node set so that the structure of the widened BVH 800 is unchanged between an uncompressed state and a compressed state. For example, since the wide BVH leaf node sets 850, 852, 854, 856, 858 are all compressible, no additional BVH internal nodes are generated during compression of the widened BVH, and no new BVH leaf nodes are created during compression of the widened BVH.

[0111] In an illustrative example, a compressed wide BVH leaf node 850 includes compressed data associated with three triangles T1, T2, and T4 and can be generated based on compressing a corresponding uncompressed wide BVH leaf node including the same three triangles T1, T2, and T4. A compressed wide BVH leaf node 852 includes compressed data associated with three triangles T3, T9, and T10 and can be generated based on compressing a corresponding uncompressed wide BVH leaf node including the same three triangles T3, T9, and T10. A compressed wide BVH leaf node 854 includes compressed data associated with two triangles T6 and T5 and can be generated based on compressing a corresponding uncompressed wide BVH leaf node including the same two triangles T6 and T5. A compressed wide BVH leaf node 856 includes compressed data associated with two triangles T12 and T13 and can be generated based on compressing a corresponding uncompressed wide BVH node including the same two triangles T12 and T13. The compressed wide BVH leaf node 858 includes compressed data associated with three triangles T7, T8, and T11 and may be generated based on compressing a corresponding uncompressed wide BVH node including the same three triangles T7, T8, T11.

[0112] In some aspects, the SAH associated with the compressed sensing widened BVH 800 may be greater than that associated with Fig. 7A The SAH associated with the calculated optimal widened BVH 700a illustrated in FIG. Fig. 7A The calculated optimal widened BVH 700a includes incompressible widened BVH leaf nodes 724 and 728, so Fig. 7A The calculated optimum widening BVH 700a applied compression results in Figure 7B800b, the compressed and widened BVH including the additional BVH internal nodes 704, 706 and the new BVH leaf nodes 762, 764, 766, 768. In some aspects, the SAH associated with the compression-aware widened BVH 800 can be less than the SAH associated with the compressed and widened BVH 700b, the compressed and widened BVH generated by applying compression to the widened BVH including the incompressible leaf nodes. In some examples, the performance of ray tracing operations performed based on the compression-aware widened BVH 800 can be better than that based on Figure 7B The performance of ray tracing operations performed by the simply compressed widened BVH 700b is improved (e.g., more efficient, faster, etc.). In one illustrative example, the compressed wide BVH leaf nodes 850-858 may each include up to four compressed triangles or other scene primitives, although Figure 8 A maximum of three compressed triangles per compressed wide BVH leaf node are depicted in FIG.

[0113] In one illustrative example, compressibility prediction may be performed based on analyzing or predicting data redundancy between sets of triangles or other scene primitives received as input. For example, compressibility prediction may be performed based on analyzing or predicting data redundancy between sets of triangles included in the same candidate widened BVH leaf node. In some aspects, systems and techniques may perform compressibility prediction based on analyzing vertices and / or coordinates of a set of input triangles. For example, each triangle may be associated with 3 vertices, where each vertex has three values ​​or components (e.g., x, y, and z; one value for each of the three dimensions associated with a 3D scene; etc.). For a set of four input triangles, a total of 36 values ​​may be obtained or determined (e.g., 4 triangles * 3 vertices * three coordinate values ​​= 36 total values).

[0114] In some aspects, compressibility prediction may be performed based on analyzing coordinates of vertices of a set of input triangles to identify one or more redundancies. For example, the compressibility prediction may determine the number or number of unique coordinate values ​​in each axis or dimension in which the set of input triangles is defined. In one illustrative example, for an input set of four triangles, the compressibility prediction may determine the number of unique coordinates included in four x-axis vertices (e.g., one x-axis vertex per triangle), the number of unique coordinates included in four y-axis vertices, and the number of unique coordinates included in four z-axis vertices.

[0115] In some aspects, triangles included in a given scene object may share one or more edges (e.g., a scene object based on a plurality of interlocking or mesh triangles that approximate a smooth surface). A pair of triangles that share an edge may share one or more coordinate values ​​at one or more vertices. For example, two of the three vertices included in a pair of triangles that share an edge may be the same, in which case the pair of triangles may share six coordinate values ​​(e.g., two shared vertices, each vertex having three values ​​x, y, z).

[0116] In one illustrative example, compressibility prediction may be performed based on determining the number or number of unique coordinates along each of the three axes in which the input triangle set is defined. For example, out of a total of 12 coordinate values ​​for each of the x, y, and z axes, an input set of four triangles may be associated with a total of six unique coordinates in each of the three dimensions. In this scenario, the initial set of 4*3*3=36 total coordinate values ​​may be reduced to a total of 3*6=18 unique coordinate values ​​in three dimensions. In some aspects, compressibility prediction may be performed based on this number of unique coordinate values ​​associated with the input triangle set (e.g., the triangle set included in the same candidate widened BVH leaf node). For example, the system and technology may calculate, estimate, or predict the number of bytes required to pack the total number of unique coordinates. If the number of bytes required to pack or store the determined number of unique coordinates is less than a predetermined maximum node size (e.g., 64 bytes), the input triangle set may be identified as compressible (e.g., and the candidate BVH leaf node including or storing the input triangle set may be added to the widened BVH 800).

[0117] In some aspects, the compressibility prediction can be used to obtain an earlier result and / or earlier determination of the compressibility (or lack of compressibility) of a given candidate widened BVH leaf node than performing compression or otherwise explicitly determining (e.g., rather than predicting) the compressibility of a given candidate widened BVH leaf node. In some examples, the aggressiveness of the compressibility prediction can vary. In one illustrative example, a compressibility prediction can be performed for each iteration of a candidate widened BVH tree configuration analyzed according to the systems and techniques described herein. For example, a compressibility prediction can be performed for each candidate leaf node of each candidate widened BVH tree configuration, wherein a determination that any candidate widened BVH leaf node of a given candidate widened BVH tree configuration is incompressible triggers exclusion of the candidate widened BVH tree configuration.

[0118] Fig. 9900 is a flow chart illustrating an example of a process 900 for graphics processing. Although the example process 900 depicts a particular order of operations, the order may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not materially affect the functionality of the process 900. In other examples, different components of an example device or system implementing the process 900 may perform functions substantially simultaneously or in a particular order.

[0119] At block 902, process 900 includes obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure. For example, the plurality of primitives may include a plurality of triangles, axis-aligned bounding boxes (AABBs), and / or other scene geometry and / or scene primitives. In some cases, the first hierarchical acceleration data structure may be composed of Figure 5 The first hierarchical acceleration data structure may be obtained by or from an acceleration data structure engine 522 associated with the ray tracing system 500 illustrated in FIG. 5 . In some cases, the first hierarchical acceleration data structure may include a bounding volume hierarchy (BVH). In some examples, the first hierarchical acceleration data structure is a binary BVH.

[0120] In some cases, multiple primitives of a scene object may be included in one or more leaf nodes of the first hierarchical acceleration data structure. For example, the multiple primitives may include Figure 6 . One or more internal nodes (e.g., BVH internal nodes) may include axis-aligned bounding boxes (AABBs) that enclose a subset of one or more primitives of the scene object. For example, one or more internal nodes may include AABBs that enclose a subset of multiple primitives included in the leaf nodes of the first hierarchical acceleration data structure.

[0121] At block 904, process 900 includes determining one or more candidate hierarchical acceleration data structures, each candidate hierarchical acceleration data structure including a plurality of primitives. For example, one or more candidate hierarchical acceleration data structures may be widened hierarchical acceleration data structures each including a plurality of primitives. In some cases, the candidate hierarchical acceleration data structure may be generated based on widening a first hierarchical acceleration data structure. In some examples, the candidate hierarchical acceleration data structure may be generated based on widening a binary BVH including a plurality of primitives. For example, one or more candidate hierarchical acceleration data structures may include a first hierarchical acceleration data structure, a second hierarchical acceleration data structure, and a third hierarchical acceleration data structure. Fig. 7A , Figure 7B and Figure 8 00a, 700b, and / or 800 illustrated in (or otherwise the same as or similar to) one or more of the widened BVHs 700a, 700b, and / or 800 illustrated in FIG. 10A . In some cases, each widened hierarchical acceleration data structure may include multiple primitives in a set of leaf nodes.

[0122] At block 906, process 900 includes determining a cost metric for one or more of the one or more candidate hierarchical acceleration data structures. For example, the cost metric may be a surface area heuristic (SAH). In some cases, the SAH may be determined for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure. For example, the cost metric may be determined as the sum of the SAHs for each leaf node and internal node included in a given candidate hierarchical acceleration data structure.

[0123] At block 908, process 900 includes determining a compressibility prediction associated with a candidate hierarchical acceleration data structure in one or more candidate hierarchical acceleration data structures. For example, the compressibility prediction may be determined based on a number of bytes predicted to be associated with compressing each leaf node included in the candidate hierarchical acceleration data structure. If the predicted number of bytes is less than (or equal to) a predetermined threshold, the compressibility prediction may indicate that the candidate hierarchical acceleration data structure is compressible. If the predicted number of bytes is greater than the predetermined threshold, the compressibility prediction may indicate that the candidate hierarchical acceleration data structure is not compressible.

[0124] In some examples, the predetermined threshold is a maximum leaf node size. In some examples, the predetermined threshold is 64 bytes.

[0125] At block 910, process 900 includes generating an output hierarchical acceleration data structure based on the compressibility prediction. For example, the output hierarchical acceleration data structure may be associated with Figure 8 In some cases, generating the output hierarchical acceleration data structure includes excluding candidate hierarchical acceleration data structures based on determining, based on the compressibility prediction, that at least one leaf node included in the candidate hierarchical acceleration data structure cannot be compressed within a predetermined maximum leaf node size. In some cases, generating the output hierarchical acceleration data structure includes identifying a candidate hierarchical acceleration data structure having an optimal (e.g., lowest) cost metric (e.g., SAH) and a compressibility prediction indicating that the candidate hierarchical acceleration data structure is compressible within a predetermined threshold number of bytes. For example, the output hierarchical acceleration data structure may be a candidate hierarchical acceleration data structure that has a lowest SAH and is compressible within a maximum leaf node size (e.g., 64 bytes) associated with the output hierarchical acceleration data structure.

[0126] In some examples, the output hierarchical acceleration data structure is a widened BVH. In some cases, process 900 may also include compressing one or more leaf nodes included in the widened BVH.

[0127] In some examples, the processes described herein (e.g., process 900 and / or any other process described herein) can be performed by a computing device, apparatus, or system. In one example, process 900 can be performed by a computer having Fig.10 The computing device, apparatus or system may be executed by a computing device or system of the computing device architecture 1000 of the present invention. The computing device, apparatus or system may include any suitable device, such as a mobile device (e.g., a mobile phone), a desktop computing device, a tablet computing device, a wearable device (e.g., a VR headset, an AR headset, AR glasses, an extended reality (XR) headset, a networked watch or smart watch, or other wearable device), a server computer, an autonomous vehicle or a computing device of an autonomous vehicle, a robotic device, a laptop computer, a smart TV, a camera and / or any other computing device having resource capabilities to perform the processes described herein (including process 900 and / or other processes described herein). In some cases, the computing device or apparatus may include various components, such as one or more input devices, one or more output devices, one or more processors, one or more microprocessors, one or more microcomputers, one or more cameras, one or more sensors, and / or other components configured to perform the steps of the processes described herein. In some examples, the computing device may include a display, a network interface configured to communicate and / or receive data, any combination thereof and / or other components. The network interface may be configured to communicate and / or receive data based on an Internet Protocol (IP) or other types of data.

[0128] The components of the computing device may be implemented in circuits. For example, the components may include and / or may be implemented using electronic circuits or other electronic hardware, which may include one or more programmable electronic circuits (e.g., microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), central processing units (CPUs), and / or other suitable electronic circuits), and / or may include and / or may be implemented using computer software, firmware, or any combination thereof for performing the various operations described herein.

[0129] Process 900 is illustrated as a logic flow diagram, the operations of which represent a sequence of operations that can be implemented in hardware, computer instructions, or a combination thereof. In the context of computer instructions, each operation represents a computer-executable instruction stored on one or more computer-readable storage media that, when executed by one or more processors, performs the described operation. Generally speaking, computer-executable instructions include routines, programs, objects, components, data structures, etc. that perform specific functions or implement specific data types. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations may be combined in any order and / or in parallel to implement the process.

[0130] Additionally, process 900 and / or any other process described herein may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed together on one or more processors, through hardware, or a combination thereof. As noted above, the code may be stored on a computer-readable or machine-readable storage medium, for example, in the form of a computer program that includes a plurality of instructions that can be executed by one or more processors. The computer-readable or machine-readable storage medium may be non-transitory.

[0131] Fig.10 An example computing device architecture 1000 of an example computing device that can implement the various techniques described herein is illustrated. In some examples, the computing device may include a mobile device, a wearable device, an extended reality device (e.g., a virtual reality (VR) device, an augmented reality (AR) device, an extended reality (XR) device, or a mixed reality (MR) device), a personal computer, a laptop, a video server, a vehicle (or a computing device of a vehicle), or other device. The components of the computing device architecture 1000 are shown as using a connector 1005 (such as a bus) to electrically communicate with each other. The example computing device architecture 1000 includes a processing unit (CPU or processor) 1010 and a computing device connector 1005, which couples various computing device components including a computing device memory 1015 (such as a read-only memory (ROM) 1020 and a random access memory (RAM) 1025) to the processor 1010.

[0132] The computing device architecture 1000 may include a cache of high-speed memory directly connected to, in close proximity to, or integrated as part of the processor 1010. The computing device architecture 1000 may copy data from the memory 1015 and / or the storage device 1030 to the cache 1012 for fast access by the processor 1010. In this way, the cache can provide a performance improvement that avoids delays in the processor 1010 when waiting for data. These engines and other engines can control or be configured to control the processor 1010 to perform various actions. Other computing device memories 1015 are also available for use. The memory 1015 may include a variety of different types of memory with different performance characteristics. The processor 1010 may include any general-purpose processor and hardware or software services (such as service 1 1032, service 2 1034, and service 3 1036 stored in the storage device 1030) configured to control the processor 1010, as well as a special-purpose processor in which software instructions are incorporated into the processor design. The processor 1010 may be a self-contained system, including multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors can be symmetric or asymmetric.

[0133] To enable user interaction with the computing device architecture 1000, the input device 1045 may represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphic input, a keyboard, a mouse, motion input, voice, etc. The output device 1035 may also be one or more of a plurality of output mechanisms known to those skilled in the art, such as a display, a projector, a television, a speaker device, etc. In some cases, a multi-modal computing device may enable a user to provide multiple types of input to communicate with the computing device architecture 1000. The communication interface 1040 may generally govern and manage user input and computing device output. There is no restriction on operating on any particular hardware arrangement, and thus the underlying features herein may be easily replaced to obtain improved hardware or firmware arrangements as they are developed.

[0134] The storage device 1030 is a non-volatile memory and may be a hard disk or other type of computer readable medium that can store computer accessible data, such as a magnetic tape cartridge, a flash memory card, a solid-state memory device, a digital versatile disk, a cassette tape, a random access memory (RAM) 1025, a read-only memory (ROM) 1020, and hybrids thereof. The storage device 1030 may include services 1032, 1034, 1036 for controlling the processor 1010. Other hardware or software modules or engines are contemplated. The storage device 1030 may be connected to the computing device connector 1005. In one aspect, a hardware module that performs a particular function may include a software component stored in a computer readable medium connected to the necessary hardware components (such as the processor 1010, the connector 1005, the output device 1035, etc.) to perform the function.

[0135] Aspects of the present disclosure are applicable to any suitable electronic device (such as a security system, smartphone, tablet, laptop, vehicle, drone, or other device) that includes or is coupled to one or more active depth sensing systems. Although described below with respect to a device having or coupled to one light projector, aspects of the present disclosure are applicable to devices having any number of light projectors and are therefore not limited to a particular device.

[0136] The term "device" is not limited to one or a specific number of physical objects (such as a smart phone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more parts that can implement at least some parts of the present disclosure. Although the following description and examples use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a specific configuration, type, or number of objects. In addition, the term "system" is not limited to multiple components or specific aspects. For example, a system can be implemented on one or more printed circuit boards or other substrates and can have movable or static components. Although the following description and examples use the term "system" to describe various aspects of the present disclosure, the term "system" is not limited to a specific configuration, type, or number of objects.

[0137] Specific details are provided in the above description to provide a detailed understanding of the aspects and examples provided herein. However, it will be understood by those skilled in the art that these aspects can also be practiced without these specific details. For clarity, in some cases, the present technology may be presented as including separate functional blocks, including functional blocks comprising devices, device components, steps or routines in the method embodied in a combination of software or hardware and software. Additional components other than those components shown in the accompanying drawings and / or described herein may be used. For example, circuits, systems, networks, processes and other components may be shown as components in block diagram form to avoid confusing these aspects in unnecessary details. In other examples, known circuits, processes, algorithms, structures and techniques may be shown without unnecessary details to avoid confusing various aspects.

[0138] Various aspects may be described above as a process or method, which is depicted as a flow chart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flow chart may describe an operation as a sequential process, many operations in the operation may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. The process is terminated when the operation of the process is completed, but the process may have additional steps not included in the accompanying drawings. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, the termination of the process may correspond to the function returning to the calling function or the main function.

[0139] The processes and methods according to the above examples can be implemented using stored computer executable instructions or otherwise obtained from a computer readable medium. Such instructions may include, for example, instructions and data that cause or otherwise configure a general purpose computer, a special purpose computer, or a processing device to perform a certain function or group of functions. Portions of the computer resources used may be accessed via a network. Computer executable instructions may be, for example, binary files, intermediate format instructions (such as assembly language), firmware, source code, etc.

[0140] The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing or carrying instructions and / or data. Computer-readable media may include non-transient media in which data may be stored and does not include carrier waves and / or transient electronic signals that are propagated wirelessly or on a wired connection. Examples of non-transient media may include, but are not limited to, disks or tapes, optical storage media (such as flash memory), memory or memory devices, disks or optical disks, flash memory, USB devices provided with non-volatile memory, network storage devices, compact discs (CDs) or digital versatile discs (DVDs), any suitable combination thereof, etc. Computer-readable media may store thereon code and / or machine-executable instructions that may represent any combination of a process, function, subroutine, program, routine, subroutine, module, engine, software package, class, or instruction, data structure, or program statement. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, independent variables, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or sent via any suitable means, including memory sharing, message passing, token passing, network sending, etc.

[0141] In some aspects, computer readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer readable storage media specifically excludes media such as power consumption, carrier signals, electromagnetic waves, and signals themselves.

[0142] Devices implementing the processes and methods according to these disclosures may include hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and may take any of a variety of form factors. When implemented in software, firmware, middleware, or microcode, program code or code segments (e.g., computer program products) for performing the necessary tasks may be stored in a computer-readable or machine-readable medium. The processor may perform the necessary tasks. Typical examples of form factors include laptop computers, smart phones, mobile phones, tablet devices or other small form factor personal computers, personal digital assistants, rack-mounted devices, stand-alone devices, etc. The functionality described herein may also be embodied in peripheral devices or add-in cards. By way of additional examples, such functionality may also be implemented on circuit boards among different chips or different processes executed on a single device.

[0143] The instructions, the media for conveying such instructions, the computing resources for executing them, and other structures for supporting such computing resources are example means for providing the functionality described in this disclosure.

[0144] In the above description, various aspects of the present application are described with reference to their specific aspects, but those skilled in the art will recognize that the present application is not limited thereto. Thus, although the exemplary aspects of the present application have been described in detail herein, it is to be understood that each inventive concept can be implemented and adopted in various other ways, and the appended claims are not intended to be interpreted as including these variations, unless limited by the prior art. Various features and aspects of the above-mentioned applications can be used individually or in combination. In addition, various aspects can be utilized in any number of environments and applications beyond those described herein without departing from the broader essence and scope of this specification. Therefore, the description and the accompanying drawings should be considered as illustrative rather than restrictive. For the purpose of illustration, each method is described in a specific order. It should be appreciated that, in alternative aspects, each method can be performed in a different order than described.

[0145] One of ordinary skill in the art will appreciate that the less than ("<") and greater than (">") symbols or terms used herein may be replaced by less than or equal to ("≤") and greater than or equal to ("≥") symbols, respectively, without departing from the scope of this specification.

[0146] Where a component is described as being “configured to” perform certain operations, such configuration may be achieved, for example, by designing electronic circuits or other hardware to perform the operations, by programming programmable electronic circuits (e.g., a microprocessor or other suitable electronic circuits) to perform the operations, or any combination thereof.

[0147] The phrase "coupled to" means that any component is directly or indirectly physically connected to another component, and / or any component is directly or indirectly in communication with another component (e.g., connected to another component via a wired or wireless connection and / or other suitable communication interface).

[0148] Claim language or other language stating "at least one of" a set and / or "one or more of" a set indicates that one member of the set or multiple members of the set (in any combination) satisfies the claim. For example, claim language stating "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, claim language stating "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, or A and B and C. The language "at least one of" a set and / or "one or more of" a set does not limit the set to the items listed in the set. For example, claim language stating "at least one of A and B" or "at least one of A or B" may mean A, B, or A and B, and may additionally include items not listed in the set of A and B.

[0149] Various exemplary logic blocks, modules, engines, circuits and algorithmic steps described in conjunction with aspects disclosed herein can be implemented as electronic hardware, computer software, firmware or a combination thereof. In order to clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits and steps have been generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints proposed for the entire system. The technician can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as departing from the scope of the present application.

[0150] The techniques described herein may also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques may be implemented in any of a variety of devices, such as general-purpose computers, wireless communication devices, or integrated circuit devices with multiple uses, including applications in wireless communication devices, mobile phones, and other devices. Any features described as modules or components may be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, these techniques may be implemented at least in part by a computer-readable data storage medium including a program code, the program code including instructions that execute one or more of the above methods when executed. A computer-readable data storage medium may form part of a computer program product, which may include packaging materials. A computer-readable medium may include a memory or data storage medium, such as a random access memory (RAM) (such as a synchronous dynamic random access memory (SDRAM)), a read-only memory (ROM), a non-volatile random access memory (NVRAM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic or optical data storage medium, and the like. Additionally or alternatively, the technology may be implemented at least in part by a computer-readable communication medium that carries or communicates program code in the form of instructions or data structures and that can be accessed, read, and / or executed by a computer, such as a propagated signal or wave.

[0151] The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processors may be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Therefore, the term "processor" as used herein may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the techniques described herein.

[0152] Illustrative aspects of the present disclosure include:

[0153] Aspect 1: A method for ray tracing, the method comprising: obtaining multiple primitives of a scene object included in a first hierarchical acceleration data structure; determining one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the multiple primitives; determining a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determining a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generating an output hierarchical acceleration data structure based on the compressibility prediction.

[0154] Aspect 2: The method according to aspect 1, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH).

[0155] Aspect 3: The method according to any one of aspects 1 to 2, wherein each of the one or more candidate hierarchical acceleration data structures is a respective widened hierarchical acceleration data structure including the plurality of primitives.

[0156] Aspect 4: The method according to aspect 3, wherein each widened hierarchical acceleration data structure includes the plurality of primitives in a leaf node set.

[0157] Aspect 5: The method according to any one of aspects 1 to 4, wherein the cost metric is a surface area heuristic (SAH).

[0158] Aspect 6: The method according to aspect 5, wherein the SAH is determined for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

[0159] Aspect 7: A method according to any one of Aspects 1 to 6, wherein determining the compressibility prediction associated with the candidate hierarchical acceleration data structure includes: predicting the number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; and determining whether the predicted number of bytes is less than a predetermined threshold.

[0160] Aspect 8: The method according to Aspect 7, wherein the predetermined threshold is a maximum leaf node size.

[0161] Aspect 9: The method according to any one of Aspects 7 to 8, wherein the predetermined threshold is 64 bytes.

[0162] Aspect 10: A method according to any one of Aspects 1 to 9, wherein generating the output hierarchical acceleration data structure includes: excluding the candidate hierarchical acceleration data structure based on determining, based on the compressibility prediction, that at least one leaf node included in the candidate hierarchical acceleration data structure cannot be compressed within a predetermined maximum leaf node size.

[0163] Aspect 11: The method according to any one of aspects 1 to 10, wherein the output hierarchical acceleration data structure is a widened bounding volume hierarchy (BVH).

[0164] Aspect 12: The method according to Aspect 11, further comprising compressing one or more leaf nodes included in the widened BVH.

[0165] Aspect 13: A device for ray tracing, the device comprising: a memory; and one or more processors, the one or more processors being coupled to the memory, the one or more processors being configured to: obtain multiple primitives of a scene object included in a first hierarchical acceleration data structure; determine one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the multiple primitives; determine a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determine a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generate an output hierarchical acceleration data structure based on the compressibility prediction.

[0166] Aspect 14: The apparatus according to aspect 13, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH).

[0167] Aspect 15: The apparatus according to any one of aspects 13 to 14, wherein each of the one or more candidate hierarchical acceleration data structures is a respective widened hierarchical acceleration data structure including the plurality of primitives.

[0168] Aspect 16: The apparatus according to aspect 15, wherein each widened hierarchical acceleration data structure comprises the plurality of primitives in a set of leaf nodes.

[0169] Aspect 17: The apparatus according to any one of aspects 13 to 16, wherein the cost metric is a surface area heuristic (SAH).

[0170] Aspect 18: The apparatus according to Aspect 17, wherein the one or more processors are configured to determine the SAH for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

[0171] Aspect 19: An apparatus according to any one of Aspects 13 to 18, wherein in order to determine the compressibility prediction associated with the candidate hierarchical acceleration data structure, the one or more processors are configured to: predict the number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; and determine whether the predicted number of bytes is less than a predetermined threshold.

[0172] Aspect 20: The apparatus according to Aspect 19, wherein the predetermined threshold is a maximum leaf node size.

[0173] Aspect 21: An apparatus according to any one of Aspects 19 to 20, wherein the predetermined threshold is 64 bytes.

[0174] Aspect 22: An apparatus according to any one of Aspects 13 to 21, wherein, in order to generate the output hierarchical acceleration data structure, the one or more processors are configured to: exclude the candidate hierarchical acceleration data structure based on determining, based on the compressibility prediction, that at least one leaf node included in the candidate hierarchical acceleration data structure cannot be compressed within a predetermined maximum leaf node size.

[0175] Aspect 23: The apparatus according to any one of aspects 13 to 22, wherein the output hierarchical acceleration data structure is a widened bounding volume hierarchy (BVH).

[0176] Aspect 24: The apparatus according to Aspect 23, wherein the one or more processors are further configured to compress one or more leaf nodes included in the widened BVH.

[0177] Aspect 25: A non-transitory computer-readable medium having instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to: obtain a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determine one or more candidate hierarchical acceleration data structures, each of the one or more candidate hierarchical acceleration data structures including the plurality of primitives; determine a cost metric for the one or more candidate hierarchical acceleration data structures; based on the cost metric, determine a compressibility prediction associated with a candidate hierarchical acceleration data structure in the one or more candidate hierarchical acceleration data structures; and generate an output hierarchical acceleration data structure based on the compressibility prediction.

[0178] Aspect 26: The non-transitory computer-readable medium of aspect 25, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH).

[0179] Aspect 27: A non-transitory computer-readable medium according to any one of Aspects 25 to 26, wherein each of the one or more candidate hierarchical acceleration data structures is a corresponding widened hierarchical acceleration data structure including the multiple primitives in the leaf node set.

[0180] Aspect 28: A non-transitory computer-readable medium according to any one of Aspects 25 to 27, wherein the cost metric is a surface area heuristic (SAH), and the one or more processors are configured to determine the SAH for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

[0181] Aspect 29: A non-transitory computer-readable medium according to any one of Aspects 25 to 28, wherein in order to determine the compressibility prediction associated with the candidate hierarchical acceleration data structure, the one or more processors are configured to: predict the number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; and determine whether the predicted number of bytes is less than a predetermined threshold.

[0182] Aspect 30: The non-transitory computer-readable medium according to Aspect 29, wherein the predetermined threshold is a maximum leaf node size.

[0183] Aspect 31: An apparatus comprising means for performing any of the operations according to aspects 1 to 30.

[0184] Aspect 32: A non-transitory computer-readable storage medium having instructions stored thereon, the instructions, when executed by one or more processors, causing the one or more processors to perform any of the operations described in aspects 1 to 30.

Claims

1. A ray tracing method, the method comprising: Obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determining one or more candidate hierarchical acceleration data structures, each candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures comprising the plurality of primitives; determining a cost metric for the one or more candidate hierarchical acceleration data structures; determining, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures; as well as An output hierarchical acceleration data structure is generated based on the compressibility prediction.

2. The method of claim 1, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH). 3 . The method of claim 1 , wherein each of the one or more candidate hierarchical acceleration data structures is a respective widened hierarchical acceleration data structure that includes the plurality of primitives. 4 . The method of claim 3 , wherein each widened hierarchical acceleration data structure includes the plurality of primitives in a set of leaf nodes. The method of claim 1 , wherein the cost metric is a surface area heuristic (SAH). 6 . The method of claim 5 , wherein the SAH is determined for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

7. The method of claim 1 , wherein determining the compressibility prediction associated with the candidate hierarchical acceleration data structure comprises: predicting a number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; as well as A determination is made as to whether the predicted number of bytes is less than a predetermined threshold. The method according to claim 7 , wherein the predetermined threshold is a maximum leaf node size.

9. The method according to claim 7, wherein the predetermined threshold is 64 bytes.

10. The method of claim 1, wherein generating the output hierarchical acceleration data structure comprises: The candidate hierarchical acceleration data structure is eliminated based on determining, based on the compressibility prediction, that at least one leaf node included in the candidate hierarchical acceleration data structure cannot be compressed within a predetermined maximum leaf node size.

11. The method of claim 1, wherein the output hierarchical acceleration data structure is a widened bounding volume hierarchy (BVH). 12 . The method of claim 11 , further comprising compressing one or more leaf nodes included in the widened BVH.

13. A device for ray tracing, the device comprising: Memory; and one or more processors, the one or more processors coupled to the memory, the one or more processors configured to: Obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determining one or more candidate hierarchical acceleration data structures, each candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures comprising the plurality of primitives; determining a cost metric for the one or more candidate hierarchical acceleration data structures; determining, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures; as well as An output hierarchical acceleration data structure is generated based on the compressibility prediction.

14. The apparatus of claim 13, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH).

15. The apparatus of claim 13, wherein each of the one or more candidate hierarchical acceleration data structures is a respective widened hierarchical acceleration data structure that includes the plurality of primitives.

16. The apparatus of claim 15, wherein each widened hierarchical acceleration data structure comprises the plurality of primitives in a set of leaf nodes.

17. The apparatus of claim 13, wherein the cost metric is a surface area heuristic (SAH).

18. The apparatus of claim 17, wherein the one or more processors are configured to determine the SAH for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

19. The apparatus of claim 13, wherein to determine the compressibility prediction associated with the candidate hierarchical acceleration data structure, the one or more processors are configured to: predicting a number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; and A determination is made as to whether the predicted number of bytes is less than a predetermined threshold.

20. The apparatus of claim 19, wherein the predetermined threshold is a maximum leaf node size.

21. The apparatus of claim 19, wherein the predetermined threshold is 64 bytes.

22. The apparatus of claim 13, wherein to generate the output hierarchical acceleration data structure, the one or more processors are configured to: The candidate hierarchical acceleration data structure is eliminated based on determining, based on the compressibility prediction, that at least one leaf node included in the candidate hierarchical acceleration data structure cannot be compressed within a predetermined maximum leaf node size.

23. The apparatus of claim 13, wherein the output hierarchical acceleration data structure is a widened bounding volume hierarchy (BVH).

24. The apparatus of claim 23, wherein the one or more processors are further configured to compress one or more leaf nodes included in the widened BVH.

25. A non-transitory computer readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to: Obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure; determining one or more candidate hierarchical acceleration data structures, each candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures comprising the plurality of primitives; determining a cost metric for the one or more candidate hierarchical acceleration data structures; determining, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures; as well as An output hierarchical acceleration data structure is generated based on the compressibility prediction.

26. The non-transitory computer readable medium of claim 25, wherein the first hierarchical acceleration data structure is a binary bounding volume hierarchy (BVH).

27. The non-transitory computer-readable medium of claim 25, wherein each of the one or more candidate hierarchical acceleration data structures is a respective widened hierarchical acceleration data structure that includes the plurality of primitives in a set of leaf nodes.

28. A non-transitory computer-readable medium according to claim 25, wherein the cost metric is a surface area heuristic (SAH), and the one or more processors are configured to determine the SAH for each leaf node included in the candidate hierarchical acceleration data structure and each internal node included in the candidate hierarchical acceleration data structure.

29. The non-transitory computer-readable medium of claim 25, wherein to determine the compressibility prediction associated with the candidate hierarchical acceleration data structure, the one or more processors are configured to: predicting a number of bytes associated with compressing each leaf node included in the candidate hierarchical acceleration data structure; and A determination is made as to whether the predicted number of bytes is less than a predetermined threshold.

30. The non-transitory computer readable medium of claim 29, wherein the predetermined threshold is a maximum leaf node size.

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