Heteroepitaxial wafer for deposition of gallium nitride

Abstract

A heteroepitaxial wafer includes, in the following order: (1) a substrate made of silicon having a thickness, a diameter, a crystal orientation, an electrical resistivity, a front side and a back side; (2) a nucleation layer comprising AlN and 3C-SiC; (3) a first boron nitride layer having a first boron nitride layer thickness; and (4) a nitride layer having a nitride layer thickness and containing elements of a list of elements selected from the group consisting of aluminum, gallium, indium, and thallium.

Description

Technical Field

[0001] The present invention relates to heteroepitaxial wafers on which gallium nitride can be deposited. Background Art

[0002] Gallium nitride (GaN) offers fundamental advantages over silicon. In particular, the higher breakdown voltage makes it very attractive for power semiconductor devices with outstanding specific dynamic on-state resistance and lower capacitance compared to silicon MOSFETs, which makes GaN HEMTs excellent for high-speed switching. Not only due to the resulting power savings and total system cost reduction, it also allows higher operating frequencies, improving power density and overall system efficiency.

[0003] Group III nitride semiconductors represented by gallium nitride (GaN) have very broad application prospects as they can also be used in blue light-emitting diodes (LEDs), high-density optical storage, high-temperature, high-power and high-frequency electronic devices, ultraviolet detectors, and other fields.

[0004] However, due to the lack of uniform substrates, it is difficult to obtain high-quality GaN films. Most device-level GaN films prepared to date are obtained on sapphire substrates. Since sapphire substrates are hard, non-conductive and expensive, they are difficult to mass produce. Therefore, people try to grow high-quality GaN on silicon substrates (silicon substrates are cheap, thermally conductive, electrically conductive, large in size, easy to handle and easy to integrate with optoelectronics) to overcome the shortcomings of sapphire substrates.

[0005] However, the lattice mismatch between silicon (Si) and gallium nitride (GaN) reaches 20%, and the thermal mismatch is as high as 56%, which makes the epitaxial growth of gallium nitride (GaN) on a silicon substrate very easy to break.

[0006] Chinese patent application CN 1 05 861 987 A discloses a method for growing a gallium nitride layer on a hexagonal boron nitride transition layer. Silicon can be used as a substrate.

[0007] Japanese patent application JP 2021 020 819A discloses a method for growing epitaxial 3C-SiC on a crystalline substrate. Japanese patent application JP 2000 178 740A discloses another method for growing epitaxial 3C-SiC on a silicon substrate.

[0008] Chinese patent application CN 1 825 539 A discloses a method for growing a crack-free III-nitride layer on a silicon substrate.

[0009] Chinese Patent Application CN 1 06 684 139A discloses a gallium nitride structure based on a Si (silicon) substrate, which includes a first AlN buffer layer, a layer slip layer, a second AlN buffer layer, Al x Ga 1-x N buffer layer and a GaN epitaxial layer stacked in sequence on the Si substrate; the Al x Ga 1-x N buffer layer has an Al content x in the range of 0 < x < 1.

[0010] The purpose of the above patent application is to reduce the influence of the lattice mismatch between silicon and gallium nitride (or other group III nitrides). Summary of the Invention

[0011] An object of the present invention is to prevent the substrate itself from negatively affecting the function of group III nitride devices constructed thereon.

[0012] The solution is achieved by the features of the independent claims and their dependent claims of the present invention. Detailed Description of the Invention

[0013] Although there are some technical measures known in the prior art, the inventors have realized that the substrate itself still negatively affects the function of group III nitride devices to a certain extent.

[0014] Therefore, the main motivation is to provide an improved heteroepitaxial wafer for this purpose, especially a heteroepitaxial wafer that is actually crack-free and suitable for manufacturing nitride-based devices with high breakdown voltage.

[0015] The given task is solved by a heteroepitaxial wafer that includes, in a given order:

[0016] (1) A substrate made of silicon, which has a front side, a back side, a thickness, a diameter, and a resistivity;

[0017] (2) A nucleation layer that contains aluminum nitride (AlN) and 3C-SiC;

[0018] (3) A first boron nitride layer that has a first boron nitride layer thickness; and

[0019] (4) A nitride layer that has a nitride layer thickness and contains elements from (or selected from) a list of elements including aluminum, gallium, indium, and thallium.

[0020] Preferably, the crystal orientation of the silicon substrate has a crystal orientation of 1-1-1. Preferably, the diameter of the heteroepitaxial wafer is greater than 125 mm, preferably greater than 200 mm, and less than 300 mm.

[0021] The crystals preferably used to produce the substrate are obtained by means of a floating zone process. Such a process is described, for example, in European patent application EP 2142 686 A1. The dopant of the crystal is preferably arsenic, red phosphorus or boron. The most preferred resistivity is not less than 0.5 mOhm cm and not more than 100 mOhm cm.

[0022] More preferably, the crystal used is produced by the Czochralski process, the crystal having a diameter greater than 200 mm, preferably a nominal diameter of 300 mm. In addition, the interstitial oxygen concentration of such a crystal is less than 2×10 17 At / cm 3 (ASTM F121). The dopant of the crystal is preferably arsenic, red phosphorus or boron. The most preferred resistivity of the crystal is not less than 1 mOhm cm and not more than 100 mOhm cm.

[0023] The crystals obtained from the crystal growth process are then preferably cut into crystal pieces, then into wafers, cleaned and polished.

[0024] The cleaning process removes contaminants and particles from the wafer surface prior to epitaxial deposition. A standard SC1 clean followed by an SC2 clean is preferably used.

[0025] Preferably, the boron nitride layer is deposited on the front side (front side) of the substrate. The deposition process can preferably be carried out by means of vapor deposition, preferably using metal organic chemical vapor deposition (MOCVD). A process suitable for this is described in Chinese patent application CN 1 825 539 A. The thickness of the boron nitride layer is preferably not less than 1 μm and not more than 10 μm.

[0026] Preferably, a nitride layer having a nitride layer thickness and comprising an element from the following list of elements, namely aluminum (Al), gallium (Ga), indium (In) and thallium (Tl) is placed on top of the boron nitride layer. More preferably, the layer comprises gallium. The thickness of the nitride layer is preferably not less than 1 μm and not more than 10 μm.

[0027] The combined thickness of the first boron nitride layer and the nitride layer (the sum of the thicknesses of both) is not less than 2 μm and not more than 12 μm.

[0028] Preferably, a second boron nitride layer having a second boron nitride layer thickness of 1000 Å is disposed on the back side (rear side) of the substrate. More preferably, the layer thickness is not less than 50 nm and not more than 10 μm.

[0029] The inventors have realized that it is particularly advantageous to additionally place a nucleation layer on the front side of the substrate before adding the first boron nitride layer. The nucleation layer preferably comprises aluminum nitride and 3C-SiC and has a thickness of not less than 50 nm and not more than 500 nm. The nucleation layer has the effect of reducing crystal defects caused by the lattice mismatch between Si and BN. In addition, the breakdown voltage of the III-N device manufactured on this additional layer is increased.

[0030] The inventors have further realised that using a combination of a nucleation layer and a boron nitride layer significantly improves the crystal defect quality of the nitride layer.

Claims

1. A heteroepitaxial wafer comprising, in the following order: (1) A substrate made of silicon having a thickness, diameter, crystal orientation, resistivity, front side and back side; (2) a nucleation layer comprising aluminum nitride (AlN) and 3C-SiC; (3) a first boron nitride layer having a first boron nitride layer thickness; as well as (4) A nitride layer having a nitride layer thickness comprising an element from the list of elements consisting of aluminum, gallium, indium, and thallium.

2. The heteroepitaxial wafer according to claim 1, characterized in that: The nitride layer includes gallium nitride.

3. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The diameter is greater than 125 mm and not greater than 300 mm.

4. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The diameter is greater than 200 mm and not greater than 300 mm.

5. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The resistivity of the substrate is not less than 0.5 mOhm cm and not more than 100 mOhm cm.

6. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The crystal orientation of the substrate is 1-1-1.

7. The heteroepitaxial wafer according to any one of the preceding claims, further comprising: A first nucleation layer having a first nucleation layer thickness is disposed between the substrate and the boron nitride layer.

8. The heteroepitaxial wafer according to claim 7, in, The first nucleation layer includes epitaxial AlN and epitaxial SiC.

9. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The first boron nitride layer has a thickness of not less than 1 μm and not more than 10 μm.

10. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The thickness of the first boron nitride layer is not less than 50 nm and not more than 10 μm.

11. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that The thickness of the nitride layer is not more than 10 μm and not less than 1 μm.

12. The heteroepitaxial wafer according to any one of the preceding claims, characterized in that A combined thickness of the first boron nitride layer and the nitride layer is not greater than 12 μm and not less than 2 μm.