Oxide semiconductor film, thin film transistor, and electronic device

Abstract

An oxide semiconductor film including a plurality of crystal grains provided on a substrate, the oxide semiconductor film including: indium (In); and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc), and lanthanide elements, the plurality of crystal grains include crystal boundaries defined when the difference in crystal orientation between two adjacent measurement points obtained by the EBSD method exceeds 5 DEG, and the average value of KAM values calculated by the EBSD method is 1.0 DEG or more. The average value of the grain boundary orientation change as calculated by the EBSD method may be 40 DEG or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to an oxide semiconductor (Poly-OS) film having a polycrystalline structure. Another embodiment of the present invention relates to a thin film transistor including the Poly-OS film. Another embodiment of the present invention relates to an electronic device including the thin film transistor. Background Art

[0002] In recent years, the development of thin film transistors using oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon has been continuously developed (for example, see Patent Documents 1 to 6). Such thin film transistors including oxide semiconductor films can be formed with a simple structure and by a low-temperature process, just like thin film transistors including amorphous silicon films. In addition, it is known that thin film transistors including oxide semiconductor films have higher field effect mobility than thin film transistors including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, the field effect mobility of a thin film transistor including a conventional oxide semiconductor film is not that high even when a crystalline oxide semiconductor film is used. Therefore, it is desirable to improve the crystal structure of an oxide semiconductor film used in a thin film transistor to increase the field effect mobility of the thin film transistor.

[0013] In view of the above problems, one object of one embodiment of the present invention is to provide an oxide semiconductor film having a novel crystal structure. In addition, one object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor film having a novel crystal structure. In addition, one embodiment of the present invention relates to an electronic device including a thin film transistor.

[0014] Means for solving problems

[0015] An oxide semiconductor film involved in one embodiment of the present invention is an oxide semiconductor film including a plurality of crystal grains disposed on a substrate, the oxide semiconductor film including: indium (In); and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc) and lanthanide elements, the plurality of crystal grains including a grain boundary defined when the crystal orientation difference between two adjacent measurement points obtained by an EBSD (electron backscatter diffraction) method exceeds 5°, and the average value of the KAM value calculated by the EBSD method is greater than 1.0°.

[0016] A thin film transistor according to one embodiment of the present invention includes the above-mentioned oxide semiconductor film as a channel.

[0017] An electronic device according to one embodiment of the present invention includes the above-mentioned thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [ Figure 1 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film involved in one embodiment of the present invention, obtained by crystal orientation analysis using the EBSD method.

[0019] [ Figure 2 ] is a schematic cross-sectional view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0020] [ Figure 3 ] is a schematic top view showing the structure of a thin film transistor involved in one embodiment of the present invention.

[0021] [ Figure 4 ] is a flow chart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0022] [ Figure 5 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0023] [ Figure 6 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0024] [ Figure 7] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0025] [ Figure 8 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0026] [ Fig. 9 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0027] [ Fig.10 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0028] [ Fig.11 ] is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0029] [ Fig.12 ] is a schematic diagram showing an electronic device involved in one embodiment of the present invention.

[0030] [ Fig.13 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 1 obtained by crystal orientation analysis using the EBSD method.

[0031] [ Fig.14 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 2-1 obtained by crystal orientation analysis using the EBSD method.

[0032] [ Fig.15 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 2-2 obtained by crystal orientation analysis using the EBSD method.

[0033] [ Fig.16 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 3-1 obtained by crystal orientation analysis using the EBSD method.

[0034] [ Fig.17 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 3-2 obtained by crystal orientation analysis using the EBSD method.

[0035] [ Fig.18] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 3-3 obtained by crystal orientation analysis using the EBSD method.

[0036] [ Fig.19 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 4-1 obtained by crystal orientation analysis using the EBSD method.

[0037] [ Fig. 20 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 4-2 obtained by crystal orientation analysis using the EBSD method.

[0038] [ Fig.21 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 5-1 obtained by crystal orientation analysis using the EBSD method.

[0039] [ Fig. 22 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of Example 5-2 obtained by crystal orientation analysis using the EBSD method.

[0040] [ Fig.23 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 1, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0041] [ Fig.24 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 2-1, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0042] [ Fig.25 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 2-2, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0043] [ Fig.26 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 3-1, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0044] [ Fig. 27 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 3-2, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0045] [ Fig.28] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 3-3, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0046] [ Fig.29 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 4-1, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0047] [ Fig.30 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 4-2, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0048] [ Fig.31 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 5-1, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0049] [ Fig.32 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of Example 5-2, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes.

[0050] [ Fig.33 ] is an IPF mapping diagram in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film of the comparative example obtained by crystal orientation analysis using the EBSD method.

[0051] [ Fig.34 ] is a graph showing the distribution diagram of the orientation changes of all adjacent points in the oxide semiconductor film of the comparative example, the distribution diagram of the KAM value, and the distribution diagram of the grain boundary orientation changes. DETAILED DESCRIPTION

[0052] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same elements as those described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0053] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. As such, for ease of explanation, the phrases such as up or below are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Up or down means the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above a thin film transistor, it may also be a positional relationship in which the thin film transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above a thin film transistor, it means a positional relationship in which the thin film transistor and the pixel electrode overlap when viewed from above.

[0054] In the present specification, the term "film" and the term "layer" can be used interchangeably according to circumstances.

[0055] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (for example, polarization components, backlight sources, touch panels, etc.) relative to a display unit. As long as no technical contradiction arises, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0056] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes multiple combinations of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0057] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0058] <First embodiment>

[0059] Reference Figure 1 An oxide semiconductor film according to one embodiment of the present invention is described.

[0060] [1. Composition of Oxide Semiconductor Film]

[0061] The oxide semiconductor film involved in this embodiment includes indium (In) and at least one metal element (M) other than indium. The composition ratio of the oxide semiconductor film preferably satisfies the formula (1) in terms of the atomic ratio of indium to at least one metal element. In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, a crystalline oxide semiconductor film can be formed. In addition, the crystal structure of the oxide semiconductor film preferably has a pyrolusite structure. By increasing the ratio of indium, an oxide semiconductor film having a pyrolusite structure can be formed.

[0062] [Mathematical formula 1]

[0063]

[0064] The at least one metal element is preferably one or more elements selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc) and lanthanoid elements.

[0065] The first metal element contained in the at least one metal element is preferably gallium. Since gallium and indium belong to the same Group 13 element, gallium does not hinder the crystallinity of the oxide semiconductor film. That is, even if the oxide semiconductor film contains gallium as the first metal element, an oxide semiconductor film having a pyrolusite structure can still be formed.

[0066] When the first metal element is gallium, the oxide semiconductor film may contain a second metal element (M2) selected from the group consisting of aluminum, yttrium, scandium and lanthanide elements. In this case, in the composition ratio of the oxide semiconductor film, the atomic ratio of indium, gallium and the second metal element preferably satisfies formula (2), formula (3) and formula (4). Since the ratio of the second metal element is lower than that of indium or gallium, the second metal element does not hinder the crystallinity of the oxide semiconductor film.

[0067] [Mathematical formula 2]

[0068]

[0069] [Mathematical formula 3]

[0070]

[0071] [Formula 4]

[0072]

[0073] The oxide semiconductor film can be formed using a sputtering method, and the detailed manufacturing method of the oxide semiconductor film is described together with the manufacturing method of the thin film transistor described later. The composition of the oxide semiconductor film formed by sputtering depends on the composition of the sputtering target. In the sputtering target having the above composition, an oxide semiconductor film without a composition deviation of the metal element can be formed by sputtering. Therefore, the composition of the metal elements (for example, indium or gallium, etc.) of the oxide semiconductor film can also be regarded as the same as the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor film can be determined based on the composition of the metal elements of the sputtering target. It should be noted that since the oxygen contained in the oxide semiconductor film will change according to the process conditions of the sputtering, it is not limited to this.

[0074] In addition, the composition of the metal elements of the oxide semiconductor film can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. In addition, since the oxide semiconductor film has a polycrystalline structure, the composition of the oxide semiconductor film can also be determined using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor film can be determined based on the crystal structure and lattice constant of the oxide semiconductor film obtained by the XRD method.

[0075] [2. Crystal structure of oxide semiconductor film]

[0076] The oxide semiconductor film involved in this embodiment has a polycrystalline structure including a plurality of crystal grains. By using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, an oxide semiconductor film having a novel polycrystalline structure different from the conventional one can be formed, and the details are described later. Therefore, in order to distinguish it from the conventional oxide semiconductor film having a polycrystalline structure, the oxide semiconductor film having a polycrystalline structure involved in this embodiment is sometimes referred to as a Poly-OS film.

[0077] The crystal grains contained in the Poly-OS film may include a plurality of crystallites. The crystallite diameter is not particularly limited, but is preferably 1 nm or more, more preferably 10 nm or more, and further preferably 10 nm or more. The crystallite diameter can be obtained using an electron beam diffraction method or an XRD method.

[0078] The crystal structure of the Poly-OS film is not particularly limited, and is preferably a pyrolusite structure. The crystal structure of the Poly-OS film can be determined using an XRD method or an electron beam diffraction method. As shown in formula (1), by increasing the ratio of indium in the oxide semiconductor film, a Poly-OS film having a pyrolusite structure can be formed. In addition, since gallium and indium belong to the same Group 13 element, gallium does not prevent the Poly-OS film from having a pyrolusite structure.

[0079] It should be noted that in the Poly-OS film, the plurality of crystal grains may have one crystal structure or may have multiple crystal structures. When the Poly-OS film has multiple crystal structures, preferably one of the multiple crystal structures is a bixbyite structure.

[0080] The crystal structure of the Poly-OS film is different from the crystal structure of the oxide semiconductor film with a polycrystalline structure in the past. Specifically, the inventors of the present application found that the grains contained in the Poly-OS film have different characteristics from the grains contained in the previous oxide semiconductor film. The characteristics of such a Poly-OS film can be measured using the Electron Backscatter Diffraction (EBSD) method. Therefore, the measurement of the oxide semiconductor film based on the EBSD method is described below.

[0081] [2-1.EBSD method]

[0082] The EBSD method is an analysis method that irradiates an object to be measured with an electron beam, analyzes the electron backscatter diffraction generated on each crystal plane of the crystal structure of the object to be measured, and measures the crystal structure in the measurement area of ​​the object to be measured. The EBSD method analyzes the data obtained from an EBSD detector mounted on a scanning electron microscope (SEM) or a transmission electron microscope (TEM), thereby obtaining information such as the grain or crystal orientation of the oxide semiconductor film in the measurement area.

[0083] [2-2.IPF Mapping Diagram]

[0084] The IPF (Inverse Pole Figure) map is an image that distinguishes the crystal orientation relative to the normal direction of the surface of the substrate (or the surface of the oxide semiconductor film formed on the substrate) according to a specified index. Usually, the crystal orientation relative to the normal direction of the surface of the substrate is distinguished by color according to the color key. In the measurement using the EBSD method, since the information of the crystal orientation can be obtained, the IPF map can be made based on the information of the obtained crystal orientation.

[0085] [2-3. Grains]

[0086] A grain is a crystal region surrounded by a grain boundary. In the EBSD method, since information related to the crystal orientation can be obtained, the grain boundary can be defined based on the crystal orientation. Generally, when the crystal orientation difference between two adjacent measurement points exceeds 5°, it is defined as the presence of a grain boundary between the two measurement points. Therefore, the above definition also applies to Poly-OS films.

[0087] [2-4. Crystalline particle size]

[0088] The crystal grain size is a value indicating the size of a crystal grain. In the EBSD method, the area S of the crystal grain can be calculated, and therefore the diameter of a circle corresponding to the area S is defined as the crystal grain size d.

[0089] [2-5. Average crystal particle size]

[0090] The average crystal grain size is the average value of the crystal grain sizes of a plurality of crystal grains. Since the Poly-OS film includes a plurality of crystal grains, the average crystal grain size can be used to evaluate the Poly-OS film. AVE Calculate using formula (2). Here, A j is the area ratio of the jth grain (the ratio of the area of ​​the grain to the area of ​​the entire EBSD measurement area (measurement area)), d j is the crystal grain size of the jth grain, and N is the number of grains. As shown in formula (2), the average crystal grain size d AVE is the average area value in the measurement area weighted by the area of ​​the grains. AVE If θ is large, it can be said that a large number of crystal grains having a large crystal grain size exist in the oxide semiconductor film.

[0091] [Formula 5]

[0092]

[0093] The average crystal grain size of the plurality of crystal grains included in the Poly-OS film is, for example, 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more.

[0094] [2-6.KAM value]

[0095] The KAM (Kernel Average Misorientation) value is the average value of the crystal orientation difference between one measurement point in a grain and all measurement points adjacent to the measurement point. The KAM value is a value calculated based on two adjacent measurement points in a grain. Therefore, the crystal orientation difference between two adjacent measurement points sandwiching the grain boundary is excluded from the calculation of the KAM value.

[0096] The KAM value is a value indicating the change of the crystal orientation in the grain. As mentioned above, when the crystal orientation difference exceeds 5°, it is regarded as a grain boundary, so the range of the KAM value is above 0° and below 5°. If the KAM value is large, it means that the change of the local crystal orientation in the grain is large, and it is a grain with large strain.

[0097] The average value of the KAM value can be calculated based on the distribution diagram of the KAM value. The average value of the KAM value is a value indicating one of the properties of the crystal grains contained in the Poly-OS film. If the average value of the KAM value is large, it means that the change in the crystal orientation of the Poly-OS film is large and contains many crystals with large strain. In the Poly-OS film, the average value of the KAM value is 0.8° or more, preferably 1.0° or more, and more preferably 1.2° or more.

[0098] [2-7. Grain boundary orientation change]

[0099] The grain boundary orientation change is the crystal orientation difference between two adjacent measurement points sandwiching the grain boundary. That is, the grain boundary orientation change corresponds to the crystal orientation difference excluded in the calculation of the KAM value.

[0100] The grain boundary orientation change is a value indicating the change in the crystal orientation at the grain boundary. As mentioned above, at the grain boundary, the crystal orientation difference exceeds 5°, so the grain boundary orientation change is in a range exceeding 5°. If the grain boundary orientation change is large, it means that the change in the crystal orientation of the two adjacent grains at the grain boundary is large, and the consistency of the crystal orientation of the two adjacent grains at the grain boundary is low. In other words, if the grain boundary orientation change is large, it means that the lattice matching is low and there are grain boundaries with many defects. Conversely, if the grain boundary orientation change is small, it means that the lattice matching at the grain boundary is high and there are grain boundaries with few defects. Here, the so-called lattice matching is defined as the consistency of the lattice constant and crystal orientation in two grains.

[0101] The average value of the grain boundary orientation change can be calculated based on the distribution diagram of the grain boundary orientation change. The average value of the grain boundary orientation change is a value indicating one of the properties of the crystal grains contained in the Poly-OS film. If the average value of the grain boundary orientation change is small, it means that the Poly-OS film has high lattice matching and contains many grain boundaries with few defects. In the Poly-OS film, the average value of the grain boundary orientation change is less than 40°, preferably less than 39°, and more preferably less than 38°.

[0102] [2-8. Crystal Orientation Analysis of Oxide Semiconductor Film by EBSD Method]

[0103] As described above, when the EBSD method is used, it is possible to obtain information related to the crystal structure of the oxide semiconductor film, in particular, the crystal orientation of the crystal grains included in the oxide semiconductor film. Figure 1 , a description is given of a crystal orientation analysis of the oxide semiconductor film, ie, the Poly-OS film, according to the present embodiment, performed based on the EBSD method.

[0104] Figure 1 This is an IPF map showing the crystal orientation in the normal direction (ND direction) relative to the film surface of the oxide semiconductor film involved in one embodiment of the present invention, obtained by crystal orientation analysis using the EBSD method. It should be noted that, Figure 1 The IPF map of the Poly-OS film shown is an example, and further examples of the Poly-OS film will be described later. In addition, the details of the conditions of the EBSD method are described in the examples described later, so the description is omitted here.

[0105] Figure 1 In the IPF map shown in FIG. 1 , the crystal orientation of each measurement point in the normal direction (ND direction) relative to the film surface in the Poly-OS film is calculated according to Figure 1 The crystal orientations of the measured points in the ND direction are distinguished by the indexes shown, and the grain boundaries are represented by black lines. That is, the crystal orientations of the measured points in the ND direction are distinguished based on the crystal orientations <001>, <101>, and <111>. Figure 1 In the graph, when the difference in crystal orientation between two adjacent measurement points exceeds 5°, it is assumed that a grain boundary exists between the two adjacent measurement points, and a black line is drawn.

[0106] Here, the crystal orientation <001> represents

[001] and its equivalents

[100] and

[010] . In addition, the crystal orientation <101> represents

[101] and its equivalents

[110] and

[011] . In addition, the crystal orientation <111> represents

[111] . In addition, in each orientation, "1" can also be "-1", which is regarded as an axis equivalent to each orientation.

[0107] It should be noted that among the crystal orientations, in addition to <001>, <101> and <111>, there are also <hk0> (h≠k, h and k are natural numbers), <hhl> (h≠l, h and l are natural numbers) and <hkl> (h≠k≠l, h, k and l are natural numbers).

[0108] according to Figure 1 , the Poly-OS film includes a plurality of grains surrounded by black lines. Multiple crystal orientations can be confirmed in one grain. That is, the crystal orientation of the grains contained in the Poly-OS film changes within the grain. For example, near the center of the grain, the crystal orientation <001> and the crystal orientation <111> are measured, and the crystal orientation changes to <101> from near the center of the grain toward the grain boundary. In addition, near the grain boundary, the same crystal orientation can be confirmed, and at the grain boundary, the deviation of the crystal orientation in the direction perpendicular to the film surface is extremely small. This means that at the grain boundary of the Poly-OS film, the lattice matching is high and there are few defects. As a state in which the lattice matching is high with the grain boundary sandwiched in the middle, the crystal orientation in the normal direction relative to the film surface is, for example, a crystal orientation <101> or a crystal orientation <111>. That is, the crystal orientation in the normal direction relative to the film surface at each of two adjacent measurement points sandwiching a grain boundary is 15° or less from the crystal orientation <101>, preferably 10° or less from the crystal orientation <101>. Alternatively, the crystal orientation in the normal direction relative to the film surface at each of two adjacent measurement points sandwiching a grain boundary is 15° or less from the crystal orientation <111>, preferably 10° or less from the crystal orientation <111>.

[0109] In addition, when the crystal orientation difference between two adjacent measurement points sandwiching a grain boundary is less than 15°, it can also be said that the grain boundary is sandwiched in the middle and the lattice matching is high. In the Poly-OS film, if the crystal orientation difference between two adjacent measurement points exceeds 5°, the area between the two measurement points is defined as a grain boundary, but there are many areas where the crystal orientation difference between two adjacent measurement points is less than 15°. Therefore, in the distribution diagram of the crystal orientation change of the Poly-OS film, the peak of the crystal orientation difference sometimes appears below 15°.

[0110] The crystal orientation of the grains contained in the Poly-OS film varies greatly within the grains. In addition, in the Poly-OS film, the change in crystal orientation inside adjacent grains occurs in a manner that increases the matching of the lattice at the grain boundaries. If these characteristics are quantified, the average value of the KAM value of the Poly-OS film is greater than 0.8°, and the average value of the change in grain boundary orientation is less than 40°. The characteristics of such a Poly-OS film are completely different from those of the previous oxide semiconductor film. In this way, the inventors of the present application conducted trial and error and discovered a Poly-OS film with a new crystal structure.

[0111] As described above, the oxide semiconductor film, i.e., the Poly-OS film, involved in one embodiment of the present invention has a novel crystal structure. In the Poly-OS film, since the lattice matching is high and the defects are few at the grain boundaries, the grain boundary scattering is suppressed and the bulk mobility is improved. Therefore, in a thin film transistor including the Poly-OS film as a channel, the grain boundary scattering is suppressed and the field effect mobility is improved.

[0112] <Second embodiment>

[0113] Reference Figure 2 to Figure 11 A thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.

[0114] [1. Configuration of Thin Film Transistor 10]

[0115] Reference Figure 2 and Figure 3 , a structure of a thin film transistor 10 according to an embodiment of the present invention will be described. Figure 2 It is a schematic cross-sectional view showing the structure of a thin film transistor 10 according to one embodiment of the present invention. Figure 3 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 2 It is along Figure 3 A cross-sectional view obtained by cutting along the A-A' line.

[0116] like Figure 2As shown, the thin film transistor 10 includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201, and a drain electrode 203. The light shielding layer 105 is provided on the substrate 100. The first insulating layer 110 covers the upper surface and end surface of the light shielding layer 105 and is provided on the substrate 100. The second insulating layer 120 is provided on the first insulating layer 110. The oxide semiconductor layer 140 is provided on the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surface of the oxide semiconductor layer 140 and is provided on the second insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surface of the gate electrode 160, and is provided on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 are provided with openings 171 and 173 that expose a portion of the upper surface of the oxide semiconductor layer 140. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. It should be noted that, hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as the source / drain electrode 200.

[0117] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the gate electrode 160. That is, the oxide semiconductor layer 140 includes a channel region CH overlapping with the gate electrode 160, and a source region S and a drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has the properties of a semiconductor. The source region S and the drain region D each have the properties of a conductor. Therefore, the conductivity of the source region S and the drain region D is greater than the conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are respectively connected to the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 can be a single-layer structure or a stacked structure.

[0118] like Figure 3As shown, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction and extend in the D2 direction orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The channel region CH completely overlaps with the light shielding layer 105. In the thin film transistor 10, the D1 direction corresponds to the direction in which the current flows from the source electrode 201 to the drain electrode 203 via the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0119] The substrate 100 can support each layer constituting the thin film transistor 10. As the substrate 100, for example, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate, a silicon substrate or other non-light-transmitting rigid substrate can be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can also be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0120] The light shielding layer 105 can reflect or absorb external light. As described above, since the light shielding layer 105 is arranged in a manner having an area larger than that of the channel region CH of the oxide semiconductor layer 140, it is possible to block external light incident on the channel region CH. As the light shielding layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W), or alloys thereof or compounds thereof, etc. can be used. In addition, as the light shielding layer 105, it is not necessary to contain a metal when conductivity is not required. For example, as the light shielding layer 105, a black matrix formed by a black resin can also be used. In addition, the light shielding layer 105 can be a single-layer structure or a stacked structure. For example, the light shielding layer 105 can also be a stacked structure of a red filter, a green filter and a blue filter.

[0121] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (for example, water, etc.) intruding from the outside. As each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO xN y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) etc. Here, silicon nitride oxide (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are silicon compounds and aluminum compounds containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a silicon compound or an aluminum compound containing oxygen at a ratio less than nitrogen (x>y). In addition, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single layer structure or a stacked structure.

[0122] In addition, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarization function or a function of releasing oxygen by heat treatment. For example, when the second insulating layer 120 has a function of releasing oxygen by heat treatment, oxygen can be released from the second insulating layer 120 by heat treatment performed in the manufacturing process of the thin film transistor 10, and the released oxygen can be supplied to the oxide semiconductor layer 140.

[0123] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys thereof or compounds thereof can be used as the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a stacked structure.

[0124] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlOx ) or aluminum oxide nitride (AlO x N y ) etc. It is preferred that the gate insulating layer 150 has a composition close to a stoichiometric ratio. In addition, it is preferred that the gate insulating layer 150 has few defects. For example, as the gate insulating layer 150, an oxide in which no defects are observed when evaluated by an electron spin resonance method (ESR) can be used.

[0125] As the oxide semiconductor layer 140 , the Poly-OS film described in the first embodiment can be used.

[0126] The structure of the thin film transistor 10 is described above, but the thin film transistor 10 described above is a so-called top-gate transistor. The thin film transistor 10 can be deformed in various ways. For example, when the light shielding layer 105 is conductive, the thin film transistor 10 can also be a structure in which the light shielding layer 105 functions as a gate electrode and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin film transistor 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 105 is conductive, the light shielding layer 105 can be a floating electrode or can be connected to the source electrode 201. In addition, the thin film transistor 10 can also be a so-called bottom-gate transistor in which the light shielding layer 105 functions as the main gate electrode.

[0127] [2. Method for Manufacturing Thin Film Transistor 10]

[0128] Reference Figures 4 to 11 A method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 4 1 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figure 5 to Figure 11 Schematic cross-sectional view showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0129] like Figure 4 As shown, the method for manufacturing the thin film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 are described in sequence below, but the order of the steps may be changed in the method for manufacturing the thin film transistor 10. In addition, the method for manufacturing the thin film transistor 10 may include further steps.

[0130] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned using photolithography. In addition, a first insulating layer 110 and a second insulating layer 120 are formed on the light shielding layer 105 (see Figure 5). The first insulating layer 110 and the second insulating layer 120 are formed using a CVD method. For example, silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block impurities that diffuse from the substrate 100 side to the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0131] In step S1020, an oxide semiconductor film 145 is formed on the second insulating layer 120 (see Figure 6 The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and more preferably not less than 15 nm and not more than 40 nm.

[0132] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order to make the oxide semiconductor layer 140 have a uniform polycrystalline structure within the substrate surface, the oxide semiconductor film 145 is preferably amorphous after film formation and before heat treatment. Therefore, it is preferred that the film formation conditions of the oxide semiconductor film 145 are conditions under which the oxide semiconductor layer 140 immediately after film formation does not crystallize as much as possible. In the case of forming the oxide semiconductor film 145 by sputtering, the oxide semiconductor film 145 is formed while the temperature of the film-forming object (substrate 100 and the layer formed on the substrate 100) is controlled to be below 100°C, preferably below 80°C, and more preferably below 50°C. In addition, the oxide semiconductor film 145 is formed under conditions of low oxygen partial pressure. The oxygen partial pressure is greater than 2% and less than 20%, preferably greater than 3% and less than 15%, and more preferably greater than 3% and less than 10%.

[0133] In step S1030, the oxide semiconductor film 145 is patterned (see Figure 7 ). The patterning of the oxide semiconductor film 145 is performed using photolithography. As the etching of the oxide semiconductor film 145, wet etching can be used, or dry etching can be used. In wet etching, an acidic etchant can be used for etching. As an etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide or hydrofluoric acid can be used.

[0134] In step S1040, the oxide semiconductor film 145 is heat treated. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing". In OS annealing, the oxide semiconductor film 145 is maintained at a specified arrival temperature for a specified time. The specified arrival temperature is greater than 300°C and less than 500°C, preferably greater than 350°C and less than 450°C. In addition, the holding time at the arrival temperature is greater than 15 minutes and less than 120 minutes, preferably greater than 30 minutes and less than 60 minutes. Through OS annealing, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure (i.e., an oxide semiconductor layer 140 including a Poly-OS film).

[0135] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see Figure 8 ). The gate insulating layer 150 is formed by a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 can be formed at a film forming temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is greater than 50 nm and less than 300 nm, preferably greater than 60 nm and less than 200 nm, and more preferably greater than 70 nm and less than 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a portion of the gate insulating layer 150 can be performed.

[0136] In step S1060, the oxide semiconductor layer 140 is heat treated. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing". If the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. If the oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140, and the oxygen defects are repaired.

[0137] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see Fig. 9 ). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0138] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see Fig. 9). The source region S and the drain region D are formed by ion implantation. Specifically, the gate electrode 160 is used as a mask to implant impurities into the oxide semiconductor layer 140 via the gate insulating layer 150. As the impurities to be implanted, for example, argon (Ar), phosphorus (P) or boron (B) can be used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen defects are generated due to the ion implantation, and hydrogen is captured by the generated oxygen defects. As a result, the resistance of the source region S and the drain region D is reduced. On the other hand, in the channel region overlapping with the gate electrode 160, since no impurities are implanted, no oxygen defects are generated, and the resistance of the channel region CH is not reduced.

[0139] It should be noted that in the thin film transistor 10 , impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150 , and thus the gate insulating layer 150 may also contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0140] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see Fig.10 ). The third insulating layer 170 and the fourth insulating layer 180 are formed by CVD. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is greater than 50 nm and less than 500 nm. The thickness of the fourth insulating layer 180 is also greater than 50 nm and less than 500 nm.

[0141] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 (see Fig.11 ). By forming the openings 171 and 173 , the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0142] In step S1110, the source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and the drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a conductive film after film formation. Through the above steps, a Figure 2 The thin film transistor 10 is shown.

[0143] As mentioned above, the manufacturing method of the thin film transistor 10 is described, but the manufacturing method of the thin film transistor 10 is not limited thereto.

[0144] In the thin film transistor 10 of this embodiment, the oxide semiconductor layer 140 includes a Poly-OS film having a novel crystal structure. Since the Poly-OS film has high lattice matching and includes many grain boundaries with few defects, grain boundary scattering is suppressed. Therefore, the field effect mobility of the thin film transistor 10 is improved.

[0145] <Third embodiment>

[0146] Reference Fig.12 An electronic device according to an embodiment of the present invention will be described.

[0147] Fig.12 1 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.12 , a smartphone is shown as an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit and a driving circuit. The pixel circuit and the driving circuit include the thin film transistor 10 described in the second embodiment. Since the thin film transistor 10 has a high field effect mobility, the responsiveness of the pixel circuit and the driving circuit can be improved, and as a result, the performance of the electronic device 1000 can be improved.

[0148] It should be noted that the electronic device 1000 involved in this embodiment is not limited to a smartphone. The electronic device 1000 also includes, for example, an electronic device with a display device such as a clock, a tablet computer, a laptop computer, a car navigation system, or a television. In addition, the thin film transistor 10 described in the first embodiment can be applied to all electronic devices, regardless of whether they have a display device or not.

[0149] Example

[0150] Based on the produced samples, the Poly-OS film is described in further detail.

[0151] [1. Sample preparation]

[0152] The samples described below use a sputtering process and an OS annealing process to make an oxide semiconductor film on a substrate. It should be noted that in the sputtering process, both the embodiment and the comparative example use a sputtering target containing indium (In) and gallium (Ga) as the first metal element (M1) in the sintered body and in which the atomic ratio of indium is 70% relative to all the metal elements contained in the sintered body. In any sample, the chemical composition of the oxide semiconductor film after the OS annealing process is the same as the chemical composition of the sputtering target. It should be noted that the first metal element (M1) contained in the sintered body of the embodiment is not limited to gallium (Ga), and aluminum (Al), yttrium (Y), scandium (Sc) and lanthanide elements also have the same effect.

[0153] [Example 1]

[0154] In the film forming process, there is SiO x A 30nm oxide semiconductor film is formed on a glass substrate as a base film by a sputtering process. The oxygen partial pressure during film formation is 5%, and the substrate temperature is controlled so that the substrate temperature during film formation is below 100°C. Then, the formed oxide semiconductor film is subjected to an OS annealing process in an atmospheric atmosphere. In the annealing process, the reaching temperature is controlled between 350°C and 450°C and maintained at the reaching temperature for 60 minutes.

[0155] [Example 2]

[0156] A laminated film (AlO x / SiO x ) as a base film. On the glass substrate with the base film formed thereon, a 30nm oxide semiconductor film is formed by a sputtering process. The oxygen partial pressure during film formation is 5%, and the substrate temperature is controlled in such a way that the substrate temperature during film formation becomes below 100°C. Then, the formed oxide semiconductor film is subjected to an OS annealing process in an atmospheric atmosphere. During the annealing process, the reaching temperature is controlled between 350°C and 450°C, and is maintained at the reaching temperature for 60 minutes ("Example 2-1" and "Example 2-2").

[0157] [Example 3]

[0158] A laminated film (AlO x / SiO x) as a base film. On a glass substrate formed with a base film, an oxide semiconductor film of 30nm ("Example 3-1"), 25nm ("Example 3-2") or 20nm ("Example 3-3") is formed by a sputtering process. The oxygen partial pressure during film formation is 3%, and the substrate temperature is controlled in such a way that the substrate temperature during film formation becomes below 100°C. Then, the formed oxide semiconductor film is subjected to an OS annealing process in an atmospheric atmosphere. In the annealing process, the reaching temperature is controlled between 350°C and 450°C, and is maintained at the reaching temperature for 60 minutes.

[0159] [Example 4]

[0160] A laminated film (AlO x / SiO x ) as a base film. On the glass substrate with the base film formed thereon, a 15nm oxide semiconductor film is formed by a sputtering process. The oxygen partial pressure during film formation is 3%, and the substrate temperature is controlled in such a way that the substrate temperature during film formation becomes below 100°C. Then, the formed oxide semiconductor film is subjected to an OS annealing process in an atmospheric atmosphere. During the annealing process, the reaching temperature is controlled between 350°C and 450°C, and is maintained at the reaching temperature for 60 minutes ("Example 4-1" and "Example 4-2").

[0161] [Example 5]

[0162] A laminated film (AlO x / SiO x ) as a base film. It should be noted that before the aluminum oxide film is formed, the silicon oxide film is surface treated by a wet process. In addition, after the aluminum oxide film is formed, the aluminum oxide film is subjected to ("Example 5-1") or not subjected to ("Example 5-2") surface treatment using plasma. On a glass substrate on which a base film is formed, a 15nm oxide semiconductor film is formed by a sputtering process. The oxygen partial pressure during film formation is 3%, and the substrate temperature is controlled in such a way that the substrate temperature during film formation becomes below 100°C. Then, the formed oxide semiconductor film is subjected to an OS annealing process in an atmospheric atmosphere. In the annealing process, the reaching temperature is controlled between 350°C and 450°C, and is maintained at the reaching temperature for 60 minutes.

[0163] [Comparative Example]

[0164] A 50nm oxide semiconductor film was formed on a quartz substrate by sputtering. The oxygen partial pressure during film formation was 10%, and the substrate temperature was not controlled during film formation. Then, the formed oxide semiconductor film was subjected to an OS annealing process in an atmospheric atmosphere. During the annealing process, the reaching temperature was controlled between 350°C and 450°C and maintained at the reaching temperature for 60 minutes.

[0165] The differences in process conditions for the samples produced are summarized in Table 1.

[0166] [Table 1]

[0167]

[0168] [2. Crystal structure analysis based on XRD method]

[0169] The crystal structure of the oxide semiconductor film of each sample produced was analyzed by XRD method. All the oxide semiconductor films had crystallinity and had a bixbyite-type crystal structure.

[0170] [3. Crystal orientation analysis based on EBSD method]

[0171] The crystal orientation analysis of the oxide semiconductor film of each sample produced was performed using the EBSD method. The measurement conditions of the EBSD method are shown in Table 2. In addition, the analysis of the crystal orientation used OIM-Analysis (version 7.1) manufactured by TSL Solutions. The orientation of the crystal structure was assigned to the crystal structure file of the 14388 ferromanganese-type structure using ICSD (Inorganic Crystal Structure Database: Chemical Information Association). As a result of the measurement and analysis, it was judged that the pattern obtained when the CI value became 0.6 or more was clear enough, and the crystal orientation was identified as a ferromanganese-type structure.

[0172] [Table 2]

[0173]

[0174] The IPF maps in the normal direction (ND direction) with respect to the film surface of the oxide semiconductor film of Example 1, Example 2-1, Example 2-2, Example 3-1, Example 3-2, Example 3-3, Example 4-1, Example 4-2, Example 5-1, Example 5-2 and Comparative Example are shown in FIG. Figure 13 to Figure 22 and Fig.33 In any IPF map, when the crystal orientation difference between two adjacent measurement points exceeds 5°, the grain boundary is indicated by a black line. Figure 13 to Figure 22 and Fig.33 In the method, the crystal orientation of each measurement point in the normal direction of the surface of the substrate (or the surface of the oxide semiconductor film) is distinguished according to the index. Specifically, the crystal orientation of each measurement point in the normal direction of the surface of the substrate is distinguished based on the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111>.

[0175] like Figure 13 to Figure 22 and Fig.33 As shown, any oxide semiconductor film includes a plurality of crystal grains divided by crystal boundaries according to the above definition. Figure 13 to Figure 22 In the embodiment, multiple crystal orientations can be confirmed in the crystal grains. Therefore, the oxide semiconductor film of the embodiment is a Poly-OS film in which the crystal orientation changes in the crystal grains. In particular, Figure 16 to Figure 22 In the oxide semiconductor film of the example shown, it can be confirmed that the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> are contained in one crystal grain. Figure 16 to Figure 22 In the oxide semiconductor film of the embodiment shown, at least one crystal grain contains a crystal orientation of <001>, a crystal orientation of <101>, and a crystal orientation of <111>, and the crystal orientation varies greatly within the crystal grain. Fig.33 In the oxide semiconductor film of the comparative example shown, multiple crystal orientations are not confirmed in the crystal grains. Therefore, the oxide semiconductor film of the comparative example is a conventional oxide semiconductor film in which the crystal orientation does not change in the crystal grains. Thus, although the oxide semiconductor film of the embodiment and the oxide semiconductor film of the comparative example have the same bixbyite-type crystal structure, the characteristics of the crystal orientation of the crystal grains contained in the oxide semiconductor film of the embodiment and the oxide semiconductor film of the comparative example are greatly different.

[0176] Next, analysis of the crystal orientation difference based on two adjacent measurement points will be described.

[0177] Graphs showing distributions of crystal orientation differences of oxide semiconductor films of Example 1, Example 2-1, Example 2-2, Example 3-1, Example 3-2, Example 3-3, Example 4-1, Example 4-2, Example 5-1, Example 5-2, and Comparative Example are shown in FIG. Figure 23 to Figure 32 and Fig.34 .exist Figure 23 to Figure 32 and Fig.34 Each of the three graphs shows a distribution diagram of orientation changes of all adjacent points ("(A)" in each figure), a distribution diagram of KAM values ​​("(B)" in each figure), and a distribution diagram of grain boundary orientation changes ("(C)" in each figure). The distribution diagram of orientation changes of all adjacent points shows all crystal orientation differences of two adjacent measurement points.

[0178] according to Figure 23 to Figure 32 In the distribution diagram of grain boundary orientation change, when the peak near 10° becomes larger, the peak of the KAM value distribution diagram moves to near 5°. Figure 25 to Figure 30 In the distribution diagram of the grain boundary orientation change, two peaks including a peak near 10° can be confirmed. Fig.31 In the distribution diagram of the grain boundary orientation change, the peak is only seen near 10°. Fig.34 As shown, in the comparative example, no peak is observed near 10°.

[0179] In addition, according to Figure 23 to Figure 32 In the KAM value distribution diagram, there are clearly KAM values ​​above 3°. Figure 25 to Figure 32 , there is also a KAM value near 5°. On the other hand, Fig.34 In the distribution diagram of KAM values, KAM values ​​above 3° are almost invisible.

[0180] Here, the ratio of the average value of the grain boundary orientation variation to the average value of the KAM value is defined as the grain boundary parameter P GB ((Grain boundary parameter P GB ) = (average value of grain boundary orientation change) / (average value of KAM value)). Grain boundary parameter P GB It is a parameter that indicates the ratio of the change in crystal orientation at the grain boundary to the change in crystal orientation within the grain. GB If the value is large, it means that the change in local crystal orientation in the grain is small, and the crystal orientation difference between two adjacent measurement points sandwiching the grain boundary is large. GB The smaller the value is and the closer it is to 1, the greater the local crystal orientation change in the grain is, and the higher the lattice matching between two adjacent measurement points sandwiching the grain boundary is. In other words, the grain boundary parameter P GB The smaller it is and the closer it is to 1, the higher the lattice matching of the oxide semiconductor film is, and the more grain boundaries with fewer defects are included.

[0181] The average KAM value, the average grain boundary orientation variation, and the grain boundary parameter P of the oxide semiconductor films of the examples and the comparative examples are calculated. GB Shown in Table 3.

[0182] [Table 3]

[0183]

[0184] As shown in Table 3, in any oxide semiconductor film of the embodiment, the average value of the KAM value is greater than 1.0°. On the other hand, the average value of the KAM value of the oxide semiconductor film of the comparative example is less than 1.0°. From this result, it can be seen that in the conventional oxide semiconductor film, the crystal orientation in the grains hardly changes, while in the Poly-OS film, the crystal orientation in the grains changes greatly.

[0185] In addition, as shown in Table 3, in any oxide semiconductor film of the embodiment, the average value of the change in grain boundary orientation is 40° or less. On the other hand, the average value of the change in grain boundary orientation of the oxide semiconductor film of the comparative example exceeds 40°. In addition, in any oxide semiconductor film of the embodiment, the grain boundary parameter P GB is less than 30. On the other hand, the average value of the change in grain boundary orientation of the oxide semiconductor film of the comparative example greatly exceeds 30. From this result, it can be seen that in the previous oxide semiconductor film, the lattice matching between two adjacent grains at the grain boundary is low. Therefore, in the previous oxide semiconductor film, there are many defects at the grain boundary. In contrast, in the Poly-OS film, the crystal orientation in two adjacent grains changes in a manner that the lattice matching at the grain boundary becomes higher. As a result, the Poly-OS film becomes a state where the lattice matching at the grain boundary is high and there are few defects.

[0186] [4. Electrical characteristics]

[0187] The thin film transistors including the oxide semiconductor films of the above-described examples were fabricated using the manufacturing method described in the second embodiment, and the electrical characteristics were measured. Table 4 shows the field effect mobility calculated from the electrical characteristics.

[0188] [Table 4]

[0189] Sample name Field Effect Mobility Example 1 20.7cm / Vs Example 2-1 33.5cm / Vs Example 2-2 33.9cmVs Example 3-1 35.0cmVs Example 3-2 35.9cmVs Example 3-3 37.2cm / Vs Example 4-1 36.2cmVs Example 4-2 38.7cm / Vs Example 5-1 39.1cmVs Example 5-2 41.3cmVs

[0190] As shown in Table 4, in any thin film transistor, a value greater than 20 cm 2 From this result, it can be seen that the field effect mobility is improved when the Poly-OS film is used as the channel of the thin film transistor.

[0191] As embodiments of the present invention, the embodiments described above can be appropriately combined for implementation as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or by adding, omitting or changing conditions of processes based on the embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0192] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0193] Description of Reference Numerals

[0194] 10: thin film transistor, 100: substrate, 105: light shielding layer, 110: first insulating layer, 120: second insulating layer, 140: oxide semiconductor layer, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 170: third insulating layer, 171: opening, 173: opening, 180: fourth insulating layer, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 1000: electronic device, 1100: display device

Claims

1. An oxide semiconductor film, which is an oxide semiconductor film including a plurality of crystal grains provided on a substrate, The oxide semiconductor film includes: Indium (In); and a first metal element selected from the group consisting of aluminum (Al), gallium (Ga), yttrium (Y), scandium (Sc) and lanthanide elements, The plurality of crystal grains include a grain boundary in which a crystal orientation difference between two adjacent measurement points obtained by an EBSD (electron backscatter diffraction) method exceeds 5°, The average value of the KAM value calculated by the EBSD method is 1.0° or more.

2. The oxide semiconductor film according to claim 1, wherein The average value of the grain boundary orientation change calculated by the EBSD method is 40° or less.

3. The oxide semiconductor film according to claim 1, wherein The ratio of the average value of the grain boundary orientation change calculated by the EBSD method to the average value of the KAM value (average value of the grain boundary orientation change / average value of the KAM value) is 30 or less.

4. The oxide semiconductor film according to claim 1, wherein The distribution diagram of the grain boundary orientation change calculated by the EBSD method has a peak when the crystal orientation difference is 15° or less.

5. The oxide semiconductor film according to claim 1, wherein The plurality of crystal grains include a first crystal grain and a second crystal grain adjacent to each other with the crystal boundary interposed therebetween, The first crystal grain includes a first measurement point of two adjacent measurement points sandwiching the grain boundary. The second crystal grain includes a second measurement point of the two adjacent measurement points sandwiching the grain boundary. The crystal orientation of each of the first measurement point and the second measurement point in the normal direction with respect to the film surface of the oxide semiconductor film is 15° or less away from the crystal orientation <101>.

6. The oxide semiconductor film according to claim 1, wherein The plurality of crystal grains include a first crystal grain and a second crystal grain adjacent to each other with the crystal boundary interposed therebetween, The first crystal grain includes a first measurement point of two adjacent measurement points sandwiching the grain boundary. The second crystal grain includes a second measurement point of the two adjacent measurement points sandwiching the grain boundary. The crystal orientation of each of the first measurement point and the second measurement point in the normal direction with respect to the film surface of the oxide semiconductor film is 15° or less away from the crystal orientation <111>.

7. The oxide semiconductor film according to claim 1, wherein In at least one of the plurality of crystal grains, a crystal orientation in a normal direction relative to a film surface of the oxide semiconductor film changes from a crystal orientation <111> to a crystal orientation <101> from near a center of the crystal grain toward the grain boundary.

8. The oxide semiconductor film according to claim 1, wherein In at least one of the plurality of crystal grains, a crystal orientation in a normal direction relative to a film surface of the oxide semiconductor film changes from a crystal orientation of <001> to a crystal orientation of <101> from near a center of the crystal grain toward the grain boundary.

9. The oxide semiconductor film according to claim 1, wherein the oxide semiconductor film includes: at least one metal element other than the indium and including the first metal element; The ratio of the indium to the indium and the at least one metal element is 50% or more.

10. The oxide semiconductor film according to claim 1, wherein The first metal element is gallium, The second metal element (M2) contained in the at least one metal element is one metal element selected from the group consisting of the aluminum, yttrium, scandium and lanthanide elements. The atomic ratio of the indium, gallium and the second metal element satisfies formula (1), formula (2) and formula (3), [Mathematical formula 1] [Mathematical formula 2] [Mathematical formula 3] 11. The oxide semiconductor film according to claim 1, wherein The crystal structure of the oxide semiconductor film is a bixbyite structure. 12 . A thin film transistor comprising the oxide semiconductor film according to claim 1 as a channel.

13. An electronic device comprising the thin film transistor according to claim 12.

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